SN74LVC2G241DCTR

Product Folder Order Now Technical Documents Support & Community Tools & Software SN74LVC2G241 SCES210P – APRIL 1999 – REVISED JANUARY 2019 SN74LVC2G241 Dual Buffer and Driver With 3-State Outputs 1 Features 3 Description • This dual buffer and line driver is designed for 1.65-V to 5.5-V VCC operation. 1 • • • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA Maximum ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCC Level Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) The SN74LVC2G241 device is designed specifically to improve both the performance and density of 3state memory-address drivers, clock drivers, and busoriented receivers and transmitters. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. The SN74LVC2G241 device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low and 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high and 2OE is low, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 2 Applications • • • • • • • • • • • • AV Receivers Blu-ray Players and Home Theaters DVD Recorders and Players Desktop or Notebook PCs Digital Radio or Internet Radio Players Digital Video Cameras (DVC) Embedded PCs GPS: Personal Navigation Devices Mobile Internet Devices Network Projector Front-Ends Portable Media Players Pro Audio Mixers Device Information(1) PART NUMBER PACKAGE SN74LVC2G241DCT SM8 (8) BODY SIZE (NOM) 2.95 mm × 2.80 mm SN74LVC2G241DCU VSOOP (8) 2.30 mm × 2.00 mm SN74LVC2G241YZP 1.91 mm × 0.91 mm DSBGA (8) (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 1OE 1A 2OE 2A 1 2 6 1Y 7 5 3 2Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC2G241 SCES210P – APRIL 1999 – REVISED JANUARY 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 5 5 6 6 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Operating Characteristics.......................................... Typical Characteristic................................................ Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 8 8.4 Device Functional Modes.......................................... 8 9 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application ................................................... 9 10 Power Supply Recommendations ..................... 10 11 Layout................................................................... 10 11.1 Layout Guidelines ................................................. 10 11.2 Layout Example .................................................... 10 12 Device and Documentation Support ................. 11 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 11 13 Mechanical, Packaging, and Orderable Information ........................................................... 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision O (December 2015) to Revision P Page • Changed Electrical Characteristics table format ................................................................................................................... 5 • Changed Switching Characteristics tables format. ................................................................................................................ 6 Changes from Revision N (November 2013) to Revision O • Page Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 Changes from Revision M (February 2007) to Revision N Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Removed Ordering Information table. .................................................................................................................................... 1 • Updated Features. .................................................................................................................................................................. 1 • Updated operating temperature range. .................................................................................................................................. 4 2 Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 SN74LVC2G241 www.ti.com SCES210P – APRIL 1999 – REVISED JANUARY 2019 5 Pin Configuration and Functions DCT Package 8-Pin SM8 Top View 1OE 1 DCU Package 8-Pin VSSOP Top View VCC 8 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 1OE 1A 2Y GND 1 8 VCC 2 7 2OE 1Y 2A 3 6 4 5 YZP Package 8-Pin DSBGA Bottom View GND 2Y 1A 1OE 4 5 3 6 2 7 1 8 2A 1Y 2OE VCC Pin Functions (1) (2) PIN NAME NO. 1A 2 1OE 1Y I/O DESCRIPTION I Input 1 I Output enable (Active low) 6 O Output 2A 5 I Input 2Y 3 O Output 2OE 7 I Output enable (Active high) GND 4 — Ground VCC 8 — Power pin (1) (2) N.C. – No internal connection See for dimensions Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 3 SN74LVC2G241 SCES210P – APRIL 1999 – REVISED JANUARY 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 6.5 V (2) VI Input voltage –0.5 6.5 V VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA TJ Maximum junction temperature 150 °C Tstg Storage temperature 150 °C (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage VI Input voltage 1.7 Output voltage 0.7 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 2.3 V High-level output current VCC = 3 V VCC = 4.5 V (1) 4 V 0.3 × VCC 0 VCC = 1.65 V IOH V 2 VCC = 4.5 V to 5.5 V VO V 0.65 × VCC VCC = 1.65 V to 1.95 V VIL UNIT V V –4 –8 –16 mA –24 –32 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, SCBA004. Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 SN74LVC2G241 www.ti.com SCES210P – APRIL 1999 – REVISED JANUARY 2019 Recommended Operating Conditions(1) (continued) MIN IOL Low-level output current MAX VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V Δt/Δv Input transition rise or fall rate mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA UNIT ns/V 5 Operating free-air temperature –40 85 °C 6.4 Thermal Information SN74LVC2G241 THERMAL METRIC (1) RθJA (1) Junction-to-ambient thermal resistance DCT (SM8) DCU (VSSOP) YZP (DSBGA) 8 PINS 8 PINS 8 PINS 220 227 102 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range, TA = –40ºC to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN IOH = –100 µA VOH 1.65 V to 5.5 V MIN VCC – 0.1 VCC – 0.1 1.2 1.2 IOH = –8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3V UNIT MAX V 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.55 0.55 0.75 0 to 5.5 V ±5 ±5 µA IOL = 16 mA 3.8 TYP IOH = –32 mA 3.8 3V IOL = 24 mA IOL = 32 mA II MAX 1.65 V IOH = –24 mA A or OE inputs TYP IOH = –4 mA IOH = –16 mA VOL –40°C to 125°C (Recommended) –40°C to 85°C 4.5 V VI = 5.5 V or GND V Ioff VI or VO = 5.5 V 0 ±10 ±10 µA IOZ VO = 0 to 5.5 V 3.6 V 10 10 µA ICC VI = 5.5 V or GND, 1.65 V to 5.5 V 10 10 µA ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 500 µA Ci Co Data Inputs Control Inputs IO = 0 VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 3.5 pF 4 6.5 pF Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 5 SN74LVC2G241 SCES210P – APRIL 1999 – REVISED JANUARY 2019 www.ti.com 6.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 3.3 9.1 1.5 5.5 1.4 4.3 1.0 4.0 ns ten OE Y 4.0 9.9 1.3 6.6 1.2 4.7 1.1 5.0 ns tdis OE Y 1.5 11.6 1.0 5.7 1.4 4.6 0.5 4.2 ns PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 3.3 10.1 1.5 5.6 1.4 5.3 1.0 4.2 ns ten OE Y 4.0 10.9 1.3 6.6 1.2 5.7 1.2 4.3 ns tdis OE Y 1.5 12.6 1.0 6.6 1.4 5.6 1.0 3.9 ns UNIT –40°C to 125°C (Recommended) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT 6.7 Operating Characteristics TA = 25°C PARAMETER TEST CONDITIONS VCC Outputs enabled Cpd Power dissipation capacitance per buffer/driver f = 10 MHz Outputs disabled TYP VCC = 1.8 V 19 VCC = 2.5 V 19 VCC = 3.3 V 20 VCC = 5 V 22 VCC = 1.8 V 2 VCC = 2.5 V 2 VCC = 3.3 V 2 VCC = 5 V 3 UNIT pF pF 6.8 Typical Characteristic 3.5 3 Propagation Delay (tPD) 2.5 2 1.5 1 0.5 Typ. Char. 0 0 1 2 3 4 5 6 Supply Voltage [VCC] (V) C001 Figure 1. tpd vs Vcc Over Full Temperature Range 6 Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 SN74LVC2G241 www.ti.com SCES210P – APRIL 1999 – REVISED JANUARY 2019 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 7 SN74LVC2G241 SCES210P – APRIL 1999 – REVISED JANUARY 2019 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC2G241 device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LVC2G241 device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low and 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high and 2OE is low, the outputs are in the high-impedance state. The SN74LVC2G241 is also an effective redriver, with a maximum output current drive of 32 mA. 8.2 Functional Block Diagram 1 1OE 2 1A 6 1Y 7 2OE 5 2A 3 2Y Figure 3. Logic Diagram (Positive Logic) 8.3 Feature Description To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.4 Device Functional Modes Table 1 and Table 2 list the functional modes of the SN74LVC2G241. Table 1. Gate 1 Functional Table INPUTS 1OE 1A OUTPUT 1Y L H H L L L H X Z Table 2. Gate 2 Functional Table INPUTS 8 2OE 2A OUTPUT 2Y H H H H L L L X Z Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 SN74LVC2G241 www.ti.com SCES210P – APRIL 1999 – REVISED JANUARY 2019 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Typical Application shows a simple application where a physical push button is connected to the SN74LVC2G241. The push button is in a physical location far enough away from the processor that the input signal is weak and needs to be redriven. The SN74LVC2G241 acts as a redriver, providing a strong input signal to the processor with as little as 1 ns of propagation delay. 9.2 Typical Application VCC Physical Push Button Microprocessor SN74LVC2G241 (One driver) Figure 4. SN74LVC2G241 Application 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions. – Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in Recommended Operating Conditions at any valid VCC. 2. Recommend Output Conditions – Load currents must not exceed (IO max) per output and must not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in Absolute Maximum Ratings. – Outputs must not be pulled above VCC during normal operation or 5.5 V in high-z state. Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 9 SN74LVC2G241 SCES210P – APRIL 1999 – REVISED JANUARY 2019 www.ti.com Typical Application (continued) 9.2.3 Application Curve 1600 Icc Icc Icc Icc 1400 1200 1.8V 2.5V 3.3V 5V Icc - µA 1000 800 600 400 200 0 0 20 40 Frequency - MHz 60 80 D001 Figure 5. ICC vs Frequency 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever make more sense or is more convenient. 11.2 Layout Example VCC Unused Input Input Output Unused Input Output Input Figure 6. Layout Diagram 10 Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 SN74LVC2G241 www.ti.com SCES210P – APRIL 1999 – REVISED JANUARY 2019 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: Implications of Slow or Floating CMOS Inputs, SCBA004 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks NanoFree, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Submit Documentation Feedback Copyright © 1999–2019, Texas Instruments Incorporated Product Folder Links: SN74LVC2G241 11 PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74LVC2G241DCTRE4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C41 Z 74LVC2G241DCTRG4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C41 Z 74LVC2G241DCUTG4 ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C41R SN74LVC2G241DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C41 Z SN74LVC2G241DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C41J, C41Q, C41R) SN74LVC2G241DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C41J, C41Q, C41R) SN74LVC2G241YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 (C2, C27) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of