SN74LVC2G79DCURE4

SN74LVC2G79 www.ti.com SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 Dual Positive-Edge-Triggered D-Type Flip-Flop Check for Samples: SN74LVC2G79 FEATURES DESCRIPTION • This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. 1 2 • • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Feature Supports Live Insertion, PartialPower-Down Mode Operation and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCT PACKAGE (TOP VIEW) When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DCU PACKAGE (TOP VIEW) 1CLK 1 8 VCC 1D 2 7 1Q 2Q 3 6 2D GND 4 5 2CLK 1CLK 1D 2Q GND YZP PACKAGE (BOTTOM VIEW) 1 8 VCC 2 7 3 6 4 5 1Q 2D 2CLK GND 2Q 1D 1CLK 4 5 3 6 2 7 1 8 2CLK 2D 1Q VCC See mechanical drawings for dimensions. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated SN74LVC2G79 SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table INPUTS CLK D OUTPUT Q ↑ H H ↑ L L L X Q0 Logic Diagram, Each Flip-Flop (Positive Logic) CLK C C C TG C C Q C C D TG TG TG C C C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.5 (2) (3) UNIT VO Output voltage range IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range DCT package 220 DCU package 227 YZP package (1) (2) (3) (4) 2 V °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 SN74LVC2G79 www.ti.com SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN 1.65 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 4.5 V to 5.5 V 0.3 × VCC VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V Low-level output current Δt/Δv Input transition rise or fall rate –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V ± 0.5 V TA mA –24 VCC = 4.5 V IOL V ns/V 5 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 3 SN74LVC2G79 SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC – 0.1 VCC – 0.1 1.2 1.2 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3.8 3.8 3V TYP (1) MAX 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.65 0.55 0.65 3V IOL = 32 mA 4.5 V VI = 5.5 V or GND VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND (1) All typical values are at VCC = 3.3 V, TA = 25°C. UNIT V IOH = –32 mA IOL = 24 mA Ioff MIN 1.65 V IOL = 16 mA D input MAX IOH = –8 mA IOH = –24 mA II –40°C to 125°C TYP (1) IOH = –4 mA IOH = –16 mA VOL MIN 1.65 V to 5.5 V IOH = –100 μA VOH –40°C to 85°C VCC V 0 to 5.5 V ±1 ±1 μA 0 ±1 ±10 μA 1.65 V to 5.5 V 5 5 μA 500 500 μA 3 V to 5.5 V 0 3.5 pF Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC2G79 –40°C to 85°C VCC = 1.8 V ± 0.15 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time before CLK↑ th Hold time, data after CLK↑ MAX VCC = 2.5 V ± 0.2 V MIN 160 MAX VCC = 3.3 V ± 0.3 V MIN 160 MAX VCC = 5 V ± 0.5 V MIN UNIT MAX 160 160 2.5 2.5 2.5 2.5 Data high 2.2 1.4 1.1 0.9 Data low 2.2 1.4 1.1 0.9 1.4 0.8 0.7 0.5 MHz ns ns ns Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC2G79 –40°C to 125°C VCC = 1.8 V ± 0.15 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time before CLK↑ th Hold time, data after CLK↑ 4 MAX VCC = 2.5 V ± 0.2 V MIN 160 MAX VCC = 3.3 V ± 0.3 V MIN 160 MAX VCC = 5 V ± 0.5 V MIN 160 MAX 160 2.2 2.5 2.5 2.5 Data high 2.2 1.4 1.1 0.9 Data low 2.2 1.4 1.1 0.9 1.4 0.8 0.7 0.5 Submit Documentation Feedback UNIT MHz ns ns ns Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 SN74LVC2G79 www.ti.com SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) SN74LVC2G79 –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax MAX 160 tpd CLK Q 3 VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V MAX 160 9.1 MIN MAX 160 1.5 6 VCC = 5 V ± 0.5 V MIN UNIT MAX 160 1.3 4.2 MHz 1.1 3.7 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC2G79 –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax MAX 160 tpd CLK Q 4.4 VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V MAX 160 9.9 MIN MAX 160 2.3 7 VCC = 5 V ± 0.5 V MIN UNIT MAX 160 2 5.2 MHz 1.3 4.5 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC2G79 –40°C to 125°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax MAX 160 tpd CLK Q 4.4 VCC = 2.5 V ± 0.2 V MIN MAX 160 10.5 VCC = 3.3 V ± 0.3 V MIN MAX 160 2.3 7.5 VCC = 5 V ± 0.5 V MIN UNIT MAX 160 2 5.8 MHz 1.3 5 ns Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 23 23 24 28 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 UNIT pF 5 SN74LVC2G79 SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 www.ti.com Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 SN74LVC2G79 www.ti.com SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 Parameter Measurement Information (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 7 SN74LVC2G79 SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision D (Feburary 2007) to Revision E Page • Updated document to new TI data sheet format. ................................................................................................................. 1 • Removed Ordering Information table. ................................................................................................................................... 1 • Added ESD warning. ............................................................................................................................................................ 2 • Updated operating temperature range. ................................................................................................................................. 3 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G79 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC2G79DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C79 (R, Z) SN74LVC2G79DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C79J, C79Q, C79R) SN74LVC2G79DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C79R SN74LVC2G79YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 CRN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of