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SN74LVCH16652A
SCAS319J – NOVEMBER 1993 – REVISED DECEMBER 2014
SN74LVCH16652A 16-Bit Bus Transceiver and Register with 3-State Outputs
1 Features
2 Applications
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Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Partial-Power-Down Mode Operation
Bus Hold on Data Inputs Eliminates the Need for
External Pull-up or Pull-down Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1500-V Charged-Device Model
Servers
PCs, Notebooks
Network switches
Telecom Infrastructure
I/O Expanders
3 Description
This 16-bit bus transceiver and register is designed
for 1.65-V to 3.6-V VCC operation.
Device Information(1)
PART NUMBER
SN74LVCH16652A
PACKAGE
BODY SIZE (NOM)
SSOP (56)
18.40 mm x 7.50 mm
TSSOP (56)
14.00 mm x 6.10 mm
TVSOP (56)
11.30 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
56
2OEBA
1
2OEAB
55
2CLKBA
54
2SBA
2
2CLKAB
3
2SAB
One of Eight Channels
1A1
28
30
31
27
26
One of Eight Channels
1D
C1
5
52
1D
29
1B1
2A1
15
42
1D
C1
1D
C1
2B1
C1
To Seven Other Channels
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCH16652A
SCAS319J – NOVEMBER 1993 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
5
5
6
6
7
8
8
8
8
9
9
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, 40°C to 85°C.........................
Timing Requirements, 40°C to 125°C.......................
Switching Characteristics, 40°C to 85°C ..................
Switching Characteristics, 40°C to 125°C ................
Operating Characteristics........................................
Typical Characteristics ............................................
8
9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
12
13
13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 14
11 Power Supply Recommendations ..................... 15
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 16
13.1 Trademarks ........................................................... 16
13.2 Electrostatic Discharge Caution ............................ 16
13.3 Glossary ................................................................ 16
14 Mechanical, Packaging, and Orderable
Information ........................................................... 16
5 Revision History
Changes from Revision I (March 2005) to Revision J
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature in Recommended Operating Conditions table........................................................... 6
2
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SCAS319J – NOVEMBER 1993 – REVISED DECEMBER 2014
6 Pin Configuration and Functions
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OEAB
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
1OEAB
I
1OEAB Input. Active-high enable for A-to-B directional data.
2
1CLKAB
I
1CLKAB Input. Clock input for D flip-flop from A to B.
3
1SAB
I
1SAB Input. Data select from A to B: A high level selects
stored data and a low-level selects real-time data.
4
GND
—
GND
5
1A1
I/O
1A1 Input/Output
6
1A2
I/O
1A2 Input/Output
7
VCC
—
Power Pin
8
1A3
I/O
1A3 Input/Output
9
1A4
I/O
1A4 Input/Output
10
1A5
I/O
1A5 Input/Output
11
GND
—
Ground Pin
12
1A6
I/O
1A6 Input/Output
13
1A7
I/O
1A7 Input/Output
14
1A8
I/O
1A8 Input/Output
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SCAS319J – NOVEMBER 1993 – REVISED DECEMBER 2014
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Pin Functions (continued)
PIN
NO.
NAME
TYPE
DESCRIPTION
15
2A1
I/O
2A1 Input/Output
16
2A2
I/O
2A2 Input/Output
17
2A3
I/O
2A3 Input/Output
18
GND
—
Ground Pin
19
2A4
I/O
2A4 Input/Output
20
2A5
I/O
2A5 Input/Output
21
2A6
I/O
2A6 Input/Output
22
VCC
—
Power Pin
23
2A7
I/O
2A7 Input/Output
24
2A8
I/O
2A8 Input/Output
25
GND
—
Ground Pin
26
2SAB
I
2SAB Input. Data select from A to B: A high level selects
stored data and a low-level selects real-time data.
27
2CLKAB
I
2CLKAB Input. Clock input for D flip-flop from A to B.
28
2OEAB
I
2OEAB Input. Active-high enable for A-to-B directional data.
29
2OEBA
I
2OEBA Input. Active-low enable for B-to-A directional data.
30
2CLKBA
I
2CLKBA Input. Clock input for D flip-flop from B to A.
31
2SBA
I
2SBA Input. Data select from B to A: A high level selects
stored data and a low-level selects real-time data.
32
GND
—
Ground Pin
33
2B8
I/O
2B8 Input/Output
34
2B7
I/O
2B7 Input/Output
35
VCC
—
Power Pin
36
2B6
I/O
2B6 Input/Output
37
2B5
I/O
2B5 Input/Output
38
2B4
I/O
2B4 Input/Output
39
GND
-
40
2B3
I/O
2B3 Input/Output
41
2B2
I/O
2B2 Input/Output
42
2B1
—
2B1 Input/Output
43
1B8
I/O
1B8 Input/Output
44
1B7
I/O
1B7 Input/Output
45
1B6
I/O
1B6 Input/Output
46
GND
—
Ground Pin
47
1B5
I/O
1B5 Input/Output
48
1B4
I/O
1B4 Input/Output
49
1B3
I/O
1B3 Input/Output
Ground Pin
50
VCC
—
Power Pin
51
1B2
I/O
1B2 Input/Output
52
1B1
I/O
1B1 Input/Output
53
GND
—
Ground Pin
54
1SBA
i
1SBA Input. Data select from B to A: A high-level selects
stored data and a low-level selects real-time data.
55
1CLKBA
I
1CLKBA Input. Clock input for D flip-flop from B to A.
56
1OEBA
I
1OEBA Input. Active-low enable for B-to-A directional data.
4
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SCAS319J – NOVEMBER 1993 – REVISED DECEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
(3)
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating
VCC
Supply voltage
VIH
High-level input voltage
Data retention only
MIN
MAX
1.65
3.6
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
Output voltage
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
IOH
V
1.5
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
mA
10
ns/V
125
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74LVCH16652A
THERMAL METRIC (1)
DGG
DGV
DL
UNIT
56 PINS
RθJA
Junction-to-ambient thermal resistance
60.6
72.8
53.1
RθJC(top)
Junction-to-case (top) thermal resistance
17.9
27.5
18.3
RθJB
Junction-to-board thermal resistance
29.4
38.3
25.8
ψJT
Junction-to-top characterization parameter
0.8
1.7
1.4
ψJB
Junction-to-board characterization parameter
29.1
37.8
25.6
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
Control
inputs
II
1.65 V
1.2
1.2
1.2
IOH = –8 mA
2.3 V
1.7
1.7
1.7
2.7 V
2.2
2.2
2.2
2.4
2.4
2.4
3V
2.2
2.2
2.2
IOL = 100 μA
1.65 V
to
3.6 V
0.2
0.2
0.2
IOL = 4 mA
1.65 V
0.45
0.45
0.45
IOL = 8 mA
2.3 V
0.7
0.7
0.7
IOL = 12 mA
2.7 V
0.4
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
0.55
VI = 0 to 5.5 V
3.6 V
1.65 V
2.3 V
VI = 1.7 V
3V
±5
See
(2)
±5
See
See (2)
(2)
±5
See
See (2)
V
μA
(2)
See (2)
45
45
45
–45
–45
–45
75
75
75
–75
UNIT
V
3V
–75
μA
–75
VI = 0 to 3.6 V (3)
3.6 V
±500
±500
±500
VI or VO = 5.5 V
0
±10
±10
±10
μA
2.3 V
to
3.6 V
±5
±5
±5
μA
20
20
20
20
20
20
500
500
500
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (5)
ΔICC
MAX
IOH = –24 mA
VO = 0 V or (VCC to 5.5 V)
ICC
MIN
IOH = –4 mA
VI = 2 V
(4)
–40°C to 125°C
MAX
VCC – 0.2
VI = 0.8 V
IOZ
MIN
VCC – 0.2
VI = 0.7 V
Ioff
MAX
VCC – 0.2
VI = 1.07 V
A or B
ports
–40°C to 85°C
TYP (1)
1.65 V
to
3.6 V
VI = 0.58 V
II(hold)
TA = 25°C
MIN
IOH = –100 μA
IOH = –12 mA
VOL
VCC
IO = 0
3.6 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V
to
3.6 V
μA
μA
Ci
Control
inputs
VI = VCC or GND
3.3 V
5
pF
Cio
A or B
ports
VO = VCC or GND
3.3 V
8
pF
(1)
(2)
(3)
(4)
(5)
All typical values are at VCC = 3.3 V, TA = 25°C.
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the
IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
This applies in the disabled state only.
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7.6 Timing Requirements, 40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time, A or B before CLKAB↑ or CLKBA↑
th
Hold time, A or B after CLKAB↑ or CLKBA↑
(1)
MAX
VCC = 2.5 V
± 0.2 V
MIN
120
MAX
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN MAX
150
150
See (1)
See (1)
3.3
5
3.8
0.7
0.5
150
UNIT
MHz
3.3
ns
3.4
3
ns
0
0.2
ns
This information was not available at the time of publication.
7.7 Timing Requirements, 40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
th
(1)
MAX
VCC = 2.5 V
± 0.2 V
MIN
120
MAX
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN MAX
150
150
150
UNIT
MHz
See (1)
See (1)
3.3
3.3
ns
Setup time, A or B before CLKAB↑ or CLKBA↑
5.3
3.5
3.4
3
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0.8
0.5
0
0.2
ns
This information was not available at the time of publication.
7.8 Switching Characteristics, 40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
fmax
MAX
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MIN
MIN
120
11.8
6.9
MAX
150
150
UNIT
MAX
150
MHz
A or B
B or A
8.6
6.4
1.4
6.3
CLKAB or CLKBA
A or B
10.4
7.3
7.3
2.4
6.4
SAB or SBA
B or A
12.5
9.6
8.8
1.9
7.4
ten
OE or OE
A or B
23.4
9.3
6.6
1.6
6.3
ns
tdis
OE or OE
A or B
15.9
8.2
6.6
1.2
6.2
ns
tpd
9.1
MAX
ns
7.9 Switching Characteristics, 40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
8
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MIN
MIN
TO
(OUTPUT)
120
150
150
A or B
B or A
10
7.6
6.4
1.4
6.3
CLKAB or CLKBA
A or B
11.6
9.1
7.3
2.4
6.4
fmax
tpd
VCC = 1.8 V
± 0.15 V
FROM
(INPUT)
MIN
MAX
MAX
MAX
UNIT
MAX
150
MHz
ns
SAB or SBA
B or A
13.1
9.9
8.8
1.9
7.4
ten
OE or OE
A or B
2.1
8.5
6.6
1.6
6.3
ns
tdis
OE or OE
A or B
18.6
8.2
6.6
1.2
6.2
ns
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7.10 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Power dissipation capacitance
per transceiver
Cpd
(1)
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
See
(1)
See
(1)
See
(1)
55
See
(1)
12
UNIT
pF
This information was not available at the time of publication.
7.11 Typical Characteristics
6
8
7
5
6
TPD (ns)
TPD (ns)
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
D001
Figure 1. TPD vs Temperature
1
2
VCC
3
Product Folder Links: SN74LVCH16652A
D002
Figure 2. TPD vs VCC at 25°C
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH16652A device consists of D-type flip-flops and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers. The device can be used as
two 8-bit transceivers or one 16-bit transceiver.
Complementary output-enable (OEAB and OEBA) inputs control the transceiver functions. Select-control (SAB
and SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data,
and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding
glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 5 illustrates the
four fundamental bus-management functions that can be performed with SN74LVCH16652A.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of
bus lines remains at its last level configuration.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pull-up or
pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
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9.2 Functional Block Diagram
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
One of Eight Channels
1A1
1D
C1
5
52
1B1
1D
C1
To Seven Other Channels
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
29
28
30
31
27
26
One of Eight Channels
2A1
1D
C1
15
42
1D
2B1
C1
To Seven Other Channels
Figure 4. Logic Diagram (Positive Logic)
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9.3 Feature Description
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
Bus hold on data Inputs eliminates the need for external pull-up/pull-down resistors
•
•
•
9.4 Device Functional Modes
Table 1. Function Table
DATA I/O (1)
INPUTS
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
Store A and B data
X
H
↑
H or L
X
X
Input
Unspecified (2)
Store A, hold B
H
H
↑
↑
X (2)
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
X
(1)
(2)
Unspecified (2)
Input
Hold A, store B
(2)
Output
Input
Store B in both registers
Input
Real-time B data to A bus
L
L
↑
↑
X
L
L
X
X
X
L
Output
X
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always
are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
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10 Application and Implementation
10.1 Application Information
SN74LVCH16652A is a high-drive CMOS device that can be used for a multitude of bus interface type
applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V,
making it Ideal for driving multiple outputs and good for high-speed applications up to 100 MHz. To ensure the
high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor
and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver. Inputs can be driven from either 3.3-V or 5-V
devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pull-up or
pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by any control pin.
10.2 Typical Application
3.3 V
Clock
signal
To
System
1OEAB
1OEBA
1CLKAB
1CLKBA
1SAB
1SBA
GND
GND
1A1
1B1
1A2
1B2
VCC
VCC
Clock
signal
To
System
Figure 5. Bus-Management Functions
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
14
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Typical Application (continued)
10.2.3 Application Curves
300
250
ICC (PA)
200
150
100
VCC 1.8 V
VCC 2.5 V
VCC 3.3 V
50
0
0
10
20
30
40
Frequency (MHz)
50
60
D003
Figure 6. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVCH16652ADGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16652A
SN74LVCH16652ADGVR
ACTIVE
TVSOP
DGV
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LDH652A
SN74LVCH16652ADL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16652A
SN74LVCH16652ADLG4
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH16652A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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