SN74SSTV32867GKER

SN74SSTV32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS SCES362B – OCTOBER 2001 – REVISED MAY 2002 D D D D D Member of the Texas Instruments Widebus+ Family Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated DIMM Load Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input D D D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads. The SN74SSTV32867 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74SSTV32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS SCES362B – OCTOBER 2001 – REVISED MAY 2002 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A D1 GND Q2 B D3 Q3 Q4 C C D5 D4 VREF NC VDDQ GND Q1 B VCC D2 GND Q5 Q6 D D D7 D6 GND Q7 Q8 VCC GND VDDQ GND Q9 VDDQ VDDQ Q10 VDDQ GND Q12 Q11 GND GND Q13 Q14 E F G H J E D9 D8 F D11 D10 G D13 D12 H D15 D14 VCC GND J CLK NC GND GND GND VCC GND VDDQ VDDQ Q15 Q16 Q17 GND GND Q18 VDDQ GND Q20 VDDQ Q19 Q22 Q21 K CLK RESET K L D16 D17 L M D18 D19 M N D20 D21 VCC GND N P D22 D23 NC P R D24 D25 NC GND Q24 Q23 R T D26 VCC GND VDDQ Q26 Q25 T ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING 0°C to 70°C LFBGA – GKE Tape and reel SN74SSTV32867GKER SV867 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS 2 RESET CLK CLK D OUTPUT Q H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTV32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS SCES362B – OCTOBER 2001 – REVISED MAY 2002 logic diagram (positive logic) RESET CLK CLK VREF D1 K2 J1 K1 B3 A1 1D C1 A5 Q1 R To 25 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74SSTV32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS SCES362B – OCTOBER 2001 – REVISED MAY 2002 recommended operating conditions (see Note 4) MIN NOM VDDQ 2.3 MAX UNIT VCC VDDQ Supply voltage VREF VTT Reference voltage (VREF = VDDQ/2) VI VIH Input voltage AC high-level input voltage Data input VIL VIH AC low-level input voltage Data input DC high-level input voltage Data input VIL VIH DC low-level input voltage Data input High-level input voltage RESET VIL VICR Low-level input voltage RESET Common-mode input voltage range CLK, CLK 0.97 VI(PP) IOH Peak-to-peak input voltage CLK, CLK 360 High-level output current –8 mA IOL TA Low-level output current 8 mA 70 _C Output supply voltage 1.15 Termination voltage VREF–40mV 0 1.25 VREF 2.7 V 2.7 V 1.35 V VREF+40mV VCC V VREF+310mV V VREF–310mV VREF+150mV Operating free-air temperature V V VREF–150mV 1.7 V V 0.7 0 V 1.53 V V mV NOTE 4: The RESET input of the device must be held at VCC or GND to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTV32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS SCES362B – OCTOBER 2001 – REVISED MAY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = –18 mA IOH = –100 µA VOH IOH = –8 mA IOL = 100 µA VOL II ICC ICCD All inputs Static standby RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle CLK, CLK VCC 2.3 V MIN 2.3 V to 2.7 V VDDQ–0.2 1.7 2.3 V IOL = 8 mA VI = VCC or GND Data inputs Ci‡ TEST CONDITIONS TYP† VI = VREF ± 310 mV VICR = 1.25 V, IO = 0 VI(PP) = 360mV UNIT –1.2 V V 2.3 V to 2.7 V 0.2 2.3 V 0.4 2.7 V IO = 0 MAX 2.7 V ±5 µA 40 µA 95 mA 44 µA/ MHz 5 µA/ clock MHz/ D input 2.5 V 2.5 3.5 4.5 4 4.5 5 3.9 5 5.5 2.5 V RESET VI = VCC or GND † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ Measured with 50-MHz input frequency V pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V MIN fclock Clock frequency tw Pulse duration 200 CLK, CLK high or low 2.5 tact Differential inputs active time (see Note 5) tinact Differential inputs inactive time (see Note 6) tsu Setup time th Hold time Fast slew rate (see Notes 7 and 9) Slow slew rate (see Notes 8 and 9) Fast slew rate (see Notes 7 and 9) NOTES: 5. 6. 7. 8. 9. Slow slew rate (see Notes 8 and 9) MHz ns 22 ns 22 ns 0.75 D t before Data b f CLK↑, CLK↑ CLK↓ UNIT MAX 0.9 ns 0.75 Data after CLK↑, CLK↑ CLK↓ 0.9 ns Data inputs must be low a minimum time of tact min, after RESET is taken high. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact min, after RESET is taken low. Data signal input slew rate ≥1 V/ns Data signal input slew rate ≥0.5 V/ns and