SN75ALS160DWG4


  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 D Suitable for IEEE Standard 488-1978 (GPIB) D 8-Channel Bidirectional Transceivers D High-Speed Advanced Low-Power Schottky D D D D D D D (ALS) Circuitry Low Power Dissipation . . . 46 mW Max Per Channel Fast Propagation Times . . . 20 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . . 650 mV Typ Open-Collector Driver Output Option No Loading of Bus When Device Is Powered Down (VCC = 0) Power-Up/Power-Down Protection (Glitch Free) DW OR N PACKAGE (TOP VIEW) GPIB I/O Ports TE B1 B2 B3 B4 B5 B6 B7 B8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC D1 D2 D3 D4 D5 D6 D7 D8 PE Terminal I/O Ports description/ordering information The SN75ALS160 eight-channel general-purpose interface bus transceivers are monolithic, high-speed, advanced low-power Schottky (ALS) devices designed for two-way data communications over single-ended transmission lines. This device is designed to meet the requirements of IEEE Standard 488 - 1978. The transceivers feature driver outputs that can be operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs when PE is high. Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads up to 48 mA of sink current. An active turn-off feature has been incorporated into the bus-terminating resistors so that the device exhibits a high impedance to the bus when VCC = 0. When combined with the SN75ALS161 or SN75ALS162 bus management transceiver, the pair provides the complete 16-wire interface for the IEEE - 488 bus. The SN75ALS160 is characterized for operation from 0°C to 70°C. ORDERING INFORMATION PACKAGE† TA PDIP (N) 0°C 0 C to 70 70°C C SOIC (DW) ORDERABLE PART NUMBER Tube of 20 SN75ALS160N Tube of 25 SN75ALS160DW Reel of 2000 SN75ALS160DWR TOP-SIDE MARKING SN75ALS160N 75ALS160 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated      ! "#$ !  %#&'" ($) (#"! "  !%$""! %$ *$ $!  $+! !#$! !(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 Function Tables EACH DRIVER INPUTS D TE PE OUTPUT B H H H H L H X H X L X L X L Z† Z† EACH RECEIVER INPUTS B TE PE OUTPUT D L L X L H L X H X H X Z H = high level, L = low level, X = irrelevant, Z = high-impedance state † This is the high-impedance state of a normal 3-state output modified by the internal resistors to VCC and GND. logic diagram (positive logic) PE TE D1 11 1 19 2 B1 18 D2 3 D3 4 D4 Terminal I/O Ports GPIB I/O Ports B5 14 7 D7 B4 15 6 D6 B3 16 5 D5 B2 17 B6 13 8 B7 12 D8 9 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B8 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS EQUIVALENT OF ALL INPUT/OUTPUT PORTS VCC 9 kΩ NOM R(eq) 1.7 kΩ NOM 10 kΩ NOM Input 4 kΩ NOM 4 kΩ NOM GND Input/Output Port Driver output R(eq) = 30 Ω NOM Receiver output R(eq) = 110 Ω NOM R(eq) = equivalent resistor Circuit inside dashed lines is on the driver outputs only. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, θJA (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High-level output current High-level input voltage MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 IOL Low-level output current TA Operating free-air temperature V Bus ports with pullups active − 5.2 mA Terminal ports − 800 µA Bus ports 48 Terminal ports 16 0 70 mA °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VIK Input clamp voltage II = − 18 mA, Vhys Hysteresis voltage (VIT+ − VIT−) VOH§ High-level output voltage Terminal Low-level output voltage Terminal VOL II MIN VCC = MIN Bus IOH = − 800 µA, IOH = − 5.2 mA, TE at 0.8 V, IOL = 16 mA, IOL = 48 mA, TE at 0.8 V, Bus Input current at maximum input voltage Terminal VI = 5.5 V, IIH High-level input current Terminal, PE, or TE IIL Low-level input current Terminal, PE, or TE VI/O(bus) Voltage at bus port Bus PE and TE at 2 V, VCC = MIN VCC = MIN Current into bus port IOS Short-circuit output current ICC Supply current UNIT − 1.5 V 0.4 0.65 2.7 3.5 2.5 3.3 VCC = MIN VCC = MIN V 0.5 0.5 VCC = MAX 0.2 100 µA VI = 2.7 V, VCC = MAX 0.1 20 µA VI = 0.5 V, VCC = MAX −10 −100 µA 3.7 V −1.5 V 2.5 3 0 − 3.2 2.5 − 3.2 VI(bus) = 2.5 V to 3.7 V Power on VI(bus) = 3.7 V to 5 V VI(bus) = 5 V to 5.5 V Terminal VCC = 0 VCC = MAX Bus VCC = MAX No load, VCC = MAX POST OFFICE BOX 655303 0 2.5 0.7 2.5 VI(bus) = 0 to 2.5 V 40 − 15 − 35 − 75 − 25 − 50 − 125 Terminal outputs low and enabled 42 65 Bus outputs low and enabled 52 80 • DALLAS, TEXAS 75265 V −1.3 CI/O(bus) Bus-port capacitance VCC = 0 to 5 V, VI/O = 0 to 2 V, f = 1 MHz 30 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § VOH applies to 3-state outputs only. 4 V 0.3 II(bus) = 0 II(bus) = −12 mA Power off MAX − 0.8 0.35 TE at 2 V, VI(bus) = −1.5 V to 0.4 V VI(bus) = 0.4 V to 2.5 V II/O(bus) TYP‡ mA µA mA mA pF 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 switching characteristics at VCC = 4.75 V, 5 V, and 5.25 V, TA = 255C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS Terminal Bus Bus TYP† MAX See Figure 1, CL = 50 pF 10 17 10 14 See Figure 2, CL = 50 pF 8 15 Terminal 8 15 24 30 9 14 Bus See Figure 3, CL = 50 pF 16 28 MIN tPLH tPHL Propagation delay time, low- to high-level output tPLH tPHL Propagation delay time, low- to high-level output tPZH tPHZ Output enable time to high level tPZL tPLZ Output enable time to low level Output disable time from low level 12 19 tPZH tPHZ Output enable time to high level 24 36 Output disable time from high level 10 18 tPZL tPLZ Output enable time to low level 15 26 15 24 16 24 9 16 Propagation delay time, high- to low-level output Propagation delay time, high- to low-level output Output disable time from high level TE TE Terminal See Figure 4, CL = 50 pF Output disable time from low level ten Output pullup enable time tdis Output pullup disable time † All typical values are at VCC = 5 V. PE Bus See Figure 5, CL = 50 pF UNIT ns ns ns ns ns switching characteristics over recommended range of operating free-air temperature, VCC = 5 V PARAMETER FROM (INPUT) TO (OUTPUT) Terminal Bus Bus Terminal TEST CONDITIONS TYP‡ MAX CL = 30 pF, See Figure 1 7 20 8 20 CL = 30 pF, See Figure 2 7 14 9 14 19 30 5 12 16 35 MIN tPLH tPHL Propagation delay time, low- to high-level output tPLH tPHL Propagation delay time, low- to high-level output tPZH tPHZ Output enable time to high level tPZL tPLZ Output enable time to low level 9 20 tPZH tPHZ Output enable time to high level 13 30 Output disable time from high level 12 20 tPZL tPLZ Output enable time to low level 12 20 11 20 11 22 6 12 Propagation delay time, high- to low-level output Propagation delay time, high- to low-level output Output disable time from high level TE Bus CL = 15 pF, See Figure 3 Output disable time from low level TE Terminal CL = 15 pF, See Figure 4 Output disable time from low level ten Output pullup enable time tdis Output pullup disable time ‡ Typical values are at TA = 25°C. PE POST OFFICE BOX 655303 Bus CL = 15 pF, See Figure 5 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns 5 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION 5V PE 3V Output Generator (see Note A) D 200 Ω 3V D Input 1.5 V 1.5 V 0 B tPHL tPLH CL = 30 pF (see Note B) 50 Ω VOH 480 Ω B Output 2.2 V 1V VOH TE 3V TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms 4.3 V TE 3V B Input Output 1.5 V 1.5 V 0 240 Ω Generator (see Note A) B tPLH D VOH CL = 30 pF (see Note B) 50 Ω tPHL 3 kΩ D Output 1.5 V 1.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION 5V 3V 200 Ω PE 3V TE Input Output S2 S1 D B CL = 15 pF (see Note B) 480 Ω 1.5 V 1.5 V 0 tPZH B Output S1 to 3 V S2 Open tPHZ 90% 2V 0.8 V tPZL Generator (see Note A) tPLZ 3.5 V B Output S1 to GND S2 Closed TE 50 Ω TEST CIRCUIT VOH 1V 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms 3V 4.3 V TE Input Generator (see Note A) TE S2 50 Ω Output D 3V S1 CL = 15 pF (see Note B) B 3 kΩ 1.5 V 0 tPZH D Output S1 to 3 V S2 Open 240 Ω 1.5 V tPHZ 90% VOH 1.5 V 0 tPLZ tPZL 4V D Output S1 to GND S2 Closed TEST CIRCUIT 1V 0.7 V VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION Generator (see Note A) PE 3V 50 Ω D PE Input B Output 1.5 V 1.5 V 0 CL = 15 pF (see Note B) RL = 480 Ω ten B Output tdis 90% VOH 2V VOL ≈0.8 3V TE TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 5. PE-to-Bus Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS TERMINAL HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TERMINAL LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 3.5 VOL − Low-Level Output Voltage − V VCC = 5 V TA = 25°C 3 2.5 2 1.5 1 0.5 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 0 − 5 − 10 − 15 − 20 − 25 − 30 − 35 IOH − High-Level Output Current − mA 0 − 40 30 40 50 10 20 IOL − Low-Level Output Current − mA Figure 6 60 Figure 7 TERMINAL OUTPUT VOLTAGE vs BUS INPUT VOLTAGE 4 VCC = 5 V No Load TA = 25°C 3.5 VO − Output Voltage − V VOH − High-Level Output Voltage − V 4 3 2.5 2 VIT + VIT − 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VI − Input Voltage − V 1.6 1.8 2 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

  
  


SLLS018E − JUNE 1986 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS BUS HIGH-LEVEL OUTPUT VOLTAGE vs BUS HIGH-LEVEL OUTPUT CURRENT BUS LOW-LEVEL OUTPUT VOLTAGE vs BUS LOW-LEVEL OUTPUT CURRENT 0.6 4 VOL− Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VCC = 5 V TA = 25°C 3 2 1 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 0 − 10 − 20 − 30 − 40 − 50 0 − 60 10 20 30 40 50 60 70 80 90 100 IOL − Low-Level Output Current − mA IOH − High-Level Output Current − mA Figure 9 Figure 10 BUS OUTPUT VOLTAGE vs TERMINAL INPUT VOLTAGE BUS CURRENT vs BUS VOLTAGE 4 2 VCC = 5 V TA = 25°C 1 I I/O(bus) − Bus Current − mA II/O(bus) VO − Output Voltage − V VCC = 5 V No Load TA = 25°C 3 2 1 0 −1 −2 −3 −4 −5 The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488 - 1978 −6 0 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 −7 −2 −1 VI − Input Voltage − V 1 2 3 4 VI/O(bus) − Bus Voltage − V Figure 11 10 0 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 6 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN75ALS160DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS160 Samples SN75ALS160DWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS160 Samples SN75ALS160DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 75ALS160 Samples SN75ALS160DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS160 Samples SN75ALS160N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN75ALS160N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of