SN75ALS161DWR


    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 D Suitable for IEEE Standard 488-1978 (GPIB) D 8-Channel Bidirectional Transceivers D Designed to Implement Control Bus D D D D D D D D D Interface Designed for Single Controller High-Speed Advanced Low-Power Schottky Circuitry Low Power Dissipation . . . 46 mW Max Per Channel Fast Propagation Times . . . 20 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . . 650 mV Typ Bus-Terminating Resistors Provided on Driver Outputs No Loading of Bus When Device Is Powered Down (VCC = 0) Power-Up/Power-Down Protection (Glitch Free) description/ordering information DW OR N PACKAGE (TOP VIEW) TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND GPIB I/O Ports 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC REN IFC NDAC NRFD DAV EOI ATN SRQ DC Terminal I/O Ports CHANNEL-IDENTIFICATION TABLE NAME DC TE ATN SRQ REN IFC EOI DAV NDAC NRFD IDENTITY Direction Control Talk Enable Attention Service Request Remote Enable Interface Clear End or Identify Data Valid Not Data Accepted Not Ready for Data CLASS Control Bus Management The SN75ALS161 eight-channel Data Transfer general-purpose interface bus transceivers are high-speed, advanced low-power Schottky-process devices designed to provide the bus-management and data-transfer signals between operating units of a single-controller instrumentation system. When combined with the SN75ALS160 octal bus transceivers, this device provides a complete 16-wire interface for the IEEE 488 bus. The SN75ALS161 device features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver pairs is determined by the direction-control (DC) and talk-enable (TE) signals. The driver outputs general-purpose interface bus (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when VCC = 0. The drivers are designed to handle sink-current loads up to 48 mA. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV on the commercial part, and 250 mV on the military part, minimum, for increased noise immunity. All receivers have 3-state outputs, to present a high impedance to the terminal when disabled. The SN75ALS161 is characterized for operation from 0°C to 70°C. ORDERING INFORMATION PACKAGE† TA PDIP (N) 0°C 0 C to 70 70°C C SOIC (DW) ORDERABLE PART NUMBER Tube of 20 SN75ALS161N Tube of 25 SN75ALS161DW Reel of 2000 SN75ALS161DWR TOP-SIDE MARKING SN75ALS161N 75ALS161 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated        !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 FUNCTION TABLE RECEIVE/TRANSMIT CONTROLS DC TE ATN† BUS-MANAGEMENT CHANNELS ATN† SRQ REN IFC EOI (CONTROLLED BY DC) H H H H H L L L H L L L H L L H DATA-TRANSFER CHANNELS DAV NDAC NRFD (CONTROLLED BY TE) T R T R R T R T T X R T R R X T R T T T R R R T T R R T T T T R R R R T H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 logic diagram (positive logic) DC TE ATN EOI SRQ REN IFC DAV NDAC NRFD 11 1 13 8 14 7 12 9 19 2 18 3 15 6 17 4 16 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ATN EOI SRQ REN IFC DAV NDAC NRFD 3 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT VCC 9 kΩ NOM 1.7 kΩ NOM Input 4 kΩ NOM GND Input/Output Port Circuit inside dashed lines is on the driver outputs only. TYPICAL OF ALL I/O PORTS, EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS R(eq) 1.7 kΩ NOM 4 kΩ NOM 4 kΩ NOM Input/Output Port Driver output R(eq) = 30 Ω NOM Receiver output R(eq) = 110 Ω NOM R(eq) = equivalent resistor Circuit inside dashed lines is on the driver outputs only. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 kΩ NOM 10 kΩ NOM 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, θJA (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current TA Operating free-air temperature High-level input voltage MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 V Bus ports with pullups active − 5.2 mA Terminal ports − 800 µA Bus ports 48 Terminal ports 16 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 mA °C 5 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VIK Vhys Input clamp voltage Hysteresis voltage (VIT+ − VIT−) II = −18 mA Bus Terminal VOH§ MIN IOH = − 800 µA, VCC = MIN High-level output voltage TYP‡ MAX UNIT −0.8 −1.5 V 0.4 0.65 2.7 3.5 TA = MIN TA = 25°C and MAX 2.7 3.5 TA = MIN 2.2 TA = 25°C and MAX V V 2.2 Bus IOH = − 5.2 mA, VCC = MIN Terminal VCC = MIN VCC = MIN 0.3 0.5 Bus IOL = 16 mA, IOL = 48 mA, 0.35 0.5 VOL Low-level output voltage II Input current at maximum input voltage Terminal VI = 5.5 V, VCC = MAX 0.2 100 µA IIH High-level input current Terminal and control inputs VI = 2.7 V, VCC = MAX 0.1 20 µA 2.5 3 3.7 VI/O Voltage at GPIB I/O port 2.5 3 3.7 II(bus) = 0 II(bus) = 0 II(bus) = −12 mA IIL Low-level input current Terminal and control inputs VI = 0.5 V, Current into GPIB I/O port Power on VCC = MAX VCC = 0 Short-circuit output current ICC Supply current Bus VCC = MAX No load, 0 POST OFFICE BOX 655303 0 2.5 0.7 2.5 40 −15 −35 −75 −25 −50 −125 55 75 TE and DC low, VCC = MAX • DALLAS, TEXAS 75265 µA −3.2 2.5 −3.2 CI/O GPIB I/O port capacitance VCC = 0 to 5 V, VI/O = 0 to 2 V, f = 1 MHz † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § VOH and IOS apply to 3-state outputs only. 6 −100 −1.3 VI(bus) = 0 to 2.5 V Terminal IOS§ −10 VI(bus) = 2.5 V to 3.7 V VI(bus) = 3.7 V to 5 V VI(bus) = 5 V to 5.5 V Power off V −1.5 VI(bus) = −1.5 V to 0.4 V VI(bus) = 0.4 V to 2.5 V II/O V 30 mA µA mA mA pF 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 switching characteristics over recommended operating free-air temperature range, VCC = 5 V PARAMETER tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output FROM (INPUT) TO (OUTPUT) TEST CONDITIONS Terminal Bus CL = 30 pF, See Figure 1 Bus Terminal CL = 30 pF, See Figure 2 MIN TYP† MAX 10 20 12 20 5 10 7 14 ns ns tPZH tPHZ Output enable time to high level 30 tPZL tPLZ Output enable time to low level Output disable time from low level 20 tPZH tPHZ Output enable time to high level 30 Output disable time from high level Output disable time from high level tPZL Output enable time to low level tPLZ Output disable time from low level † All typical values are at TA = 25°C. UNIT TE or DC Bus (ATN, EOI, REN, IFC, and DAV) TE or DC Terminal CL = 15 pF, See Figure 3 CL = 15 pF, See Figure 4 20 45 25 30 ns ns 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION 5V 200 Ω From (Bus) Output Under Test Test Point CL = 30 pF (see Note A) 480 Ω LOAD CIRCUIT 3V Terminal Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH Bus Output VOH 2.2 V 1V VOH VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION 4.3 V 240 Ω From (Terminal) Output Under Test Test Point CL = 30 pF (see Note A) 3 kΩ LOAD CIRCUIT 3V Bus Input (see Note B) 1.5 V 1.5 V 0V tPLH Terminal Output tPHL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION S1 5V 200 Ω From (Bus) Output Under Test Test Point CL = 15 pF (see Note A) 480 Ω LOAD CIRCUIT 3V Control Input (see Note B) 1.5 V 1.5 V 0V tPZH Bus Output S1 Open tPHZ VOH 90% 2V 0V tPLZ tPZL ≈3.5 V Bus Output S1 Closed 1V 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 3. Bus Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION S1 4.3 V 240 Ω From (Terminal) Output Under Test Test Point CL = 15 pF (see Note A) 3 kΩ LOAD CIRCUIT 3V Control Input (see Note B) 1.5 V 1.5 V 0V tPZH Terminal Output S1 Open tPHZ 90% 1.5 V 0V tPLZ tPZL Terminal Output S1 Closed VOH ≈4 V 1V 0.7 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 4. Terminal Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 TYPICAL CHARACTERISTICS† TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TERMINAL I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 VCC = 5 V TA = 25°C 3.5 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 4 3 2.5 2 1.5 1 0.5 0 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 − 5 − 10 − 15 − 20 − 25 − 30 − 35 IOH − High-Level Output Current − mA − 40 0 30 40 50 10 20 IOL − Low-Level Output Current − mA 60 Figure 6 Figure 5 TERMINAL OUTPUT VOLTAGE vs BUS INPUT VOLTAGE 4 VCC = 5 V No Load TA = 25°C VO − Terminal Output Voltage − V 3.5 3 2.5 2 VIT − VIT + 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VI − Bus Input Voltage − V 1.8 2 Figure 7 † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    
  

 
SLLS019F − JUNE 1986 − REVISED JULY 2004 TYPICAL CHARACTERISTICS† GPIB I/O BUS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT GPIB I/O BUS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 0.6 VOL− Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VCC = 5 V TA = 25°C 3 2 1 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 − 10 − 20 − 30 − 40 − 50 0 − 60 0 IOH − High-Level Output Current − mA 10 20 30 40 50 60 70 80 90 100 IOL − Low-Level Output Current − mA Figure 8 Figure 9 GPIB I/O BUS CURRENT vs VOLTAGE BUS OUTPUT VOLTAGE vs TERMINAL INPUT VOLTAGE 4 2 VCC = 5 V TA = 25°C 1 3 0 I I/O − Current − mA VO − Bus Output Voltage − V VCC = 5 V No Load TA = 25°C 2 1 −1 −2 −3 −4 −5 The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488 -1978 −6 0 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 −7 −2 −1 0 1 2 3 4 5 6 VI/O − Voltage − V VI − Terminal Input Voltage − V Figure 10 Figure 11 † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN75ALS161DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS161 Samples SN75ALS161DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS161 Samples SN75ALS161DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS161 Samples SN75ALS161N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN75ALS161N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of