SN75ALS164DWR

SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 D D D D D D D D D D D 8-Channel Bidirectional Transceiver Designed to Implement Control Bus Interface Designed for Multiple-Controller Systems High-Speed Advanced Low-Power Schottky Circuitry Low-Power Dissipation . . . 46 mW Max Per Channel Fast Propagation Times . . . 20 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . . 650 mV Typ Bus-Terminating Resistors Provided on Driver Outputs No Loading of Bus When Device Is Powered Down (VCC = 0) Power-Up/Power-Down Protection (Glitch Free) DW PACKAGE (TOP VIEW) GPIB I/O Ports SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ NC GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC ATN + EOI REN IFC NDAC NRFD Terminal DAV I/O Ports EOI ATN SRQ NC DC NC – No internal connection NOT RECOMMENDED FOR NEW DESIGNS description The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed, advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS164 provides the complete 16-wire interface for the IEEE 488 bus. The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state) during VCC power-up and power-down transitions for glitch-free operation. The direction of data flow through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard totem-pole output. The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs that present a high impedance to the terminal when disabled. The SN75ALS164 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 CHANNEL IDENTIFICATION TABLE NAME IDENTITY CLASS DC TE SC Direction-Control Talk-Enable System Control Control ATN SRQ REN IFC EOI Attention Service Request Remote Enable Interface Clear End or Identity Bus Management ATN+EOI ATN Logical or EOI Logic DAV NDAC NRFD Data Valid No Data Accepted Not Ready for Data Data Transfer Function Tables RECEIVE/TRANSMIT FUNCTION TABLE CONTROLS SC DC TE BUS-MANAGEMENT CHANNELS ATN† ATN† SRQ REN (controlled by DC) IFC DATA-TRANSFER CHANNELS EOI DAV (controlled by SC) NDAC NRFD (controlled by TE) H H H H H L L L H L L L H L X R T R R T T L H X T R T T R R R T T R T R R T H T T L R R T R R R T T H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI when the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. ATN + EOI FUNCTION TABLE INPUTS EOI OUTPUT ATN + EOI H X H X H H L L L ATN 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 logic symbol† DC TE SC 13 2 1 logic diagram (positive logic) EN1/G4 EN3 ≥1 5 4 ATN DC EN2/G5 TE EN6 SC 16 1 1 EOI 1 23 ≥1 17 6 1 1 REN NRFD 3 1 18 2 1 20 19 10 3 1 21 2 NDAC 8 3 3 DAV 1 22 3 IFC 1 15 2 2 1 2 2 ATN ATN 2 1 16 9 4 7 5 6 ATN ATN + EOI 23 6 SRQ 9 13 ATN + EOI EOI SRQ REN EOI SRQ 17 8 15 10 22 3 21 4 18 7 20 5 19 6 EOI SRQ IFC REN REN DAV NDAC IFC IFC NRFD 1 DAV † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs NDAC NRFD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DAV NDAC NRFD 3 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT VCC VCC 9 kΩ NOM 1.7 kΩ NOM 10 kΩ NOM Input 4 kΩ NOM GND GND Input/Output Port Circuit inside dashed lines is on the driver outputs only. TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS ATN + EOI OUTPUT VCC Req 1.7 kΩ NOM 10 kΩ NOM 8 kΩ VCC 200 kΩ 4.6 kΩ 4 kΩ NOM 4 kΩ NOM Output 1.3 kΩ 2.5 kΩ GND Input/Output Port Driver output Req = 30 Ω NOM Receiver output Req = 110 Ω NOM Circuit inside dashed lines is on the driver outputs only. GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 recommended operating conditions Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX UNIT 4.75 5 5.25 V 2 V Low-level input voltage, VIL High-level output current, IOH Low-level output current, IOL 0.8 Bus ports with 3-state outputs – 5.2 Terminal ports – 800 ATN + EOI – 400 Bus ports 48 Terminal ports 16 ATN + EOI V mA µA mA 4 Operating free-air temperature, TA 0 70 °C electrical characteristics over recommended supply-voltage and operating free-air temperature ranges (unless otherwise noted) PARAMETER VIK Vhys TEST CONDITIONS Input clamp voltage Hysteresis (VT+ – VT–) Bus Terminal VOH‡ High-level output voltage Bus ATN+EOI Terminal VOL Low-level output voltage MIN II = –18 mA Bus ATN+EOI Terminal§ TYP† MAX UNIT – 0.8 –1.5 V 0.4 0.65 IOH = – 800 µA IOH = – 5.2 mA 2.7 3.5 2.5 3.3 IOH = – 400 µA IOL = 16 mA 2.7 IOL = 48 mA IOL = 4 mA 0.3 0.5 0.5 VI = 5.5 V VI = 5.5 V 0.2 ATN, EOI IIH High-level g input current Terminal control VI = 2.7 V 0.1 ATN, EOI VI = 2.7 V Terminal control VI = 0.5 V ATN, EOI VI = 0.5 V VI/O(b I/O(bus)) Voltage at bus port Current into bus port –10 IOS Short-circuit output current –100 II(bus) = 0 II(bus) = –12 mA Driver disabled VCC = 0, 2.5 3.0 3.7 –1.5 0 VI(bus) = 2.5 V to 3.7 V 0 2.5 – 40 – 35 – 75 Bus – 25 – 50 –125 –10 µA mA –100 No load, TE, DC, and SC low 55 VCC = 0 to 5 V, VI/O = 0 to 2 V, f = 1 MHz 30 • DALLAS, TEXAS 75265 mA 2.5 0.7 VI(bus) = 0 to 2.5 V ATN + EOI V – 3.2 + 2.5 – 3.2 –15 POST OFFICE BOX 655303 µA µ –1.3 Terminal ICC Supply current CI/O(bus) Bus-port capacitance † All typical values are at VCC = 5 V, TA = 25°C. ‡ VOH applies for 3-state outputs only. § Except ATN and EOI terminals. µA µ – 500 VI(bus) = 3.7 V to 5 V VI(bus) = 5 V to 5.5 V Power off 20 µA 40 Driver disabled Power on 100 200 VI(bus) = –1.5 V to 0.4 V VI(bus) = 0.4 V to 2.5 V II/O(bus) V 0.4 Input current at maximum input voltage Low-level input current V 0.35 II IIL V 75 mA pF 5 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 switching characteristics over recommended operating free-air temperature range, VCC = 5 V PARAMETER tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output FROM (INPUT) TO (OUTPUT) Terminal Bus Bus Terminal TEST CONDITIONS CL = 30 pF, See Figure 1 CL = 30 pF,, See Figure 2 MIN TYP MAX 10 20 12 20 5 10 7 14 UNIT ns ns tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output Terminal ATN or Terminal EOI ATN+EOI CL = 15 pF, See Figure 3 3.5 10 ns tPHL Propagation delay time, high-to-low-level output Terminal ATN or Terminal EOI ATN+EOI CL = 15 pF, See Figure 3 7 15 ns TE DC, TE, DC or SC Bus (ATN, EOI, REN, IFC, and REN IFC DAV) tPZH tPHZ Output enable time to high level tPZL tPLZ Output enable time to low level Output disable time from low level 20 tPZH tPHZ Output enable time to high level 30 tPZL tPLZ Output enable time to low level 6 Output disable time from high level Output disable time from high level 30 TE DC, TE, DC or SC Terminal Output disable time from low level CL = 15 pF,, See Figure 4 CL = 15 pF, See Figure 5 20 45 25 30 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION 5V 200 Ω From (bus) Output Under Test Test Point CL = 30 pF (see Note A) 480 Ω LOAD CIRCUIT Terminal Input 3V 0V tPHL tPLH Bus Output 1.5 V 1.5 V (see Note B) VOH 2.2 V 1.0 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms 4.3 V 240 Ω From (terminal) Output Under Test Test Point CL = 30 pF (see Note A) 3 kΩ LOAD CIRCUIT 3V Bus Input 1.5 V 1.5 V (see Note B) tPLH Terminal Output 0V tPHL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION Test Point VCC 2 kΩ Terminal ATN + EOI 3V 1.5 V 1.5 V 0V tPLH From ATN + EOI ATN + EOI CL (see Note A) tPHL 1.5 V 1.5 V VOL (see Note B) VOLTAGE WAVEFORMS LOAD CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064 Figure 3. ATN + EOI Load Circuit and Voltage Waveforms 8 VOH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION S1 5V 200 Ω From (bus) Output Under Test Test Point CL = 15 pF (see Note A) 480 Ω LOAD CIRCUIT 3V Control Input tPZH Bus Output S1 Open 1.5 V (see Note B) 0V tPHZ 90% 2V tPZL Bus Output S1 Closed 1.5 V VOH ≈0V tPLZ 1V ≈ 3.5 V 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 4. Bus Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION S1 4.3 V 240 Ω From (terminal) Output Under Test Test Point CL = 15 pF (see Note A) 3 kΩ LOAD CIRCUIT 3V Control Input 1.5 V (see Note B) 1.5 V 0V tPZH Terminal Output S1 Open tPZL Terminal Output S1 Closed tPHZ 90% VOH 1.5 V ≈0V tPLZ 1V ≈4V 0.7 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 5. Terminal Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 TYPICAL CHARACTERISTICS TERMINAL HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TERMINAL LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 3.5 VOL – Low-Level Output Voltage – V VCC = 5 V TA = 25°C 3 2.5 2 1.5 1 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0.5 0 0 0 0 – 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40 IOH – High-Level Output Current – mA 30 40 50 10 20 IOL – Low-Level Output Current – mA Figure 6 60 Figure 7 TERMINAL OUTPUT VOLTAGE vs BUS INPUT VOLTAGE 4 VCC = 5 V No Load TA = 25°C 3.5 VO – Output Voltage – V VOH – High-Level Output Voltage – V 4 3 2.5 2 VT + VT – 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VI – Input Voltage – V 1.6 1.8 2 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75ALS164 OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS022C – JUNE 1986 – REVISED MAY 1998 TYPICAL CHARACTERISTICS BUS HIGH-LEVEL OUTPUT VOLTAGE vs BUS HIGH-LEVEL OUTPUT CURRENT BUS LOW-LEVEL OUTPUT VOLTAGE vs BUS LOW-LEVEL OUTPUT CURRENT 0.6 4 VOL– Low-Level Output Voltage – V VOH – High-Level Output Voltage – V VCC = 5 V TA = 25°C 3 2 1 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 0 – 10 – 20 – 30 – 40 – 50 0 – 60 10 20 30 Figure 9 70 80 90 100 BUS CURRENT vs BUS VOLTAGE 4 3 VCC = 5 V No Load TA = 25°C 2 VCC = 5 V TA = 25°C 1 I I/O(bus) – Bus Current – mA II/O(bus) VO – Output Voltage – V 60 Figure 10 BUS OUTPUT VOLTAGE vs TERMINAL INPUT VOLTAGE 3 2 1 0 –1 –2 –3 –4 –5 The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488-1978 –6 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 –7 –2 –1 0 1 2 3 4 VI/O(bus) – Bus Voltage – V VI – Input Voltage – V Figure 11 12 50 IOL – Low-Level Output Current – mA IOH – High-Level Output Current – mA 0 0.9 40 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 6 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN75ALS164DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS164 SN75ALS164DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS164 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of