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SN75LVPE801
SLLSEW8 – SEPTEMBER 2016
SN75LVPE801 8.0 Gbps SATA Express Equalizer and Redriver
1 Features
3 Description
•
•
•
•
•
The SN75LVPE801 is a versatile single channel,
SATA Express signal conditioner supporting data
rates up to 8 Gbps. The device supports SATA Gen
1, 2, and 3 specifications as well as PCIe 1.0, 2.0,
and 3.0. The SN75LVPE801 operates from a single
3.3-V supply and has 100-Ω line termination with selfbiasing feature, making the device suitable for AC
coupling. The inputs incorporate an out-of-band
(OOB) detector, which automatically squelches the
output when the input differential voltage falls below
threshold while maintaining a stable common-mode
voltage. The device is also designed to handle
spread spectrum clocking (SSC) transmission per
SATA standard.
1
•
•
•
•
•
•
•
•
SATA Express Support
Selectable Equalization and De-Emphasis
Hot Plug Capable
Receiver Detect and OOB Support
Multirate Operation
– SATA: 1.5 Gpbs, 3.0 Gpbs, 6.0 Gpbs
– PCIe: 2.5 Gbps, 5.0 Gbps, 8.0 Gbps
Suitable to Receive 8.0 Gbps Data Over Up to 40
Inches (1.0 Meter) of FR4 PC Board
Compensates Up to 14-dB Loss on the Receive
Side and 1.2dB Loss on the Transmit Side at
3 GHz
Integrated Output Squelch
Temperature range 0°C – 85°C
Auto Low Power Feature Lowers Power by > 90%
– < 100 mW (Active Mode, Typical)
– < 11 mW (Auto Low Power Mode, Typical)
Single 3.3-V Supply
High Protection Against ESD Transient
– HBM: 6 kV
– CDM: 1.5 kV
Ultra-Small Footprint: 2 mm × 2 mm WSON
Package
The SN75LVPE801 handles interconnect losses at its
input with selectable equalization settings that can be
programmed to match the loss in the channel. For
data rates of 8 Gbps and lower the SN75LVPE801
equalizes signals for a span of up to 50 inches of
FR4 board material. For data rates of 8 Gbps the
device compensates up to 40 in of FR4 material. The
equalization level is controlled by the setting of the
signal control pin EQ.
Device Information(1)
PART NUMBER
SN75LVPE801
PACKAGE
WSON (8)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
Notebooks
Desktops
Docking Stations
Servers
Workstations
SATA Express Reference Schematic
Connector
Host Controller
Device
VCC
1
220nF
2
3
220nF
4
VCC
DE
RX+
TX+
RX-
TX-
EQ
GND
8
200nF
7
6
200nF
5
SN75LVPE801
330
330
VCC
8
220nF
7
6
220nF
5
DE
VCC
TX+
RX+
TX-
RX-
GND
EQ
1
2
470nF
200nF
3
4
200nF
470nF
SN75LVPE801
330
330
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVPE801
SLLSEW8 – SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 13
10 Applications and Implementation...................... 14
10.1 Application Information.......................................... 14
10.2 Typical SATA Applications.................................... 14
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
12.2 Layout Example .................................................... 24
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
13.6
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
9.1 Overview ................................................................. 10
9.2 Functional Block Diagram ....................................... 10
4 Revision History
2
DATE
REVISION
NOTES
September 2016
*
Initial release.
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5 Description (continued)
Two de-emphasis levels can be selected on the transmit side to provide 0 dB or 1.2 dB of additional highfrequency loss compensation at the output.
The device is hot-plug capable(1) preventing device damage under device hot-insertion such as async signal plug
and removal, unpowered plug and removal, powered plug and removal, or surprise plug and removal.
(1) Requires use of AC coupling capacitors at differential inputs and outputs.
6 Pin Configuration and Functions
DRF Package
8-Pin WSON
Top View
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
HIGH SPEED DIFFERENTIAL I/O
RX+
2
I
RX–
3
I
TX+
7
O
TX–
6
O
Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias by
dual termination resistor circuit.
Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual
termination resistor circuit.
CONTROL PINS
EQ
4
I
Selects equalization settings per Table 1. Internally tied to GND.
DE
8
I
Selects de-emphasis settings per Table 1. Internally tied to GND.
POWER
VCC
1
P
Positive supply must be 3.3 V ±10%
GND
5
G
Supply ground
(1)
G = Ground, I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC (2)
Voltage
(2)
MAX
UNIT
4
V
V
Differential I/O
–0.5
4
Control I/O
–0.5
VCC + 0.5
–65
150
Storage temperature, Tstg
(1)
MIN
–0.5
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground pin.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
UNIT
±6000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
VCC
Supply voltage
Coupling capacitor
TA
Operating free-air temperature
MIN
TYP
MAX
3
3.3
3.6
V
75
100
200
nF
85
°C
0
UNIT
7.4 Thermal Information
SN75LVPE801
THERMAL METRIC (1)
DRF (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
97.8
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
81.9
°C/W
RθJB
Junction-to-board thermal resistance
65.6
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
65.6
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
19.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DEVICE PARAMETERS
ICCMax-s
Active mode supply current
EQ/DE = NC, K28.5 pattern at 8 Gbps, VID = 700 mVpp
29
40
ICCPS
Auto power save mode ICC
When auto low power conditions are met
3.3
5.9
Maximum data rate
mA
mA
8
Gbps
OOB
VOOB
Input OOB threshold
90
mVpp
DVdiffOOB
OOB differential delta
F = 750 MHz
50
70
25
mV
DVCMOOB
OOB common-mode delta
50
mV
CONTROL LOGIC
VIH
High-level input voltage
For all control pins
VIL
Low-level input voltage
VINHYS
Input hysteresis
IIH
High-level input current
VIH = VCC (DE/EQ)
IIL
Low-level input current
VIL = 0V (DE/EQ)
1.4
V
0.5
V
115
mV
20
μA
10
μA
RECEIVER AC/DC
ZDIFFRX
Differential input impedance
85
ZSERX
Single-ended input impedance
40
VCMRX
Common-mode voltage
RLDiffRX
RXDiffRLSlope
RLCMRX
Differential mode return loss
(RL)
Differential mode RL slope
Common-mode return loss
IBRX
Differential input voltage PP
Impedance balance
Ω
115
Ω
1.7
f = 150 MHz to 300 MHz
20
26
f = 300 MHz to 600 MHz
18
22
f = 600 MHz to 1.2 GHz
14
17
f = 1.2 GHz to 2.4 GHz
10
12
f = 2.4 GHz to 3 GHz
8
12
f = 3 GHz to 5 GHz
6
11
f = 300 MHz to 6 GHz (see Figure 6)
V
dB
–13
f = 150 MHz to 300 MHz
8
9
f = 300 MHz to 600 MHz
14
17
f = 600 MHz to 1.2 GHz
12
18
f = 1.2 GHz to 2.4 GHz
8
10
f = 2.4 GHz to 3 GHz
6
8
6
8.5
f = 3 GHz to 5 GHz
VdiffRX
100
f = 1.5 GHz and 3 GHz
120
dB/dec
dB
1600
f = 150 MHz to 300 MHz
30
41
f = 300 MHz to 600 MHz
34
41
f = 600 MHz to 1.2 GHz
24
33
f = 1.2 GHz to 2.4 GHz
14
24
f = 2.4 GHz to 3 GHz
12
26
f = 3 GHz to 5 GHz
6
18
f = 5 GHz to 6.5 GHz
5
18
100
mVpp
dB
TRANSMITTER AC/DC
ZdiffTX
Pair differential impedance
85
ZSETX
Single-ended input impedance
40
VTXtrans
Sequencing transient voltage
Transient voltages on the serial data bus during power
sequencing (lab load)
–1.2
122
Ω
0.3
1.2
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Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
RLDiffTX
Differential mode return loss
TEST CONDITIONS
MIN
f = 150 MHz to 300 MHz
14
22
f = 300 MHz to 600 MHz
12
21
f = 600 MHz to 1.2 GHz
11
18
f = 1.2 GHz to 2.4 GHz
10
14
f = 2.4 GHz to 3 GHz
10
14
f = 3 GHz to 5 GHz
TXDiffRLSlope
RLCMTX
IBTX
Differential mode RL slope
Common-mode return loss
Impedance balance
8
f = 300 MHz to 3 GHz (see Figure 6)
Differential output voltage
swing
VCMTX
TX AC CM voltage
14
dB/dec
f = 150 MHz to 300 MHz
10
f = 300 MHz to 600 MHz
9
16
f = 600 MHz to 1.2 GHz
8
13.5
f = 1.2 GHz to 2.4 GHz
6
8.5
f = 2.4 GHz to 3 GHz
5
8
f = 3 GHz to 5 GHz
4
7
f = 150 MHz to 300 MHz
34
38
f = 300 MHz to 600 MHz
32
38
f = 600 MHz to 1.2 GHz
24
33
f = 1.2 GHz to 2.4 GHz
18
25
f = 2.4 GHz to 3 GHz
18
25
f = 3 GHz to 5 GHz
12
21
8
21
400
650
900
15
50
mVpp
f = 3 GHz (under no interconnect loss)
At 1.5 GHz
VCMAC_TX
UNIT
dB
–13
f = 5 GHz to 6.5 GHz
DiffVppTX
TYP MAX
20
dB
dB
mVpp
At 3 GHz
10
26
dBmV
(rms)
At 6 GHz
12
30
dBmV
(rms)
Common-mode voltage
1.70
V
TRANSMITTER JITTER 3 Gbps
DJTX
Residual deterministic jitter
VID = 500 mVpp, UI = 333 ps, K28.5 control character,
see Figure 7
0.12
0.19
RJTX
Random jitter
VID = 500 mVpp, UI = 333 ps, K28.7 control character,
see Figure 7
1
2
UIpp
ps-rms
TRANSMITTER JITTER 6 Gbps
DJTX
Residual deterministic jitter
VID = 500 mVpp, UI = 167 ps, K28.5 control character,
see Figure 7
0.12
0.34
RJTX
Random jitter
VID = 500 mVpp, UI = 167 ps, K28.7 control character,
see Figure 7
0.95
2
UIpp
ps-rms
TRANSMITTER JITTER 8 Gbps
DJTX
Residual deterministic jitter
VID = 500 mVpp, UI = 125 ps, K28.5 control character,
see Figure 7
4.7
5.76
8.7
(ps) (DD)
RJTX
Random jitter
VID = 500 mVpp, UI = 125 ps, K28.5 control character,
see Figure 7
0.93
0.94
0.95
ps-rms
DJTX
Residual deterministic jitter
VID = 500 mVpp, UI = 125 ps, K28.7 control character,
see Figure 7
0.8
1.24
2.7
(ps) (DD)
RJTX
Random jitter
VID = 500 mVpp, UI = 125 ps, K28.7 control character,
see Figure 7
0.9
0.92
0.93
ps-rms
6
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7.6 Timing Requirements
MIN
TYP MAX
UNIT
DEVICE PARAMETERS
tPDelay
Propagation delay
Measured using K28.5 pattern (see Figure 1)
AutoLPENTRY
Auto low power entry time
Electrical idle at input (see Figure 3)
275
11
350
ps
AutoLPEXIT
Auto low power exit time
After first signal activity (see Figure 3)
33
50
ns
tOOB1
OOB mode enter
See Figure 2
1
5
ns
tOOB2
OOB mode exit
See Figure 2
1
5
ns
75
ps
30
ps
58
85
ps
2
15
ps
6%
20%
1%
10%
47.5
%
48.3
%
1.5%
3%
μs
OOB
RECEIVER AC/DC
t20-80RX
Rise and fall time
Rise times and fall times measured between 20% and
80% of the signal. SATA 8 Gbps speed measured 1" from
device pin.
tskewRX
Differential skew
Difference between the single-ended mid-point of the RX+
signal rising and falling edge, and the single-ended midpoint of the RX– signal falling and rising edge.
62
TRANSMITTER AC/DC
t20-80TX
Rise and fall time
Rise times and fall times measured between 20% and
80% of the signal. At 8 Gbps under no load conditions
measured at the pin.
tskewTX
Differential skew
Difference between the single-ended mid-point of the TX+
signal rising edge and falling edge, and the single-ended
mid-point of the TX– signal falling edge and rising edge,
D1, D0 = VCC
txR/Flmb
TX rise and fall imbalance
At 8 Gbps
txAmplmb
TX amplitude imbalance
44
TRANSMITTER JITTER
46.5
%
Rise and Fall time
Rise and Fall mismatch
IN
tPDelay
tPDelay
OUT
Figure 1. Propagation Delay Timing Diagram
IN+
Vcm
50 mV
INtOOB2
tOOB1
OUT+
Vcm
OUT-
Figure 2. OOB Enter and Exit Timing
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RX1, 2P
VCMRX
RX1, 2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY
Power Saving
Mode
Figure 3. Auto Low Power Mode Entry and Exit Timing
7.7 Typical Characteristics
50
35
8" EQ = 1, DE = 0
16" EQ = 1, DE = 0
24" EQ = 1, DE = 0
32" EQ = 1, DE = 1
36" EQ = 1, DE = 1
40
35
30
Deterministic Jitter (pspp)
Deterministic Jitter (psPP)
45
30
25
20
15
10
25
20
15
10
5
5
0
1
2
3
4
5
Data Rate (Gbps)
6
7
0
300
400
D001
A function of input trace length of 4 mil FR-4
xx
Figure 4. Deterministic Jitter vs Data Rate
8
8
1.5 Gbps
3.0 Gbps
6.0 Gbps
8.0 Gpbs
500
600
700
Input Voltage (mV)
800
900
D002
Function of data rate after equalizing for 32" of input
FR = 4 trace, EQ = 1, DE = 1
Figure 5. Deterministic Jitter vs Launch Amplitude
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8 Parameter Measurement Information
-RL
dB
Rx0.
TX
0.3
4
Log Frequency - GHz
6
Figure 6. TX, RX Differential Return Loss Limits
Jitter
Measurement
CP
40" 4mil
Stripline
AWG
4" 4 mil Stripline
Figure 7. Jitter Measurement Test Condition
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9 Detailed Description
9.1 Overview
The SN75LVPE801 is a single channel equalizer and redriver. The device operates over a wide range of
signaling rates, supporting operation from DC to 8 Gbps. The wide operating range supports SATA Gen 1,2,3
(1.5 Gbps, 3.0 Gbps, and 6.0 Gbps respectively) as well as PCI Express 1.0, 2.0, 3.0 (2.5 Gbps, 5.0 Gbps, and
8.0 Gbps). The device also supports SATA Express (SATA 3.2) which is a form factor specification that allows
for SATA and PCI Express signaling over a single connector.
9.2 Functional Block Diagram
VCC[1]
GND[5]
VBB = 1.7 V TYP
LVPE801
RT
RX+ [2]
TX+ [7]
RT
Equalizer
Driver
RX– [3]
TX– [6]
OOB
Detect
CTRL
EQ
[4]
DE
[8]
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9.3 Feature Description
9.3.1 SATA Express
SATA Express (sometimes SATAe) is an electro-mechanical standard that supports both SATA and PCI Express
storage devices. SATAe is standardized in the SATA 3.2 standard. The standard is concerned with providing a
smooth transition from SATA to PCIe storage devices. The standard provides for standardized cables and
connectors, and muxes the PCIe and SATA lanes at the host side so that either SATA compliant or PCIe
compliant devices may operate with a host.
SATAe provides support for SATA1, SATA2 and SATA3 devices (operating from 1.5 Gbps to 6.0 Gbps), as well
as PCIe1, PCIe2 and PCIe3 devices (operating from 2.5 Gbps to 8.0 Gbps).
The SN75LVPE801 provides for equalization and re-drive of a single channel input signal complying with any of
the SATA or PCIe standards available with SATAe.
The SATAe standard provides for a mechanism for a host to recognize and detect whether a SATA or PCIe
device is plugged into the host. See the Typical SATA Applications section for the details of the SATA Express
Interface Detect operation.
9.3.2 Receiver Termination
The receiver has integrated terminations to an internal bias voltage. The receiver differential input impedance is
nominally 100 Ω, with a ±15% variation.
For PCI Express compatibility it is necessary to include 330 Ω pull-down resistors between the connector and the
AC capacitors, refer to Figure 24 for more information.
9.3.3 Receiver Internal Bias
The SN75LVPE801 receiver is internally biased to 1.7 V, providing support for AC coupled inputs.
10
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Feature Description (continued)
9.3.4 Receiver Equalization
The SN75LVPE801 incorporates programmable equalization. The EQ input controls the level of equalization that
is used to open the eye of the received input signal. If the EQ input is left open, or pulled LO, 8 dB (at 4 GHz) of
equalization is applied. When the EQ input is HIGH, the equalization is set to 16 dB (again at 4 GHz).Table 1
shows the equalization values discussed.
Table 1. EQ and DE Settings
EQUALIZATION
dB (at 8 Gbps)
DE
0 (default)
8
0 (default)
0
1
16
1
–1.2
EQ
DE-EMPHASIS
9.3.5 OOB/Squelch
The SN75LVPE801 receiver incorporates an Out-Of-Band (OOB) detection circuit in addition to the main signal
chain receiver. The OOB detector continuously monitors the differential input signal to the device. The OOB
detector has a 50-mVpp entry threshold. If the differential signal at the receiver input is less than the OOB entry
threshold, the device transmitter transitions to squelch. The SN75LVPE801 enters squelch within 5 ns of the
input signal falling below the OOB entry threshold. The SN75LVPE801 continues to monitor the input signal while
in squelch. While in squelch, if the OOB detector determines that the input signal now exceeds the 90 mVpp exit
threshold, the SN75LVPE801 exits squelch within 5 ns. See Figure 8.
IN+
Vcm
50 mV
INtOOB2
tOOB1
OUT+
Vcm
OUT-
Figure 8. OOB Enter and Exit Timing
Receiver Input Termination is Disabled
When the SN75LVPE801 enters squelch state the transmitter output is squelched. The transmitter non-inverting
(TX+) output and the transmitter inverting output (TX-) are both driven to the transmitter nominal common mode
voltage which is 1.7 V .
9.3.6 Auto Low Power
The SN75LVPE801 also includes an Auto Low Power Mode (ALP). ALP is entered when the differential input
signal has been less than 50 mV for > 10 µs. The device enters and exits Low Power Mode by actively
monitoring the input signal level. In this state the device selectively shuts off internal circuitry to lower power by >
90% of its normal operating power. While in ALP mode the device continues to actively monitor input signal
levels. When the input signal exceeds the OOB exit threshold level, the device reverts to the active state. Exit
time from Auto Low Power Mode is < 50 ns (max). See Figure 9.
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RX1, 2P
VCMRX
RX1, 2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY
Power Saving
Mode
Figure 9. Auto Low Power Mode Entry and Exit Timing
9.3.7 Transmitter Output Signal
The SN75LVPE801 differential output signal is 650 mVpp when de-emphasis is disabled (DE input is open or
pulled low).
9.3.8 Transmitter Common Mode
The SN75LVPE801 transmitter common mode output is set to 1.7 V.
9.3.9 De-Emphasis
The SN75LVPE801 transmitter incorporates programmable de-emphasis to provide signal conditioning to offset
the anticipated channel losses based on expected use cases for the device. Figure 10 shows an example of a
SATA host communicating with a SATA device through a backplane. In such a use case, an SN75LVPE801
would be located at the end of the interconnect channels (i.e. at the device end for the host TX channel, and at
the host end for the host RX channel. These locations are selected based on the signal conditioning that is
incorporated into the SN75LVPE801. The SN75LVPE801 provides up to 16 dB of equalization, while supporting
up to 1.2 dB of de-emphasis. The optimum location would therefore be at the end of the interconnect, allowing
the receiver equalization to address the majority of the channel loss, while the de-emphasis would be employed
to overcome the much shorter interconnect length.
The DE input controls the amount of de-emphasis that is applied at the transmitter output. The de-emphasis
selections are shown in Table 1. When DE is left open, or pulled low, de-emphasis shall be off. When DE is
pulled HIGH, 1.2 dB of de-emphasis is used at the transmitter output.
Figure 10. Trace Length Example
12
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9.3.10 Transmitter Termination
The SN75LVPE801 transmitter includes integrated terminations. The receiver differential output impedance is
nominally 100 Ω, with a ≤ 22% variation.
9.4 Device Functional Modes
9.4.1 Active
Active mode is the normal operating mode. When power is applied to the device, and the differential input signal
to the receiver is greater than 90 mVpp, the device is in active mode and meets all the specifications in the data
sheet.
9.4.2 Squelch
When the device is powered, and the differential input signal to the receiver is less than 50 mVpp, the device is in
squelch mode. In squelch mode the transmitter outputs are both set to VCMTX or 1.7 V.
9.4.3 Auto Low Power
When the device is powered and the differential input signal to the receiver has been less than 50 mVpp for
greater than 10 ns, the device transitions to Auto Low Power (ALP) mode. In ALP, the transmitter outputs are
both set to VCMTX. In addition, while in ALP, the device shuts off internal circuitry to lower power to less than
10% of the power in the Active mode.
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN75LVPE801 can be used for SATA applications as well as SATA Express applications. The device
supports SATA Gen1, Gen2, and Gen3 applications with data rates from 1.5 to 8 Gbps. The built-in equalization
circuits provide up to 16 dB of equalization at 4 GHz. This equalization can support SATA GEN2 (3 Gbps)
applications over up to 50 inches of FR-4 material. The same 16 dB equalizer is suited to SATA Gen3 (8 Gbps)
applications up to 40 inches of FR4.
In addition to SATA applications, the SN75LVPE801 can support SATA Express applications. SATA Express
provides a standardized interface to support both SATA (Gen1, Gen2, and Gen3) and PCI Express (PCIe 1.0,
2.0 and 3.0).
All applications of the SN75LVPE801 share some common applications issues. For example, power supply
filtering, board layout, and equalization performance with varying interconnect losses. Other applications issues
are specific, such as implementing receiver detection for SATA Express applications. The Typical Application
examples demonstrate common implementations of the SN75LVPE801 supporting SATA, as well as SATA
Express applications.
10.2 Typical SATA Applications
Copyright © 2016, Texas Instruments Incorporated
(1)
Place supply caps close to the device pin
(2)
EQ and DE selection at 8 dB and 0 dB respectively
(3)
Actual EQ and DE settings depend on the device placement relative to the host and SATA connector
Figure 11. Typical Device Implementation
14
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Typical SATA Applications (continued)
10.2.1 Design Requirements
DESIGN PARAMETERS
VALUE
SATA Signaling Rate
1.5 - 6.0 Gbps
AC Coupling Capacitance
10 nF
Interconnect Characteristic Impedance
100 Ohms
Interconnect Length
Up to 50" FR4 for SATA Gen2
Up to 40" FR4 for SATA Gen3
Termination Resistance
100 Ohms differential integrated into TX and RX
10.2.2 Detailed Design Procedure
Figure 11 shows a typical SATA Application. The SATA host, which may be a notebook or desktop,
communicates with a SATA sink, which could be a SSD mass storage device. The SATA host and sink
communicate over a backplane differential pair, or a SATA cable. When using the SN75LVPE801 as an
equalizer/redriver, the designer would optimally place the SN75LVPE801 close to the end of the interconnect.
The SN75LVPE801 provides up to 16 dB of equalization, and up to 1.2 dB of de-emphasis. Placing the
SN75LVPE801 close to the end of the interconnect allows the device equalizer to address the majority of the
high frequency losses introduced in the channel.
Ensure that the channel loss for the interconnect material and length is matched reasonably well to the
selectable equalization and de-emphasis settings available on the SN75LVPE801. The table above provides an
estimate of the amount of FR4 material that could be used as a function of the signal rate. In any case, channel
modeling would be prudent to ensure that the SATA host, interconnect, SATA equalizer/re-driver, and SATA Sink
can establish and maintain a low BER link.
The AC coupling capacitors of 10 nF are chosen to comply with the SATA standard (< 12 nF)
Often a designer may not be sure whether a signal conditioning device like the SN75LVPE801 is needed in their
specific application. The SN75LVPE801 allows the user to take the guess work of using a signal conditioning
device in a SATA link. With the SN75LVPE801 the designer has the option to use or remove the device based
on signal conditioning needs. Figure 12 shows guidelines that could be used to allow in situ testing when a board
is available. The designer would start with 0 Ω resistors in place to determine if the eye quality at the end of the
link is satisfactory. If the eye opening is not sufficient, the 0 Ω resistors could be replaced with the
SN75LVPE801.
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Figure 12. Implementation Guideline
To demonstrate the effectiveness of the SN75LVPE801 signal conditioning for varied configurations that may be
encountered, Figure 13 is used as a reference. A Gen3, 6 Gbps SATA host communicates with a sink located at
point B. The host and sink are separated by “X+Y” inches, where X represents the distance between the host
and the SN75LVPE801, while Y represents the distance between the SN75LVPE801 and the sink. The
Application Curves are for a 6-Gbps K28.5 pattern, with VCC = 3.3 V and at an ambient temperature of 25°C.
DE EQ
A
SATA 6G
Host
X
(4 mil)
B
801
Y
(4 mil)
Figure 13. Test Points
16
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10.2.3 Application Curves
All graphs at 6 Gbps
DE = 1
EQ = 0
DE = 1
EQ = 0
Figure 14. Eye Pattern at A → X = 8”; Y = 2”
Figure 15. Eye Pattern at B → X = 8”; Y = 2”
DE = 1
EQ = 0
DE = 1
Figure 16. Eye Pattern at A → X = 16”; Y = 2”
DE = 1
EQ = 0
Figure 17. Eye Pattern at B → X = 16”; Y = 2”
DE = 1
Figure 18. Eye Pattern at A → X = 24”; Y = 2”
EQ = 0
EQ = 0
Figure 19. Eye Pattern at B→ X = 24”; Y = 2”
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DE = 1
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EQ = 1
DE = 1
Figure 20. Eye Pattern at A → X = 32”; Y = 2”
DE = 1
EQ = 1
18
Figure 21. Eye Pattern at B → X = 32”; Y = 2”
DE = 1
Figure 22. Eye Pattern at A → X = 40”; Y = 2”
EQ = 1
EQ = 1
Figure 23. Eye Pattern at B → X = 40”; Y = 2”
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10.2.4 SATA Express Applications
Connector
Host Controller
Device
VCC
1
220nF
2
3
220nF
4
VCC
DE
RX+
TX+
RX-
TX-
EQ
GND
8
200nF
7
6
200nF
5
SN75LVPE801
330
330
VCC
8
220nF
7
6
5
220nF
DE
VCC
TX+
RX+
TX-
RX-
GND
EQ
1
2
470nF
200nF
3
4
200nF
470nF
SN75LVPE801
330
330
Copyright © 2016, Texas Instruments Incorporated
Figure 24. SN75LVPE801 SATA Express Reference Schematic
EQ: 8 dB when Floated, DE: 0 dB when Floated
10.2.4.1 Design Requirements
DESIGN PARAMETERS
VALUE
SATA Express Signaling Rate
1.5 - 8.0 Gbps
AC Coupling Capacitance
200 - 220 nF
Interconnect Characteristic Impedance
100 Ω
Interconnect Length
Up to 50" FR4 for SATA Gen2
Up to 40" FR4 for SATA Gen3
Receiver pull-down terminations
330 Ω
Termination Resistance
100 Ohms differential integrated into TX and RX
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10.2.4.2 Detailed Design Procedure
Figure 24 is a reference schematic of a SATAe implementation using the SN75LVPE801. With a SATAe design,
both SATA and PCI Express must be supported. SATAe supports both cabled and direct connections. Using a
cabled application as an example, the SATAe power connector includes an Interface Detect (IFDet, power
connector pin P4) signal that indicates whether a SATA client or a PCIe client is connected.
When the SATAe host determines that a PCIe client is connected, the SATAe host performs receiver detection.
Receiver detection determines the presence of a client by detecting the load impedance. The transmitter
performs a common mode voltage shift, and measures the rate at which the voltage at the transmitter output
changes. The rate of change indicates if a client is present (fast charging when a low impedance load is present,
or slow charging when the load is open or high impedance). With the implementation in Figure 24, 330-Ω
pulldowns have been inserted between the host and the SN75LVPE801. The pulldown resistors indicate to the
host that a client is present. While an actual client would be expected to have an active load of 50 Ω single
ended, the 330 Ω is chosen here to meet two requirements. The 330 Ω is low enough to force the SATAe host to
decide that a receiver is present, while also high enough to only marginally affect the load when the
SN75LVPE801 is active, and presenting a 50-Ω load. With the 50 Ω and 330 Ω are both present, the parallel
combination of 43 Ω is satisfactory for most applications.
Assuming that the SATAe host has detected (via IFDet) that a SATA client is present, the SATAe host
communicates with the client via the SN75LVPE801. The SATA standard does not have a receiver detection
mode as is present in PCIe. A SATA host does use OOB signaling to communicate identification information. The
SN75LVPE801 incorporates an OOB detector in order to support OOB signaling through the device. The OOB
detector drives a squelch circuit on the SN75LVPE801 output transmitter. (See OOB/Squelch for more details on
the OOB/Squelch circuitry.)
Returning again to Figure 24, we see 200-nF AC coupling capacitors on the device or client side of the interface.
These capacitors allow interfacing to both SATA and PCIe clients. In the case of a PCIe client, the 200 nF is
within the acceptable range for all PCIe devices. When a SATA client is present, the 200 nF capacitor has little
effect on the overall link, as it appears in series with the 12-nF (max) AC coupling capacitor incorporated into the
SATA client. The 200 nF in series with the 12 nF presents an effective capacitance of 11.3 nF, as expected less
than the 12-nF maximum permitted.
The physical placement of the resistors on the high-speed transmission lines can be made as not to create a
stub on the transmission line by using resistors with the 0201 package size, an example is provided in Figure 25.
SN75LVPE801
0201 Package Size
300-W Resistor
Rx +/-
TRACE
VIA to GND
Figure 25. Resistor Placement to Avoid Stub (All Dimensions in mm)
20
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10.2.4.3 Application Curve
Eye-diagrams were taken on the SN75LVPE801 configured as in Figure 24 above. Testing was performed at a
PCIe 3.0 speed of 8Gbps.
Figure 26. SN75LVPE801 8-Gbps Eye-Diagram
10.2.5 PCIe Applications
PCIe-only applications are implemented in a manner very similar to SATA Express applications as covered in
Detailed Design Procedure. Looking at Figure 27, and comparing it to the SATA Express application in Figure 24,
a single change is noted. For PCIe applications the 220 nF AC-coupling capacitors on the Host-to-Device link are
relocated from the Device side of the connector to the Host side. No other changes are required.
Connector
VCC
Host Controller
Device
1
220nF
2
3
220nF
4
VCC
DE
RX+
TX+
RX-
TX-
EQ
GND
8
220nF
7
6
220nF
5
SN75LVPE801
330
330
VCC
8
220nF
7
6
220nF
5
DE
VCC
TX+
RX+
TX-
RX-
GND
EQ
1
2
470nF
200nF
3
4
200nF
470nF
SN75LVPE801
330
330
Copyright © 2016, Texas Instruments Incorporated
Figure 27. SN75LVPE801 PCI-Express Reference Schematic
EQ: 7 dB when Floated, DE: 0 dB when Floated
11 Power Supply Recommendations
The SN75LVPE801DRF is designed to operate from a single 3.3-V supply. Always practice proper power-supply
sequencing procedure. Apply VCC first before any input signals are applied to the device. The power-down
sequence is in reverse order.
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12 Layout
12.1 Layout Guidelines
12.1.1 Return Current and Plane References
High frequency return signal/current is defined as the path that a signal follows back to its original source as all
signals flow in a closed loop. Minimizing the loop area of the closed loop is beneficial for both EMI (ElectroMagnetic Interference) reduction and signal integrity.
The best way to minimize loop area is to always have a signal reference their nearest solid ground or power
plane. Obstructions to the return signal causes signal integrity problems like reflections, crosstalk, undershoot
and overshoot.
Signals can reference either power or ground planes, but ground is preferred. Without solid plane references,
single ended and differential impedance control is very hard to accomplish; crosstalk to other signals may
happen as the return signals have no other path. This type of crosstalk is difficult to troubleshoot.
Symmetric pairing of solid planes in the layer stackup can significantly reduce warping of the PCB during the
manufacturing process. Warping of the PCB is crucial to minimize on boards that uses BGA components.
12.1.2 Split Planes – What to Avoid
Never route signals over splits in their perspective reference planes.
Figure 28. Overlapping Analog and Digital Planes
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Layout Guidelines (continued)
Figure 29. Incorrect Routing
Figure 30. Proper Routing
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Layout Guidelines (continued)
12.1.3 Avoiding Crosstalk
Crosstalk is defined as interference from one trace to another by either or both inductive and capacitive coupling.
Best ways to avoid crosstalk are:
• Provide stable reference planes for all high speed signals (as noted in previous sections).
• Use the 3W rule (3 times the width of trace for separation) where applicable on all signals, but absolutely use
on clock signals.
• Use ground traces/guards around either victim or aggressor signals prone to crosstalk.
• When space is constrained and limited on areas of the PCB to route parallel buses, series or end termination
resistors can be used to route traces closer than what is normally recommended. However, calculations and
simulations must be done to validate the use of series or end termination resistors to eliminate crosstalk.
Figure 31. Ways to Avoid Crosstalk
12.2 Layout Example
Figure 32. Printed-Circuit Board Stackup (FR-4 Example)
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Layout Example (continued)
PCB layer configuration suggestions for stackup symmetry and signal integrity.
Figure 33. PCB Layer Configuration Suggestions
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75LVPE801DRFR
ACTIVE
WSON
DRF
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 85
801
SN75LVPE801DRFT
ACTIVE
WSON
DRF
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 85
801
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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