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SN75LVPE802
SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
SN75LVPE802 Two-Channel 8 Gbps SATA Express Equalizer and Redriver
1 Features
3 Description
•
•
•
•
•
•
The SN75LVPE802 is a versatile dual channel, SATA
Express signal conditioner supporting data rates up to
8 Gbps. The device supports SATA Gen 1, 2, and 3
specifications as well as PCIe 1, 2, 3. The
SN75LVPE802 operates from a single 3.3-V supply
and has 100-Ω line termination with self-biasing
feature, making the device suitable for AC coupling.
The inputs incorporate an out-of-band (OOB)
detector, which automatically squelches the output
when the input differential voltage falls below
threshold while maintaining a stable common-mode
voltage. The device is also designed to handle
spread spectrum clocking (SSC) transmission per
SATA standard.
1
•
•
•
•
•
SATA Express Support
Selectable Equalization and De-Emphasis
Hot Plug Capable
Receiver Detect and OOB Support
Integrated Output Squelch
Multirate Operation
– SATA: 1.5 Gpbs, 3 Gpbs, 6 Gpbs
– PCIe: 2.5 Gbps, 5 Gbps, 8 Gbps
Excellent Jitter and Loss Compensation Capability
to Over 24-Inch (61-cm) FR4 Trace
Low Power
– < 220 mW (Typical)
– < 50 mW (in Auto Low-Power Mode)
– < 5 mW (in Standby Mode)
20-Pin 4-mm × 4-mm QFN Package
High Protection Against ESD Transient
– HBM: 10,000 V
– CDM: 1,500 V
– MM: 200 V
Extended Commercial Temperature Support 0°C
to 85°C
The SN75LVPE802 handles interconnect losses at its
input with selectable equalization settings that can be
programmed to match the loss in the channel. For
data rates of 3 Gbps and lower, the SN75LVPE802
equalizes signals for a span of up to 50 inches of
FR4 board material. For data rates of 8 Gbps, the
device compensates up to 40 in of FR4 material. The
equalization level is controlled by the setting of the
signal control pin EQ.
Two de-emphasis levels can be selected on the
transmit side to provide 0 or 1.2 dB of additional highfrequency loss compensation at the output.
2 Applications
•
•
•
•
Device Information(1)
PART NUMBER
Tablets
Notebooks
Desktops
Docking Stations
SN75LVPE802
PACKAGE
WQFN (20)
BODY SIZE (NOM)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematics
Connector
Host
Controller
330
330
VCC
U1
220nF
220nF
220nF
220nF
VCC
RX1P
VCC
RX1N
EQ2
GND
GND
TX2N
EQ1
TX2P
DEW1
DEW2
TX1P
EN
TX1N
DE2
GND
DE1
RX2N
VCC
RX2P
Device
220nF
220nF
220nF
220nF
470nF
220nF
220nF
470nF
SN75LVPE802
330
330
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVPE802
SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical SATA Application ....................................... 19
9.3 SATA Express Applications .................................... 25
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Revision A (September 2016) to Revision B
Page
•
Changed Figure 27 note From: Input Trace Length = 53 in. To: Input Trace Length = 3 in. ............................................... 22
•
Changed title of Figure 35 From: Output Eye (TP2) to: Input Eye (TP2) ............................................................................ 23
•
Changed Figure 37 note From: Input Trace Length = 36 in. To: Input Trace Length = 48 in. ............................................ 23
•
Changed Figure 38 note From: Input Trace Length = 36 in. To: Input Trace Length = 48 in. ............................................ 23
•
Changed title of Figure 38 From: Input Eye (TP4) To: Output Eye (TP4)............................................................................ 23
•
Changed note in Figure 40 From: Output Trace Length = 0 in To: Output Trace Length = 3 in. ........................................ 24
•
Changed note in Figure 42 From: Output Trace Length = 6 in To: Output Trace Length = 12 in. ...................................... 24
Changes from Original (January 2016) to Revision A
•
Page
Changed the device From: Product Preview To: Production ................................................................................................ 1
5 Description (continued)
The device is hot-plug capable (requires use of AC coupling capacitors at differential inputs and outputs)
preventing device damage under device hot-insertion such as async signal plug/removal, unpowered
plug/removal, powered plug/removal, or surprise plug/removal.
2
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SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
6 Pin Configuration and Functions
1
RX1N
2
GND
3
TX2N
4
TX2P
5
15
TX1P
14
TX1N
13
GND
12
RX2N
11
RX2P
VCC
EQ2
GND
EQ1
DEW1
19
18
17
16
1
RX1P
20
RTJ Package
20 Pin (WQFN)
Top View
6
7
8
9
10
DEW2
EN
DE2
DE1
VCC
2
LVPE802
Package Thermal Pad
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Control Pins
DE1 (1)
9
I, LVCMOS
(1)
8
I, LVCMOS
DEW1
16
I, LVCMOS
DEW2
6
I, LVCMOS
EN
7
I, LVCMOS
EQ1 (1)
17
I, LVCMOS
EQ2 (1)
19
I, LVCMOS
DE2
Selects de-emphasis settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
De-emphasis width control for CH 1 and CH 2.
0 = De-emphasis pulse duration, short
1 = De-emphasis pulse duration, long (default)
Device enable and disable pin, internally pulled to VCC.
0 = Device in standby mode
1 = Device enabled (default)
Select equalization settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
High Speed Differential I/O
RX1N
2
I, CML
RX1P
1
I, CML
RX2N
12
I, CML
RX2P
11
I, CML
TX1N
14
O, VML
TX1P
15
O, VML
TX2N
4
O, VML
TX2P
5
O, VML
GND
3, 13, 18
Power
Supply ground
VCC
10, 20
Power
Positive supply must be 3.3V ± 10%
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins connect to
an internal voltage bias via a dual termination resistor circuit.
Non-inverting and inverting VML differential input for CH 1 and CH 2. These pins connect to
an internal voltage bias via a dual termination resistor circuit.
POWER
(1)
Internally biased to VCC / 2 with >200-Ωk pullup or pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be < 1
µA; otherwise, drive to VCC / 2 to assert mid-level state.
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SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage Range (2), VCC
Voltage Range
MIN
MAX
UNIT
–0.5
4
V
Differential I/O
–0.5
4
V
Control I/O
–0.5
VCC + 0.5
V
Continuous power dissipation
See Thermal Information
Storage temperature, Tstg
(1)
(2)
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±10000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model (3)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with JEDEC Standard 22, Test Method A115-A
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply Voltage
C(coupling)
Coupling Capacitor
TA
Operating free-air temperature
MIN
NOM
MAX
3
3.3
3.6
12
UNIT
V
nF
0
85
°C
7.4 Thermal Information
SN75LVPE802
THERMAL METRIC (1)
RTJ (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
38
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40
°C/W
RθJB
Junction-to-board thermal resistance
10
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
0.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
15.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PD
Power dissipation in active mode
DEWX = EN = VCC, EQX = DEX = NC,
K28.5 pattern at 6 Gbps, VID = 700 mVpp
PSD
Power dissipation in standby mode
EN = 0 V, DEWX = EQX = DEX = NC,
K28.5 pattern at 6 Gbps, VID = 700 mVpp
ICC
Active mode supply current
EN = 3.3 V, DEWX = EQX = DEX = NC,
K28.5 pattern at 6 Gbps, VID = 700 mVpp
ICC(STDBY)
Standby mode supply current
EN = 0 V
MIN
TYP
MAX
UNIT
188
205
mW
4
mW
62
mA
57
Maximum data rate
1
mA
8
Gbps
OOB
V(OOB)
Input OOB threshold
150
mVpp
DVdiff(OOB)
OOB differential delta
F = 750 MHz
50
78
25
mV
DVCM(OOB)
OOB common-mode delta
50
mV
CONTROL LOGIC
VIH
High-level input voltage
VIL
Low-level input voltage
VIN(HYS)
Input hysteresis
IIH
High-level input current
IIL
Low-level input current
For all control pins
1.4
V
0.5
V
115
mV
EQx, DEx = VCC
30
µA
EN, DEWx = VCC
1
µA
EQx, DEx = GND
–30
µA
EN, DEWx = GND
–10
µA
RECEIVER AC/DC
Z(DIFFRX)
Differential-Input Impedance
85
Z(SERX)
Single-Ended Input Impedance
40
VCM(RX)
Common-mode voltage
RL(DiffRX)
RX(DiffRLSlope)
RL(CMRX)
Differential mode return Loss (RL)
Differential mode RL slope
Common mode return loss
IB(RX)
Differential input voltage PP
Impedance Balance
115
Ω
Ω
1.8
V
f = 150 MHz – 300 MHz
22
28
dB
f = 300 MHz – 600 MHz
14
17
dB
f = 600 MHz – 1.2 GHz
10
12
dB
f = 1.2 GHz – 2.4 GHz
8
9
dB
f = 2.4 GHz – 3 GHz
7
9
dB
f = 3 GHz – 5 GHz
6
8
dB
14
dB/dec
f = 300 MHz – 6 GHz
f = 150 MHz – 300 MHz
9
10
dB
f = 300 MHz – 600 MHz
14
17
dB
f = 600 MHz – 1.2 GHz
15
23
dB
f = 1.2 GHz – 2.4 GHz
13
16
dB
f = 2.4 GHz – 3 GHz
10
12
dB
4
6
f = 3 GHz – 5 GHz
V(diffRX)
100
dB
f = 1.5 GHz and 3 GHz
120
1600
mVppd
f = 150 MHz – 300 MHz
30
41
dB
f = 300 MHz – 600 MHz
30
38
dB
f = 600 MHz – 1.2 GHz
20
32
dB
f = 1.2 GHz – 2.4 GHz
10
26
dB
f = 2.4 GHz – 3 GHz
10
25
dB
f = 3 GHz – 5 GHz
4
20
dB
f = 5 GHz – 6.5 GHz
4
17
dB
100
TRANSMITTER AC/DC
Z(diffTX)
Pair differential impedance
85
Z(SETX)
Single-Ended input Impedance
40
V(TXtrans)
Sequencing transient voltage
Transient voltages on the serial data bus
during power sequencing (lab load)
–1.2
122
Ω
1.2
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Ω
V
5
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SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RL(DiffTX)
Diff Mode return Loss
TX(DiffRLSlope)
RL(CMTX)
Differential-mode RL slope
Common Mode return Loss
I(BTX)
Impedance Balance
Output de-emphasis
(relative to transition bit)
DE
Diff(VppTX_DE) Differential output-voltage swing dc level
V(CMAC_TX)
TX AC CM Voltage
V(CMTX)
Common-Mode Voltage
TX(R/FImb)
TX rise-fall imbalance
TX(AmpImb)
TX amplitude imbalance
MIN
TYP
f = 150 MHz – 300 MHz
TEST CONDITIONS
19
25
dB
f = 300 MHz – 600 MHz
17
19
dB
f = 600 MHz – 1.2 GHz
11
14
dB
f = 1.2 GHz – 2.4 GHz
8
10
dB
f = 2.4 GHz – 3 GHz
8
10
dB
f = 3 GHz – 5 GHz
8
10
dB
14
dB/dec
f = 300 MHz to 3 GHz
MAX
UNIT
f = 150 MHz – 300 MHz
16
20
dB
f = 300 MHz – 600 MHz
15
19
dB
f = 600 MHz – 1.2 GHz
14
17
dB
f = 1.2 GHz – 2.4 GHz
10
12
dB
f = 2.4 GHz – 3 GHz
9
11
dB
f = 3 GHz – 5 GHz
6
7
dB
f = 150 MHz – 300 MHz
30
41
dB
f = 300 MHz – 600 MHz
30
38
dB
f = 600 MHz – 1.2 GHz
20
33
dB
f = 1.2 GHz – 2.4 GHz
10
24
dB
f = 2.4 MHz – 3 GHz
10
26
dB
f = 3 GHz – 5 GHz
4
22
dB
f = 5 GHz – 6.5 GHz
4
21
dB
DE1 0r DE2 = 0
0
dB
DE1 0r DE2 = 1
–2
dB
DE1 0r DE2 = NC
–4
dB
DE1 0r DE2 = 0
550
mV
DE1 0r DE2 = 1
830
mV
DE1 0r DE2 = NC
630
mV
At 1.5 GHz
20
50
mVppd
At 3 GHz
12
26
dBmV (rms)
13
30
dBmV (rms)
At 6 GHz
1.8
At 3 GHz
V
6%
20%
V
2%
10%
V
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
80
105
130
ps
42
50
ps
DEVICE PARAMETERS
Auto low-power entry time
Electrical idle at input (see Figure 24)
Auto low-power exit time
After first signal activity (see Figure 24)
TRANSMITTER AC/DC
tDE
Input OOB threshold
DEW1 or DEW2 = 0
94
ps
DEW1 or DEW2 = 1
215
ps
OUT-OF-BAND (OOB)
tOOB1
OOB mode enter
tOOB2
OOB mode exit
6
See Figure 23
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3
5
ns
3
5
ns
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7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
323
400
ps
DEVICE PARAMETERS
tPDelay
Propagation delay
Measured using K28.5 pattern
(see Figure 1)
tENB
Device enable time
EN 0 → 1
5
µs
tDIS
Device disable time
EN 1 → 0
2
µs
75
ps
30
ps
55
75
ps
RECEIVER AC/DC
t20-80RX
tSKEWRX
Rise/fall time
Rise times and fall times measured
between 20% and 80% of the signal.
SATA 6-Gbps speed measured 1 in,
(2.5 cm) from device pin.
Differential skew
Difference between the single-ended
midpoint of the RX+ signal rising or
falling edge, and the single-ended
midpoint of the RX– signal falling or
rising edge.
62
TRANSMITTER AC/DC
t20-80TX
tSKEWTX
Rise/fall time
Rise times and fall times measured
between 20% and 80% of the signal.
At 6 Gbps under no load conditions.
Differential skew
Difference between the single-ended
midpoint of the TX+ signal rising or
falling edge, and the single-ended
midpoint of the TX– signal falling or
rising edge.
6
20
ps
VID = 500 mVpp, UI = 333 ps, K28.5
control character
0.06
5
UIp-p
VID = 500 mVpp, UI = 333 ps, K28.7
control character
0.01
5
ps-rms
VID = 500 mVpp, UI = 167 ps, K28.5
control character
0.08
0.16
UIp-p
VID = 500 mVpp, UI = 167 ps, K28.7
control character
0.09
2
ps-rms
VID = 500 mVpp, UI = 125 ps, K28.5
control character
0.1
0.2
UIp-p
VID = 500 mVpp, UI = 125 ps, K28.7
control character
0.3
1.5
ps-rms
42
TRANSMITTER JITTER
(1)
DJTX
Deterministic jitter
RJTX
Residual Random jitter (1)
DJTX
Deterministic jitter
RJTX
Residual random jitter
DJTX
Deterministic jitter
RJTX
Residual random jitter (1)
(1)
(1)
(1)
at CP in
at CP in
(1)
at CP in
(1) TJ = (14.1 x RJSD + DJ), where RJSD is one standard deviation value
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SN75LVPE802
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IN
tPDELAY
tPDELAY
OUT
Copyright © 2016, Texas Instruments Incorporated
Figure 1. Propagation Delay Timing Diagram
8
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SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
7.8 Typical Characteristics
Input signal characteristics:
• Data rate = 8 Gbps 6 bps, 3 Gbps, 1.5 Gbps
• Amplitude = 500 mVpp
• o Data pattern = K28.5
SN75LVPE802 device setup:
• Temperature = 25°C
• Voltage = 3.3 V
• De-emphasis duration = 117 ps (short)
• Equalization and de-emphasis set to optimize performance at 6 Gbps
With LVPE802
Agilent
ParBERT
16-in, 4-mil FR4 Trace
+ 2-in, 9.5-mil FR4 Trace
8-in, 4-mil FR4 Trace
+2-in, 9.5-mil FR4 Trace
LVPE802
TP1
TP2
TP3
Agilent
DCA-J
TP4
Without LVPE802
16-in, 4-mil FR4 Trace
+ 4-in, 9.5-mil FR4 Trace
+ 8in, 4-mil FR4 Trace
Agilent
ParBERT
Agilent
DCA-J
TP1
TP4
Copyright © 2016, Texas Instruments Incorporated
Figure 2. Performance Curve Measurement Setup
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Typical Characteristics (continued)
Figure 3. Jitter Measurement Test Condition
10
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SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
7.8.1 Jitter and VOD results: Case 1 at 6 Gbps
TJ
(1e-12)
ps
29
DJ
(σ-σ)
ps
3.3
RJ
(rms)
ps
1.88
Eye
Amplitude
mV
412.4
Eye
Width
ps
159.2
Eye
Opening
(mV)
350.52
TJ
(1e-12)
ps
91.8
DJ
(σ-σ)
ps
65.4
Figure 4. Test Point 1
TJ
(1e-12)
ps
42
DJ
(σ-σ)
ps
15.9
RJ
(rms)
ps
1.91
Eye
Amplitude
mV
788.8
Eye
Width
ps
141.3
DJ
(σ-σ) ps
29.8
Eye
Amplitude
mV
240
Eye
Width
ps
28.9
Eye
Opening
(mV)
81.24
Figure 5. Test Point 2
Eye
Opening
(mV)
623.02
TJ
(1e-12)
ps
39
DJ
(σ-σ)
ps
12.7
Figure 6. Test Point 3
TJ
(1e-12) ps
56.7
RJ
(rms)
ps
1.93
RJ
(rms)
ps
1.92
Eye
Amplitude
mV
557.1
Eye
Width
ps
149.7
Eye
Opening
(mV)
459.62
Figure 7. Test Point 4 With LVPE802
RJ
(rms) ps
2
Eye
Amplitude mV
165.4
Eye
Width ps
101
Eye
Opening (mV)
13.24
Figure 8. Test Point 4 Without LVPE802
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7.8.2 Jitter and VOD Results: Case 2 at 3 Gbps
TJ
(1e-12)
ps
29.7
DJ
(σ-σ)
ps
3.8
RJ
(rms)
ps
1.89
Eye
Amplitude
mV
430.9
Eye
Width
ps
326
Eye
Opening
(mV)
392.84
TJ
(1e-12)
ps
72.7
DJ
(σ-σ)
ps
46.8
RJ
(rms)
ps
1.89
DJ
(σ-σ)
ps
12.8
RJ
(rms)
ps
1.96
Eye
Amplitude
mV
714.5
Eye
Width
ps
321
Eye
Opening
(mV)
611.62
DJ
(σ-σ) ps
101.8
Eye
Opening
(mV)
222.36
TJ
(1e-12)
ps
47.9
DJ
(σ-σ)
ps
20.3
RJ
(rms)
ps
1.99
Eye
Amplitude
mV
615.3
Eye
Width
ps
305.0
Eye
Opening
(mV)
463.42
Figure 12. Test Point 4 With LVPE802
Figure 11. Test Point 3
TJ
(1e-12) ps
128.6
Eye
Width
ps
237
Figure 10. Test Point 2
Figure 9. Test Point 1
TJ
(1e-12)
ps
39.6
Eye
Amplitude
mV
314.9
RJ
(rms) ps
1.96
Eye
Amplitude mV
258.8
Eye
Width ps
118
Eye
Opening (mV
122.26
Figure 13. Test Point 4 Without LVPE802
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7.8.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
TJ
(1e-12)
ps
34.3
DJ
(σ-σ)
ps
3.4
RJ
(rms)
ps
2.26
Eye
Amplitude
mV
448
Eye
Width
ps
659
Eye
Opening
(mV)
417.28
TJ
(1e-12)
ps
67.5
DJ
(σ-σ)
ps
38.6
Figure 14. Test Point 1
TJ
(1e-12)
ps
44.9
DJ
(σ-σ)
ps
13.2
RJ
(rms)
ps
2.31
Eye
Amplitude
mV
753.1
RJ
(rms)
ps
2.11
Eye
Amplitude
mV
363.4
Eye
Width
ps
595
Eye
Opening
(mV)
318.48
Figure 15. Test Point 2
Eye
Width
ps
649
Eye
Opening
(mV)
604.02
Figure 16. Test Point 3
TJ
(1e-12)
ps
57.3
DJ
(σ-σ)
ps
21.5
RJ
(rms)
ps
2.62
Eye
Amplitude
mV
672.8
Eye
Width
ps
632
Eye
Opening
(mV)
442.42
Figure 17. Test Point 4 With LVPE802
TJ
(1e-12) ps
113.3
DJ
(σ-σ) ps
81.9
RJ
(rms) ps
2.3
Eye
Amplitude mV
322.8
Eye
Width ps
493
Eye
Opening (mV)
217.48
Figure 18. Test Point 4 Without LVPE802
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7.8.4 Jitter and VOD Results: Case 4 at 8 Gbps
Figure 21 Test Point 3 and Figure 22 Test Point 4 were taken without pre-emphasis.
TJ
(1e-12)
ps
14.4
DJ
(σ-σ)
ps
10.1
RJ
(rms)
ps
0.31
Eye
Amplitude
mV
580
Eye
Width
ps
108
Eye
Opening
(mV)
274
TJ
(1e-12)
ps
78.1
DJ
(σ-σ)
ps
68.9
Figure 19. Test Point 1
TJ
(1e-12)
ps
30.6
DJ
(σ-σ)
ps
23.6
RJ
(rms)
ps
0.51
Eye
Amplitude
mV
406
Eye
Amplitude
mV
310
Eye
Width
ps
45
Eye
Opening
(mV)
48
Figure 20. Test Point 2
Eye
Width
ps
86
Eye
Opening
(mV)
292
TJ
(1e-12)
ps
34.4
DJ
(σ-σ)
ps
26.8
Figure 21. Test Point 3
14
RJ
(rms)
ps
0.67
RJ
(rms)
ps
0.56
Eye
Amplitude
mV
262
Eye
Width
ps
85
Eye
Opening
(mV)
95
Figure 22. Test Point 4
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8 Detailed Description
8.1 Overview
The SN75LVPE802 is a dual channel equalizer and redriver. The device operates over a wide range of signaling
rates, supporting operation from DC to 8 Gbps. The wide operating range supports SATA Gen 1, 2, 3 (1.5 Gbps,
3.0 Gbps, and 6.0 Gbps respectively) as well as PCI Express 1.0, 2.0, 3.0 (2.5 Gbps, 5.0 Gbps, and 8.0 Gbps).
The device also supports SATA Express (SATA 3.2) which is a form factor specification that allows for SATA and
PCI Express signaling over a single connector.
8.2 Functional Block Diagram
GND[3,13,18]
VBB = 1.7 V TYP
RT
RX1P [1]
TX1P [15]
RX1N [2]
Driver
Equalizer
RT
TX1N [14]
OOB
Detect
VBB
RT
RX2N [12]
RT
RX2P [11]
OOB
Detect
Driver
TX2P [5]
Equalizer
TX2N [4]
DEW1 [16]
CTRL
DEW2 [6]
EQ1[17]
DE1[9]
EQ2[19]
VCC[10,20]
DE2[8]
EN[7]
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8.3 Feature Description
8.3.1 SATA Express
SATA Express (sometimes SATAe) is an electro-mechanical standard that supports both SATA and PCI Express
storage devices. SATAe is standardized in the SATA 3.2 standard. The standard is concerned with providing a
smooth transition from SATA to PCIe storage devices. The standard provides for standardized cables and
connectors, and muxes the PCIe and SATA lanes at the host side so that either SATA compliant or PCIe
compliant devices may operate with a host.
SATAe provides support for SATA1, SATA2 and SATA3 devices (operating from 1.5 Gbps to 6.0 Gbps), as well
as PCIe1, PCIe2 and PCIe3 devices (operating from 2.5 Gbps to 8.0 Gbps).
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Feature Description (continued)
The SN75LVPE802 provides for equalization and re-drive of a single channel input signal complying with any of
the SATA or PCIe standards available with SATAe.
The SATAe standard provides for a mechanism for a host to recognize and detect whether a SATA or PCIe
device is plugged into the host. See the Typical SATA Application section for the details of the SATA Express
Interface Detect operation.
8.3.2 Receiver Termination
The receiver has integrated terminations to an internal bias voltage. The receiver differential input impedance is
nominally 100 Ω, with a ±15% variation.
8.3.3 Receiver Internal Bias
The SN75LVPE802 receiver is internally biased to 1.7 V, providing support for AC coupled inputs.
8.3.4 Input Equalization
The SN75LVPE802 incorporates programmable equalization. The EQ input controls the level of equalization that
is used to open the eye of the received input signal. If the EQ input is left open, or pulled LO, 6 dB (at 3 GHz) of
equalization is applied. When the EQ input is HIGH, the equalization is set to 13 dB (again at 3 GHz). Table 1
shows the equalization values discussed.
Table 1. EQ and DE Settings
EQ1 OR EQ2
CH1 OR CH2 EQUALIZATION
dB
(at 6 Gbps)
CH1 OR CH2 EQUALIZATION
dB
(at 8 Gbps)
DE1 OR DE2
CH1 OR CH2 DE-EMPHASIS
dB
(at 6 Gbps)
NC (default)
0
0
NC (default)
-4
0
6
7
0
0
1
13
15
1
-2
8.3.5 OOB/Squelch
The SN75LVPE802 receiver incorporates an Out-Of-Band (OOB) detection circuit in addition to the main signal
chain receiver. The OOB detector continuously monitors the differential input signal to the device. The OOB
detector has a 50-mVpp entry threshold. If the differential signal at the receiver input is less than the OOB entry
threshold, the device transmitter transitions to squelch. The SN75LVPE802 enters squelch within 5 ns of the
input signal falling below the OOB entry threshold. The SN75LVPE802 continues to monitor the input signal while
in squelch. While in squelch, if the OOB detector determines that the input signal now exceeds the 90 mVpp exit
threshold, the SN75LVPE802 exits squelch within 5 ns.
IN+
50 mV
Vcm
IN-
tOOB2
tOOB1
OUT+
Vcm
OUT-
Figure 23. OOB Enter and Exit Timing Receiver Input Termination Is Disabled
When the SN75LVPE802 enters squelch state the transmitter output is squelched. The transmitter non-inverting
(TX+) output and the transmitter inverting output (TX-) are both driven to the transmitter nominal common mode
voltage which is 1.7 V.
16
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8.3.6 Auto Low Power
The SN75LVPE801 also includes an Auto Low Power Mode (ALP). ALP is entered when the differential input
signal has been less than 50 mV for > 10 µs. The device enters and exits Low Power Mode by actively
monitoring the input signal level. In this state the device selectively shuts off internal circuitry to lower power by >
90% of its normal operating power. While in ALP mode the device continues to actively monitor input signal
levels. When the input signal exceeds the OOB exit threshold level, the device reverts to the active state. Exit
time from Auto Low Power Mode is < 50 ns (max).
RX1,2P
VCMRX
RX1,2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY
Power Saving
Mode
Figure 24. Auto Low Power Mode Entry and Exit Timing
8.3.7 Transmitter Output Signal
The SN75LVPE802 differential output signal is 650 mVpp when de-emphasis is disabled (DE input is open or
pulled low).
8.3.8 Transmitter Common Mode
The SN75LVPE802 transmitter common mode output is set to 1.7 V.
8.3.9 De-Emphasis
The SN75LVPE802 device provides the de-emphasis settings shown in Table 2. De-emphasis control is
independent for each channel, controlled by the DE1 and DE2 pin settings as shown in Table 2. The reference
for the de-emphasis settings available in the device is the transition bit amplitude for each given configuration;
this transition bit amplitude is different at 0 dB than the –2-dB and –4-dB settings by design. DEW1 and DEW2
control the DE durations for channels one and two, respectively. Table 2 lists the recommended settings for
these control pins. Output de-emphasis is capable of supporting FR4 trace at the output anywhere from 2 in. (5.1
cm) to 12 in. (30.5 cm) at SATA 3G/6G speed.
Table 2. TX and Rx EQ and DE Pulse-Duration Settings
DEW1 OR DEW2
DEVICE FUNCTION → DE WIDTH FOR CH1/CH2
0
De-emphasis pulse duration, short
1 (default)
De-emphasis pulse duration, long
8.3.10 Transmitter Termination
The SN75LVPE802 transmitter includes integrated terminations. The receiver differential output impedance is
nominally 100 Ω, with a ≤ 22% variation.
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8.4 Device Functional Modes
8.4.1 Low-Power Mode
There are two low-power modes supported by the SN75LVPE802 device, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V)
– The enable (EN) pin controls th low-power mode. Pulling this pin LOW puts the device in standby mode
within 2 µs (max). In this mode, the device drives all its active components to their quiescent level, and
differential outputs Hi-Z (open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode
to normal operation requires a maximum latency of 5 µs.
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs
and EN = VCC)
– The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on each
of its channels independently. When the input signal on either or both channels is in the electrically idle
state, that is, VIDp-p < 50 mV and stays in this state for > 100 µs, the associated channel enters into the
low-power state. In this state, output of the associated channel goes to VCM and the device selectively
shuts off some circuitry to lower power by > 80% of its normal operating power. Exit time from the auto
low-power mode is < 50 ns.
18
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN75LVPE802 can be used for SATA applications as well as SATA Express applications. The device
supports SATA Gen1, Gen2, and Gen3 applications with data rates from 1.5 to 6 Gbps. The built-in equalization
circuits provide up to 13 dB of equalization at 3 GHz. This equalization can support SATA GEN2 (3 Gbps)
applications over up to 50 inches of FR-4 material. The same 13 dB equalizer is suited to SATA Gen3 (6 Gbps)
applications up to 40 inches of FR4.
In addition to SATA applications, the SN75LVPE802 can support SATA Express applications. SATA Express
provides a standardized interface to support both SATA (Gen1, Gen2, and Gen3) and PCI Express (PCIe 1, 2
and 3).
All applications of the SN75LVPE802 share some common applications issues. For example, power supply
filtering, board layout, and equalization performance with varying interconnect losses. Other applications issues
are specific, such as implementing receiver detection for SATA Express applications. The Typical Application
examples demonstrate common implementations of the SN75LVPE802 supporting SATA, as well as SATA
Express applications.
9.2 Typical SATA Application
This typical application describes how to configure the EQ, DE, and DEW configuration pins of the
SN75LVPE802 device based on board trace length between the SATA Host and the SN75LVPE802 and the
SN75LVPE802 and SATA Device. Actual configuration settings may differ due to additional factors such as
board layout, trace widths, and connectors used in the signal path.
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EQ1
DEW1
VCC
0.1 uF
18
19
20
10 nF
0.01 uF
16
3.3 V
1.0 uF
17
EQ2
Typical SATA Application (continued)
10 nF
1
RX1P
RX1N
TX1N
14
SATA Host
10 nF
3
10 nF
13
LVPE802
10 nF
10 nF
4
TX2N
RX2N
12
5
TX2P
RX2P
11
10 nF
SATA Connector
2
TX1P
15
10 nF
10
9
8
7
6
VCC
DE2
DE1
EN
DEW2
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(1)
Place supply caps close to device pin
(2)
EN can be left open or tied to supply when no external control is implemented
(3)
Output de-emphasis selection is set at -3 dB, EQ at 7 dB and DE width for SATA I/II/III operation for both channels.
(4)
Actual EQ/DE/DE width settings will depend on device placement relative to host and SATA connector.
Figure 25. Typical Device Implementation
9.2.1 Design Requirements
Typically, system trace length from the SATA host to the SN75LVPE802 device and trace length from the
SN75LVPE802 device to a SATA device differ and require different equalization and de-emphasis settings for the
host side and device side.
For example:
• A system with a 6-inch trace from the SN75LVPE802 device to a SATA host may set EQ1 (Rx1±) to 7 dB,
and DE2 (Tx2±) to –2 dB and DEW2 (Tx2±) to long pulse duration.
• The same system with a 1-inch trace from the SN75LVPE802 device to a SATA HDD may set EQ2 (Rx2±) to
0 dB, and DE1 (Tx1±) to 0 dB and DEW1 (Tx1±) to short pulse duration.
Refer to
Application Curves for recommended EQ, DE and DEW settings based on trace length. It is highly
recommended to add both pullup- and pulldown-resistor options in the layout to fine-tune the settings if needed.
Input Signal Characteristics:
• Data Rate: 6 Gbps
• Pattern: PRBS7
• No pre-emphasis
• Signal amplitude: 500 mVpp
• 18-inch SMA cable from test equipment to input and output trace
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Typical SATA Application (continued)
Lecroy PERT3
SN75LVPE802
TP1
TP2
25-GHz Scope
TP3
TP4
Figure 26. Measurement Set-up
9.2.2 Detailed Design Procedure
9.2.2.1 Equalization Configuration
Each differential input of the SN75LVPE802 device has programmable equalization in the front stage. The
equalization setting is shown in Table 1. The input equalizer is designed to recover a signal even when no eye is
present at the receiver and effectively supports FR4 trace input from 3 inches to greater than 24 inches at SATA
6 Gbps speed.
9.2.3 De-emphasis Configuration
The SN75LVPE802 device provides the de-emphasis settings shown in Table 1 and Table 2. TX and Rx EQ and
DE Pulse-Duration Settings. De-emphasis is controlled independently for each channel and is set by the DE1,
DE2, DEW1 and DEW2 pins of the SN75LVPE802 device.
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Typical SATA Application (continued)
9.2.4 Application Curves
Typical application curves correspond to SATA application at 6 Gbps.
9.2.4.1 SN75LVPE802 Equalization Settings for Various Input Trace Length
Input Trace Length = 3 in.
EQ1, EQ2 Setting = NC (0 dB)
Input Trace Length = 3 in.
EQ1, EQ2 Setting = NC (0 dB)
Figure 28. Output Eye (TP4)
Figure 27. Input Eye (TP2)
Input Trace Length = 6 in.
EQ1, EQ2 Setting = 0 (7 dB)
Input Trace Length = 6 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 29. Input Eye (TP2)
Input Trace Length = 12 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 30. Output Eye (TP4)
Input Trace Length = 12 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 31. Input Eye (TP2)
22
Figure 32. Output Eye (TP4)
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Typical SATA Application (continued)
Input Trace Length = 24 in.
EQ1, EQ2 Setting = 0 (7 dB)
Input Trace Length = 24 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 33. Input Eye (TP2)
Input Trace Length = 36 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 34. Output Eye (TP4)
Input Trace Length = 36 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 35. Input Eye (TP2)
Input Trace Length = 48 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 36. Output Eye (TP4)
Input Trace Length = 48 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 37. Input Eye (TP2)
Figure 38. Output Eye (TP4)
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Typical SATA Application (continued)
9.2.4.2 SN75LVCP802 De-emphasis Settings For various Output Trace Lengths
Output Trace Length = 0 in.
DE, DE2 Setting = 0 (0 dB)
DEW1, DEW2 Setting = 0 (Short pulse duration)
Output Trace Length = 3 in.
DE, DE2 Setting = 0 (0 dB)
DEW1, DEW2 Setting = 0 (Short pulse duration)
Figure 39. Output Eye (TP4)
Figure 40. Output Eye (TP4)
Output Trace Length = 6 in.
DE, DE2 Setting = 1 (-2 dB)
DEW1, DEW2 Setting = 1 (Long pulse duration)
Output Trace Length = 12 in.
DE, DE2 Setting = 1 (-2 dB)
DEW1, DEW2 Setting = 1 (Long pulse duration)
Figure 41. Output Eye (TP4)
Figure 42. Output Eye (TP4)
Output Trace Length = 12 in.
DEW1, DEW2 Setting = 1 (Long pulse duration)
DE, DE2 Setting = NC (-4 dB)
Figure 43. Output Eye (TP4)
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9.3 SATA Express Applications
Connector
Host
Controller
330
330
VCC
U1
220nF
220nF
220nF
220nF
VCC
RX1P
VCC
RX1N
EQ2
GND
GND
TX2N
EQ1
TX2P
DEW1
DEW2
TX1P
EN
TX1N
DE2
GND
DE1
RX2N
VCC
RX2P
Device
220nF
220nF
220nF
220nF
470nF
220nF
220nF
470nF
SN75LVPE802
330
330
Copyright © 2017, Texas Instruments Incorporated
Figure 44. SATAe Reference Schematic
9.3.1 Detailed Design Procedure
Figure 44 is a reference schematic of a SATAe implementation using the SN75LVPE802. With a SATAe design,
both SATA and PCI Express must be supported. SATAe supports both cabled and direct connections. Using a
cabled application as an example, the SATAe power connector includes an Interface Detect (IFDet, power
connector pin P4) signal that indicates whether a SATA client or a PCIe client is connected.
When the SATAe host determines that a PCIe client is connected, the SATAe host performs receiver detection.
Receiver detection determines the presence of a client by detecting the load impedance. The transmitter
performs a common mode voltage shift, and measures the rate at which the voltage at the transmitter output
changes. The rate of change indicates if a client is present (fast charging when a low impedance load is present,
or slow charging when the load is open or high impedance). With the implementation in Figure 44, 330-Ω
pulldowns have been inserted between the host and the SN75LVPE802. The pulldown resistors indicate to the
host that a client is present. While an actual client would be expected to have an active load of 50 Ω single
ended, the 330 Ω is chosen here to meet two requirements. The 330 Ω is low enough to force the SATAe host to
decide that a receiver is present, while also high enough to only marginally affect the load when the
SN75LVPE802 is active, and presenting a 50-Ω load. With the 50 Ω and 330 Ω are both present, the parallel
combination of 43 Ω is satisfactory for most applications.
Assuming that the SATAe host has detected (via IFDet) that a SATA client is present, the SATAe host
communicates with the client via the SN75LVPE802. The SATA standard does not have a receiver detection
mode as is present in PCIe. A SATA host does use OOB signaling to communicate identification information. The
SN75LVPE802 incorporates an OOB detector in order to support OOB signaling through the device. The OOB
detector drives a squelch circuit on the SN75LVPE802 output transmitter. (See OOB/Squelch for more details on
the OOB/Squelch circuitry.)
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SATA Express Applications (continued)
Returning to Figure 44, there is a 200-nF AC coupling capacitors on the device or client side of the interface.
These capacitors allow interfacing to both SATA and PCIe clients. In the case of a PCIe client, the 200 nF is
within the acceptable range for all PCIe devices. When a SATA client is present, the 200 nF capacitor has little
effect on the overall link, as it appears in series with the 12-nF (max) AC coupling capacitor incorporated into the
SATA client. The 200 nF in series with the 12 nF presents an effective capacitance of 11.3 nF, as expected less
than the 12-nF maximum permitted.
9.3.2 PCIe Applications
PCIe-only applications are implemented in a manner very similar to SATA Express applications as covered in
Detailed Design Procedure. Looking at Figure 45 and comparing it to the SATA Express application in Figure 8
20 SATAe Reference Schematic, a single change is noted. For PCIe applications the 220 nF AC-coupling
capacitors on the Host-to-Device link are relocated from the Device side of the connector to the Host side. No
other changes are required.
Connector
Host
Controller
330
330
VCC
U1
220nF
220nF
220nF
220nF
VCC
RX1P
VCC
RX1N
EQ2
GND
GND
TX2N
EQ1
TX2P
DEW1
DEW2
TX1P
EN
TX1N
DE2
GND
DE1
RX2N
VCC
RX2P
Device
220nF
220nF
470nF
220nF
220nF
470nF
SN75LVPE802
330
330
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Figure 45. SN75LVPE802 PCIe Reference Schematic
10 Power Supply Recommendations
The design of SN75LVPE802 device is for operation from one 3.3-V supply. Always practice proper power supply
sequencing procedure. Apply VCC first, before application of any input signals to the device. The power down
sequence is in reverse order.
26
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www.ti.com
SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
11 Layout
11.1 Layout Guidelines
24"
SATA
connector
Redriver
SATA Host
8"
16"
Redriver on Motherboard
24"
SATA Host
Redriver
Main Board
Dock Board
SATA
connector
8"
16"
Redriver on Dock Board
Copyright © 2016, Texas Instruments Incorporated
(1)
Trace lengths are suggested values based on TI spice simulations (done over programmable limits of input EQ and
output
de-emphasis)
to
meet
SATA
loss
and
jitter
spec.
Actual trace length supported by the LVPE802 may be more or less than suggested values and will depend on board
layout, trace widths and number of connectors used in the SATA signal path.
Figure 46. Trace Length Example for LVPE802
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Product Folder Links: SN75LVPE802
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SN75LVPE802
SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
www.ti.com
11.2 Layout Example
Figure 47. Example Layout
28
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Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: SN75LVPE802
SN75LVPE802
www.ti.com
SLLSET1B – JANUARY 2016 – REVISED FEBRUARY 2017
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN75LVPE802
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75LVPE802RTJR
ACTIVE
QFN
RTJ
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 85
LVP802
SN75LVPE802RTJT
ACTIVE
QFN
RTJ
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 85
LVP802
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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