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SRC4190
SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
SRC4190 192-kHz Stereo Asynchronous Sample-Rate Converters
1 Features
2 Applications
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1
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Automatic Sensing of the Input-to-Output
Sampling Ratio
Wide Input-to-Output Sampling Range:
16:1 to 1:16
Supports Input and Output Sampling Rates
up to 212 kHz
Dynamic Range: 128 dB (–60-dB fS Input,
BW = 20 Hz to fS / 2, A-Weighted)
THD+N: –125 dB (0-dB fS Input,
BW = 20 Hz to fS / 2)
Attenuates Sampling and Reference Clock Jitter
High-Performance, Linear Phase Digital Filtering
Flexible Audio Serial Ports:
– Master or Slave Mode Operation Supports I2S,
Left Justified, Right Justified, and TDM Data
Formats
– Supports 16-, 18-, 20-, or 24-Bit Audio Data,
TDM Mode Allows Daisy Chaining of up to
Eight Devices
Supports 24-, 20-, 18-, or 16-Bit Input and Output
– All Output Data is Dithered from the Internal
28-Bit Data Path
Low Group Delay Option for Interpolation Filter
Soft Mute Function
Bypass Mode
Power-Down Mode
Operates from a Single 3.3-V Power Supply
Small 28-Pin SSOP Package
Pin Compatible With the SRC4192, AD1895, and
AD1896
NOTE: U.S. Patent No. 7,262,716
NOTE: See Application and Implementation for details.
Digital Mixing Consoles
Digital Audio Workstations
Audio Distribution Systems
Broadcast Studio Equipment
High-End A/V Receivers
General Digital Audio Processing
3 Description
The SRC4190 device is an asynchronous sample
rate converter designed for professional and
broadcast audio applications. The SRC4190
combines a wide input-to-output sampling ratio with
outstanding dynamic range and low distortion. Input
and output serial ports support standard audio
formats, as well as a Time Division Multiplexed
(TDM) mode. Flexible audio interfaces allow the
SRC4190 to connect to a wide range of audio data
converters, digital audio receivers and transmitters,
and digital signal processors.
The SRC4190 is a standalone pin-programmed
device, with control pins for mode, data format, mute,
bypass, and low group delay functions.
The SRC4190 may be operated from a single 3.3-V
power supply. A separate digital I/O supply (VIO)
operates with a 1.65-V to 3.6-V supply, allowing
greater flexibility when interfacing to current and
future generation signal processors and logic devices.
The SRC4190 is available in a 28-pin SSOP
package.
Device Information(1)
PART NUMBER
SRC4190
PACKAGE
SSOP (28)
BODY SIZE (NOM)
10.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
Reference
Clock
DSP
Data
LRCK
BCK
SRC4190
Data
LRCK
BCK
DIT4192
TX+
TX-
AES,
S/PDIF
Output
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SRC4190
SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2007) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Added Thermal Information table ........................................................................................................................................... 4
Changes from Revision A (July 2003) to Revision B
•
2
Page
Added U.S. patent number to note (1) ................................................................................................................................... 1
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SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
DB Package
28-Pin SSOP
Top View
LGRP
1
28
RCKI
2
27
MODE1
NC
3
26
MODE0
SDIN
4
25
BCKO
BCKI
5
24
LRCKO
LRCKI
6
23
SDOUT
VIO
7
22
VDD
MODE2
DGND
8
21
DGND
BYPAS
9
20
TDMI
IFMT0
10
19
OFMT0
IFMT1
11
18
OFMT1
IFMT2
12
17
OWL0
RST
13
16
OWL1
MUTE
14
15
RDY
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BCKI
5
Input and Output
Input port bit clock I/O
BCKO
25
Input and Output
Output port bit clock I/O
BYPAS
9
Input
DGND
8, 21
Ground
ASRC bypass control input (active high)
IFMT0
10
Input
Input port data format control input
IFMT1
11
Input
Input port data format control input
IFMT2
12
Input
Input port data format control input
LGRP
1
Input
Low group delay control input (active high)
LRCKI
6
Input and Output
Input port left and right word clock I/O
LRCKO
24
Input and Output
Output port left and right word clock I/O
MODE0
26
Input
Serial port mode control input
MODE1
27
Input
Serial port mode control input
MODE2
28
Input
Serial port mode control input
MUTE
14
Input
Output mute control input (active high)
NC
3
—
OFMT0
19
Input
Output port data format control input
OFMT1
18
Input
Output port data format control input
OWL0
17
Input
Output port data word length control input
OWL1
16
Input
Output port data word length control input
RCKI
2
Input
Reference clock input
RDY
15
Output
RST
13
Input
Reset input (active low)
Audio serial data input
Digital ground
No connection
ASRC ready status output (active low)
SDIN
4
Input
SDOUT
23
Output
TDMI
20
Input
VDD
22
Power
Digital core supply, 3.3 V
VIO
7
Power
Digital I/O supply, 1.65 V to VDD
Audio serial data output
TDM data input. Connect to DGND when not in use.
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SRC4190
SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VDD
–0.3
4
V
Supply voltage, VIO
–0.3
4
V
Digital input voltage
–0.3
4
V
Operating temperature
–45
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
MIN
NOM
MAX
3
3.3
3.6
V
VIO 1.8-V supply voltage
1.65
1.8
1.95
V
VIO 3.3-V supply voltage
3
3.3
3.6
V
85
°C
VDD supply voltage
Operating temperature
–45
UNIT
6.4 Thermal Information
SRC4190
THERMAL METRIC (1)
DB (SSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
77.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.6
°C/W
RθJB
Junction-to-board thermal resistance
38.4
°C/W
ψJT
Junction-to-top characterization parameter
8.8
°C/W
ψJB
Junction-to-board characterization parameter
38.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
6.5 Electrical Characteristics
TA = 25°C, VDD = 3.3 V = VIO = 3.3 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
212
kHz
212
kHz
DYNAMIC PERFORMANCE (1)
Resolution
fSIN
Input sampling frequency
fSOUT
Output sampling frequency
Input:Output sampling ratio
Dynamic range
Total harmonic
distortion + noise
24
4
4
Upsampling
1:16
Downsampling
16:1
BW = 20 Hz to fSOUT / 2,
–60-dBFS input,
fIN = 1 kHz,
Unweighted (add 3 dB for
A‑weighted result)
BW = 20 Hz to fSOUT / 2,
0-dBFS input,
fIN = 1 kHz,
Unweighted
44.1 kHz:48 kHz
125
48 kHz:44.1 kHz
125
48 kHz:96 kHz
125
44.1 kHz:192 kHz
125
96 kHz:48 kHz
125
192 kHz:12 kHz
125
192 kHz:32 kHz
125
192 kHz:48 kHz
125
32 kHz:48 kHz
125
12 kHz:192 kHz
125
44.1 kHz:48 kHz
–125
48 kHz:44.1 kHz
–125
48 kHz:96 kHz
–125
44.1 kHz:192 kHz
–125
96 kHz:48 kHz
–125
192 kHz:12 kHz
–125
192 kHz:32 kHz
–125
192 kHz:48 kHz
–125
32 kHz:48 kHz
–125
12 kHz:192 kHz
–125
Interchannel gain mismatch
0
Interchannel phase deviation
0
Mute attenuation
Bits
24-bit word length, A-weighted
dB
dB
dB
°
–128
dB
DIGITAL INTERPOLATION FILTER
Passband
Passband ripple
Transition band
0.4535 × fSIN
Stop band
0.5465 × fSIN
Stop band attenuation
0.4535 × fSIN
Hz
±0.007
dB
0.5465 × fSIN
Hz
Hz
–125
Normal group delay (LGRP = 0)
Low group delay (LGRP = 1)
dB
102.53125 / fSIN
s
70.53125 / fSIN
s
DIGITAL DECIMATION FILTER
Passband
Passband ripple
Transition band
0.4535 × fSOUT
Stop band
0.5465 × fSOUT
Stop band attenuation
0.4535 × fSOUT
Hz
±0.008
dB
0.5465 × fSOUT
Hz
Hz
–125
Group delay
dB
36.46875 / fSOUT
s
DIGITAL I/O
VIH
High-level input voltage
0.7 × VIO
VIO
VIL
Low-level input voltage
0
0.3 × VIO
V
IIH
High-level input current
0.5
10
µA
IIL
Low-level input current
0.5
10
µA
(1)
V
Dynamic performance measured with an Audio Precision System Two Cascade or Cascade Plus.
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SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
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Electrical Characteristics (continued)
TA = 25°C, VDD = 3.3 V = VIO = 3.3 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IO = –4 mA
VOL
Low-level output voltage
IO = 4 mA
CIN
Input capacitance
MIN
TYP
MAX
0.8 × VIO
VIO
0
0.2 × VIO
3
UNIT
V
V
pF
POWER SUPPLY
VDD
VDD operating voltage
VIO
VIO operating voltage
VDD supply current
VDD = VIO = 3.3 V, RST = 0,
No clocks, fSIN = 192 kHz,
fSOUT = 192 kHz
Power down
IDD
Power down
IIO
VIO supply current
VDD = VIO = 3.3 V, RST = 0,
No clocks, fSIN = 192 kHz,
fSOUT = 192 kHz
Power dissipation
VDD = VIO = 3.3 V, RST = 0,
No clocks, fSIN = 192 kHz,
fSOUT = 192 kHz
Power down
PD
3
3.3
3.6
1.65
3.3
3.6
100
Dynamic
66
2
µA
mA
660
Dynamic
µA
mA
100
Dynamic
V
225
µW
mW
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
128 × fSMIN
50
MHz
20
1 / (128 × fSMIN)
REFERENCE CLOCK TIMING
RCKI frequency (1) (2)
tRCKIP
RCKI period
tRCKIH
RCKI pulse width HIGH
0.4 × tRCKIP
ns
ns
tRCKIL
RCKI pulse width LOW
0.4 × tRCKIP
ns
500
ns
RESET TIMING
tRSTL
RST pulse width LOW
INPUT SERIAL PORT TIMING
tLRIS
LRCKI to BCKI setup time
10
ns
tSIH
BCKI pulse width HIGH
10
ns
tSIL
BCKI pulse width LOW
10
ns
tLDIS
SDIN data setup time
10
ns
tLDIH
SDIN data hold time
10
ns
OUTPUT SERIAL PORT TIMING
tDOPD
SDOUT data delay time
tDOH
SDOUT data hold time
2
10
ns
ns
tSOH
BCKO pulsewidth HIGH
10
ns
tSOL
BCKO pulse width LOW
5
ns
TDM MODE TIMING
tLROS
LRCKO setup time
10
ns
tLROH
LRCKO hold time
10
ns
tTDMS
TDMI data setup time
10
ns
tTDMH
TDMI data hold time
10
ns
(1)
(2)
6
fSMIN = minimum (fSIN, fSOUT).
fSMAX = maximum (fSIN, fSOUT).
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SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
6.7 Typical Characteristics
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
20k
40k
60k
80k
96k
0
20k
Frequency (Hz)
40k
60k
80k
96k
Frequency (Hz)
Figure 1. FFT With 1 kHz Input Tone at 0 dBFS
(12 kHz:192 kHz)
Figure 2. FFT With 1 kHz Input Tone at –60 dBFS
(12 kHz:192 kHz)
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k
0
24k
5k
Figure 3. FFT With 1 kHz Input Tone at 0 dBFS
(32 kHz:48 kHz)
15k
20k
24k
Figure 4. FFT With 1 kHz Input Tone at –60 dBFS
(32 kHz:48 kHz)
0
–60
–20
–70
–80
–40
–90
–60
–100
dBFS
dBFS
10k
Frequency (Hz)
Frequency (Hz)
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k
24k
0
5k
10k
15k
20k
24k
Frequency (Hz)
Frequency (Hz)
Figure 5. FFT With 1 kHz Input Tone at 0 dBFS
(44.1 kHz:48 kHz)
Figure 6. FFT With 1 kHz Input Tone at –60 dBFS
(44.1 kHz:48 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
10k
20k
30k
40k
48k
0
10k
Frequency (Hz)
Figure 7. FFT With 1 kHz Input Tone at 0 dBFS
(44.1 kHz:96 kHz)
30k
40k
48k
Figure 8. FFT With 1 kHz Input Tone at –60 dBFS
(44.1 kHz:96 kHz)
0
–60
–20
–70
–80
–40
–90
–60
–100
dBFS
dBFS
20k
Frequency (Hz)
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
20k
40k
60k
80k
0
96k
20k
Figure 9. FFT With 1 kHz Input Tone at 0d BFS
(44.1 kHz:192 kHz)
60k
80k
96k
Figure 10. FFT With 1 kHz Input Tone at –60 dBFS
(44.1 kHz:192 kHz)
0
–60
–20
–70
–80
–40
–90
–60
–100
dBFS
dBFS
40k
Frequency (Hz)
Frequency (Hz)
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k 22k
0
Frequency (Hz)
10k
15k
20k 22k
Frequency (Hz)
Figure 11. FFT With 1 kHz Input Tone at 0 dBFS
(48 kHz:44.1 kHz)
8
5k
Figure 12. FFT With 1 kHz Input Tone at –60 dBFS
(48 kHz:44.1 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
10k
20k
30k
40k
0
48k
10k
20k
30k
40k
48k
Frequency (Hz)
Frequency (Hz)
Figure 13. FFT With 1 kHz Input Tone at 0 dBFS
(48 kHz:96 kHz)
Figure 14. FFT With 1 kHz Input Tone at –60 dBFS
(48 kHz:96 kHz)
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
20k
40k
60k
80k
96k
0
20k
Figure 15. FFT With 1 kHz Input Tone at 0 dBFS
(48 kHz:192 kHz)
60k
80k
96k
Figure 16. FFT With 1 kHz Input Tone at –60 dBFS
(48 kHz:192 kHz)
0
–60
–20
–70
–80
–40
–90
–60
–100
dBFS
dBFS
40k
Frequency (Hz)
Frequency (Hz)
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k 22k
0
5k
10k
15k
20k 22k
Frequency (Hz)
Frequency (Hz)
Figure 17. FFT With 1 kHz Input Tone at 0 dBFS
(96 kHz:44.1 kHz)
Figure 18. FFT With 1 kHz Input Tone at –60 dBFS
(96 kHz:44.1 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k
24k
0
5k
10k
Frequency (Hz)
15k
20k
24k
Frequency (Hz)
Figure 19. FFT With 1 kHz Input Tone at 0 dBFS
(96 kHz:48 kHz)
Figure 20. FFT With 1 kHz Input Tone at –60 dBFS
(96 kHz:48 kHz)
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
20k
40k
60k
80k
96k
0
20k
40k
Frequency (Hz)
Figure 21. FFT With 1 kHz Input Tone at 0 dBFS
(96 kHz:192 kHz)
80k
96k
Figure 22. FFT With 1 kHz Input Tone at –60 dBFS
(96 kHz:192 kHz)
0
–60
–20
–70
–80
–40
–90
–60
–100
dBFS
dBFS
60k
Frequency (Hz)
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
1k
2k
3k
4k
5k
6k
0
Figure 23. FFT With 1 kHz Input Tone at 0 dBFS
(192 kHz:12 kHz)
10
1k
2k
3k
4k
5k
6k
Frequency (Hz)
Frequency (Hz)
Figure 24. FFT With 1 kHz Input Tone at –60 dBFS
(192 kHz:12 kHz)
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SBFS023C – JUNE 2003 – REVISED DECEMBER 2016
Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
2.5k
5k
7.5k
10k
12.5k
15k 16k
0
2.5k
5k
Frequency (Hz)
Figure 25. FFT With 1 kHz Input Tone at 0 dBFS
(192 kHz:32 kHz)
10k
12.5k
15k 16k
Figure 26. FFT With 1 kHz Input Tone at –60 dBFS
(192 kHz:12 kHz)
0
–60
–20
–70
–80
–40
–90
–60
–100
dBFS
dBFS
7.5k
Frequency (Hz)
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k 22k
0
5k
Frequency (Hz)
10k
15k
20k 22k
Frequency (Hz)
Figure 27. FFT With 1 kHz Input Tone at 0 dBFS
(192 kHz:44.1 kHz)
Figure 28. FFT With 1 kHz Input Tone at –60 dBFS
(192 kHz:44.1 kHz)
–60
0
–70
–20
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
5k
10k
15k
20k
24k
0
5k
10k
15k
20k
24k
Frequency (Hz)
Frequency (Hz)
Figure 29. FFT With 1 kHz Input Tone at 0 dBFS
(192 kHz:48 kHz)
Figure 30. FFT With 1 kHz Input Tone at –60 dBFS
(192 kHz:48 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
0
–60
–20
–70
–80
–40
–90
–100
dBFS
dBFS
–60
–80
–100
–110
–120
–130
–120
–140
–140
–150
–160
–160
–170
0
10k
20k
30k
40k
0
48k
10k
0
0
–20
–20
–40
–40
–60
–60
–80
–100
–140
–140
–160
–160
15k
48k
–100
–120
10k
40k
–80
–120
5k
30k
Figure 32. FFT With 1 kHz Input Tone at –60 dBFS
(192kHz:96 kHz)
dBFS
dBFS
Figure 31. FFT With 1 kHz Input Tone at 0 dBFS
(192 kHz:96 kHz)
0
20k
Frequency (Hz)
Frequency (Hz)
20k
24k
0
5k
Frequency (Hz)
10k
15k
20k 22k
Frequency (Hz)
Figure 33. FFT With 20 kHz Input Tone at 0 dBFS
(44.1 kHz:48 kHz)
Figure 34. FFT With 20 kHz Input Tone at 0 dBFS
(48 kHz:44.1 kHz)
–20
–20
–40
–40
–60
–60
dBFS
dBFS
0
–80
–80
–100
–100
–120
–120
–140
–140
–160
–160
0
10k
20k
30k
40k
48k
0
10k
15k
20k
24k
Frequency (Hz)
Frequency (Hz)
Figure 35. FFT With 20 kHz Input Tone at 0 dBFS
(48 kHz:96 kHz)
12
5k
Figure 36. FFT With 20 kHz Input Tone at 0 dBFS
(96 kHz:48 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
–100
Total Harmonic Distortion+Noise (dB)
0
–20
–40
dBFS
–60
–80
–100
–120
–140
–160
0
20k
40k
60k
80k
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–140
96k
–120
Figure 37. FFT With 80 kHz Input Tone at 0 dBFS
(192 kHz:192 kHz)
–60
–40
–20
0
–100
Total Harmonic Distortion+Noise (dB)
Total Harmonic Distortion+Noise (dB)
–80
Figure 38. THD+N vs Input Amplitude fIN = 1 kHz
(44.1 kHz:48 kHz)
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–140
–120
–100
–80
–60
–40
–20
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–140
0
–120
Input Amplitude (dBFS)
–100
–80
–60
–40
–20
0
Input Amplitude (dBFS)
Figure 39. THD+N vs Input Amplitude fIN = 1 kHz
(48 kHz:44.1 kHz)
Figure 40. THD+N vs Input Amplitude fIN = 1 kHz
(48 kHz:96 kHz)
–100
–100
Total Harmonic Distortion+Noise (dB)
Total Harmonic Distortion+Noise (dB)
–100
Input Amplitude (dBFS)
Frequency (Hz)
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–140
–120
–100
–80
–60
–40
–20
0
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–140
–120
–100
–80
–60
–40
–20
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 41. THD+N vs Input Amplitude fIN = 1 kHz
(96 kHz:48 kHz)
Figure 42. THD+N vs Input Amplitude fIN = 1 kHz
(44.1 kHz:192 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
–100
Total Harmonic Distortion+Noise (dB)
Total Harmonic Distortion+Noise (dB)
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–140
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–120
–100
–80
–60
–40
–20
0
0
5k
Input Amplitude (dBFS)
Figure 43. THD+N vs Input Amplitude fIN = 1 kHz
(192 kHz:44.1 kHz)
Total Harmonic Distortion+Noise (dB)
Total Harmonic Distortion+Noise (dB)
20k
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
0
5k
10k
15k
20k
0
5k
Input Frequency (Hz)
10k
15k
20k
Input Frequency (Hz)
Figure 45. THD+N vs Input Frequency With
0 dBFS Input = 1 kHz (48 kHz:44.1 kHz)
Figure 46. THD+N vs Input Frequency With 0 dBFS
(48 kHz:96 kHz)
–100
Total Harmonic Distortion+Noise (dB)
–100
Total Harmonic Distortion+Noise (dB)
15k
Figure 44. THD+N vs Input Frequency With 0 dBFS Input
(44.1 kHz:48 kHz)
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–150
0
5k
10k
15k
20k
0
Input Frequency (Hz)
5k
10k
15k
20k
Input Frequency (Hz)
Figure 47. THD+N vs Input Frequency With 0 dBFS
(96 kHz:48 kHz)
14
10k
Input Frequency (Hz)
Figure 48. THD+N vs Input Frequency With 0 dBFS
(44.1 kHz:192 kHz)
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Typical Characteristics (continued)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
–105
–110
Output Amplitude (dBFS)
Total Harmonic Distortion+Noise (dB)
–100
–115
–120
–125
–130
–135
–140
–145
–150
0
5k
10k
15k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–130 –120 – 110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
20k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
Figure 50. Linearity With fIN = 200 Hz (44.1 kHz:48 kHz)
Output Amplitude (dBFS)
Output Amplitude (dBFS)
Figure 49. THD+N vs Input Frequency With 0 dBFS
(192 kHz:44.1 kHz)
– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10
Input Amplitude (dBFS)
0
Input Amplitude (dBFS)
Figure 51. Linearity With fIN = 200 Hz (48 kHz:44.1 kHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
Figure 52. Linearity With fIN = 200 Hz (48 kHz:96 kHz)
Output Amplitude (dBFS)
Output Amplitude (dBFS)
0
Input Amplitude (dBFS)
Input Frequency (Hz)
–130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–130 –120 – 110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 53. Linearity With fIN = 200 Hz (96 kHz:48 kHz)
Figure 54. Linearity With fIN = 200 Hz (44.1 kHz:192 kHz)
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Typical Characteristics (continued)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
dBFS
Output Amplitude (dBFS)
TA = 25°C, VDD = VIO = 3.3 V (unless otherwise noted).
– 130 – 120 – 110 – 100 – 90 – 80 – 70 – 60 – 50 – 40 – 30 – 20 – 10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
192kHz:48kHz
192kHz:32kHz
192kHz:96kHz
0
0
10k
20k
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
–0.11
–0.12
–0.13
–0.14
–0.15
5k
10k
15k
50k
60k
20k 22k
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
–0.11
–0.12
–0.13
–0.14
–0.15
0
5k
Input Frequency (Hz)
10k
15k
20k 22k
Input Frequency (Hz)
Figure 57. Passband Ripple (48 kHz:48 kHz)
16
40k
Figure 56. Frequency Response With 0 dBFS Input
(dBFS)
(dBFS)
Figure 55. Linearity With fIN = 200 Hz (192 kHz:44.1 kHz)
0
30k
Frequency (Hz)
Input Amplitude (dBFS)
Figure 58. Passband Ripple (192 kHz:48 kHz)
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7 Detailed Description
7.1 Overview
The SRC4190 device is an asynchronous sample rate converter (ASRC) designed for professional audio
applications. Operation at input and output sampling frequencies up to 212 kHz is supported, with an input-tooutput sampling ratio from 16:1 to 1:16. Excellent dynamic range and total harmonic distortion plus noise
(THD+N) are achieved by employing high performance and linear phase digital filtering. Digital filtering options
allow for lower group delay processing.
The audio input and output ports support standard audio data formats, as well as a TDM interface mode. 24-,
20-, 18-, and 16-bit word lengths are supported. Both ports may operate in slave mode, deriving their word and
bit clocks from external input and output devices. Alternatively, one port may operate in master mode while the
other remains in slave mode. In master mode, the LRCK and BCK clocks are derived from the reference clock
input (RCKI). The flexible configuration of the input and output ports allows connection to a wide variety of audio
data converters, interface devices, digital signal processors, and programmable logic.
A bypass mode is included, which allows audio data to be passed directly from the input port to the output port,
bypassing the ASRC function. The bypass option is useful for passing through encoded or compressed audio
data, or nonaudio control or status data.
A soft mute function is available providing artifact-free operation while muting the audio output signal. The mute
attenuation is typically –128 dB.
The output port data is clocked by either the audio data source in slave mode, or by the SRC4190 in master
mode. The input data is passed through interpolation filters which up-sample the data, which is then passed on
to the re-sampler. The rate estimator compares the input and output sampling frequencies by comparing LRCKI,
LRCKO, and a reference clock. The results include an offset for the FIFO pointer and the coefficients needed for
re-sampling function. The output of the re-sampler is then passed on to the decimation filter. The decimation filter
performs down-sampling and anti-alias filtering functions.
7.2 Functional Block Diagram
LRCKI
BCKI
SDIN
Audio
Input
Port
fSIN
Interpolation
Filters
16fSIN
Re-Sampler
16fSOUT
MODE [2:0]
IFMT [2:0]
REFCLK
OFMT [1:0]
OWL [1:0]
MUTE
LRCKI
Control
Logic
Rate
Estimator
BYPAS
LGRP
RST
LRCKO
RDY
fSOUT
Decimation
Filters
LRCKO
BCKO
SDOUT
Audio
Output
Port
TDMI
VDD
DGND
RCKI
Reference
Clock
Power
REFCLK
VIO
DGND
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7.3 Feature Description
7.3.1 Soft Mute Function
The soft mute function of the SRC4190 may be invoked by forcing the MUTE pin high. The soft mute function
slowly attenuates the output signal level down to all zeroes plus ±4 LSB of dither. This provides an artifact-free
muting of the audio output port.
7.3.2 Ready Output
The SRC4190 includes an active low ready output (RDY). This is an output from the rate estimator block, which
indicates that the input-to-output sampling frequency ratio has been determined. The ready signal can be used
as a flag or indicator output. The ready signal can also be connected to the active high MUTE pin to provide an
auto-mute function, so that the output port is muted when the rate estimator is in transition.
7.4 Device Functional Modes
7.4.1 Bypass Mode
The SRC4190 includes a bypass function, which routes the input port data directly to the output port, bypassing
the ASRC function. Bypass mode may be invoked by forcing the BYPAS pin high. For normal ASRC operation,
the BYPAS pin must be set to 0.
No dithering is applied to the output data in bypass mode; digital attenuation and mute functions are also
unavailable in this mode.
7.4.2 Audio Port Modes
The SRC4190 supports seven serial port modes, shown in Table 1. The audio port mode is selected using the
MODE0, MODE1, and MODE2 pins.
In slave mode, the port LRCK and BCK clocks are configured as inputs, and receive their clocks from an external
audio device. In master mode, the LRCK and BCK clocks are configured as outputs, being derived from the
reference clock input (RCKI). Only one port can be set to master mode at any given time, as indicated in Table 1.
Table 1. Setting the Serial Port Modes
MODE2
MODE1
MODE0
0
0
0
Both input and output ports are slave mode
SERIAL PORT MODE
0
0
1
Output port is master mode with RCKI = 128 fS
0
1
0
Output port is master mode with RCKI = 512 fS
0
1
1
Output port is master mode with RCKI = 256 fS
1
0
0
Both input and output ports are slave mode
1
0
1
Input port is master mode with RCKI = 128 fS
1
1
0
Input port is master mode with RCKI = 512 fS
1
1
1
Input port is master mode with RCKI = 256 fS
7.4.3 Input Port Operation
The audio input port is a three-wire synchronous serial interface that may operate in either slave or master mode.
The SDIN pin 4 is the serial audio data input. Audio data is input at this pin in one of three standard audio data
formats: Philips I2S, Left Justified, or Right Justified. The audio data word length may be up to 24 bits for I2S and
Left Justified formats, while the Right Justified format supports 16, 18, 20, or 24-bit data. The data formats are
shown in Figure 59, while critical timing parameters are shown in Figure 60 and listed in Switching
Characteristics.
The bit clock is either an input or output at BCKI. In slave mode, BCKI is configured as an input pin, and may
operate at rates from 32 fS to 128 fS, with a minimum of one clock cycle per data bit. In master mode, BCKI
operates at a fixed rate of 64 fS.
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Right Channel
Left Channel
LRCKO
BCKI
SDIN
MSB
LSB
MSB
LSB
(a) Left Justified Data Format
LRCKI
BCKI
MSB
SDIN
LSB
MSB
LSB
(b) Right Justified Data Format
LRCKI
BCKI
SDIN
MSB
LSB
MSB
LSB
(c) I2S Data Format
1/fS
Figure 59. Input Data Formats
LRCKI
tLRIS
tSIH
BCKI
tLDIS
tSIL
SDIN
tLDIH
Figure 60. Input Port Timing
The left and right word clock (LRCKI), may be configured as an input or output pin. In slave mode, LRCKI is an
input pin, while in master mode LRCKI is an output pin. In either case, the clock rate is equal to the input
sampling frequency (fS). The LRCKI duty cycle is fixed to 50% for master mode operation. Table 2 illustrates data
format selection for the input port. The IFMT0, IFMT1, and IFMT2 pins are utilized to set the input port data
format.
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Table 2. Input Port Data Format Selection
IFMT2
IMFT1
IMFT0
0
0
0
24-Bit Left Justified
INPUT PORT DATA FORMAT
0
0
1
24-Bit I2S
0
1
0
Unused
0
1
1
Unused
1
0
0
16-Bit Right Justified
1
0
1
18-Bit Right Justified
1
1
0
20-Bit Right Justified
1
1
1
24-Bit Right Justified
7.4.4 Output Port Operation
The audio output port is a four-wire synchronous serial interface that may operate in either slave or master
mode. The SDOUTpin is the serial audio data output. Audio data is output at this pin in one of four data formats:
Philips I2S, Left Justified, Right Justified, or TDM. The audio data word length may be 16, 18, 20, or 24 bits. For
all word lengths, the data is triangular PDF dithered from the internal 28-bit data path. The data formats (with the
exception of TDM mode) are shown in Figure 61, while critical timing parameters are shown in Figure 62 and
listed in Switching Characteristics. The TDM format and timing are shown in Figure 66 and Figure 66,
respectively, while examples of standard TDM configurations are shown in Figure 69 and Figure 70. The bit clock
is either input or output at BCKO. In slave mode, BCKO is configured as an input pin, and may operate at rates
from 32 fS to 128 fS, with a minimum of one clock cycle for each data bit. The exception is the TDM mode, where
the BCKO must operate at N × 64fS, where N is equal to the number of SRC4190 devices included on the TDM
interface. In master mode, BCKO operates at a fixed rate of 64 fS for all data formats except TDM, where BCKO
operates at the reference clock (RCKI) frequency. Additional information regarding TDM mode operation is
included in Application and Implementation.
Left Channel
Right Channel
LRCKO
BCKO
SDOUT
MSB
LSB
MSB
LSB
(a) Left Justified Data Format
LRCKO
BCKO
MSB
SDOUT
LSB
MSB
LSB
(b) Right Justified Data Format
LRCKO
BCKO
SDOUT
MSB
LSB
MSB
LSB
(c) I2S Data Format
1/fS
Figure 61. Output Data Formats
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LRCKO
tSOH
BCKO
tSOL
tDOPD
SDOUT
tDOH
Figure 62. Output Port Timing
The left and right word clock (LRCKO), may be configured as an input or output pin. In slave mode, LRCKO is an
input pin, while in master mode it is an output pin. In either case, the clock rate is equal to the output sampling
frequency (fS). The clock duty cycle is fixed to 50% for I2S, Left Justified, and Right Justified formats in master
mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode.
Table 3 shows data format selection for the output port. The OFMT0, OFMT1, OWL0, and OWL1 inputs are
utilized to set the output port data format and word length.
Table 3. Output Port Data Format Selection
OFMT1
OFMT0
OUTPUT PORT DATA FORMAT
0
0
Left Justified
0
1
I2S
1
0
TDM
1
1
Right Justified
OWL1
OWL2
0
0
24 bits
0
1
20 bits
1
0
18 bits
1
1
16 bits
OUTPUT PORT DATA WORD LENGTH
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The audio input and output ports can handle 16-, 18-, 20-, or 24-bit right-justified PCM serial data, as well as
24-bit I2S or left-justified PCM serial data at up to 212-kHz sampling rate. A TDM format is also available. Both
input and output can operate in slave mode, or one can operate as a master while the other operates as a slave.
A 16:1 or 1:16 ratio is the maximum supported between the input and output audio sampling rates.
8.2 Typical Application
From
Control
Logic
SRC4190
1
2
3
Reference
Clock
4
5
6
7
8
9
10
11
12
13
14
Audio Input
Device
From/To
Control
Logic
LGRP
RCKI
NC
MODE2
MODE1
MODE0
SDIN
BCKI
LRCKI
VIO
DGND
BYPAS
IFMT0
IFMT1
IFMT2
RST
MUTE
BCKO
LRCKO
SDOUT
VDD
DGND
TDMI
OFMT0
OFMT1
OWL0
OWL1
RDY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD = +3.3V
VIO = +1.65V to VDD
10µF
Audio Output
Device
To Pin 7
To Pin 22
To Pin 8
To Pin 21
0.1µF
0.1µF
10µF
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Figure 63. Typical Connection Diagram for the SRC4190
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
Table 4. Design Parameters
PARAMETER
22
VALUE
VDD supply voltage, VDD
3.3 V
VIO supply voltage, VIO
1.65 V to VDD
Bypass capacitors
0.1 µF and 10 µF
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8.2.2 Detailed Design Procedure
The typical connection diagram for the SRC4190 is shown in Figure 63. Recommended values for power supply
bypass capacitors are included. These capacitors must be placed as close to the IC package as possible.
8.2.2.1 Reference Clock
The SRC4190 requires a reference clock for operation. The reference clock is applied at the RCKI input.
Figure 64 shows the reference clock connections and requirements for the SRC4190. The reference clock may
operate at 128 fS, 256 fS, or 512 fS, where fS is the input or output sampling frequency. The maximum external
reference clock input frequency is 50 MHz.
SRC4190
RCKI
2
From External
Clock Source
50MHz max
tRCKIP
tRCKIP > 20ns min
tRCKIH > 0.4 tRCKIP
tRCKIL > 0.4 tRCKIP
RCKI
tRCKIH
tRCKIL
Figure 64. Reference Clock Input Connections and Timing Requirements
8.2.2.2 Interfacing to Digital Audio Receivers and Transmitters
The SRC4190 input and output ports are designed to interface to a variety of audio devices, including receivers
and transmitters commonly used for AES/EBU, S/PDIF, and CP1201 communications. Texas Instruments
manufactures the DIR1703 digital audio interface receiver and the DIT4096 and DIT4192 digital audio
transmitters to address these applications.
Figure 65 illustrates interfacing the DIR1703 to the SRC4190 input port. The DIR1703 operates from a single
3.3‑V supply, which requires the VIO supply for the SRC4190 to be set to 3.3-V for interface compatibility.
SRC4190
DIR1703
LRCKI
LRCKO
AES3, S/PDIF
Input
RCV
DIN
BCKO
BCKI
DATA
SDIN
SCKO
RCLI
Clock
Generator
Clock
Select
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Figure 65. Interfacing the SRC4190 to the DIR1703 Digital Audio Interface Receiver
Figure 66 shows the interface between the SRC4190 output port and the DIT4096 or DIT4192 audio serial port.
Once again, the VIO supplies for both the SRC4190, DIT4096, and DIT4192 are set to 3.3 V for compatibility.
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DIT4096, DIT4192
SRC4190
LRCKO
SYNC
TX+
BCKO
SCLK
TX–
AES3, S/PDIF
OUTPUT
SDATA
SDOUT
RCKI
MCLK
REF Clock
Generator
DIT Clock
Generator
Clock
Select
Copyright © 2016, Texas Instruments Incorporated
Figure 66. Interfacing the SRC4190 to the DIT4096 and DIT4192 Digital Audio Interface Transmitter
Like the SRC4190 output port, the DIT4096 and DIT4192 audio serial port may be configured as a master or
slave. In cases where the SRC4190 output port is set to master mode, TI recommends using the reference clock
source (RCKI) as the master clock source (MCLK) for the DIT4096 and DIT4192, to ensure that the transmitter is
synchronized to the SRC4190 output port data.
8.2.2.3 TDM Applications
The SRC4190 supports a TDM output mode, which allows multiple devices to be daisy-chained together to
create a serial frame. Each device occupies one sub-frame within a frame, and each sub-frame carries two
channels (Left followed by Right). Each sub-frame is 64 bits long, with 32 bits allotted for each channel. The
audio data for each channel is Left Justified within the allotted 32 bits. Figure 66 illustrates the TDM frame
format, while Figure 68 shows the TDM input timing parameters, which are listed in Switching Characteristics.
LRCKO
BCKO
SDOUT
Left
Right
Left
Sub-Frame 1
Right
Sub-Frame 2
Left
Right
Sub-Frame N
One Frame = 1/fs
N = Number of Daisy-Chained Devices
One Sub-Frame contains 64 bits, with 32 bits per channel.
For each channel, the audio data is Left Justified, MSB first format, with the word length determined by OWL[1:0].
Figure 67. TDM Frame Format
24
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tLROS
LRCKO
tLROH
BCKO
tTDMS
TDMI
tTDMH
Figure 68. Input Timing for TDM Mode
The frame rate is equal to the output sampling frequency. The BCKO frequency for the TDM interface is
N × 64 fS, where N is the number of devices included in the daisy chain. For master mode, the output BCKO
frequency is fixed to the reference clock (RCKI) input frequency. The number of devices that can be daisychained in TDM mode is dependent upon the output sampling frequency and the BCKO frequency, leading to the
numerical relationship in Equation 1
Number of daisy-chained devices = (fBCKO / fS) / 64
where
•
•
fBCKO = Output port bit clock (BCKO) (27.136-MHz maximum)
fS = Output port sampling (LRCKO) frequency (212-kHz maximum)
(1)
This relationship holds true for both slave and master modes. Figure 69 and Figure 70 show typical connection
schemes for the TDM mode. Although the TMS320C671x DSP family is shown as the audio processing engine in
these figures, other TI digital signal processors with a multi-channel buffered serial port (McBSPTM) may also
function with this arrangement. Interfacing to processors from other manufacturers is also possible. See
Figure 62, along with the equivalent serial port timing diagrams shown in the DSP data sheet, to determine
compatibility.
SRC4190
Slave #N
TDMI
SRC4190
Slave #2
SDOUT
DRn
LRCKO
LRCKO
LRCKO
FSRn
BCKO
BCKO
BCKO
RCKI
RCKI
RCKI
SDOUT
TDMI
TMS320C671x
McBSP
SRC4190
Slave #1
SDOUT
TDMI
n = 0 or 1
CLKRn
CLKIN or CLKSn
Clock
Generator
Copyright © 2016, Texas Instruments Incorporated
Figure 69. TDM Interface With All Devices as Slaves
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SRC4190
Master
TDMI
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SRC4190
Slave #2
SDOUT
TDMI
TMS320C671x
McBSP
SRC4190
Slave #1
SDOUT
TDMI
SDOUT
DRn
FSRn
LRCKO
LRCKO
LRCKO
BCKO
BCKO
BCKO
RCKI
RCKI
RCKI
n = 0 or 1
CLKRn
CLKIN or CLKSn
Clock
Generator
Copyright © 2016, Texas Instruments Incorporated
Figure 70. TDM Interface With One Device as Master to Multiple Slaves
8.2.2.4 Pin Compatibility With the Analog Devices AD1895 and AD1896
The SRC4190 is pin and function-compatible with the AD1895 and AD1896 when observing the guidelines
indicated in the following paragraphs.
8.2.2.4.1 Power Supplies
To ensure compatibility, the VDD_IO and VDD_CORE supplies of the AD1895 and AD1896 must be set to 3.3 V,
while the VIO and VDD supplies of the SRC4190 must be set to 3.3 V.
8.2.2.4.2 Pin 1 Connection
For the AD1895, pin 1 is not connected. For the SRC4190, pin 1 (LGRP) functions as the low group delay
selection input, and must not be left unconnected. LGRP must be connected to either digital ground or the VIO
supply, dependent upon the desired group delay.
8.2.2.4.3 Crystal Oscillator
The SRC4190 does not have an on-chip crystal oscillator. An external reference clock is required at the RCKI
pin.
8.2.2.4.4 Reference Clock Frequency
The reference clock input frequency for the SRC4190 must be no higher than 30 MHz, in order to match the
master clock frequency specification of the AD1895 and AD1896. In addition, the SRC4190 does not support the
768-fS reference clock rate.
8.2.2.4.5 Master Mode Maximum Sampling Frequency
When the input or output ports are set to master mode, the maximum sampling frequency must be limited to
96 kHz in order to support the AD1895 and AD1896 specification. This is despite the fact that the SRC4190
supports a maximum sampling frequency of 212 kHz in master mode. The user must consider building an option
into his or her design to support the higher sampling frequency of the SRC4190.
8.2.2.4.6 Matched Phase Mode
Due to the internal architecture of the SRC4190, it does not require or support the matched phase mode of the
AD1896. Given multiple SRC4190 devices, if all reference clock (RCKI) inputs are driven from the same clock
source, the devices is phase matched.
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–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
dBFS
dBFS
8.2.3 Application Curves
–110
–120
–110
–120
–130
–130
–140
–140
–150
–150
–160
–160
–170
–170
0
5k
10k
15k
20k
24k
0
Frequency (Hz)
10k
20k
30k
40k
48k
Frequency (Hz)
Figure 71. FFT With 1 kHz Input Tone at –60 dBFS
(44.1 kHz:48 kHz)
Figure 72. FFT With 1 kHz Input Tone at –60 dBFS
(44.1 kHz:96 kHz)
9 Power Supply Recommendations
The SRC4190 has two supply inputs (VDD and VIO). VDD operates at 3.3 V, while VIO can operate at either
1.8 V or 3.3 V to allow interaction with a range of digital devices. TI recommends using a decoupling capacitor
for each supply pin placed as close to the pin as possible.
10 Layout
10.1 Layout Guidelines
10.1.1 Power Supply Pins
Place power supply decoupling capacitors as close to the supply pins as possible to minimize noise on device
supplies. TI recommends values of 10 µF and 0.1 µF for these capacitors.
10.1.2 Digital Interface
With high frequency clocks being input or produced on the digital interface pins, reflections can become an issue,
causing system noise. A series resistor in the tens of ohms can be placed on each trace to minimize reflections.
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10.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around SRC4190 and connect to lower main PCB
ground plane by multiple vias
Reference
Clock
Audio Input
Device
+1.65 to Vdd
1
LGRP
MODE2
28
2
RCKI
MODE1
27
3
NC
MODE0
26
4
SDIN
BCKO
25
5
BCKI
LRCKO
24
6
LRCKI
SDOUT
23
7
VIO
Vdd
8
22
SRC4190
Control Logic
+3.3V
+
+
10 F
Audio Output
Device
0.1 F
8
DGND
DGND
21
9
BYPAS
TDMI
20
10
IFMT0
OFMT0
19
11
IFMT1
OFMT1
18
12
IFMT2
OWL0
17
13
RST
OWL1
16
14
MUTE
RDY
15
0.1 F
10 F
Control Logic
Top Layer Ground Pour
Top Layer Signal Traces
Control Logic
Via to bottom Ground Plane
Pad to top layer ground pour
Figure 73. Diagram of an Example Layout
28
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• DIT4096 96-kHz Digital Audio Transmitter (SBOS225)
• DIT4192 192-kHz Digital Audio Transmitter (SBOS229)
• SRC4190/92/93EVM, User's Guide (SBAU088)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SRC4190IDB
ACTIVE
SSOP
DB
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SRC4190I
SRC4190IDBR
ACTIVE
SSOP
DB
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SRC4190I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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