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TAS5721
SLOS739A – JULY 2012 – REVISED MARCH 2016
TAS5721 Digital Audio Power Amplifier With EQ, DRC, 2.1 Support, and Headphone/Line
Driver
1 Features
•
1
•
•
2 Applications
Audio Input/Output
– 10 W x 2 into 8 Ω With PVDD = 24 V
– 8 W x 2 + 12 W x 1 into 8 Ω With PVDD = 24
V
– Supports 2.0, Single Device 2.1, and Mono
Modes
– Supports 8-kHz to 48-kHz Sample Rate
(LJ/RJ/I2S)
– Integrated DirectPath™ Headphone Amplifier
and 2 VRMS Line Driver
Audio/PWM Processing
– Independent Channel Volume Controls With
24-dB to Mute in 0.5 dB Steps
– Separate Dynamic Range Control for Satellite
and Sub Channels
– 21 Programmable Biquads for Speaker EQ
– Programmable Two-Band Dynamic Range
Control
– Support for 3D Effects
General Features
– I2C™ Serial Control Interface Operational
Without MCLK
– Configurable I2C Address (0x34 or 0x36)
– Automatic Sample Rate Detection
– Thermal and Short-Circuit Protection
– Wide PVDD Supply Range (4.5 V to 24 V)
LED/LCD TVs, Soundbar, Docking Stations, PC
Speakers
3 Description
The TAS5721 is an efficient, digital-input audio
amplifier for driving 2.0 speaker systems configured
as a bridge tied load (BTL), 2.1 systems with two
satellite speakers and one subwoofer, or in PBTL
systems driving a single speaker configured as a
parallel bridge tied load (PBTL). One serial data input
allows processing of up to two discrete audio
channels and seamless integration to most digital
audio processors and MPEG decoders. The device
accepts a wide range of input data formats and
sample rates. A fully programmable data path routes
these channels to the internal speaker drivers.
The TAS5721 is a slave-only device, receiving all
clocks from external sources. The TAS5721 operates
with a PWM carrier frequency between a 384-kHz
switching rate and a 288-KHz switching rate,
depending on the input sample rate. Oversampling,
combined with a fourth-order noise shaper, provides
a flat noise floor and excellent dynamic range from 20
Hz to 20 kHz.
An integrated ground centered DirectPath™
combination headphone amplifier and 2VRMS line
driver is integrated in the TAS5721.
Device Information(1)
PART NUMBER
TAS5721
PACKAGE
HTSSOP (48)
BODY SIZE (NOM)
12.50 mm × 6.10
mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Power vs. PVDD in 2.0 Mode
Signal Processing Flow
TA = 25°C
14
Output Power (W)
12
10
8
6
RL = 8Ÿ THD+N = 1%
4
RL = 8Ÿ THD+N = 10%
RL = 6Ÿ THD+N = 1%
RL = 6Ÿ THD+N = 10%
2
RL = 4Ÿ THD+N = 1%
RL = 4Ÿ THD+N = 10%
0
8
10
12
14
16
18
20
22
24
Supply Voltage (V)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5721
SLOS739A – JULY 2012 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics – I/O Pin Characteristics... 7
Master Clock Characteristics .................................... 8
Speaker Amplifier Characteristics............................. 8
Headphone Amplifier and Line Driver
Characteristics ........................................................... 9
7.9 Protection Characteristics ......................................... 9
7.10 I2C Serial Control Port Requirements and
Specifications ............................................................ 9
7.11 Serial Audio Port Timing ......................................... 9
7.12 Typical Characteristics .......................................... 12
8
9
Parameter Measurement Information ................ 20
Detailed Description ............................................ 21
9.1 Overview ................................................................. 21
9.2
9.3
9.4
9.5
9.6
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps ........................................................
21
22
35
36
38
10 Application and Implementation........................ 57
10.1 Application Information.......................................... 57
10.2 Typical Application ................................................ 58
10.3 System Examples ................................................. 63
11 Power Supply Recommendations ..................... 68
11.1 DVDD and AVDD Supplies ................................... 68
11.2 PVDD Power Supply ............................................. 68
12 Layout................................................................... 68
12.1 Layout Guidelines ................................................. 68
12.2 Layout Example .................................................... 69
13 Device and Documentation Support ................. 70
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
70
70
70
70
70
70
14 Mechanical, Packaging, and Orderable
Information ........................................................... 70
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2012) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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5 Device Comparison Table
TAS5721
TAS5731M
Max. Power to Single-Ended Load
10
18
TAS5729MD
TAS5727
Max. Power to Bridge Tied Load
15
37
20
35
Max. Power to Parallel Bridge Tied Load
Min. Supported Single-Ended Load
30
70
40
70
4
2
Min. Supported Bridge Tied Load
8
4
4
4
Min. Supported Parallel Bridge Tied Load
4
2
4
2
Open
Closed/Open Loop
Open
Open
Open
Max Speaker Outputs (#)
3
3
2
2
Headphone Channels
Yes
No
Yes
No
Architecture
Class D
Class D
Class D
Class D
Dynamic Range Control (DRC)
2-Band DRC
2-Band DRC
2-Band AGL
2-Band AGL
Biquads (EQ)
21
21
28
28
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6 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP
Top View
PGND
1
48 SPK_OUTB
SPK_OUTA
2
47 BSTRPB
BSTRPA
3
46 BSTRPC
PVDD
4
45 SPK_OUTC
TEST1
5
44 PGND
TEST2
6
43 SPK_OUTD
DR_INA
7
42 BSTRPD
DR_OUTA
8
41 PVDD
DR_OUTB
9
40 GVDD_REG
DR_INB 10
39 DR_SD
DR_VSS 11
38 SSTIMER
DR_CN 12
PowerPAD
DR_CP 13
37 AVDD_REG2
36 AGND
DRVDD 14
35 DGND
PLL_GND 15
34 DVDD
PLL_FLTM 16
33 TEST3
PLL_FLTP 17
32 RST
31 NC
AVDD_REG1 18
AVDD 19
30 SCL
ADR/FAULT 20
29 SDA
MCLK 21
28 SDIN
OSC_RES 22
27 SCLK
OSC_GND 23
26 LRCLK
DVDD_REG 24
25 PDN
Pin Functions
PIN
NAME
NO.
TYPE (1)
TERMINATION
DESCRIPTION
ADR/FAULT
20
DI/DO
-
Dual function terminal which sets the LSB of the I2C address to 0 if pulled
to GND, 1 if pulled to DVDD. If configured to be a fault output by the
methods described in I²C Address Selection and Fault Output, this terminal
is pulled low when an internal fault occurs. A pull-up or pull-down resistor is
required, as is shown in the Typical Application Circuit Diagrams.
AGND
36
P
-
Ground reference for analog circuitry (2)
AVDD
19
P
-
Power supply for internal analog circuitry
AVDD_REG1
18
P
-
Voltage regulator derived from AVDD supply (3)
AVDD_REG2
37
P
-
Voltage regulator derived from AVDD supply (3)
3, 42, 46,
47
P
-
Connection points for the bootstrap capacitors, which are used to create a
power supply for the high-side gate drive of the device
DGND
35
P
-
Ground reference for digital circuitry (2)
DR_CN
12
P
-
Negative terminal for capacitor connection used in headphone amplifier
and line driver charge pump
DR_CP
13
P
-
Positive terminal for capacitor connection used in headphone amplifier and
line driver charge pump
DR_INx
7, 10
AI
-
Input for channel A or B of headphone amplifier or line driver
DR_OUTx
8, 9
AO
-
Output for channel A or B of headphone amplifier or line driver
39
DI
-
Places the headphone amplifier/line driver in shutdown when pulled low.
BSTRPx
DR_SD
(1)
(2)
(3)
4
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
This terminal should be connected to the system ground
This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external
circuitry.
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
TERMINATION
DESCRIPTION
DR_VSS
11
P
-
Negative supply generated by charge pump for ground centered
headphone and line driver output
DRVDD
14
P
-
Power supply for internal headphone and line driver circuitry
DVDD
34
P
-
Power supply for the internal digital circuitry
DVDD_REG
24
P
-
Voltage regulator derived from DVDD supply (3)
GVDD_REG
40
P
-
Voltage regulator derived from PVDD supply (3)
LRCLK
26
DI
Pulldown
Word select clock for the digital signal that is active on the input data line of
the serial port
MCLK
21
DI
Pulldown
Master clock used for internal clock tree and sub-circuit and state machine
clocking
NC
31
-
-
Not connected inside the device (all no connect terminals should be
connected to ground)
OSC_GND
23
P
-
Ground reference for oscillator circuitry (this terminal should be connected
to the system ground)
OSC_RES
22
AO
-
Connection point for oscillator trim resistor
Quick powerdown of the device that is used upon an unexpected loss of
PVDD or DVDD power supply in order to quickly transition the outputs of
the speaker amplifier to a 50/50 duty cycle. This quick powerdown feature
avoids the audible anamolies that would occur as a result of loss of either
of the supplies. If this pin is used to place the device into quick powerdown
mode, the RST pin of the device must be toggled before the device is
brought out of quick powerdown.
PDN
25
DI
Pullup
PGND
1
P
-
Ground reference for power device circuitry (2)
PLL_FLTM
16
AI/AO
-
Negative connection point for the PLL loop filter components
PLL_FLTP
17
AI/AO
-
Positive connection point for the PLL loop filter components
PLL_GND
15
P
-
Ground reference for PLL circuitry (this terminal should be connected to the
system ground)
PowerPAD
-
P
-
Thermal and ground pad thatprovides both an electrical connection to the
ground plane and a thermal path to the PCB for heat dissipation. This pad
must be grounded to the system ground.
Power supply for internal power circuitry
PVDD
4, 41
P
-
RST
32
DI
Pullup
SCL
30
DI
-
SCLK
27
DI
Pulldown
SDA
29
DI/DO
-
SDIN
Places the device in reset when pulled low
I2C serial control port clock
Bit clock for the digital signal that is active on the input data line of the
serial data port
I2C serial control port data
28
DI
Pulldown
2, 43, 45,
48
AO
-
SSTIMER
38
AI
-
Connection point for the capacitor that is used by the ramp timing circuit,
as described in Output Mode and MUX Selection
TEST1
5
DO
-
Used by TI for testing during device production (this terminal must be left
floating)
TEST2
6
DO
-
Used by TI for testing during device production (this terminal must be left
floating)
TEST3
33
DI
-
Used by TI for testing during device production (this terminal must be
connected to GND)
SPK_OUTx
Data line to the serial data port
Speaker amplifier outputs
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted).
Supply
voltage
(1)
MIN
MAX
UNIT
DVDD, AVDD, DRVDD
–0.3
3.6
V
PVDD
–0.3
30
V
–0.3
DRVDD + 6
V
3.3-V digital input
–0.5
DVDD + 0.5
5-V tolerant (2) digital input (except MCLK)
–0.5
DVDD + 2.5 (3)
5-V tolerant MCLK input
–0.5
AVDD + 2.5 (3)
DR_INx
Input voltage
32 (4)
SPK_OUTx to GND
BSTRPx to GND
39
Operating free-air temperature
Storage temperature, Tstg
(1)
V
V
(4)
V
0
85
°C
–40
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RST, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6 V.
DC voltage + peak AC waveform measured at the pin should be below the allowed limit for all conditions.
(2)
(3)
(4)
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
xVDD
Digital, analog, headphone supply
voltage
3
3.3
3.6
PVDD
Half-bridge supply voltage
8
VIH
High-level input voltage
5-V tolerant
VIL
Low-level input voltage
5-V tolerant
TA
Operating ambient temperature
Operating junction temperature
TJ
(2)
UNIT
26.4 (1)
2
V
V
V
0.8
V
0
85
°C
0
125
°C
RSPK
(SE, BTL, and
PBTL)
Minimum supported speaker
impedance
Output filter: L = 15 μH, C = 330 nF
Lo(BTL)
Output-filter inductance
Minimum output inductance
under short-circuit condition
RHP
Headphone mode load impedance
16
32
Ω
RLD
Line-diver mode load impedance
0.6
10
kΩ
(1)
(2)
6
4
Ω
8
μH
10
For operation at PVDD levels greater than 18 V, the modulation limit must be set to 93.8% via the control port register 0x10.
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
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7.4 Thermal Information
TAS5721
THERMAL METRIC (1)
DCA (HTSSOP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
27.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
RθJB
Junction-to-board thermal resistance
13
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics – I/O Pin Characteristics
PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance
with recommended operating conditions (unless otherwise specified).
PARAMETER
VOH
High-level output voltage
ADR/FAULT and SDA
TEST CONDITIONS
MIN
IOH = –4 mA
DVDD = AVDD = 3 V
2.4
TYP
MAX
V
VOL
Low-level output voltage
IOL = 4 mA
DVDD = AVDD = 3 V
0.5
IIL
Low-level input current
VI < VIL ; DVDD = AVDD
= 3.6 V
75
VI > VIH ; DVDD =
AVDD = 3.6 V
75
Digital Inputs
IIH
High-level input current
IDD
3.3 V supply current
3.3 V supply voltage (DVDD,
AVDD)
tw(RST)
Pulse duration, RST active
RST
td(I2C_ready)
Time before the I2C port is able
communicate after RST goes
high
UNIT
μA
Normal mode
48
70
Reset (RST = low, PDN
= high, DR_SD = low)
21
38
μs
100
12
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ms
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7.6 Master Clock Characteristics (1)
PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance
with recommended operating conditions (unless otherwise specified).
PARAMETER
fMCLK
tr(MCLK) / tf(MCLK)
(1)
TEST CONDITIONS
MIN
MCLK frequency
2.8224
MCLK duty cycle
40%
TYP
50%
MAX
UNIT
24.576
MHz
60%
Rise/fall time for MCLK
5
ns
For clocks related to the serial audio port, please see Serial Audio Port Timing
7.7 Speaker Amplifier Characteristics
TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48
kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with
recommended operating conditions (unless otherwise specified).
PARAMETER
PoSPK
(BTL)
PoSPK
(PBTL)
PoSPK
(SE)
THD+N
ICN
Power output per channel of
speaker amplifier when used in
BTL mode (1)
Power output per channel of
speaker amplifier when used in
PBTL mode (1)
Power output per channel of
speaker amplifier when used in
SE mode (1)
Total harmonic distortion +
noise
Idle channel noise
Crosstalk
TEST CONDITIONS
MIN
10
PVDD = 12 V, RSPK = 8Ω, 10% THD+N, 1-kHz
input signal
8.8
PVDD = 12 V, RSPK = 8Ω, 7% THD+N, 1-kHz input
signal
8.3
PVDD = 8 V, RSPK = 8Ω, 10% THD+N, 1-kHz input
signal
4
PVDD = 8 V, RSPK = 8Ω, 7% THD+N, 1-kHz input
signal
3.8
PVDD = 12 V, RSPK = 4Ω,
10% THD+N, 1-kHz input signal
10
PVDD = 12 V, RSPK = 4Ω,
7% THD+N, 1-kHz input signal
10
PVDD = 18 V, RSPK = 4Ω,
1-kHz input signal
10
PVDD = 12 V, RSPK = 4 Ω,
10% THD+N, 1-kHz input signal
4.3
PVDD = 24 V, RSPK = 4 Ω,
10% THD+N, 1-kHz input signal
5.5
PVDD = 18 V, PO = 1 W
0.07%
PVDD = 12 V, PO = 1 W
0.11%
PVDD = 8 V, PO = 1 W
0.2%
UNIT
W
W
A-weighted
61
μV
PO = 1 W, f = 1 kHz (BD Mode), PVDD = 24 V
58
dB
PO =1 W, f = 1 kHz (AD Mode), PVDD = 24 V
48
dB
106
dB
A-weighted, f = 1 kHz, maximum power at THD <
1%
Signal-to-noise ratio (2)
fPWM
Output switching frequency
IPVDD
Supply current
rDS(on)
Drain-to-source resistance (for
each of the Low-Side and High- TJ = 25°C, includes metallization resistance
Side Devices)
RPD
Internal pulldown resistor at the Connected when drivers are in the high-impedance
output of each half-bridge
state to provide bootstrap capacitor charge.
11.025/22.05/44.1-kHz data rate ±2%
352.8
48/24/12/8/16/32-kHz data rate ±2%
No load (PVDD)
kHz
384
Normal mode
8
MAX
W
SNR
(1)
(2)
TYP
PVDD = 18 V, RSPK = 8Ω, 1-kHz input signal
Reset (RST = low, PDN =
high)
32
50
5
8
mA
200
mΩ
3
kΩ
Power levels are thermally limited.
SNR is calculated relative to 0-dBFS input level.
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7.8 Headphone Amplifier and Line Driver Characteristics
TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48
kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with
recommended operating conditions (unless otherwise specified).
PARAMETER
TEST CONDITIONS
PoHP
Power output per channel of
headphone amplifier
DRVDD = 3.3 V (RHP = 32; THD = 1%)
AVDR
Gain for headphone amplifier and line
driver
Adjustable through Rin and Rfb
SNRHP
SNRLD
MIN
TYP
MAX
UNIT
50
mW
-
dB
Signal-to-noise ratio (headphone mode) Rhp = 32
101
dB
Signal-to-noise ratio (line driver mode)
105
dB
2-VRMS output
7.9 Protection Characteristics
TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48
kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with
recommended operating conditions (unless otherwise specified).
MIN
TYP
MAX
UNIT
Vuvp(fall)
Undervoltage protection limit
PVDD falling
4
Vuvp(rise)
Undervoltage protection limit
PVDD rising
4.1
V
V
OTE
Overtemperature error threshold
150
°C
ΔOTE
Variation in overtemperature detection circuit
±15
°C
IOCE
Overcurrent limit protection threshold
tOCE
Overcurrent response time
3
A
150
ns
7.10 I2C Serial Control Port Requirements and Specifications
PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance
with recommended operating conditions (unless otherwise specified).
MIN
No wait states
MAX
UNIT
400
kHz
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
0
ns
t(buf)
Bus free time between stop and start conditions
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
μs
μs
100
ns
μs
400
pF
7.11 Serial Audio Port Timing
PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8
Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with
recommended operating conditions (unless otherwise specified).
MIN
CL = 30 pF
1.024
TYP
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
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Serial Audio Port Timing (continued)
PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8
Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with
recommended operating conditions (unless otherwise specified).
MIN
TYP
MAX
UNIT
8
48
48
kHz
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
LRCLK frequency
SCLK rising edges between LRCLK rising edges
32
64
SCLK
edges
–1/4
1/4
SCLK
period
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
tr/tf
Rise/fall time for SCLK/LRCLK
8
ns
LRCLK allowable drift before LRCLK reset
4
MCLK
Periods
RST
tw(RST)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTE: On power up, it is recommended that the TAS5721 RST be held LOW for at least 100 μs after DVDD has reached 3
V.
NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is
deasserted (HIGH).
Figure 1. Reset Timing
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
10
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SCL
t(buf)
th2
tsu3
tsu2
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
tr
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 4. Serial Audio Port Timing
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7.12 Typical Characteristics
30
7
TA = 25°C
TA = 25°C
6
25
Output Power (W)
Output Power (W)
5
4
3
2
1
0
8
10
12
14
Ÿ THD+N = 1%
RL = 2x8Ÿ
Ÿ THD+N = 10%
RL = 2x4Ÿ
Ÿ THD+N = 1%
RL = 2x4Ÿ
Ÿ THD+N = 10%
RL = 2x4Ÿ
Ÿ THD+N = 1%
RL = 2x4Ÿ
Ÿ THD+N = 10%
18
20
22
15
10
RL = 2x8Ÿ
16
20
RL = 4Ÿ THD+N = 1%
RL = 4Ÿ THD+N = 10%
5
RL = 2Ÿ THD+N = 1%
RL = 2Ÿ THD+N = 10%
0
8
24
10
12
Supply Voltage (V)
14
16
18
20
22
C002
Figure 5. Output Power vs PVDD IN 2.1 Mode
C003
Figure 6. Output Power vs PVDD in PBTL Mode
10
10
2.0 BTL Mode
PVDD = 12V
PO = 1W
TA = 25°C
2.0 BTL Mode
PVDD = 18V
PO = 1W
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 4Ω
RL = 6Ω
RL = 8Ω
0.001
20
100
RL = 4Ω
RL = 6Ω
RL = 8Ω
1k
Frequency (Hz)
10k
0.001
20k
20
100
1k
Frequency (Hz)
10k
G004
Figure 7. Total Harmonic Distortion + Noise vs Frequency in
2.0 Mode With PVDD = 12 V
G005
10
2.0 BTL Mode
PVDD = 24V
PO = 1W
TA = 25°C
2.1 SE Mode
PVDD = 12V
PO = 1W
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 2x8+8Ω
RL = 2x8+4Ω
RL = 2x4+8Ω
RL = 2x4+4Ω
RL = 4Ω
RL = 6Ω
RL = 8Ω
20
100
1k
Frequency (Hz)
10k
20k
0.001
G006
Figure 9. Total Harmonic Distortion + Noise vs Frequency in
2.0 Mode With PVDD = 24 V
12
20k
Figure 8. Total Harmonic Distortion + Noise vs Frequency in
2.0 Mode With PVDD = 18 V
10
0.001
24
Supply Voltage (V)
20
100
1k
Frequency (Hz)
10k
20k
G007
Figure 10. Total Harmonic Distortion + Noise vs Frequency
in 2.1 Mode With PVDD = 12 V
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Typical Characteristics (continued)
10
10
2.1 SE Mode
PVDD = 18V
PO = 1W
TA = 25°C
2.1 SE Mode
PVDD = 24V
PO = 1W
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
RL = 2x8+8Ω
RL = 2x8+4Ω
RL = 2x4+8Ω
RL = 2x4+4Ω
0.001
20
100
RL = 2x8+8Ω
RL = 2x8+4Ω
RL = 2x4+8Ω
1k
Frequency (Hz)
10k
0.001
20k
20
100
1k
Frequency (Hz)
10k
20k
G009
Figure 11. Total Harmonic Distortion + Noise vs Frequency
in 2.1 Mode With PVDD = 18 V
G009
Figure 12. Total Harmonic Distortion + Noise vs Frequency
in 2.1 Mode With PVDD = 24 V
10
10
PBTL Mode
PVDD = 12V
PO = 1W
TA = 25°C
PBTL Mode
PVDD = 18V
PO = 1W
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
RL = 4Ω
RL = 6Ω
RL = 8Ω
0.001
20
100
RL = 4Ω
RL = 6Ω
RL = 8Ω
1k
Frequency (Hz)
10k
20k
0.001
20
100
1k
Frequency (Hz)
10k
20k
G010
Figure 13. Total Harmonic Distortion + Noise vs Frequency
in PBTL Mode With PVDD = 12 V
G011
Figure 14. Total Harmonic Distortion + Noise vs Frequency
in PBTL Mode With PVDD = 18 V
10
60
2.0 BTL Mode
TA = 25°C
PBTL Mode
PVDD = 24V
PO = 1W
TA = 25°C
50
Idle Channel Noise (µV)
THD+N (%)
1
0.1
40
30
0.01
20
RL = 4Ω
RL = 6Ω
RL = 8Ω
0.001
20
100
RL = 4Ω
RL = 6Ω
RL = 8Ω
1k
Frequency (Hz)
10k
10
20k
G012
Figure 15. Total Harmonic Distortion + Noise vs Frequency
in PBTL Mode With PVDD = 24 V
8
10
12
14
16
18
Supply Voltage (V)
20
22
24
G013
Figure 16. 2.0 Idle Channel Noise vs PVDD
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Typical Characteristics (continued)
60
45
2.1 SE Mode
TA = 25°C
PBTL Mode
TA = 25°C
55
40
Idle Channel Noise (µV)
Idle Channel Noise (µV)
50
35
30
25
45
40
35
30
20
25
15
10
RL = 2x8+8Ω
RL = 2x4+8Ω
RL = 2x4+4Ω
8
10
12
14
16
18
Supply Voltage (V)
20
22
20
15
24
RL = 4Ω
RL = 8Ω
8
10
12
14
16
18
Supply Voltage (V)
20
22
24
G014
G015
Figure 17. 2.1 Idle Channel Noise vs PVDD
Figure 18. PBTL Idle Channel Noise vs PVDD
10
10
PVDD = 12V
f = 1kHz
TA = 25°C
PVDD = 18V
f = 1kHz
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 8Ÿ
RL = 8Ÿ
RL = 6Ÿ
RL = 6Ÿ
RL = 4Ÿ
0.001
0.01
0.1
1
RL = 4Ÿ
0.001
0.01
10
0.1
Output Power (W)
1
10
Output Power (W)
C016
Figure 19. Total Harmonic Distortion + Noise vs Output
Power in 2.0 Mode With PVDD = 12 V
C017
Figure 20. Total Harmonic Distortion + Noise vs Output
Power in 2.0 Mode With PVDD = 18 V
10
10
PVDD = 24V
f = 1kHz
TA = 25°C
PVDD = 12V
f = 1kHz
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.001
0.01
0.1
0.01
0.1
1
RL = 8Ÿ
RL = 2x8Ÿ
Ÿ
RL = 6Ÿ
RL = 2x4Ÿ
Ÿ
RL = 4Ÿ
RL = 2x4Ÿ
Ÿ
0.001
0.01
10
Output Power (W)
1
10
Output Power (W)
C018
Figure 21. Total Harmonic Distortion + Noise vs Output
Power in 2.0 Mode With PVDD = 24 V
14
0.1
C019
Figure 22. Total Harmonic Distortion + Noise vs Output
Power in 2.1 Mode With PVDD = 12 V
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Typical Characteristics (continued)
10
10
PVDD = 18V
f = 1kHz
TA = 25°C
PVDD = 24V
f = 1kHz
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
0.001
0.01
0.1
RL = 2x8Ÿ
Ÿ
RL = 2x4Ÿ
Ÿ
RL = 2x4Ÿ
Ÿ
1
0.001
0.01
10
0.1
Output Power (W)
RL = 2x8Ÿ
Ÿ
RL = 2x4Ÿ
Ÿ
1
10
Output Power (W)
C020
Figure 23. Total Harmonic Distortion + Noise vs Output
Power in 2.1 Mode With PVDD = 18 V
C021
Figure 24. Total Harmonic Distortion + Noise vs Output
Power in 2.1 Mode With PVDD = 24 V
10
10
PVDD = 12V
f = 1kHz
TA = 25°C
PVDD = 18V
f = 1kHz
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 4Ÿ
RL = 4Ÿ
RL = 2Ÿ
0.001
0.01
0.1
1
RL = 2Ÿ
0.001
0.01
10
0.1
Output Power (W)
1
10
Output Power (W)
C022
Figure 25. Total Harmonic Distortion + Noise vs Output
Power in PBTL Mode With PVDD = 12 V
C023
Figure 26. Total Harmonic Distortion + Noise vs Output
Power in PBTL Mode With PVDD = 18 V
100
10
PVDD = 24V
f = 1kHz
TA = 25°C
90
80
1
Efficiency (%)
THD+N (%)
70
0.1
60
50
40
30
PVDD = 12V
PVDD = 18V
PVDD = 24V
0.01
20
RL = 4Ÿ
10
RL = 2Ÿ
0.001
0.01
0
0.1
1
10
Output Power (W)
0
5
2.0 BTL Mode
RL = 8Ω
TA = 25°C
All Channels Driven
10
15
Total Output Power (W)
20
G025
C024
Figure 27. Total Harmonic Distortion + Noise vs Output
Power in PBTL Mode With PVDD = 24 V
All channels driven
Figure 28. Efficiency vs Output Power in 2.0 Mode
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100
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
Typical Characteristics (continued)
50
40
50
40
30
30
PVDD = 12V
PVDD = 18V
PVDD = 24V
20
10
0
0
5
10
15
20
Total Output Power (W)
25
PVDD = 12V
PVDD = 18V
PVDD = 24V
20
2.1 SE Mode
RL = 2x8+8Ω
TA = 25°C
All Channels Driven
10
0
30
0
5
2.1 SE Mode
RL = 2x4+8Ω
TA = 25°C
All Channels Driven
10
15
20
Total Output Power (W)
25
30
G026
G027
All channels driven
Figure 30. Efficiency vs Output Power in 2.1 Mode
100
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
All channels driven
Figure 29. Efficiency vs Output Power in 2.1 Mode
50
40
50
40
30
30
PVDD = 12V
PVDD = 18V
PVDD = 24V
20
10
0
0
5
10
15
20
Total Output Power (W)
25
PVDD = 12V
PVDD = 18V
PVDD = 24V
20
PBTL Mode
RL = 8Ω
TA = 25°C
All Channels Driven
10
0
30
0
5
PBTL Mode
RL = 6Ω
TA = 25°C
All Channels Driven
10
15
20
Total Output Power (W)
25
30
G029
All channels driven
Figure 31. Efficiency vs Output Power in PBTL Mode
G030
All channels driven
Figure 32. Efficiency vs Output Power in PBTL Mode
0
0
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 4Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
−100
20
100
1k
Frequency (Hz)
10k
20k
G032
Figure 33. Crosstalk vs Frequency in 2.0 Mode
16
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 8Ω
TA = 25°C
−10
20
100
1k
Frequency (Hz)
10k
20k
G033
Figure 34. Crosstalk vs Frequency in 2.0 Mode
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Typical Characteristics (continued)
0
0
2.0 BTL Mode
PO = 1W
PVDD = 24V
RL = 4Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
2.0 BTL Mode
PO = 1W
PVDD = 24V
RL = 8Ω
TA = 25°C
−10
20
100
1k
Frequency (Hz)
10k
20k
−100
20
100
1k
Frequency (Hz)
10k
20k
G034
Figure 35. Crosstalk vs Frequency in 2.0 Mode
G035
Figure 36. Crosstalk vs Frequency in 2.0 Mode
0
0
2.1 SE Mode
PO = 1W
PVDD = 12V
RL = 2x8+8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
−30
Crosstalk (dB)
2.1 SE Mode
PO = 1W
PVDD = 12V
RL =2x4+8Ω
TA = 25°C
−10
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
−100
20
100
1k
Frequency (Hz)
10k
20k
20
100
1k
Frequency (Hz)
10k
20k
G036
Figure 37. Crosstalk vs Frequency in 2.1 Mode
G037
Figure 38. Crosstalk vs Frequency in 2.1 Mode
0
0
2.1 SE Mode
PO = 1W
PVDD = 24V
RL = 2x8+8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
2.1 SE Mode
PO = 1W
PVDD = 24V
RL =2x4+8Ω
TA = 25°C
−10
20
100
1k
Frequency (Hz)
10k
20k
−100
G038
Figure 39. Crosstalk vs Frequency in 2.1 Mode
20
100
1k
Frequency (Hz)
10k
20k
G039
Figure 40. Crosstalk vs Frequency in 2.1 Mode
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7.12.1 Headphone Typical Characteristics
10
10
Driver
DRVDD = 3.3V
VO = 0.5Vrms
TA = 25°C
Driver
DRVDD = 3.3V
VO = 1Vrms
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
RL = 16Ω
RL = 32Ω
0.001
20
100
RL = 5kΩ
RL = 10kΩ
1k
Frequency (Hz)
10k
0.001
20k
20
100
1k
Frequency (Hz)
10k
G040
20k
G041
Figure 41. Total Harmonic Distortion + Noise vs Frequency
Headphone With DRVDD = 3.3 V
Figure 42. Total Harmonic Distortion + Noise vs Frequency
Headphone With DRVDD = 3.3 V
10
Driver
DRVDD = 3.3V
f = 1kHz
TA = 25°C
THD+N (%)
1
0.1
0.01
RL = 16Ω
RL = 32Ω
0.001
0.001
0.01
Output Power (W)
0.1
G042
Figure 43. Total Harmonic Distortion + Noise vs Output Power Headphone With DRVDD = 3.3 V
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7.12.2 Line Driver Typical Characteristics
10
0
Driver
DRVDD = 3.3V
f = 1kHz
TA = 25°C
Driver
VO = 1Vrms
DRVDD = 3.3V
RL = 5kΩ
TA = 25°C
−10
−20
1
Right to Left
Left to Right
Crosstalk (dB)
THD+N (%)
−30
0.1
−40
−50
−60
−70
0.01
−80
−90
RL = 5kΩ
RL = 10kΩ
0.001
0.01
0.1
Output Voltage (V)
1
4
−100
20
100
1k
Frequency (Hz)
10k
20k
G043
Figure 44. Total Harmonic Distortion + Noise vs Output
Voltage Headphone With DRVDD = 3.3 V
G044
Figure 45. Crosstalk vs Frequency Headphone With
DRVDD = 3.3 V
0
0
Driver
VO = 1Vrms
DRVDD = 3.3V
RL = 16Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
Driver
VO = 1Vrms
DRVDD = 3.3V
RL = 32Ω
TA = 25°C
−10
20
100
1k
Frequency (Hz)
10k
20k
−100
G045
Figure 46. Crosstalk vs Frequency Headphone With
DRVDD = 3.3 V
20
100
1k
Frequency (Hz)
10k
20k
G046
Figure 47. Crosstalk vs Frequency Headphone With
DRVDD = 3.3 V
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
20
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9 Detailed Description
9.1 Overview
The TAS5721 device is an efficient stereo I2S input Class-D audio power amplifier with a digital audio processor
and a DirectPath headphone/line driver.
The digital audio processor of the device uses noise shaping and customized correction algorithms to achieve a
great power efficiency and high audio performance. Also, the device has up to eight Equalizers per channel and
two -band configurable Dynamic Range Control (DRC).
The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal
voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of
the device enables its use in a multitude of applications.
The device has an integrated DirectPath headphone amplifier / line driver to increase system level integration
and reduce total solution costs. DirectPath architecture eliminates the requirement for external dc-blocking output
capacitors.
The TAS5721 device is a slave-only device that is controlled by a bidirectional I2C interface that supports both
100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control
interface is used to program the registers of the device and read the device status. The PWM of this device
operates with a carrier frequency between 384 kHz and 354 kHz, depending the sampling rate. This device
allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using a sampling frequency of
44.1 kHz or 48 kHz.
This device can be used in three different modes of operation, Stereo BTL Mode, Single Filter PBTL Mono Mode,
and 2.1 Mode.
9.2 Functional Block Diagram
DVDD
DRVDD
AVDD
PVDD
TAS5721
DRVDD
MCLK Monitoring
and Watchdog
MCLK
LRCLK
Internal Regulation and Power Distribution
Power-On Reset
(POR)
SCLK
SDIN
PLL
Digital Audio
Processor
(DAP)
Open Loop 4 Channel
PWM Amplifier
Digital to PWM
Converter
(DPC)
Serial Audio Port
(SAP)
Sample Rate
Auto-Detect
Internal Voltage Supplies
Sample Rate
Converter
(SRC)
Sensing and
Protection
3 Ch. PWM
Modulator
Noise Shaping
Click and Pop
Suppression
SPK_OUTA
Temperature
Short Circuits
PVDD Voltage
Output Current
SPK_OUTB
Fault Notification
SPK_OUTD
SPK_OUTC
Internal Register/State Machine Interface
DRVDD
2
I C Control Port
SCL
SDA
PDN
RST
Stereo Headphone
Amplifier
Charge Pump
DR_CP
DR_CN
DR_VSS
DR_INA
DR_OUTA
DR_OUTB
DR_INB
Figure 48. Functional Block Diagram
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Functional Block Diagram (continued)
Figure 49. DAP Process Structure
9.3 Feature Description
9.3.1 Power Supply
To facilitate system design, the TAS5721 needs only a 3.3-V supply in addition to the PVDD power-stage supply.
The required sequencing of the power supplies is shown in the Recommended Use Model section. An internal
voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a
floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry
requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD
voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap
capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X)
and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the
output potential and thus provides a suitable voltage supply for the high-side gate driver. As shown in the Typical
Application section, it is recommended to use ceramic capacitors, for the bootstrap supply pins. These capacitors
ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET
(LDMOS) fully turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD pin is
decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the Typical
Application section.
The TAS5721 is fully protected against erroneous power-stage turn-on due to parasitic gate charging.
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Feature Description (continued)
9.3.2 I2C Address Selection and Fault Output
ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the
Typical Application section in order to set the I2C address. Pulling this pin HIGH through the resistor results in
setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the
address to 0011010 (0x34).
During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault
notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's
default state when register 0x02 is cleared. The device will pull the fault pin low for over-current, overtemperature, over-voltage lock-out, and under-voltage lock-out.
9.3.3 Device Protection System
9.3.3.1 Overcurrent (OC) Protection With Current Limiting
The device has independent, fast reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by a protection system. If the high-current condition situation persists, a
protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (HiZ) state. After the power stage enters into this state, the power stage will attempt to restart after a period of time
defined in register 0x1C. If the high-current condition persists, the device will begin the shutdown and retry
sequence again. The device will return to normal operation once the fault condition is removed. Current limiting
and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between halfbridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down.
9.3.3.2 Overtemperature Protection
The TAS5721 has an overtemperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low. The TAS5721 recovers
automatically once the temperature drops approximately 30 °C.
9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5721 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit ensures that all circuits are fully operational when the PVDD and AVDD
supply voltages reach 4.1 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a
supply voltage drop below the UVP threshold on AVDD or on either PVDD pin results in all half-bridge outputs
immediately being set in the high-impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being
asserted low.
9.3.4 Clock, Auto Detection, and PLL
The TAS5721 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the Clock Control Register section.
The TAS5721 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock control register.
TAS5721 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)
and then force PLL to operate in a reduced capacity using the internal oscillator as a reference clock. Once the
clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process,
the default volume will be restored in a single step (also called hard unmute) by default. If desired, the unmuting
process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).
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Feature Description (continued)
9.3.5 PWM Section
The TAS5721 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs up to three PWM audio output channels.
The PWM modulation block has individual channel dc blocking filters that can be enabled and disabled. The filter
cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and
can be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. It is important to note
that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.
9.3.6 SSTIMER Functionality
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor,
similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin
capacitance. The SSTIMER capacitor size determines the start-up time, 2200 pF is the maximum recommended
value. The SSTIMER pin can be left floating when using BD modulation, but leaving the capacitor connected
does not represent any issue.
9.3.7 2.1-Mode Support
The TAS5721 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation.
To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must
be set to 1. The SSTIMER pin should be left floating in this mode.
9.3.7.1 Supply Pumping and Polarity Inversion for 2.1 Mode
The high degree of correlation between the left and right channels of a stereo audio signal dictates that, when
the left audio signal is positive, the right audio signal tends to be positive as well. When the Class D is configured
for single-ended operation (as would be the case for Single Device 2.1 Operation), this results in both outputs
drawing current from the supply rail "in phase". Similarly, when the left audio signal is negative, the right audio
signal tends to be negative as well. For single-ended operation, both outputs will likewise force current into the
ground rail. This can lead to a phenomenon called "supply pumping" in which the capacitances on the PVDD rail
begin to store charge- raising the voltage level of PVDD as well. This noise injection onto the rail is in phase with
and at a similar frequency of the signal being produced by the amplifier output stage. This phenomenon can
cause issues for other devices attached to the PVDD rail. The problem does not occur for BTL outputs since
outputs of both polarities are always present for each channel.
To combat supply pumping in 2.1 Mode, the device has an integrated speaker-mode volume negation feature,
which, essentially introduces a polarity inversion (shift by 180°) to any of the given channels. By setting the
correct bit in 0x20[31:24], it is possible to invert the polarity of the DAP channels that drive the PWM modulator
blocks. This allows, for instance, the left channel to operate with its default polarity, while the right channel could
have its polarity inverted to balance current flow into and out of the supplies. This procedure could have an
adverse implication on the stereo imaging of the audio system because, if the speakers in the system are
connected in the same manner as they would be connected when being driven by traditional BTL channels, the
phase of the signals being sent to the speakers is 180° out of phase. In order to prevent this from occurring, the
speaker on the negated channel must be connected "backwards" (i.e. the Class D signal for the negated channel
gets connected to the negative speaker terminal and the positive terminal is grounded). In this way, supply
pumping is reduced while keeping the effective signal polarity the same. The table above includes register
settings which enable the polarity inversion, so care should be taken to adjust the polarity of the speakers if this
feature is left enabled. Of course this feature can be left disabled if desired, provided the supply pumping
phenomenon doesn't cause any other system level issues
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Feature Description (continued)
9.3.8 PBTL-Mode Support
The TAS5721 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected after
the LC filter. In order to put the part in PBTL configuration, the PWM output multiplexers should be updated to
set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x01 10 32 45. Also,
the PWM shutdown register (0x19) should be written with a value of 0x3A.
9.3.9 I2C Serial Control Interface
The TAS5721 DAP has a bidirectional inter-integrated circuit (I2C) interface that is compatible with the I2C bus
protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read
operations. This is a slave only device that does not support a multimaster bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
9.3.9.1 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5721
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5721. For I2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
9.3.9.2 Single-Byte Write
As shown in Figure 50, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5721 internal memory address being accessed. After receiving
the address byte, the TAS5721 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5721 again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the singlebyte data write transfer.
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Feature Description (continued)
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 50. Single-Byte Write Transfer
9.3.9.3 Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 51. After receiving each data byte, the
TAS5721 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
A5
2
A4
A3
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
Other Data Bytes
First Data Byte
Subaddress
I C Device Address and
Read/Write Bit
Last Data Byte
Stop
Condition
T0036-02
Figure 51. Multiple-Byte Write Transfer
9.3.9.4 Single-Byte Read
As shown in Figure 52, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5721 address
and the read/write bit, TAS5721 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5721 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5721 again responds with an acknowledge bit. Next, the TAS5721
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A4
A0 ACK
Subaddress
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
2
I C Device Address and
Read/Write Bit
D6
D1
Data Byte
D0 ACK
Stop
Condition
T0036-03
Figure 52. Single-Byte Read Transfer
9.3.9.5 Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5721 to the master device as shown in Figure 53. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
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Feature Description (continued)
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 53. Multiple Byte Read Transfer
9.3.10 Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
left/right channels and one DRC for the subchannel.
The DRC input/output diagram is shown in Figure 54.
Output Level (dB)
Refer to GDE software tool for more description on T, K, and O parameters.
K
1:1 Transfer Function
O
Implemented Transfer Function
T
Input Level (dB)
M0091-02
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each DRC has adjustable threshold, offset, and compression levels.
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 54. Dynamic Range Control
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Feature Description (continued)
Energy
Filter
Compression
Control
Attack
and
Decay
Filters
a, w
T, K, O
aa, wa / ad, wd
DRC1
0x3A
0x40, 0x41, 0x42
0x3B / 0x3C
DRC2
0x3D
0x43, 0x44, 0x45
0x3E / 0x3F
Audio Input
DRC Coefficient
Alpha Filter Structure
S
a
w
–1
Z
NOTE:
w=1–α
B0265-01
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 55. DRC Structure
9.3.11 Bank Switching
The TAS5721 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in three banks. The
user can program which sample rates map to each bank. By default, bank 1 is used in 32-kHz mode, bank 2 is
used in 44.1- or 48-kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection
feature, bank switching allows the TAS5721 to detect automatically a change in the input sample rate and switch
to the appropriate bank without any MCU intervention.
An external controller configures bankable locations (0x29-0x36, 0x3A-0x3F, and 0x58-0x5F) for all three banks
during the initialization sequence.
If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5721 automatically swaps the coefficients
for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate
change.
By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to
bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5721
automatically swaps banks based on the sample rate.
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Command sequences for updating DAP coefficients can be summarized as follows:
1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not
influenced by subsequent sample rate changes.
OR
2. Bank switching enabled:
(a) Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients.
(b) Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients.
(c) Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients.
(d) Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50.
9.3.12 Serial Data Interface
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5721 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
9.3.12.1 Serial Interface Control and Timing
The I2S mode is set by writing to register 0x04.
9.3.12.1.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 56. I2S 64-fS Format
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2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 57. I2S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
LSB
15 14 13 12
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 58. I2S 32-fS Format
9.3.12.1.2 Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
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2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 59. Left-Justified 64-fS Format
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 60. Left-Justified 48-fS Format
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2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 61. Left-Justified 32-fS Format
9.3.12.1.3 Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 62. Right Justified 64-fS Format
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 63. Right Justified 48-fS Format
Figure 64. Right Justified 32-fS Format
9.3.13 DirectPath Headphone/Line Driver
The TAS5721 device has a stereo output which can be used as a line driver or a headphone driver that can
output 2-Vrms stereo. An audio system can be set up for different applications using this device.
9.3.13.1 Using Headphone Amplifier in TAS5721
The device can be represented as shown in Figure 65: analog inputs (single-ended) as DR_INA (pin 7) and
DR_INB (pin 10) with the outputs DR_OUTA (pin 8) and DR_OUTB (pin 9).
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R2
R1
VIN
VOUT
DR_INx
DR_OUTx
S0490-02
Figure 65. Headphone/Line Driver with Analog Input
DR_SD pin can be used to turn ON or OFF the headphone amplifier and line driver.
Speaker channels are independent of headphone and line driver in this mode.
9.3.13.2 Using Line Driver Amplifier in TAS5721
Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in
Figure 66 illustrates the conventional line driver amplifier connection to the load and output signal.
DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power
up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits
consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal.
Conventional Solution
9–12 V
VDD
+
Mute Circuit
Co
+
+
OPAMP
Output
VDD/2
–
GND
MUTE
TAS5721 Solution
3.3 V
DirectPath
VDD
+
Mute Circuit
Output
GND
TAS5721
–
VSS
DR_SD
Figure 66. Conventional and DirectPath HP and Line Driver
The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to
provide a negative voltage rail.
Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
34
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The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail,
combining this with the built in click and pop reduction circuit, the DirectPath amplifier requires no output dc
blocking capacitors.
The bottom block diagram and waveform of Figure 66 illustrate the ground-referenced headphone and line driver
architecture. This is the architecture of the TAS5721.
9.4 Device Functional Modes
9.4.1 Output Mode and MUX Selection
The TAS5721 is a highly configurable device, capable of operating in 2.0, Single Device 2.1 and parallel bridge
tied load (PBTL) configurations. Addtionally, the modulation scheme can be changed for the channels to operate
either in AD or BD Modulation mode. While many configurations are possible because of this flexibility, the
majority of use cases uses will operate in one of the configurations shown below. For ease of use and reduced
complexity, the figure below outlines both the register settings and the output configurations required to set the
device up for operation in these various modes.
The output configuration quick reference table below highlights the controls that are required to configure the
device for various operational modes. Please note that other controls, which are not directly related to the output
configuration muxes may also be required. For example, the Inter Channel Delay (ICD) settings will likely need to
be modified to optimize for idle channel noise, cross-talk, and distortion performance for each of these
considerations, in addition to start and stop time and others. Please consult the respective registers for these
controls to optimize for various other performance parameters and use cases.
Table 1. Output Configuration Quick Reference
OUTPUT
CONFIGURATION
MODULATION MODE
REGISTER SETTINGS
AD for Both Outputs
0x20[23] = 0
0x20[19] = 0
0x20[15:8] = 0x77
0x05[7] = 0
0x05[2] = 0
0x25[23:8] = 0x0213
0x1A[7:0] = 0x0F
BLOCK DIAGRAM
PWM1
A (L+)
PWM2
B (L–)
PWM3
C (R+)
PWM4
D (R–)
CH1_audio
CH2_audio
B0487-01
2.0 (Stereo BTL)
BD for Both Outputs
0x20[23] = 1
0x20[19] = 1
0x20[15:8] = 0x77
0x05[7] = 0
0x05[2] = 0
0x25[23:8] = 0x0213
0x1A[7:0] = 0x0A
PWM1
A (L+)
PWM2
B (L–)
PWM3
C (R+)
PWM4
D (R–)
CH1_audio
CH2_audio
B0487-02
Single Device 2.1
(Stereo Single
Ended + Mono
BTL)
Note: In these
described
configurations, the
polarity of the
signal being sent to
SPK_OUTB is
inverted. For this
reason, care
should be taken to
ensure that the
speakers are
connected as
shown in the block
diagram.
AD for Both SE Outputs
AD for Single BTL
Output
AD for both SE Outputs
BD for Single BTL
Output
0x20[23] = 0
0x20[19] = 0
0x20[3] = 0
0x05[7] = 1
0x05[2] = 1
0x25[23:8] = 0x0132
0x1A[7:0] = 0x95
0x20[7:4] = 0x7
0x21[8] = 0
0x20[25] = 1
0x20[23] = 0
0x20[19] = 0
0x20[3] = 1
0x05[7] = 1
0x05[2] = 1
0x25[23:8] = 0x0132
0x1A[7:0] = 0x95
0x20[7:4] = 0x7
0x21[8] = 0
0x20[25] = 1
PWM1
A (L+)
PWM2
B (R–)
PWM3
C (S+)
PWM4
D (S–)
CH1_audio
CH2_audio
CH3_audio
B0487-03
PWM1
A (L+)
PWM2
B (R–)
PWM3
C (S+)
PWM4
D (S–)
CH1_audio
CH2_audio
CH3_audio
B0487-04
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Device Functional Modes (continued)
Table 1. Output Configuration Quick Reference (continued)
OUTPUT
CONFIGURATION
MODULATION MODE
REGISTER SETTINGS
AD
0x05[7] = 0
0x05[5] = 0
0x05[2] = 0
0x19[7:0] = 0x3A
0x1A[7:0] = 0x0F
0x20[23] = 0
0x20[15:12] = 0x7
0x25[23:8] = 0x0123
1.0 Mono PBTL
BLOCK DIAGRAM
CH1_audio
A (L+)
OFF2
B (Off)
PWM3
C (L–)
OFF4
D (Off)
+
–
B0488-02
0x05[7] = 0
0x05[5] = 0
0x05[2] = 0
0x19[7:0] = 0x3A
0x1A[7:0] = 0x0A
0x20[23] = 1
0x20[15:12] = 0x7
0x25[23:8] = 0x0123
BD
PWM1
CH1_audio
PWM1
A (L+)
CH2_audio
PWM2
B (Off)
OFF3
C (R–)
OFF4
D (Off)
+
–
+
–
B0488-01
9.5 Programming
9.5.1 General I2C Operation
The I2C bus employs two signals to communicate between integrated circuits in a system: (data) SDA and (clock)
SCL. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 67. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5721 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used
for the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 67. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 67.
Pin ADR/FAULT defines the I2C device address. An external 15-kΩ pull down on this pin gives a device address
of 0x34 and a 15-kΩ pull up gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010
(0x34).
36
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Programming (continued)
9.5.1.1 I2C Device Address Change Procedure
• Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5.
• Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
• Any writes after that should use the new device address XX.
9.5.2 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in Figure 68.
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 68. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 68. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 69 applied to obtain the magnitude
of the negative number.
1
0
2 Bit
2 Bit
1
2
0
–1
Bit
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 69. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 70.
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Programming (continued)
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
2
Figure 70. Alignment of 3.23 Coefficient in 32-Bit I C Word
Table 2. Sample Calculation for 3.23 Format
dB
LINEAR
DECIMAL
HEX (3.23
FORMAT)
0
1
8,388,608
0080 0000
5
1.7782794
14,917,288
00E3 9EA8
–5
0.5623413
4,717,260
0047 FACC
X
L = 10(X/20)
D = 8,388,608 × L
H = dec2hex (D, 8)
Table 3. Sample Calculation for 9.17 Format
dB
HEX (9.17
FORMAT)
LINEAR
DECIMAL
0
1
131,072
2 0000
5
1.77
231,997
3 8A3D
–5
0.56
73,400
1 1EB8
D = 131,072 × L
H = dec2hex (D, 8)
X
(X/20)
L = 10
9.6 Register Maps
Table 4. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
CONTENTS
DEFAULT
VALUE
A u indicates unused bits.
38
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x00
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
REGISTER NAME
DEFAULT
VALUE
CONTENTS
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
1
Reserved (1)
1
Description shown in subsequent section
1
Reserved (1)
0x0B–0x0D
0x0E
Volume configuration
register
0x0F
0x91
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
0x15–0x18
(1)
1
Reserved
0x19
PWM channel shutdown
group register
1
Description shown in subsequent section
0x30
0x1A
Start/stop period register
1
Description shown in subsequent section
0x0F
0x1B
Oscillator trim register
1
Description shown in subsequent section
0x82
0x1C
BKND_ERR register
1
Description shown in subsequent section
0x02
1
Reserved (1)
0x1D–0x1F
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
4
Reserved (1)
4
Description shown in subsequent section
4
Reserved (1)
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x22–0x24
0x25
PWM MUX register
0x26–0x28
0x29
0x2A
0x2B
0x2C
(1)
NO. OF
BYTES
ch1_bq[0]
ch1_bq[1]
ch1_bq[2]
ch1_bq[3]
20
20
20
0x0102 1345
Reserved registers should not be accessed.
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
40
REGISTER NAME
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
ch2_bq[5]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
DEFAULT
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x36
REGISTER NAME
ch2_bq[6]
0x37–0x39
0x3A
DRC1 ae (2)
NO. OF
BYTES
20
DRC1 aa
DRC1 ad
DRC2 ae
DRC2 aa
DRC2 ad
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
8
8
8
8
8
DRC2 (1 – ad)
u[31:26], (1 – ad)[25:0]
0x0000 0000
0x40
DRC1-T
4
T1[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC1-K
4
u[31:26], K1[25:0]
0x0384 2109
0x42
DRC1-O
4
u[31:26], O1[25:0]
0x0008 4210
0x43
DRC2-T
4
T2[31:0] (9.23 format)
0xFDA2 1490
0x44
DRC2-K
4
u[31:26], K2[25:0]
0x0384 2109
0x45
DRC2-O
4
u[31:26], O2[25:0]
0x0008 4210
0x46
DRC control
4
Description shown in subsequent section
0x0000 0000
4
Reserved (1)
0x47–0x4F
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
0x51
Ch 1 output mixer
12
Ch 1 output mix1[2]
0x0080 0000
Ch 1 output mix1[1]
0x0000 0000
0x52
0x53
0x54
0x55
(2)
0x0000 0000
u[31:26], a1[25:0]
0x0080 0000
DRC2 (1 – aa)
0x3F
0x0000 0000
u[31:26], b2[25:0]
u[31:26], ae[25:0]
DRC 2 (1 – ae)
0x3E
u[31:26], b1[25:0]
8
DRC1 (1 – ad)
0x3D
0x0080 0000
Reserved (1)
DRC1 (1 – aa)
0x3C
u[31:26], b0[25:0]
4
DRC1 (1 – ae)
0x3B
DEFAULT
VALUE
CONTENTS
Ch 2 output mixer
Ch 1 input mixer
Ch 2 input mixer
Channel 3 input mixer
12
16
16
12
Ch 1 output mix1[0]
0x0000 0000
Ch 2 output mix2[2]
0x0080 0000
Ch 2 output mix2[1]
0x0000 0000
Ch 2 output mix2[0]
0x0000 0000
Ch 1 input mixer[3]
0x0080 0000
Ch 1 input mixer[2]
0x0000 0000
Ch 1 input mixer[1]
0x0000 0000
Ch 1 input mixer[0]
0x0080 0000
Ch 2 input mixer[3]
0x0080 0000
Ch 2 input mixer[2]
0x0000 0000
Ch 2 input mixer[1]
0x0000 0000
Ch 2 input mixer[0]
0x0080 0000
Channel 3 input mixer [2]
0x0080 0000
Channel 3 input mixer [1]
0x0000 0000
Channel 3 input mixer [0]
0x0000 0000
ae stands for ∝ of energy filter, aa stands for ∝ of attack filter and ad stands for ∝ of decay filter and 1- ∝ = ω.
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
REGISTER NAME
0x56
Output post-scale
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
CONTENTS
DEFAULT
VALUE
4
u[31:26], post[25:0]
0x0080 0000
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
ch1 BQ[7]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
ch1 BQ[8]
Subchannel BQ[0]
Subchannel BQ[1]
ch2 BQ[7]
ch2 BQ[8]
pseudo_ch2 BQ[0]
0x5F
20
20
20
20
20
20
(1)
4
Reserved
Channel 4 (subchannel)
output mixer
8
Ch 4 output mixer[1]
0x0000 0000
Ch 4 output mixer[0]
0x0080 0000
0x61
Channel 4 (subchannel)
input mixer
8
Ch 4 input mixer[1]
0x0040 0000
Ch 4 input mixer[0]
0x0040 0000
0x62
IDF post scale
4
Post-IDF attenuation register
0x0000 0080
Reserved (1)
0x0000 0000
0x60
0x63–0xF7
42
NO. OF
BYTES
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
NO. OF
BYTES
REGISTER NAME
DEFAULT
VALUE
CONTENTS
0xF8
Device address enable
register
4
Write F9 A5 A5 A5 in this register to enable write to
device address update (0xF9)
0x0000 0000
0xF9
Device address Update
Register
4
u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id
(7:1) defines the new device address
0X0000 0036
4
Reserved (1)
0x0000 0000
0xFA–0xFF
9.6.1 Clock Control Register (0x00)
The clocks and data rates are automatically determined by the TAS5721. The clock control register contains the
auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The
device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of
192 fS and 384 fS only.
Table 5. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved (1)
0
1
0
–
–
–
–
–
Reserved (1)
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate
1
0
0
–
–
–
–
–
fs = 16-kHz sample rate
1
0
1
–
–
–
–
–
fs = 22.05/24-kHz sample rate
1
1
0
–
–
–
–
–
fs = 8-kHz sample rate
1
1
1
–
–
–
–
–
fs = 11.025/12-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS
(3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS
(4)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved (1)
–
–
–
1
1
1
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Reserved (1)
–
(1)
(2)
(3)
(4)
(5)
–
–
–
–
–
–
0
FUNCTION
Reserved
(2)
(3)
(2) (5)
(2)
(1) (2)
Reserved registers should not be accessed.
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates.
Rate only available for 32/44.1/48-kHz sample rates
Not available at 8 kHz
9.6.2 Device ID Register (0x01)
The device ID register contains the ID code for the firmware revision
Table 6. Device ID Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
FUNCTION
Identification code
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9.6.3 Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal frame sync.
Table 7. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, overvoltage or undervoltage errors
–
–
–
–
–
–
–
0
Reserved
0
0
0
0
0
0
0
–
No errors
(1)
44
FUNCTION
(1)
Default values are in bold.
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9.6.4 System Control Register 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff < 1 Hz) for each channel is enabled (default).
Bit D5:
If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the
same time as the volume ramp defined in register 0x0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp
Bits D1–D0: Select de-emphasis
Table 8. System Control Register 1 (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
PWM high-pass (dc blocking) disabled
FUNCTION
1
–
–
–
–
–
–
–
PWM high-pass (dc blocking) enabled
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Soft unmute on recovery from clock error
–
–
1
–
–
–
–
–
Hard unmute on recovery from clock error
–
–
–
0
–
–
–
–
Reserved
–
–
–
–
0
–
–
–
Reserved
(1)
(1)
(1)
(1)
–
–
–
–
–
0
–
–
Reserved
–
–
–
–
–
–
0
0
No de-emphasis
–
–
–
–
–
–
0
1
De-emphasis for fS = 32 kHz
–
–
–
–
–
–
1
0
De-emphasis for fS = 44.1 kHz
–
–
–
–
–
–
1
1
De-emphasis for fS = 48 kHz
(1)
(1)
(1)
(1)
Default values are in bold.
9.6.5 Serial Data Interface Register (0x04)
As shown in Table 9, the TAS5721 supports nine serial data modes. The default is 24-bit, I2S mode,
Table 9. Serial Data Interface Control Register (0x04) Format
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD
LENGTH
D7–D4
D3
D2
D1
D0
Right-justified
16
0000
0
0
0
0
Right-justified
20
0000
0
0
0
1
Right-justified
24
0000
0
0
1
0
2
I S
16
000
0
0
1
1
I2S
20
0000
0
1
0
0
24
0000
0
1
0
1
Left-justified
16
0000
0
1
1
0
Left-justified
20
0000
0
1
1
1
Left-justified
24
0000
1
0
0
0
Reserved
0000
1
0
0
1
Reserved
0000
1
0
1
0
Reserved
0000
1
0
1
1
Reserved
0000
1
1
0
0
Reserved
0000
1
1
0
1
Reserved
0000
1
1
1
0
Reserved
0000
1
1
1
1
I2S
(1)
(1)
Default values are in bold.
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9.6.6 System Control Register 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs
are shut down (hard mute).
Table 10. System Control Register 2 (0x05)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
Mid-Z ramp disabled
1
–
–
–
–
–
–
–
Mid-Z ramp enabled
–
0
–
–
–
–
–
–
Exit all-channel shutdown (normal operation)
–
1
–
–
–
–
–
–
Enter all-channel shutdown (hard mute) (1)
–
–
–
–
–
0
–
–
2.0 mode [2.0 BTL]
–
–
–
–
–
1
–
–
2.1 mode [2 SE + 1 BTL]
–
–
–
–
–
–
0
–
ADR/FAULT pin is configured as to serve as an address input only (1)
–
–
–
–
–
–
1
–
ADR/FAULT pin is configured as fault output
–
–
0
0
0
–
–
0
Reserved
(1)
FUNCTION
(1)
(1)
(1)
Default values are in bold.
9.6.7 Soft Mute Register (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 11. Soft Mute Register (0x06)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
–
–
–
Reserved
–
–
–
–
–
0
–
–
Soft unmute channel 3
–
–
–
–
–
1
–
–
Soft mute channel 3
–
–
–
–
–
–
0
–
Soft unmute channel 2
–
–
–
–
–
–
1
–
Soft mute channel 2
–
–
–
–
–
–
–
0
Soft unmute channel 1
–
–
–
–
–
–
–
1
Soft mute channel 1
(1)
46
FUNCTION
(1)
(1)
(1)
(1)
Default values are in bold.
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9.6.8 Volume Registers (0x07, 0x08, 0x09, 0x0A)
Step size is 0.5 dB
Master volume
– 0x07 (default is mute)
Channel-1 volume
– 0x08 (default is 0 dB)
Channel-2 volume
– 0x09 (default is 0 dB)
Channel-3 volume
– 0x0A (default is 0 dB)
Table 12. Volume Registers (0x07, 0x08, 0x09, 0x0A)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
24 dB
0
0
1
1
0
0
0
0
0 dB (default for individual channel volume)
1
1
1
1
1
1
1
0
–103 dB
1
1
1
1
1
1
1
1
Soft mute (default for the master volume) (1)
(1)
FUNCTION
(1)
Default values are in bold.
9.6.9 Volume Configuration Register (0x0E)
Bits
D2–D0:
Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the
number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows:
Sample Rate (KHz)
Approximate Ramp Rate
8/16/32
125 us/step
11.025/22.05/44.1
90.7 us/step
12/24/48
83.3 us/step
Table 13. Volume Control Register (0x0E)
D7
(1)
(2)
D6
D5
D4
D3
D2
D1
D0
FUNCTION
(1)
1
–
–
1
0
–
–
–
Reserved
–
0
–
–
–
–
–
–
Subchannel (ch4) volume = ch1 volume (2) (1)
–
1
–
–
–
–
–
–
Subchannel volume = register 0x0A (2)
–
–
0
–
–
–
–
–
Ch3 volume = ch2 volume (1)
–
–
1
–
–
–
–
–
Ch3 volume = register 0x0A
–
–
–
–
–
0
0
0
Volume slew 512 steps (43-ms volume ramp time at 48 kHz)
–
–
–
–
–
0
0
1
Volume slew 1024 steps (85-ms volume ramp time at 48 kHz)
–
–
–
–
–
0
1
0
Volume slew 2048 steps (171- ms volume ramp time at 48 kHz)
–
–
–
–
–
0
1
1
Volume slew 256 steps (21-ms volume ramp time at 48 kHz)
–
–
–
–
–
1
X
X
Reserved
(1)
Default values are in bold.
Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)].
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9.6.10 Modulation Limit Register (0x10)
The modulation limit is the maximum duty cycle of the PWM output waveform. It is important to note that for any
applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.
Table 14. Modulation Limit Register (0x10)
(1)
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION LIMIT
–
–
–
–
–
0
0
0
99.2%
–
–
–
–
–
0
0
1
–
–
–
–
–
0
1
0
–
–
–
–
–
0
1
1
96.9%
–
–
–
–
–
1
0
0
96.1%
–
–
–
–
–
1
0
1
95.3%
–
–
–
–
–
1
1
0
94.5%
–
–
–
–
–
1
1
1
93.8%
0
0
0
0
0
–
–
–
RESERVED
98.4%
97.7%
(1)
Default values are in bold.
9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 15. Channel Interchannel Delay Register Format
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Delay = (value) × 4 DCLKs
0x11
1
0
1
0
1
1
–
–
Default value for channel 1
0x12
0
1
0
1
0
1
–
–
Default value for channel 2
(1)
(1)
0x13
1
0
1
0
1
1
–
–
Default value for channel 1
(1)
0x14
0
1
0
1
0
1
–
–
Default value for channel 2
(1)
0
0
0
0
0
0
–
–
Minimum absolute delay, 0 DCLK cycles
0
1
1
1
1
1
–
–
Maximum positive delay, 31 × 4 DCLK cycles
1
0
0
0
0
0
–
–
Maximum negative delay, –32 × 4 DCLK cycles
0
0
RESERVED
RANGE OF VALUES FOR 0x11 - 0x14
(1)
Default values are in bold.
The ICD settings have high impact on audio performance (for example, dynamic range, THD+N, crosstalk, and
so forth). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD
mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.
48
REGISTER
AD MODE
BD MODE
0x11
AC
B8
0x12
54
60
0x13
AC
A0
0x14
54
48
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9.6.12 Pwm Shutdown Group Register (0x19)
Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and
0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the
state of bit D6 in the system control register.
This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group
register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D6 is
set to 0 in system control register 2, 0x05).
Table 16. Shutdown Group Register
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
Reserved
(1)
–
0
–
–
–
–
–
–
Reserved
(1)
–
–
1
–
–
–
–
–
Reserved
(1)
–
–
–
1
–
–
–
–
Reserved
(1)
–
–
–
–
0
–
–
–
PWM channel 4 does not belong to shutdown group.
–
–
–
–
1
–
–
–
PWM channel 4 belongs to shutdown group.
–
–
–
–
–
0
–
–
PWM channel 3 does not belong to shutdown group.
–
–
–
–
–
1
–
–
PWM channel 3 belongs to shutdown group.
–
–
–
–
–
–
0
–
PWM channel 2 does not belong to shutdown group.
–
–
–
–
–
–
1
–
PWM channel 2 belongs to shutdown group.
–
–
–
–
–
–
–
0
PWM channel 1 does not belong to shutdown group.
–
–
–
–
–
–
–
1
PWM channel 1 belongs to shutdown group.
(1)
FUNCTION
(1)
(1)
(1)
(1)
Default values are in bold.
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9.6.13 Start/stop Period Register (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times
are only approximate and vary depending on device activity level and I2S clock stability.
Table 17. Start/Stop Period Register (0x1A)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
SSTIMER enabled (1)
1
–
–
–
–
–
–
–
SSTIMER disabled
–
0
0
–
–
–
–
–
Reserved
–
–
–
0
0
–
–
–
No 50% duty cycle start/stop period
–
–
–
0
1
0
0
0
16.5-ms 50% duty cycle start/stop period
–
–
–
0
1
0
0
1
23.9-ms 50% duty cycle start/stop period
–
–
–
0
1
0
1
0
31.4-ms 50% duty cycle start/stop period
–
–
–
0
1
0
1
1
40.4-ms 50% duty cycle start/stop period
–
–
–
0
1
1
0
0
53.9-ms 50% duty cycle start/stop period
–
–
–
0
1
1
0
1
70.3-ms 50% duty cycle start/stop period
–
–
–
0
1
1
1
0
94.2-ms 50% duty cycle start/stop period
–
–
–
0
1
1
1
1
125.7-ms 50% duty cycle start/stop period (1)
–
–
–
1
0
0
0
0
164.6-ms 50% duty cycle start/stop period
–
–
–
1
0
0
0
1
239.4-ms 50% duty cycle start/stop period
–
–
–
1
0
0
1
0
314.2-ms 50% duty cycle start/stop period
–
–
–
1
0
0
1
1
403.9-ms 50% duty cycle start/stop period
–
–
–
1
0
1
0
0
538.6-ms 50% duty cycle start/stop period
–
–
–
1
0
1
0
1
703.1-ms 50% duty cycle start/stop period
–
–
–
1
0
1
1
0
942.5-ms 50% duty cycle start/stop period
–
–
–
1
0
1
1
1
1256.6-ms 50% duty cycle start/stop period
–
–
–
1
1
0
0
0
1728.1-ms 50% duty cycle start/stop period
–
–
–
1
1
0
0
1
2513.6-ms 50% duty cycle start/stop period
–
–
–
1
1
0
1
0
3299.1-ms 50% duty cycle start/stop period
–
–
–
1
1
0
1
1
4241.7-ms 50% duty cycle start/stop period
–
–
–
1
1
1
0
0
5655.6-ms 50% duty cycle start/stop period
–
–
–
1
1
1
0
1
7383.7-ms 50% duty cycle start/stop period
–
–
–
1
1
1
1
0
9897.3-ms 50% duty cycle start/stop period
–
–
–
1
1
1
1
1
13,196.4-ms 50% duty cycle start/stop period
(1)
50
FUNCTION
(1)
Default values are in bold.
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9.6.14 Oscillator Trim Register (0x1B)
The TAS5721 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. TI recommends a reference resistor value of
that shown in the Typical Application Diagrams. The circuit that uses this resistor should be calibrated or trimmed
after each time the device is reset.
Writing 0x00 to register 0x1B enables the trim that was programmed at the factory. It is important to note that
after writing the value 0x00 to the trim register, the register will repor the value 0xC0, to indicate the trim process
is complete.
Table 18. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
1
–
–
–
–
–
–
–
Reserved
–
0
–
–
–
–
–
–
Oscillator trim not done (read-only)
–
1
–
–
–
–
–
–
Oscillator trim done (read only)
–
–
0
0
0
0
–
–
Reserved
–
–
–
–
–
–
0
–
Select factory trim (Write a 0 to select factory trim; default is 1.)
–
–
–
–
–
–
1
–
Factory trim disabled
–
(1)
–
–
–
–
–
–
0
FUNCTION
Reserved
(1)
(1)
(1)
(1)
(1)
Default values are in bold.
9.6.15 BKND_ERR Register (0x1C)
When a backend error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting
to restart the power stage.
Table 19. BKND_ERR Register (0x1C) (1)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
X
Reserved
–
–
–
–
0
0
1
0
Set back-end reset period to 299 ms
–
–
–
–
0
0
1
1
Set back-end reset period to 449 ms
–
–
–
–
0
1
0
0
Set back-end reset period to 598 ms
–
–
–
–
0
1
0
1
Set back-end reset period to 748 ms
–
–
–
–
0
1
1
0
Set back-end reset period to 898 ms
–
–
–
–
0
1
1
1
Set back-end reset period to 1047 ms
–
–
–
–
1
0
0
0
Set back-end reset period to 1197 ms
–
–
–
–
1
0
0
1
Set back-end reset period to 1346 ms
–
–
–
–
1
0
1
X
–
–
–
–
1
1
X
X
(1)
(2)
FUNCTION
(2)
Set back-end reset period to 1496 ms
This register can be written only with a non-reserved value. Also this register can be only be written once after the device is reset. If a
different value is desired, the device must be reset before changing 0x1C again.
Default values are in bold.
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9.6.16 Input Multiplexer Register (0x20)
This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal
channels.
Table 20. Input Multiplexer Register (0x20)
D31
0
D30
0
D29
0
D28
0
D27
0
D26
-
D25
-
D24
-
Polarity of Ch3 is not inverted
1
Polarity of Ch3 is inverted
Polarity of Ch2 is not inverted
1
Polarity of Ch2 is inverted
0
Polarity of Ch1 is not inverted
1
Polarity of Ch1 is inverted
D23
D22
D21
D20
D19
D18
D17
D16
0
–
–
–
–
–
–
–
Channel-1 AD mode
1
–
–
–
–
–
–
–
Channel-1 BD mode
–
0
0
0
–
–
–
–
SDIN-L to channel 1
–
0
0
1
–
–
–
–
SDIN-R to channel 1
–
0
1
0
–
–
–
–
Reserved
–
0
1
1
–
–
–
–
Reserved
–
1
0
0
–
–
–
–
Reserved
–
1
0
1
–
–
–
–
Reserved
–
1
1
0
–
–
–
–
Ground (0) to channel 1
–
1
1
1
–
–
–
–
Reserved
–
–
–
–
0
–
–
–
Channel 2 AD mode
–
–
–
–
1
–
–
–
Channel 2 BD mode
–
–
–
–
–
0
0
0
SDIN-L to channel 2
–
–
–
–
–
0
0
1
SDIN-R to channel 2
–
–
–
–
–
0
1
0
Reserved
–
–
–
–
–
0
1
1
Reserved
–
–
–
–
–
1
0
0
Reserved
–
–
–
–
–
1
0
1
Reserved
–
–
–
–
–
1
1
0
Ground (0) to channel 2
–
–
–
–
–
1
1
1
Reserved
D15
D14
D13
D12
D11
D10
D9
D8
0
1
1
1
0
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
52
Reserved
0
0
(1)
FUNCTION
(1)
1
1
1
FUNCTION
(1)
(1)
(1)
(1)
FUNCTION
Reserved
(1)
FUNCTION
0
Sub channel in 2.1 mode, AD modulation
1
Sub channel in 2.1 mode, BD modulation
-
0
1
0
Reserved
(1)
Default values are in bold.
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9.6.17 Channel 4 Source Select Register (0x21)
This register selects the channel 4 source.
Table 21. Subchannel Control Register (0x21)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved (1)
FUNCTION
Reserved
(1)
Reserved
(1)
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
1
0
0
0
0
1
–
–
–
–
–
–
–
0
(L + R)/2
–
–
–
–
–
–
–
1
Left-channel post-BQ
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
1
(1)
FUNCTION
(1)
FUNCTION
Reserved
(1)
Default values are in bold.
9.6.18 PWM Output MUX Register (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D21–D20:
Selects which PWM channel is output to OUT_A
Bits D17–D16:
Selects which PWM channel is output to OUT_B
Bits D13–D12:
Selects which PWM channel is output to OUT_C
Bits D09–D08:
Selects which PWM channel is output to OUT_D
Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.
See Table 22 for details.
Table 22. PWM Output Mux Register (0x25)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
1
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved (1)
FUNCTION
(1)
0
0
–
–
–
–
–
–
Reserved
–
–
0
0
–
–
–
–
Multiplex PWM 1 to OUT_A
–
–
0
1
–
–
–
–
Multiplex PWM 2 to OUT_A
–
–
1
0
–
–
–
–
Multiplex PWM 3 to OUT_A
–
–
1
1
–
–
–
–
Multiplex PWM 4 to OUT_A
–
–
–
–
0
0
–
–
Reserved
–
–
–
–
–
–
0
0
Multiplex PWM 1 to OUT_B
–
–
–
–
–
–
0
1
Multiplex PWM 2 to OUT_B
–
–
–
–
–
–
1
0
Multiplex PWM 3 to OUT_B
–
–
–
–
–
–
1
1
Multiplex PWM 4 to OUT_B
D15
D14
D13
D12
D11
D10
D9
D8
0
0
–
–
–
–
–
–
Reserved
–
–
0
0
–
–
–
–
Multiplex PWM 1 to OUT_C
–
–
0
1
–
–
–
–
Multiplex PWM 2 to OUT_C (1)
(1)
(1)
(1)
(1)
FUNCTION
(1)
Default values are in bold.
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Table 22. PWM Output Mux Register (0x25) (continued)
–
–
1
0
–
–
–
–
Multiplex PWM 3 to OUT_C
–
–
1
1
–
–
–
–
Multiplex PWM 4 to OUT_C
–
–
–
–
0
0
–
–
Reserved
–
–
–
–
–
–
0
0
Multiplex PWM 1 to OUT_D
–
–
–
–
–
–
0
1
Multiplex PWM 2 to OUT_D
–
–
–
–
–
–
1
0
Multiplex PWM 3 to OUT_D
–
–
–
–
–
–
1
1
Multiplex PWM 4 to OUT_D
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
1
(1)
(1)
FUNCTION
Reserved
(1)
9.6.19 DRC Control (0x46)
Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.
Table 23. DRC Control Register
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved
(1)
Reserved
(1)
Reserved
(1)
FUNCTION
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Disable complementary (1–H) low-pass filter generation
–
–
1
–
–
–
–
–
Enable complementary (1–H) low-pass filter generation
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
–
0
0
(1)
54
FUNCTION
FUNCTION
Reserved
(1)
(1)
(1)
–
–
–
–
–
–
0
–
DRC2 turned OFF
–
–
–
–
–
–
1
–
DRC2 turned ON
–
–
–
–
–
–
–
0
DRC1 turned OFF
–
–
–
–
–
–
–
1
DRC1 turned ON
(1)
(1)
Default values are in bold.
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9.6.20 Bank Switch and EQ Control (0x50)
The bank switching feature is described in detail in section Bank Switching.
Table 24. Bank Switching Command
D31
D30
D29
D28
D27
D26
D25
D24
0
–
–
–
–
–
–
–
32 kHz, does not use bank 3
1
–
–
–
–
–
–
–
32 kHz, uses bank 3
–
0
–
–
–
–
–
–
Reserved (1)
–
–
0
–
–
–
–
–
Reserved (1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 3
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 3
–
–
–
–
0
–
–
–
16 kHz, does not use bank 3
–
–
–
–
1
–
–
–
16 kHz, uses bank 3
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 3
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 3
–
–
–
–
–
–
0
–
8 kHz, does not use bank 3
–
–
–
–
–
–
1
–
8 kHz, uses bank 3
–
–
–
–
–
–
–
0
11.025 kHz/12, does not use bank 3
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 3
D23
D22
D21
D20
D19
D18
D17
D16
0
–
–
–
–
–
–
–
32 kHz, does not use bank 2
1
–
–
–
–
–
–
–
32 kHz, uses bank 2
–
1
–
–
–
–
–
–
Reserved
(1)
–
–
1
–
–
–
–
–
Reserved
(1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 2
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 2
–
–
–
–
0
–
–
–
16 kHz, does not use bank 2
–
–
–
–
1
–
–
–
16 kHz, uses bank 2
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 2
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 2
–
–
–
–
–
–
0
–
8 kHz, does not use bank 2
–
–
–
–
–
–
1
–
8 kHz, uses bank 2
–
–
–
–
–
–
–
0
11.025/12 kHz, does not use bank 2
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 2
D15
D14
D13
D12
D11
D10
D9
D8
0
–
–
–
–
–
–
–
32 kHz, does not use bank 1
1
–
–
–
–
–
–
–
32 kHz, uses bank 1
(1)
FUNCTION
(1)
(1)
(1)
(1)
(1)
(1)
FUNCTION
(1)
(1)
(1)
(1)
(1)
(1)
FUNCTION
(1)
(1)
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Reserved (1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 1
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 1
–
–
–
–
0
–
–
–
16 kHz, does not use bank 1
–
–
–
–
1
–
–
–
16 kHz, uses bank 1
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 1
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 1
–
–
–
–
–
–
0
–
8 kHz, does not use bank 1
–
–
–
–
–
–
1
–
8 kHz, uses bank 1
–
–
–
–
–
–
–
0
11.025/12 kHz, does not use bank 1
(1)
(1)
(1)
(1)
(1)
Default values are in bold.
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Table 24. Bank Switching Command (continued)
–
–
–
–
–
–
–
1
D7
D6
D5
D4
D3
D2
D1
D0
0
11.025/12 kHz, uses bank 1
FUNCTION
EQ ON
1
–
–
–
–
–
–
–
EQ OFF (bypass BQ 0-7 of channels 1 and 2)
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Ignore bank-mapping in bits D31–D8.Use default mapping.
–
–
–
0
–
–
–
–
L and R can be written independently.
–
–
–
1
–
–
–
–
L and R are ganged for EQ biquads; a write to left-channel BQ is also
written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also
0x58–0x5B is ganged to 0x5C–0x5F)
–
–
–
–
0
–
–
–
Reserved
–
–
–
–
–
0
0
0
No bank switching. All configuration of the BiQuads are applied
directly to the DAP (1)
–
–
–
–
–
0
0
1
Configure bank 1 (32 kHz by default)
–
–
–
–
–
0
1
0
Configure bank 2 (44.1/48 kHz by default)
–
–
–
–
–
0
1
1
Configure bank 3 (other sample rates by default)
–
–
–
–
–
1
0
0
Automatic bank selection
–
–
–
–
–
1
0
1
Reserved
–
–
–
–
–
1
1
X
Reserved
1
(1)
(1)
Use bank-mapping in bits D31–D8.
(1)
(1)
All DAP coefficients are 3.23 format unless specified otherwise.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The typical connection diagram highlights the required external components and system level connections for
proper operation of the device in several popular system examples.
Each of these configurations can be realized using the Evaluation Module (EVM) for the device. These flexible
modules allow full evaluation of the device in the most common modes of operation. Any design variation can be
supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the
audio amplifier discussion forum for additional information.
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10.2 Typical Application
R2
10K
0402
C1
1.5 µfd/10 V
0402 X5R
R1
R3
10K
0402
C2
DNP
C3
DNP
220 pfd/50 V
0402 COG
0
0402
HEADPHONES
FOR PWM
INPUT ONLY
1000 pfd/50 V
0402 COG
GND
STUFF
OPTION
R5
L1
10K
0402
C4
1.5 µfd/10 V
0402 X5R
R4
R6
10K
0402
C5
C6
DNP
C27
220 pfd/50 V
0402 COG
C7
0
0402
U1
0.033 µfd/50 V
0402 X7R
1
PVDD
DNP
2
1000 pfd/50 V
0402 COG
3
+
GND
C8
C9
4
220 µfd/35 V
M
0.1 µfd/50 V
0402 X7R
5
PGND
SPK_OUTB
SPK_OUTA
BSTRPB
AVDD
C12
C13
10 µfd/6.3 V
0603 X5R
1 µfd/10 V
0402 X5R
GND
6
GND
DR_INA
7
DR_OUTA
8
DR_OUTB
GND
9
DR_INB
C10
10
0.047 µfd/16 V
0402 X7R
11
System Processor
and
Associated Components
R7
470
0402
C15
14
15
16
17
18
19
AVDD
C19
0.1 µfd/16 V
0402 X7R
GND
BSTRPD
21
R9
GND
22
18.20K
0402
GND
DR_INB
SSTIMER
42
R15
C23
GND
330 pfd/50 V
0402 COG
C30
GND
GND
R16
330 pfd/50 V
0402 COG
18
0603
DGND
DVDD
TEST3
AVDD_REG1
RST
AVDD
ADR/FAULT
SCL
MCLK
SDA
SDIN
OSC_RES
LRCLK
OSC_GND
PDN
DVDD_REG
C39
C36
0.33 µfd/50 V
0805 X7R
15 µH/3.5 A
A7503AY
0.33 µfd/50 V
0805 X7R
GND
C40
0.33 µfd/50 V
0805 X7R
OUTPUTS
STUFF OPTION NOTE
PVDD
GND
C26
PLL_FLTP
GND
GND
38
0.1 µfd/16 V
0402 X7R
35
C32
0.1 µfd/50 V
0402 X7R
37
36
15 µH/3.5 A
A7503AY
18
0603
39
DRVDD
PLL_FLTM
C38
0.33 µfd/50 V
0805 X7R
L4
40
2200 pfd/50 V
0402 X7R
AVDD_REG2
15 µH/3.5 A
A7503AY
18
0603
41
DR_CP
PLL_GND
0.33 µfd/50 V
0805 X7R
GND
+
C31
220 µfd/35 V
M
GND
GND
GND
34
33
32
31
30
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
DVDD
C34
C33
0.1 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
GND
GND
29
28
27
26
25
TAS5721DCA
C20
GND
R14
330 pfd/50 V
0402 COG
C29
43
C24
DR_CN
0.33 µfd/50 V
0805 X7R
44
DR_VSS
DR_SD
C37
C35
L3
0.033 µfd/50 V
0402 X7R
SCLK
23
24
4.7 µfd/6.3 V
0402 X5R
C28
GND
45
DR_OUTB
NC
20
15k
GND
SPK_OUTD
DR_OUTA
AGND
0.047 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
PGND
DR_INA
1 µfd/10 V
0402 X5R
R8
C18
SPK_OUTC
18
0603
C25
13
4700 pfd/25 V
0402 X7R
TEST2
1 µfd/25 V
0603 X5R
12
GND
C16
TEST1
GVDD_REG
GND
C17
C22
C11
4700 pfd/25 V
0402 X7R
470
0402
46
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
L2
0.033 µfd/50 V
0402 X7R
1 µfd/10 V
0402 X5R
GND
C21
0.033 µfd/50 V
0402 X7R
PVDD
PVDD
C14
47
BSTRPA
BSTRPC
GND
GND
48
R13
GND
HTSSOP48-DCA
GND
U1
HTSSOP48-DCA
PowerPAD
GND
Figure 71. Mono PBTL System With Headphone Driver
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10.2.1 Design Requirements
Table 25 lists the design parameters of the TAS5721.
Table 25. Design Parameters
PARAMETER
EXAMPLE
Low Power Supply
3.3 V
High Power Supply
8 V to 24 V
Host Processor
I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters
Inductor-Capacitor Low Pass Filter (1)
Speaker
8 Ω minimum BTL
4 Ω minimum PBTL and Single Ended
(1)
Refer to SLOA119 for a detailed description on the filter design.
10.2.2 Detailed Design Procedure
10.2.2.1 Component Selection and Hardware Connections
The typical connections required for proper operation of the device can be found on the TAS5721EVM User’s
Guide (SLOU346). The device was tested this this list of components, deviation from this typical application
components unless recommended by this document may produce unwanted results, which could range from
degradation of audio performance to destructive failure of the device. The application report SLOA119 offers a
detailed description on proper component selection and design of the output filter based upon the modulation
used, desired load and response.
10.2.2.2 I2C Pullup Resistors
Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical
Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part
of the associated passive components for the System Processor. These resistor values should be chosen per the
guidance provided in the I²C Specification.
10.2.2.3 Digital I/O Connectivity
The digital I/O lines of the TAS5721 are described in previous sections. As discussed, whenever a static digital
pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to
DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not,
however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor
can be used to tie all static I/O lines HIGH to reduce BOM count.
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10.2.2.4 Recommended Startup and Shutdown Procedures
10.2.2.4.1 Recommended Use Model
Normal Operation
Initialization
AVDD/DVDD
Powerdown
Shutdown
3V
3V
0 ns
PDN
2 ms
0 ns
2
I C
SCL
SDA
DAP
Config
Trim
Other
Config
Exit
SD
Enter
SD
Volume and Mute Commands
(2)(3)
50 ms
1 ms + 1.3 tstop
1 ms + 1.3 tstart
(2)
2 ms
0 ns
100 ms
RST
13.5 ms
(1)
tPLL
2 ms
100 μs
10 ms
PVDD
8V
6V
8V
6V
(1) tPLL has to be greater than 240 ms + 1.3 tstart.
This constraint only applies to the first trim command following AVDD/DVDD power-up.
It does not apply to trim commands following subsequent resets.
(2) tstart/tstop = PWM start/stop time as defined in register 0X1A
(3) When Mid-Z ramp is enabled (for 2.1 mode), tstart = 300 ms
T0419-07
Figure 72. Recommended Command Sequence
3V
AVDD/DVDD
0 ns
PDN
2 ms
0 ns
2
I C
2 ms
RST
2 ms
0 ns
8V
PVDD
6V
T0420-06
Figure 73. Power Loss Sequence
10.2.2.4.1.1 Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
2. Initialize digital inputs and PVDD supply as follows:
– Drive RST = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never
more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RST = 1, and wait at least another 13.5
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3.
4.
5.
6.
SLOS739A – JULY 2012 – REVISED MARCH 2016
ms.
– Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after
AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
Configure the DAP via I2C (see Users's Guide for typical values).
Configure remaining registers.
Exit shutdown (sequence defined below).
10.2.2.4.1.2 Normal Operation
The following are the only events supported during normal operation:
1. Writes to master/channel volume registers.
2. Writes to soft mute register.
3. Enter and exit shutdown (sequence defined below).
NOTE
Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD powerup
ramp (where tstart is 300 ms when mid-Z ramp is enabled and is otherwise specified by
register 0x1A).
10.2.2.4.1.3 Shutdown Sequence
Enter:
1. Write 0x40 to register 0x05.
2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A).
3. If desired, reconfigure by returning to step 4 of initialization sequence.
Exit:
1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim
following AVDD/DVDD powerup ramp).
2. Wait at least 1 ms + 1.3 × tstart (where tstart is 300 ms when mid-Z ramp is enabled and is otherwise specified
by register 0x1A).
3. Proceed with normal operation.
10.2.2.4.1.4 Power-Down Sequence
Use the following sequence to powerdown the device and its supplies:
1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert PDN =
0 and wait at least 2 ms.
2. Assert RST = 0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
– Drive all digital inputs low after RST has been low for at least 2 µs.
– Ramp down PVDD while ensuring that it remains above 8 V until RST has been low for at least 2 µs.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is
never more than 2.5 V below the digital inputs.
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10.2.3 Application Curves
100
7
TA = 25°C
90
6
80
70
Efficiency (%)
Output Power (W)
5
4
3
2
1
0
8
10
12
14
RL = 2x8Ÿ
Ÿ THD+N = 1%
RL = 2x8Ÿ
Ÿ THD+N = 10%
RL = 2x4Ÿ
Ÿ THD+N = 1%
RL = 2x4Ÿ
Ÿ THD+N = 10%
RL = 2x4Ÿ
Ÿ THD+N = 1%
RL = 2x4Ÿ
Ÿ THD+N = 10%
16
18
20
22
60
50
40
30
PVDD = 12V
PVDD = 18V
PVDD = 24V
20
10
0
24
Supply Voltage (V)
0
5
C002
2.0 BTL Mode
RL = 8Ω
TA = 25°C
All Channels Driven
10
15
Total Output Power (W)
20
G025
Figure 75. Efficiency vs Output Power in 2.0 Mode
Figure 74. Output Power vs PVDD in 2.1 Mode
0
2.0 BTL Mode
PO = 1W
PVDD = 12V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
Crosstalk (dB)
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
Frequency (Hz)
10k
20k
G033
Figure 76. Crosstalk vs Frequency in 2.0 Mode
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10.3 System Examples
R2
10K
0402
C1
1.5 µfd/10 V
0402 X5R
R1
R3
10K
0402
0
0402
C2
DNP
C3
DNP
220 pfd/50 V
0402 COG
HEADPHONES
FOR PWM
INPUT ONLY
1000 pfd/50 V
0402 COG
GND
STUFF
OPTION
R5
L1
10K
0402
C4
1.5 µfd/10 V
0402 X5R
R4
R6
10K
0402
C5
C6
DNP
C27
220 pfd/50 V
0402 COG
C7
0
0402
U1
0.033 µfd/50 V
0402 X7R
1
PVDD
DNP
2
1000 pfd/50 V
0402 COG
3
+
GND
C8
C9
4
220 µfd/35 V
M
0.1 µfd/50 V
0402 X7R
5
SPK_OUTB
PGND
BSTRPB
SPK_OUTA
AVDD
C12
C13
10 µfd/6.3 V
0603 X5R
1 µfd/10 V
0402 X5R
GND
6
GND
7
8
9
GND
10
0.047 µfd/16 V
0402 X7R
System Processor
and
Associated Components
R7
470
0402
TEST2
SPK_OUTC
PGND
DR_INA
SPK_OUTD
DR_OUTA
BSTRPD
4700 pfd/25 V
0402 X7R
13
14
R8
15
C17
4700 pfd/25 V
0402 X7R
17
18
19
AVDD
C19
10 µfd/6.3 V
0603 X5R
0.1 µfd/16 V
0402 X7R
GND
21
R9
22
18.20K
0402
GND
24
GND
GND
0.33 µfd/50 V
0805 X7R
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
18
0603
DGND
PLL_FLTM
DVDD
PLL_FLTP
TEST3
AVDD_REG1
RST
AVDD
ADR/FAULT
SCL
MCLK
SDA
SDIN
OSC_RES
LRCLK
OSC_GND
PDN
DVDD_REG
GND
OUTPUTS
C30
GND
GND
R16
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
18
0603
0.33 µfd/50 V
0805 X7R
GND
C40
0.33 µfd/50 V
0805 X7R
GND
STUFF OPTION NOTE
38
PVDD
GND
0.1 µfd/16 V
0402 X7R
35
C32
0.1 µfd/50 V
0402 X7R
37
36
C39
C36
0.33 µfd/50 V
0805 X7R
L4
C26
AVDD_REG2
PLL_GND
C38
+
C31
220 µfd/35 V
M
GND
GND
GND
34
33
32
31
30
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
DVDD
C34
C33
0.1 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
GND
GND
29
28
27
26
25
TAS5721DCA
C20
GND
15 µH/3.5 A
A7503AY
39
2200 pfd/50 V
0402 X7R
SCLK
23
15k
4.7 µfd/6.3 V
0402 X5R
C23
40
DRVDD
NC
20
GND
R15
41
DR_CP
AGND
16
0.047 µfd/16 V
0402 X7R
C18
SSTIMER
0.33 µfd/50 V
0805 X7R
GND
18
0603
C25
1 µfd/10 V
0402 X5R
GND
C16
42
C24
DR_SD
R14
330 pfd/50 V
0402 COG
C29
43
DR_VSS
DR_CN
0.33 µfd/50 V
0805 X7R
L3
1 µfd/25 V
0603 X5R
12
C28
GND
0.033 µfd/50 V
0402 X7R
GVDD_REG
C37
C35
44
DR_OUTB
DR_INB
18
0603
45
C11
GND
470
0402
C22
TEST1
1 µfd/10 V
0402 X5R
GND
46
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
L2
0.033 µfd/50 V
0402 X7R
PVDD
11
C15
C21
0.033 µfd/50 V
0402 X7R
PVDD
C10
C14
47
BSTRPA
BSTRPC
GND
GND
48
R13
GND
HTSSOP48-DCA
GND
U1
HTSSOP48-DCA
PowerPAD
GND
Figure 77. Typical Application Circuit for Stereo (BTL) Configuration
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System Examples (continued)
R2
10K
0402
C1
1.5 µfd/10 V
0402 X5R
R1
R3
10K
0402
C2
DNP
C3
DNP
220 pfd/50 V
0402 COG
0
0402
HEADPHONES
FOR PWM
INPUT ONLY
1000 pfd/50 V
0402 COG
GND
STUFF
OPTION
R5
L1
10K
0402
C4
1.5 µfd/10 V
0402 X5R
R4
R6
10K
0402
C5
C6
DNP
C27
220 pfd/50 V
0402 COG
C7
0
0402
U1
0.033 µfd/50 V
0402 X7R
1
PVDD
DNP
2
1000 pfd/50 V
0402 COG
3
+
GND
C8
C9
4
220 µfd/35 V
M
0.1 µfd/50 V
0402 X7R
5
PGND
SPK_OUTB
SPK_OUTA
BSTRPB
AVDD
C12
C13
10 µfd/6.3 V
0603 X5R
1 µfd/10 V
0402 X5R
GND
6
GND
7
8
9
GND
10
0.047 µfd/16 V
0402 X7R
R7
System Processor
and
Associated Components
470
0402
TEST2
SPK_OUTC
PGND
DR_INA
SPK_OUTD
DR_OUTA
BSTRPD
4700 pfd/25 V
0402 X7R
13
14
R8
15
C17
4700 pfd/25 V
0402 X7R
17
18
19
AVDD
C19
10 µfd/6.3 V
0603 X5R
0.1 µfd/16 V
0402 X7R
GND
21
R9
22
18.20K
0402
GND
24
GND
C38
0.33 µfd/50 V
0805 X7R
GND
GND
R15
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
18
0603
C39
C36
0.33 µfd/50 V
0805 X7R
0.33 µfd/50 V
0805 X7R
L4
C30
GND
GND
R16
330 pfd/50 V
0402 COG
GND
15 µH/3.5 A
A7503AY
C40
18
0603
0.33 µfd/50 V
0805 X7R
39
GND
STUFF OPTION NOTE
38
2200 pfd/50 V
0402 X7R
PVDD
GND
C26
AVDD_REG2
PLL_GND
PLL_FLTM
DGND
PLL_FLTP
DVDD
TEST3
AVDD_REG1
RST
AVDD
ADR/FAULT
SCL
MCLK
SDA
SDIN
OSC_RES
OSC_GND
LRCLK
PDN
DVDD_REG
0.1 µfd/50 V
0402 X7R
37
36
0.1 µfd/16 V
0402 X7R
35
C32
+
C31
220 µfd/35 V
M
GND
GND
GND
34
33
32
31
30
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
DVDD
C34
C33
0.1 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
GND
29
28
GND
STUFF OPTION
PVDD
PVDD
27
26
25
+
R17
15K
0402 1/16W
TAS5721DCA
C20
GND
SSTIMER
SCLK
23
15k
4.7 µfd/6.3 V
0402 X5R
C29
C23
40
DRVDD
NC
20
GND
15 µH/3.5 A
A7503AY
18
0603
41
DR_CP
AGND
16
0.047 µfd/16 V
0402 X7R
C18
GND
C25
1 µfd/10 V
0402 X5R
GND
C16
42
C24
DR_SD
R14
330 pfd/50 V
0402 COG
43
DR_VSS
DR_CN
0.33 µfd/50 V
0805 X7R
0.33 µfd/50 V
0805 X7R
L3
1 µfd/25 V
0603 X5R
12
C28
GND
0.033 µfd/50 V
0402 X7R
GVDD_REG
C37
C35
44
DR_OUTB
DR_INB
18
0603
45
C11
GND
470
0402
C22
TEST1
1 µfd/10 V
0402 X5R
GND
46
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
L2
0.033 µfd/50 V
0402 X7R
PVDD
11
C15
C21
0.033 µfd/50 V
0402 X7R
PVDD
C10
C14
47
BSTRPA
BSTRPC
GND
GND
48
R13
GND
HTSSOP48-DCA
GND
U1
HTSSOP48-DCA
PowerPAD
220 µfd/35 V
M
+
R18
15K
0402 1/16W
C42
220 µfd/35 V
M
GND
PVDD
OUTPUTS
C41
GND
PVDD
GND
+
R19
15K
0402 1/16W
+
R20
15K
0402 1/16W
GND
C43
220 µfd/35 V
M
C44
220 µfd/35 V
M
GND
SPLIT CAP
Figure 78. 2.1 System With Headphone Driver
64
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System Examples (continued)
STUFF
OPTION
L1
C27
C7
U1
0.033 µfd/50 V
0402 X7R
1
PVDD
2
3
+
4
C8
C9
220 µfd/35 V
M
0.1 µfd/50 V
0402 X7R
GND
SPK_OUTB
SPK_OUTA
BSTB
GND
AVDD
C12
10 µfd/6.3 V
0603 X5R
GND
6
GND
7
C13
8
1 µfd/10 V
0402 X5R
9
GND
10
C14
0.047 µfd/16 V
0402 X7R
System Processor
and
Associated Components
R7
470
0402
46
C22
PWM2
SPK_OUTC
GND
NC
SPK_OUTD
NC
BSTD
GND
R14
330 pfd/50 V
0402 COG
C29
42
R15
C23
GND
330 pfd/50 V
0402 COG
13
14
R8
15
470
0402
C17
C16
4700 pfd/25 V
0402 X7R
C30
GND
GND
R16
330 pfd/50 V
0402 COG
18
0603
39
17
18
19
AVDD
C19
10 µfd/6.3 V
0603 X5R
0.1 µfd/16 V
0402 X7R
GND
FLTP
DVDD
TEST
AVDD_REG1
RST
AVDD
NC
20
21
R9
GND
22
18.20K
0402
GND
SDIN1
ROSC
GND
LRCLK
PDN
DVDD_REG
0.1 µfd/16 V
0402 X7R
C32
0.1 µfd/50 V
0402 X7R
37
36
C36
0.33 µfd/50 V
0805 X7R
15 µH/3.5 A
A7503AY
0.33 µfd/50 V
0805 X7R
GND
C40
0.33 µfd/50 V
0805 X7R
+
C31
220 µfd/35 V
M
GND
35
GND
GND
34
33
32
31
30
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
DVDD
C34
C33
0.1 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
GND
GND
29
28
27
26
25
TAS5723DCA
C20
GND
SCL
SDA
SCLK
23
24
4.7 µfd/6.3 V
0402 X5R
ADR
MCLK
OUTPUTS
C39
PVDD
GND
C26
AVDD_REG2
15 µH/3.5 A
A7503AY
STUFF OPTION NOTE
2200 pfd/50 V
0402 X7R
FLTM
GND
GND
38
AVDD2
GND
C38
0.33 µfd/50 V
0805 X7R
L4
40
NC
GND
16
0.047 µfd/16 V
0402 X7R
C18
SSTIMER
15 µH/3.5 A
A7503AY
18
0603
C25
GND
0.33 µfd/50 V
0805 X7R
GND
18
0603
41
C24
TEST
0.33 µfd/50 V
0805 X7R
L3
43
NC
NC
C37
C35
44
1 µfd/25 V
0603 X5R
12
C28
0.033 µfd/50 V
0402 X7R
GVDD_REG
4700 pfd/25 V
0402 X7R
18
0603
45
NC
NC
R13
330 pfd/50 V
0402 COG
L2
0.033 µfd/50 V
0402 X7R
PWM1
C15
GND
GND
C21
0.033 µfd/50 V
0402 X7R
PVDD
PVDD
11
47
BSTA
BSTC
5
GND
48
15 µH/3.5 A
A7503AY
GND
HTSSOP48-DCA
GND
U1
HTSSOP48-DCA
PowerPAD
GND
Figure 79. Stereo (BTL) System
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System Examples (continued)
STUFF
OPTION
L1
C27
C7
U1
0.033 µfd/50 V
0402 X7R
1
PVDD
2
3
+
4
C8
C9
220 µfd/35 V
M
0.1 µfd/50 V
0402 X7R
GND
SPK_OUTB
SPK_OUTA
BSTB
GND
AVDD
C12
C13
10 µfd/6.3 V
0603 X5R
1 µfd/10 V
0402 X5R
GND
6
GND
7
8
9
GND
10
C14
0.047 µfd/16 V
0402 X7R
System Processor
and
Associated Components
R7
470
0402
46
C22
PWM2
SPK_OUTC
GND
NC
SPK_OUTD
NC
BSTD
GND
42
R14
330 pfd/50 V
0402 COG
C29
GND
330 pfd/50 V
0402 COG
13
14
R8
15
470
0402
C17
C16
4700 pfd/25 V
0402 X7R
C30
R16
40
GND
GND
330 pfd/50 V
0402 COG
18
0603
39
16
17
18
19
AVDD
C19
10 µfd/6.3 V
0603 X5R
0.1 µfd/16 V
0402 X7R
AVDD2
FLTM
GND
FLTP
DVDD
TEST
AVDD_REG1
RST
AVDD
NC
20
21
R9
GND
22
18.20K
0402
GND
SDIN1
ROSC
GND
LRCLK
PDN
DVDD_REG
0.33 µfd/50 V
0805 X7R
15 µH/3.5 A
A7503AY
0.33 µfd/50 V
0805 X7R
GND
C40
0.33 µfd/50 V
0805 X7R
0.1 µfd/16 V
0402 X7R
C32
0.1 µfd/50 V
0402 X7R
+
C31
OUTPUTS
220 µfd/35 V
M
GND
35
GND
GND
34
33
32
31
30
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
DVDD
C34
C33
0.1 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
GND
GND
29
28
27
26
25
TAS5723DCA
C20
GND
SCL
SDA
SCLK
23
24
4.7 µfd/6.3 V
0402 X5R
ADR
MCLK
C39
C36
STUFF OPTION NOTE
37
36
15 µH/3.5 A
A7503AY
PVDD
GND
C26
AVDD_REG2
GND
GND
38
2200 pfd/50 V
0402 X7R
GND
C38
0.33 µfd/50 V
0805 X7R
L4
41
NC
GND
0.047 µfd/16 V
0402 X7R
C18
SSTIMER
15 µH/3.5 A
A7503AY
18
0603
C25
GND
0.33 µfd/50 V
0805 X7R
GND
18
0603
R15
C23
C24
TEST
0.33 µfd/50 V
0805 X7R
L3
43
NC
NC
C37
C35
44
1 µfd/25 V
0603 X5R
12
C28
0.033 µfd/50 V
0402 X7R
GVDD_REG
4700 pfd/25 V
0402 X7R
18
0603
45
NC
NC
R13
330 pfd/50 V
0402 COG
L2
0.033 µfd/50 V
0402 X7R
PWM1
C15
GND
GND
C21
0.033 µfd/50 V
0402 X7R
PVDD
PVDD
11
47
BSTA
BSTC
5
GND
48
15 µH/3.5 A
A7503AY
GND
HTSSOP48-DCA
GND
U1
HTSSOP48-DCA
PowerPAD
GND
Figure 80. Mono (PBTL) System
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SLOS739A – JULY 2012 – REVISED MARCH 2016
System Examples (continued)
STUFF
OPTION
L1
C27
C7
U1
0.033 µfd/50 V
0402 X7R
1
PVDD
2
3
+
C8
C9
4
220 µfd/35 V
M
0.1 µfd/50 V
0402 X7R
5
GND
SPK_OUTB
SPK_OUTA
BSTB
AVDD
C12
C13
10 µfd/6.3 V
0603 X5R
1 µfd/10 V
0402 X5R
GND
6
GND
7
8
9
GND
10
0.047 µfd/16 V
0402 X7R
R7
System Processor
and
Associated Components
470
0402
PWM2
SPK_OUTC
GND
NC
SPK_OUTD
NC
BSTD
4700 pfd/25 V
0402 X7R
13
14
R8
15
C17
4700 pfd/25 V
0402 X7R
17
18
19
AVDD
C19
10 µfd/6.3 V
0603 X5R
0.1 µfd/16 V
0402 X7R
GND
21
R9
22
18.20K
0402
GND
SSTIMER
24
GND
C38
0.33 µfd/50 V
0805 X7R
GND
GND
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
18
0603
C39
C36
0.33 µfd/50 V
0805 X7R
0.33 µfd/50 V
0805 X7R
L4
C30
GND
GND
R16
330 pfd/50 V
0402 COG
GND
15 µH/3.5 A
A7503AY
C40
18
0603
0.33 µfd/50 V
0805 X7R
39
GND
STUFF OPTION NOTE
38
2200 pfd/50 V
0402 X7R
PVDD
GND
C26
AVDD_REG2
GND
FLTM
GND
FLTP
DVDD
TEST
AVDD_REG1
RST
AVDD
ADR
SCL
MCLK
SDA
SDIN1
ROSC
SCLK
23
GND
LRCLK
PDN
DVDD_REG
0.1 µfd/50 V
0402 X7R
37
36
0.1 µfd/16 V
0402 X7R
35
C32
+
C31
220 µfd/35 V
M
GND
GND
GND
34
33
32
31
30
29
28
GROUND REFERENCED CAPS
REQUIRED IF BD MODULATION
IS USED
DVDD
C34
C33
0.1 µfd/16 V
0402 X7R
10 µfd/6.3 V
0603 X5R
GND
GND
STUFF OPTION
PVDD
PVDD
27
26
25
+
R17
15K
0402 1/16W
TAS5723DCA
C20
4.7 µfd/6.3 V
0402 X5R
R15
C23
40
AVDD2
NC
20
GND
15 µH/3.5 A
A7503AY
18
0603
41
NC
GND
16
0.047 µfd/16 V
0402 X7R
C18
GND
C25
1 µfd/10 V
0402 X5R
GND
C16
42
C24
TEST
R14
330 pfd/50 V
0402 COG
C29
43
NC
NC
0.33 µfd/50 V
0805 X7R
0.33 µfd/50 V
0805 X7R
L3
1 µfd/25 V
0603 X5R
12
C28
GND
0.033 µfd/50 V
0402 X7R
GVDD_REG
C37
C35
44
NC
NC
18
0603
45
C11
GND
470
0402
C22
PWM1
1 µfd/10 V
0402 X5R
GND
46
330 pfd/50 V
0402 COG
15 µH/3.5 A
A7503AY
L2
0.033 µfd/50 V
0402 X7R
PVDD
11
C15
C21
0.033 µfd/50 V
0402 X7R
PVDD
C10
C14
47
BSTA
BSTC
GND
GND
48
R13
GND
HTSSOP48-DCA
GND
U1
HTSSOP48-DCA
PowerPAD
220 µfd/35 V
M
+
R18
15K
0402 1/16W
C42
220 µfd/35 V
M
GND
PVDD
OUTPUTS
C41
GND
PVDD
GND
+
R19
15K
0402 1/16W
+
R20
15K
0402 1/16W
GND
C43
220 µfd/35 V
M
C44
220 µfd/35 V
M
GND
SPLIT CAP
Figure 81. 2.1 System
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11 Power Supply Recommendations
The TAS5721 requires two power supplies; a low voltage 3.3 V nominal for the pins DVDD, AVDD and DRVDD
and a high power supply, 8 V to 24 V for the pin PVDD. There is no requirement for power up sequencing of low
and high power supplies, however is recommended to put /PDN pin to low before removing the low voltage
power supplies in order to protect the outputs.
11.1 DVDD and AVDD Supplies
The AVDD Supply is used to power the analog internal circuit of the device, and needs a well regulated and
filtered 3.3-V supply voltage. The DVDD Supply is used to power the digital circuitry. DVDD needs a well
regulated and filtered 3.3-V supply voltage.
11.2 PVDD Power Supply
The TAS5721 class-D audio amplifier requires adequate power supply decoupling to ensure the output total
harmonic distortion (THD) and noise is as low as possible. A good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 µF, placed as close as possible to the device PVDD leads works best. For filtering
lower frequency noise signals, a 10µF or greater capacitor placed near the audio power amplifier is
recommended.
12 Layout
12.1 Layout Guidelines
Class-D switching edges are fast and switched currents are high so it is necessary to take care when planning
the layout of the printed circuit board. The following suggestions will help to meet audio, thermal and EMC
requirements.
• uses the PCB for heat sinking therefore the powerPad needs to be soldered to the PCB and adequate copper
area and copper vias connecting the top, bottom and internal layers should be used.
• Decoupling capacitors: the high-frequency decoupling capacitors should be placed as close to the supply pins
as possible; on the a 1-µF high-quality ceramic capacitor is used. Large (10μ-F or greater) bulk power supply
decoupling capacitors should be placed near the on the PVDD supplies.
• Keep the current loop from each of the outputs through the output inductor and the small filter cap and back
to GND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• To avoid crosstalk issues on the headphone/line driver output, it is recommended to have a wide space
between the traces of the outputs.
• Grounding: A big common GND plane is recommended. The PVDD decoupling capacitors should connect to
GND. The TAS5721 PowerPAD should be connected to GND.
• Output filter: remember to select inductors that can handle the high short circuit current of the device. The LC
filter should be placed close to the outputs.
The EVM product folder (http://www.ti.com/tool/tas5721evm) and User’s Guide available on www.ti.com shows
schematic, bill of material, gerber files and more detailed layout plots.
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12.2 Layout Example
Wide open areas for
thermal flow
Refer to SLOA119
for a detailed
description of the
filter design
Bulk Capacitor for
good audio
decoupling close to
PVDD source
0.01µF
0.01µF 0.01µF
PVDD
220µF
0.1µF
Wide space
between driver
output traces
Driver Output
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
High Frequency
Decupling Capacitor
placed as close as
possible to the device
0.01µF
0.1µF
1µF
PVDD
1µF
220µF
2200pF
1µF
10KΩ
3.3V
10KΩ
0.1µF
4.7µF
0.1µF
47nF
10KΩ
10KΩ
18
31
19
30
20
29
21
28
22
27
4700pF
470Ω
1.5µF
23
47nF
3.3V
26
4700pF
TAS5721
24
25
0.1µF
3.3V
18.0KΩ
Solid GND plane with vias
close to decoupling points
for low impedance return
path
Star routing for better
thermal performance
4.7µF
470Ω
1.5µF
0.1µF
4.7µF
Several Via connection
between top and bottom
ground layers for EMI and
Thermal performance
4.7µF
0.1µF
HP/Line Driver
Input
System Processor
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
PowerPAD
Via to Ground Plane
V
Via to Power Supply Plane
Figure 82. Layout Recommendation
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For development support, see the following:
EVM product folder (http://www.ti.com/tool/tas5721evm)
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
• TAS5721EVM User’s Guide (SLOU346)
• Class-D LC Filter Design Application Report (SLOA119)
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
DirectPath, E2E are trademarks of Texas Instruments.
I2C is a trademark of Philips Semiconductor Corp.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TAS5721DCA
ACTIVE
HTSSOP
DCA
48
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
TAS5721
Samples
TAS5721DCAR
ACTIVE
HTSSOP
DCA
48
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
TAS5721
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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