TAS5760LDAP

Order Now Product Folder Support & Community Tools & Software Technical Documents TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 TAS5760L General-Purpose I2S Input Class-D Amplifier 1 Features 3 Description • The TAS5760L is a stereo I2S input device which includes hardware and software (I²C) control modes, integrated digital clipper, several gain options, and a wide power supply operating range to enable use in a multitude of applications. The TAS5760L operates with a nominal supply voltage from 4.5 to 15 VDC. Audio I/O Configuration: – Single Stereo I²S Input – Stereo Bridge Tied Load (BTL) or Mono Parallel Bridge Tied Load (PBTL) Operation – 32, 44.1, 48, 88.2, 96 kHz Sample Rates General Operational Features: – Selectable Hardware or Software Control – Integrated Digital Output Clipper – Programmable I²C Address (1101100[R/W] or 1101101[R/W]) – Closed-Loop Amplifier Architecture – Adjustable Switching Frequency for Speaker Amplifier Robustness Features: – Clock Error, DC, and Short-Circuit Protection – Overtemperature and Programmable Overcurrent Protection Audio Performance (PVDD = 12 V, RSPK = 8 Ω, SPK_GAIN[1:0] Pins = 01) – Idle Channel Noise = 65 µVrms (A-Wtd) – THD+N = 0.09% (at 1 W, 1 kHz) – SNR = 100 dB A-Wtd (Ref. to THD+N = 1%) 1 • • • 2 Applications • • • An optimal mix of thermal performance and device cost is provided in the 120-mΩ RDS(ON) of the output MOSFETs. Additionally, a thermally enhanced 48-Pin TSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices. The entire TAS5760xx family is pin-to-pin compatible in the 48-Pin TSSOP package. Alternatively, to achieve the smallest possible solutions size for applications where pin-to-pin compatibility and a headphone or line driver are not required, a 32-Pin TSSOP package is offered for the TAS5760M and TAS5760L devices. The I2C register map in all of the TAS5760xx devices are identical, to ensure low development overhead when choosing between devices based upon system-level requirements. Device Information(1) PART NUMBER TAS5760L Functional Block Diagram Internal Voltage Supplies AVDD Internal Reference Regulators Serial Audio Port Digital Boost & Volume Control 40 Internal Gate Drive Regulator Digital Clipper Digital to PWM Conversion Soft Clipper Analog Gain Gate Drives Gate Drives 12.50 mm × 6.10 mm HTSSOP (32) 11 mm × 6.2 mm Output Power vs PVDD GVDD_REG Closed Loop Class D Amplifier SFT_CLIP MCLK SCLK LRCK SDIN PVDD Full Bridge Power Stage A SPK_OUTA+ OverCurrent Protection Full Bridge Power Stage B SPK_OUTASPK_OUTB+ SPK_OUTB- Clock Monitoring Die Temp. Monitor Internal Control Registers and State Machines PBTL/ SPK_GAIN0 SPK_GAIN1 SPK_SD SPK_FAULT SPK_SLEEP/ FREQ/ ADR SDA SCL Maximum Output Power (W) ANA_REG BODY SIZE (NOM) HTSSOP (48) (1) For all available packages, see the orderable addendum at the end of the datasheet. LCD/LED TV and Multipurpose Monitors Sound Bars, Docking Stations, PC Audio General-Purpose Audio Equipment DVDD PACKAGE RL = 4 Ω RL = 6 Ω RL = 8 Ω 4 Ω Thermal Limit 6 Ω Thermal Limit 8 Ω Thermal Limit 35 30 25 THD+N = 10% 20 15 10 5 0 4 6 8 10 12 Supply Voltage (V) 14 16 G001 NOTE: Thermal Limits were determined via the TAS5760xxEVM 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Absolute Maximum Ratings ..................................... 7 ESD Ratings.............................................................. 8 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 8 Digital I/O Pins .......................................................... 8 Master Clock ............................................................. 9 Serial Audio Port ....................................................... 9 Protection Circuitry.................................................... 9 Speaker Amplifier in All Modes ............................... 10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode ........................................................................ 10 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode................................................... 12 7.12 I²C Control Port ..................................................... 12 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption ............................................................ 13 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode).......................... 15 7.15 Typical Performance Characteristics (Mono PBTL Mode) ....................................................................... 20 8 9 Parameter Measurement Information ................ 21 Detailed Description ............................................ 22 9.1 9.2 9.3 9.4 9.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Register Maps ......................................................... 22 22 22 27 35 10 Application and Implementation........................ 42 10.1 Application Information.......................................... 42 10.2 Typical Applications .............................................. 42 11 Power Supply Recommendations ..................... 60 11.1 DVDD Supply ........................................................ 60 11.2 PVDD Supply ........................................................ 60 12 Layout................................................................... 60 12.1 Layout Guidelines ................................................. 60 12.2 Layout Example .................................................... 63 13 Device and Documentation Support ................. 67 13.1 13.2 13.3 13.4 13.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 67 67 67 67 67 14 Mechanical, Packaging, and Orderable Information ........................................................... 67 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2015) to Revision C Page • Updated the Register Map section to the new format. No new data added......................................................................... 36 • Deleted statement of 64-kHz sample rate ............................................................................................................................ 37 Changes from Revision A (October 2013) to Revision B Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Changed Features list item, Audio Performance From: RLOAD = 8Ω To: RSPK = 8Ω .............................................................. 1 • Changed From: Voltage at speaker amplifier output pins To: Speaker Amplifier Output Voltage in the Abs Max table ....... 7 • Modified Master clock and Serial Audio Port specifications to reflect the clocking improvements of the device. ................ 9 • Changed the Soft Clipper Control (SFT_CLIP Pin) section.................................................................................................. 28 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 43 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 45 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 47 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 49 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 51 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 54 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 56 • Changed High Power Supply value from 24 V to 15 V. ...................................................................................................... 58 2 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Changes from Original (July 2013) to Revision A Page • Changed Figure 63............................................................................................................................................................... 56 • Changed Figure 64............................................................................................................................................................... 58 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 3 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 5 Device Comparison Table DEVICE DESCRIPTION PACKAGE TAS5760MDDCA Flexible, general-purpose I2S input class-D Amplifier with integrated headphone and line driver and integrated digital clipper, which supports PVDD levels ≤ 24 V 48 Pin, 0.5-mm Lead-Pitch, Pad-down TSSOP (DCA) TAS5760MDCA TAS5760MDAP Flexible, general-purpose I2S input class-D Amplifier with integrated digital clipper, which supports PVDD levels ≤ 24 V 48 Pin, 0.5-mm Lead-Pitch, Pad-down TSSOP (DCA) 32 Pin, 0.65mm Lead Pitch, Pad-down TSSOP (DAP) TAS5760LDDCA Flexible, general-purpose I2S input class-D Amplifier with integrated headphone and line driver and integrated digital clipper, which supports PVDD levels ≤ 15 V 48 Pin, 0.5-mm Lead-Pitch, Pad-down TSSOP (DCA) TAS5760LD2DCA Flexible, general-purpose I2S input class-D Amplifier with integrated headphone and line driver and integrated digital clipper, which supports PVDD levels ≤ 15 V and 3 Wire I²S Mode. 48 Pin, 0.5-mm Lead-Pitch, Pad-down TSSOP (DCA) TAS5760LDCA TAS5760LDAP Flexible, general-purpose I2S input class-D Amplifier with integrated digital clipper, which supports PVDD levels ≤ 15 V and 3 Wire I²S Mode. 48 Pin, 0.5-mm Lead-Pitch, Pad-down TSSOP (DCA) 32 Pin, 0.65-mm Lead Pitch, Pad-down TSSOP (DAP) 6 Pin Configuration and Functions DCA PACKAGE 48-PIN TSSOP TOP VIEW SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN LRCK DGND NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PowerPAD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GVDD_REG GGND AVDD PVDD PVDD BSTRPA+ SPK_OUTA+ PGND SPK_OUTABSTRPABSTRPBSPK_OUTBPGND SPK_OUTB+ BSTRPB+ PVDD PVDD NC NC NC NC NC NC NC Pin Functions TAS5760L NO. TYPE (1) INTERNAL TERMINATION AVDD 46 P - Power supply for internal analog circuitry ANA_REF 4 P - Connection point for internal reference used by ANA_REG and VCOM filter capacitors NAME (1) 4 DESCRIPTION AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0V) Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Pin Functions (continued) TAS5760L NO. TYPE (1) INTERNAL TERMINATION ANA_REG 2 P - Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) BSTRPA- 39 P - Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA- BSTRPA+ 43 P - Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA BSTRPB- 38 P - Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB- BSTRPB+ 34 P - Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB+ DGND 17 G - Ground for digital circuitry (NOTE: This pin should be connected to the system ground) DVDD 9 P - Power supply for the internal digital circuitry FREQ/SDA 7 DI Weak Pull-Down GGND 47 G - Ground for gate drive circuitry (this terminal should be connected to the system ground) GVDD_REG 48 P - Voltage regulator derived from PVDD supply (NOTE: This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) LRCK 16 DI Weak Pull-Down Word select clock for the digital signal that is active on the serial port's input data line MCLK 13 DI Weak Pull-Down Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port clocking NC 1831 - - Not connected inside the device (all "no connect" pins should be connected to ground for best thermal performance, however they can be used as routing channels if required.) 8 DI Weak Pull-Down Dual function pin that functions as an I²C clock input terminal in I²C Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode PGND 36, 41 G - Ground for power device circuitry (NOTE: This terminal should be connected to the system ground) PVDD 32, 33, 44, 45 P - Power Supply for internal power circuitry SCLK 14 DI Weak Pull-Down Bit clock for the digital signal that is active on the serial data port's input data line SDIN 15 DI Weak Pull-Down Data line to the serial data port SFT_CLIP 1 AI - sets the maximum output voltage before clipping SPK_FAULT 5 DO - Speaker amplifier fault terminal, which is pulled LOW when an internal fault occurs SPK_GAIN0 10 DI Weak Pull-Down Adjusts the LSB of the multi-bit gain of the speaker amplifier SPK_GAIN1 11 DI Weak Pull-Down Adjusts the MSB of the multi-bit gain of the speaker amplifier SPK_SLEEP/ ADR 12 DI Weak Pull-Up SPK_OUTA- 40 AO - Negative pin for differential speaker amplifier output A SPK_OUTA+ 42 AO - Positive pin for differential speaker amplifier output A SPK_OUTB- 37 AO - Negative pin for differential speaker amplifier output B SPK_OUTB+ 35 AO - Positive pin for differential speaker amplifier output B SPK_SD 6 AO - Places the speaker amplifier in shutdown VCOM 3 P - Bias voltage for internal PWM conversion block NAME PBTL/SCL DESCRIPTION Dual function pin that functions as an I²C data input pin in I²C Control Mode or as a Frequency Select terminal when in Hardware Control Mode. In Hardware Control Mode, places the speaker amplifier in sleep mode. In Software Control Mode, is used to determine the I²C Address of the device Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 5 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Pin Functions (continued) TAS5760L NAME PowerPAD™ NO. TYPE (1) INTERNAL TERMINATION - G - DESCRIPTION Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it via solder. For proper electrical operation, this ground pad must be connected to the system ground. DAP PACKAGE 32-PIN TSSOP TOP VIEW AVDD 1 32 GVDD_REG SFT_CLIP 2 31 GGND ANA_REG 3 30 BSTRPA+ VCOM 4 29 SPK_OUTA+ ANA_REF 5 28 PVDD SPK_FAULT 6 27 PGND SPK_SD 7 26 SPK_OUTA- FREQ/SDA 8 25 BSTRPA- PBTL/SCL 9 24 BSTRPB- DVDD 10 23 SPK_GAIN0 11 PowerPAD 22 PGND SPK_OUTB- SPK_GAIN1 12 21 PVDD SPK_SLEEP/ADR 13 20 SPK_OUTB+ MCLK 14 19 BSTRPB+ SCLK 15 18 DGND SDIN 16 17 LRCK Pin Functions TAS5760L NO. TYPE (1) INTERNAL TERMINATION AVDD 1 P - Power supply for internal analog circuitry ANA_REF 5 P - Connection point for internal reference used by ANA_REG and VCOM filter capacitors ANA_REG 3 P - Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) BSTRPA- 25 P - Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA- BSTRPA+ 30 P - Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA BSTRPB- 24 P - Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB- BSTRPB+ 19 P - Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB+ DGND 18 G - Ground for digital circuitry (NOTE: This terminal should be connected to the system ground) DVDD 10 P - Power supply for the internal digital circuitry FREQ/SDA 8 DI Weak Pull-Down Dual function terminal that functions as an I²C data input terminal in I²C Control Mode or as a Frequency Select terminal when in Hardware Control Mode. GGND 31 G - Ground for gate drive circuitry (this terminal should be connected to the system ground) NAME (1) 6 DESCRIPTION AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0V) Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Pin Functions (continued) TAS5760L NO. TYPE (1) INTERNAL TERMINATION DESCRIPTION GVDD_REG 32 P - Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) LRCK 17 DI Weak Pull-Down Word select clock for the digital signal that is active on the serial port's input data line MCLK 14 DI Weak Pull-Down Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port clocking PBTL/SCL 9 DI Weak Pull-Down Dual function terminal that functions as an I²C clock input terminal in I²C Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode PGND 22, 27 G - Ground for power device circuitry (NOTE: This terminal should be connected to the system ground) PVDD 21, 28 P - Power Supply for internal power circuitry SCLK 15 DI Weak Pull-Down Bit clock for the digital signal that is active on the serial data port's input data line SDIN 16 DI Weak Pull-Down Data line to the serial data port SFT_CLIP 2 AI - SPK_FAULT 6 DO Open Drain SPK_GAIN0 11 DI Weak Pull-Down Adjusts the LSB of the multi-bit gain of the speaker amplifier SPK_GAIN1 12 DI Weak Pull-Down Adjusts the MSB of the multi-bit gain of the speaker amplifier SPK_SLEEP/ ADR 13 DI Weak Pull-Up NAME Sets the maximum output voltage before clipping Fault terminal, which is pulled LOW when an internal fault occurs Places the speaker amplifier in mute SPK_OUTA- 26 AO - Negative terminal for differential speaker amplifier output A SPK_OUTA+ 29 AO - Positive terminal for differential speaker amplifier output A SPK_OUTB- 23 AO - Negative terminal for differential speaker amplifier output B SPK_OUTB+ 20 AO - Positive terminal for differential speaker amplifier output B SPK_SD 7 DI - Places the device in shutdown when pulled LOW VCOM 4 P - Bias voltage for internal PWM conversion block PowerPAD™ - G - Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it via solder 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Temperature Supply Voltage MIN MAX UNIT –25 85 °C Ambient Storage Temperature, TS –40 125 °C AVDD Supply –0.3 20 V PVDD Supply –0.3 20 V Ambient Operating Temperature, TA DVDD Supply –0.3 4 V DVDD Referenced Digital Input Voltages Digital Inputs referenced to DVDD supply –0.5 DVDD + 0.5 V Speaker Amplifier Output Voltage VSPK_OUTxx, measured at the output pin –0.3 22 V –40 125 °C Storage temperature range, Tstg (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 7 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Ambient Operating Temperature –25 85 °C AVDD AVDD Supply 4.5 16.5 V PVDD PVDD Supply 4.5 16.5 V DVDD DVDD Supply 2.8 3.63 V VIH(DR) Input Logic HIGH for DVDD Referenced Digital Inputs DVDD V VIL(DR) Input Logic LOW for DVDD Referenced Digital Inputs 0 V RSPK (BTL) Minimum Speaker Load in BTL Mode 4 Ω RSPK (PBTL) Minimum Speaker Load in PBTL Mode 2 Ω 7.4 Thermal Information TAS5760L DCA [HTSSOP] THERMAL METRIC (1) 32-PIN Junction-to-ambient thermal resistance θJA (2) DCA [HTSSOP] 48-PIN DAP [HTSSOP] (2) 32-PIN (3) DAP [HTSSOP] 48-PIN UNIT (3) 60.3 30.2 60.3 31.9 °C/W θJC(top) Junction-to-case (top) thermal resistance 16 14.3 16 16 °C/W θJB Junction-to-board thermal resistance 12 12.7 12 17 °C/W ψJT Junction-to-top characterization parameter 0.4 0.6 0.4 0.4 °C/W ψJB Junction-to-board characterization parameter 11.9 12.7 11.9 16.8 °C/W θJC(bott Junction-to-case (bottom) thermal resistance 0.8 0.7 0.8 0.81 °C/W om) (1) (2) (3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. JEDEC Standard 2 Layer Board JEDEC Standard 4 Layer Board 7.5 Digital I/O Pins over operating free-air temperature range (unless otherwise noted) PARAMETER 8 TEST CONDITIONS VIH1 Input Logic HIGH threshold for DVDD Referenced Digital Inputs All digital pins VIL1 Input Logic LOW threshold for DVDD Referenced Digital Inputs All digital pins IIH1 Input Logic HIGH Current Level IIL1 Input Logic LOW Current Level VOH Output Logic HIGH Voltage Level IOH = 2 mA VOL Output Logic LOW Voltage Level IOH = -2 mA MIN TYP MAX 70 UNIT %DVDD 30 %DVDD All digital pins 15 µA All digital pins –15 µA Submit Documentation Feedback 90 %DVDD 10 %DVDD Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 7.6 Master Clock over operating free-air temperature range (unless otherwise noted) PARAMETER DMCLK TEST CONDITIONS Allowable MCLK Duty Cycle MIN TYP MAX 45% 50% 55% MCLK Input Frequency fMCLK 25 Supported single-speed MCLK Frequencies Values: 64, 128, 192, 256, 384, and 512 64 512 Supported double-speed MCLK Frequencies Values: 64, 128, and 256 64 256 UNIT MHz x fs 7.7 Serial Audio Port over operating free-air temperature range (unless otherwise noted) PARAMETER DSCLK tH_L TEST CONDITIONS Allowable SCLK Duty Cycle Time high and low, SCLK, LRCK, SDIN MIN TYP MAX 45% 50% 55% 10 ns Input tRISE ≤ 1 ns, input tFALL ≤ 1 ns tSU tHLD UNIT Setup and Hold time. LRCK, SDIN input to SCLK edge 5 Input tRISE ≤ 4 ns, input tFALL ≤ 4 ns 8 Input tRISE ≤ 8 ns, input tFALL ≤ 8 ns 12 ns tRISE Rise-time SCLK, LRCK, SDIN inputs 8 ns tFALL Fall-time SCLK, LRCK, SDIN inputs 8 ns fS Supported Input Sample Rates Sample rates above 48kHz supported by "double speed mode," which is activated through the I²C control port 32 96 kHz fSCLK Supported SCLK Frequencies Values include: 32, 48, 64 32 64 fS 7.8 Protection Circuitry over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERTHRES(PVDD) PVDD Overvoltage Error Threshold PVDD Rising 18 V OVEFTHRES(PVDD) PVDD Overvoltage Error Threshold PVDD Falling 17.3 V UVEFTHRES(PVDD) PVDD Undervoltage Error (UVE) Threshold PVDD Falling 3.95 V UVERTHRES(PVDD) PVDD UVE Threshold (PVDD Rising) PVDD Rising 4.15 V OTETHRES Overtemperature Error (OTE) Threshold 150 °C OTEHYST Overtemperature Error (OTE) Hysteresis 15 °C 7 A OCETHRES Overcurrent Error (OCE) Threshold for PVDD= 15V, TA = 25 °C each BTL Output DCETHRES DC Error (DCE) Threshold PVDD= 12V, TA = 25 °C 2.6 V TSPK_FAULT Speaker Amplifier Fault Time Out period DC Detect Error 650 ms OTE or OCP Fault 1.3 s Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 9 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 7.9 Speaker Amplifier in All Modes over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AV00 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 00 Hardware Control Mode (Additional gain settings available in Software Control Mode) (1) 25.2 dBV AV01 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 01 Hardware Control Mode (Additional gain settings available in Software Control Mode) (1) 28.6 dBV AV10 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 10 Hardware Control Mode (Additional gain settings available in Software Control Mode) (1) 31 dBV AV11 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 11 (This setting places the device in Software Control Mode) |VOS|(SPK_ Speaker Amplifier DC Offset AMP) (Set via I²C) BTL, Worst case over voltage, gain settings 10 mV PBTL, Worst case over voltage, gain settings 15 mV fSPK_AMP(0) Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 0 (Hardware Control Mode. Additional switching rates available in Software Control Mode.) 16 fS fSPK_AMP(1) Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 1 (Hardware Control Mode. Additional switching rates available in Software Control Mode.) 8 fS RDS(ON) On Resistance of Output MOSFET (both high-side and low-side) –3-dB Corner Frequency of High-Pass Filter fC PVDD = 15 V, TA = 25 °C, Die Only 120 mΩ PVDD= 15V, TA = 25 °C, Includes: Die, Bond Wires, Leadframe 150 mΩ fS = 44.1 kHz 3.7 fS = 48 kHz 4 fS = 88.2 kHz fS = 96 kHz (1) Hz 7.4 8 The digital boost block contributes +6dB of gain to this value. The audio signal must be kept below -6dB to avoid clipping the digital audio path. 7.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted) PARAMETER ICN(SPK) PO(SPK) 10 Idle Channel Noise Maximum Instantaneous Output Power Per. Ch. MIN TYP MAX UNIT PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted TEST CONDITIONS - 66 - µVrms PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted - 75 - µVrms PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, - 14.2 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% - 8 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, - 21.9 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% - 12.5 - W Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode (continued) input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted) PARAMETER PO(SPK) SNR(SPK) THD+N(SPK) X-Talk(SPK) (1) Maximum Continuous Output Power Per. Ch. (1) Signal to Noise Ratio (Referenced to THD+N = 1%) Total Harmonic Distortion and Noise Cross-talk (worst case between LtoR and RtoL coupling) TEST CONDITIONS MIN TYP MAX UNIT PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, - 14 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% - 8 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, - 13.25 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% - 12.5 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted, -60dBFS Input - 99.7 - dB PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted, -60dBFS Input - 98.2 - dB PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, Po = 1 W - 0.02% - PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, Po = 1 W - 0.03% - PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, Po = 1 W - 0.03% - PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, Po = 1 W - 0.03% - PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine - -92 - dB PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine - -93 - dB The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed in this section are achievable on the TAS5760L's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760L if steps are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs. PVDD plots shown in the typical performance plots section of this data sheet. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 11 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted) PARAMETER ICN PO(SPK) PO(SPK) SNR THD+N(SPK) (1) Idle Channel Noise Maximum Instantaneous Output Power Maximum Continuous Output Power (1) Signal to Noise Ratio (Referenced to THD+N = 1%) Total Harmonic Distortion and Noise TEST CONDITIONS MIN TYP MAX UNIT - 69 - µVrms PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted - 85 - µVrms PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, THD+N = 0.1%, - 28.6 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, - 15.9 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% - 8.4 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, - 43.2 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, - 25 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% - 13.3 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, THD+N = 0.1%, - 30 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, - 15.9 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% - 8.4 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, - 28.5 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, - 25 - W PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% - 13.3 - W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted, -60dBFS Input - 100.4 - dB PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted, -60dBFS Input - 99.5 - dB PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, Po = 1 W - 0.03% - PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, Po = 1 W - 0.02% - PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, Po = 1 W - 0.02% - PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, Po = 1 W - 0.03% - PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, Po = 1 W - 0.02% - PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, Po = 1 W - 0.02% - PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed in this section are achievable on the TAS5760L's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760L if steps are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs. PVDD plots shown in the typical performance plots section of this data sheet. 7.12 I²C Control Port specifications are over operating free-air temperature range (unless otherwise noted) PARAMETER CL(I²C) fSCL 12 TEST CONDITIONS Allowable Load Capacitance for Each I²C Line Support SCL frequency No Wait States Submit Documentation Feedback MIN TYP MAX UNIT 400 pF 400 kHz Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 I²C Control Port (continued) specifications are over operating free-air temperature range (unless otherwise noted) PARAMETER tbuf TEST CONDITIONS MIN Bus Free time between STOP and START conditions tf(I²C) TYP UNIT 1.3 µS Rise Time, SCL and SDA 300 th1(I²C) Hold Time, SCL to SDA th2(I²C) Hold Time, START condition to SCL tI²C(start) MAX ns 0 ns 0.6 µs I²C Startup Time 12 mS 300 ns tr(I²C) Rise Time, SCL and SDA tsu1(I²C) Setup Time, SDA to SCL 100 ns tsu2(I²C) Setup Time, SCL to START condition 0.6 µS tsu3(I²C) Setup Time, SCL to STOP condition 0.6 µS Tw(H) Required Pulse Duration, SCL HIGH 0.6 µS Tw(L) Required Pulse Duration, SCL LOW 1.3 µS 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted) VPVDD [V] RSPK [Ω] SPEAKER AMPLIFIER STATE 4 4 4 0.15 23.53 3.72 0.15 23.46 3.72 0.15 13.26 0.48 0.08 13.27 0.53 0.08 0.046 0.04 0 0.046 0.03 0 30.94 3.71 0.2 30.94 3.71 0.2 29.37 3.71 0.19 29.39 3.71 0.19 13.24 0.5 0.08 13.23 0.52 0.08 0.046 0.03 0 0.046 0.03 0 39.39 3.7 0.25 39.43 3.7 0.25 36.91 3.7 0.23 Idle 8 4 Mute fSPK_AMP = 768kHz Sleep 8 4 Shutdown 8 4 Idle 8 4 4 0.15 3.72 Shutdown 4 8 3.73 23.44 Sleep 8 4 23.48 Mute 4 8 PDISS [W] fSPK_AMP = 384kHz 8 6 IDVDD [mA] Idle 8 8 IPVDD+AVDD [mA] Mute fSPK_AMP = 1152kHz 8 4 8 Sleep Shutdown 36.9 3.69 0.23 13.17 0.53 0.08 13.13 0.45 0.08 0.046 0.03 0 0.046 0.03 0 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 13 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Typical Idle, Mute, Shutdown, Operational Power Consumption (continued) input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted) VPVDD [V] RSPK [Ω] SPEAKER AMPLIFIER STATE 4 4 4 4 3.73 0.41 12.71 0.47 0.15 12.75 0.5 0.15 0.053 0.04 0 0.053 0.04 0 44.84 3.73 0.55 44.82 3.73 0.55 42.71 3.72 0.52 42.66 3.72 0.52 12.71 0.49 0.15 12.73 0.52 0.15 0.063 0.03 0 0.053 0.03 0 59.3 3.73 0.72 59.3 3.73 0.72 55.74 3.72 0.68 55.74 3.72 0.68 12.67 0.49 0.15 12.61 0.43 0.15 0.053 0.02 0 0.053 0.03 0 Shutdown 4 Idle 8 4 14 32.97 Sleep 8 8 0.41 fSPK_AMP = 768kHz 4 4 3.73 Mute 8 8 0.41 32.98 Idle 8 4 0.41 3.73 Shutdown 4 8 3.74 32.93 Sleep 8 4 32.95 fSPK_AMP = 384kHz 4 12 PDISS [W] Mute 8 8 IDVDD [mA] Idle 8 8 IPVDD+AVDD [mA] Mute fSPK_AMP = 1152kHz Sleep Shutdown Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode) At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted. RL = 4 Ω RL = 6 Ω RL = 8 Ω 4 Ω Thermal Limit 6 Ω Thermal Limit 8 Ω Thermal Limit 35 30 25 10 RL = 4 Ω RL = 6 Ω RL = 8 Ω THD+N = 10% 1 THD+N (%) Maximum Output Power (W) 40 20 15 10 0.1 0.01 5 0 4 6 8 10 12 Supply Voltage (V) 14 20 10 Noise (µVRMS) 80 70 60 50 40 20 Idle Channel RL = 8 Ω 10 10k 20k 0 G025 8 10 10 1 1 0.1 0.001 0.01 10 11 12 13 Supply Voltage (V) 14 15 16 G026 RL = 4 Ω RL = 6 Ω RL = 8 Ω 0.1 0.01 RL = 4Ω RL = 6Ω RL = 8Ω 0.1 9 Ch1 ICN @ Gain = 00 Ch2 ICN @ Gain = 00 Ch1 ICN @ Gain = 01 Ch2 ICN @ Gain = 01 Figure 4. Idle Channel Noise vs PVDD THD+N (%) THD+N (%) PVDD = 12 V, POSPK = 1 W Figure 3. THD+N vs Frequency 0.01 G024 90 30 1k Frequency (Hz) 20k 100 0.01 100 10k 110 0.1 20 1k Frequency (Hz) PVDD = 12 V, POSPK = 1 W Figure 2. THD+N vs Frequency RL = 4 Ω RL = 6 Ω RL = 8 Ω 1 0.001 100 G001 Thermal Limits are referenced to TAS5760xxEVM Rev D Figure 1. Output Power vs PVDD THD+N (%) 0.001 16 1 Output Power (W) 10 50 0.001 0.01 G027 PVDD = 12 V, Both Channels Driven Figure 5. THD+N vs Output Power 0.1 1 Output Power (W) 10 80 G029 PVDD = 12 V, Both Channels Driven Figure 6. THD+N vs Output Power Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 15 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode) (continued) At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted. 100 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 RL = 8 Ω 95 85 Crosstalk (dB) Power Efficiency (%) 90 80 75 70 65 60 PVDD = 12 V PVDD = 15 V 55 50 0 5 10 15 20 25 Total Output Power (W) 30 35 PVDD = 15 V RL = 4 Ω 20 100 G030 Figure 7. Efficiency vs Output Power 10k 20k G031 0 PVDD = 12 V RL = 8 Ω −10 −20 −20 −30 −30 −40 −50 −40 −50 −60 −60 −70 −70 −80 −80 20 100 PVDD = 12 V RL = 8 Ω DVDD = 3.3 V + 200 mVP-P −10 PSRR (dB) PSRR (dB) 1k Frequency (Hz) Figure 8. Crosstalk vs Frequency 0 −90 Right-to-Left Left-to-Right 1k Frequency (Hz) 10k −90 20k 20 100 G019 Figure 9. PVDD PSRR vs Frequency 40 1k Frequency (Hz) 10k 20k G020 Figure 10. DVDD PSRR vs Frequency 35 RL = 8 Ω RL = 8 Ω 32 Current (mA) Current (mA) 35 30 29 26 23 25 20 20 8 9 10 11 12 13 PVDD (V) 14 15 G042 Figure 11. Idle Current Draw vs PVDD (Filterless) 16 8 16 9 10 11 12 13 PVDD (V) 14 15 16 G023 With LC Filter as shown on the EVM Figure 12. Idle Current Draw vs PVDD Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode) (continued) At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted. 50 RL = 8 Ω Current (µA) 47 44 41 38 35 8 9 10 11 12 13 PVDD (V) 14 15 16 G022 Figure 13. Shutdown Current Draw vs PVDD (Filterless) At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted. RL = 4 Ω RL = 6 Ω RL = 8 Ω 4 Ω Thermal Limit 6 Ω Thermal Limit 8 Ω Thermal Limit 35 30 25 10 RL = 4 Ω RL = 6 Ω RL = 8 Ω THD+N = 10% 1 THD+N (%) Maximum Output Power (W) 40 20 15 10 0.1 0.01 5 0 4 6 8 10 12 Supply Voltage (V) 14 20 100 G039 Thermal Limits are referenced to TAS5760xxEVM Rev D Figure 14. Output Power vs PVDD 10 1k Frequency (Hz) Noise (µVRMS) 80 70 60 50 40 30 Ch1 ICN @ Gain = 00 Ch2 ICN @ Gain = 00 Ch1 ICN @ Gain = 01 Ch2 ICN @ Gain = 01 20 10 100 1k Frequency (Hz) G002 90 0.01 20 20k 100 0.1 0.001 10k PVDD = 12 V, POSPK = 1 W Figure 15. THD+N vs Frequency RL = 4 Ω RL = 6 Ω RL = 8 Ω 1 THD+N (%) 0.001 16 10k 20k G003 0 8 PVDD = 12 V, POSPK = 1 W Figure 16. THD+N vs Frequency 9 10 11 12 13 PVDD (V) 14 15 Product Folder Links: TAS5760L G006 Figure 17. Idle Channel Noise vs PVDD Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated 16 17 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode) (continued) At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted. 10 0.1 0.1 0.01 0.01 0.001 0.01 0.1 1 Output Power per Channel (W) 10 100 0.001 0.01 30 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 85 Crosstalk (dB) Efficiency (%) 90 80 75 70 65 60 PVDD = 12 V PVDD = 15 V 55 0 5 10 15 20 Total Output Power (W) 25 30 −100 −110 −120 PVDD = 15 V RL = 4 Ω 20 100 G014 Figure 20. Efficiency vs Output Power 60 Right-to-Left Left-to-Right 1k Frequency (Hz) 10k 20k G018 RL = 8 Ω PVDD = 12 V RL = 8 Ω 55 −20 −30 Current (mA) PSRR (dB) G010 Figure 21. Crosstalk vs Frequency 0 −10 60 PVDD = 12 V, Both Channels Driven Figure 19. THD+N vs Output Power RL = 8 Ω 95 0.1 1 10 Output Power per Channel (W) G008 PVDD = 12 V, Both Channels Driven Figure 18. THD+N vs Output Power 50 RL = 4 Ω RL = 6 Ω RL = 8 Ω 1 THD+N (%) 1 THD+N (%) 10 RL = 4 Ω RL = 6 Ω RL = 8 Ω −40 −50 −60 −70 50 45 40 −80 −90 20 100 1k Frequency (Hz) 10k 35 8 G019 Figure 22. PVDD PSRR vs Frequency 18 20k 9 10 11 12 13 PVDD (V) 14 15 16 G045 Figure 23. Idle Current Draw vs PVDD (Filterless) Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode) (continued) At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted. 60 50 RL = 8 Ω 47 Current (µA) Current (mA) 55 50 45 40 35 RL = 8 Ω 44 41 38 8 9 10 11 12 13 PVDD (V) 14 15 16 35 8 G045 Figure 24. Idle Current Draw vs PVDD (with LC Filter as shown on EVM) 9 10 11 12 13 PVDD (V) 14 15 16 G022 Figure 25. Shutdown Current Draw vs PVDD (Filterless) Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 19 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 7.15 Typical Performance Characteristics (Mono PBTL Mode) At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine unless otherwise noted. 10 0.1 0.01 0.001 RL = 2 Ω RL = 4 Ω RL = 6 Ω RL = 8 Ω 1 THD+N (%) 1 THD+N (%) 10 RL = 4 Ω RL = 6 Ω RL = 8 Ω 0.1 0.01 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 G032 PVDD = 12 V, POSPK = 1 W Figure 26. THD+N vs Frequency 10k 20k G033 PVDD = 12 V, POSPK = 1 W Figure 27. THD+N vs Frequency 100 10 RL = 2 Ω RL = 4 Ω RL = 6 Ω RL = 8 Ω 90 80 1 70 THD+N (%) Noise (µVRMS) 1k Frequency (Hz) 60 50 40 30 0.1 0.01 20 Idle Channel RL = 8 Ω 10 0 8 9 10 Gain = 00 Gain = 01 11 12 13 Supply Voltage (V) 14 15 0.001 0.01 G034 Figure 28. Idle Channel Noise vs PVDD THD+N (%) 1 100 RL = 2 Ω RL = 4 Ω RL = 6 Ω RL = 8 Ω 1 Output Power (W) 10 50 G035 PVDD = 12 V with 1 kHz Sine Input Figure 29. THD+N vs Output Power RL = 4 Ω 95 90 Power Efficiency (%) 10 0.1 16 0.1 0.01 85 80 75 70 65 60 0.001 0.01 PVDD = 12 V PVDD = 15 V 55 0.1 1 10 Output Power (W) 100 200 G037 50 0 PVDD = 12 V with 1 kHz Sine Input Figure 30. THD+N vs Output Power 20 Submit Documentation Feedback 5 10 15 20 25 Total Output Power (W) 30 35 G038 Figure 31. Efficiency vs Output Power Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Typical Performance Characteristics (Mono PBTL Mode) (continued) At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine unless otherwise noted. 10 0.1 0.01 0.001 RL = 2 Ω RL = 4 Ω RL = 6 Ω RL = 8 Ω 1 THD+N (%) 1 THD+N (%) 10 RL = 4 Ω RL = 6 Ω RL = 8 Ω 0.1 0.01 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 PVDD = 12 V, POSPK = 1 W Figure 32. THD+N vs Frequency 10 80 1 70 THD+N (%) Noise (µVRMS) 20k G005 RL = 2 Ω RL = 4 Ω RL = 6 Ω RL = 8 Ω 90 60 50 40 30 0.1 0.01 20 Idle Channel RL = 8 Ω 10 8 9 10 ICN @ Gain = 00 ICN @ Gain = 01 11 12 13 PVDD (V) 14 15 0.001 0.01 16 1 1 Output Power (W) 100 RL = 2 Ω RL = 4 Ω RL = 6 Ω RL = 8 Ω 50 G011 RL = 4 Ω 95 90 0.1 85 80 75 70 65 0.01 60 PVDD = 12 V PVDD = 15 V 55 0.001 0.01 10 Figure 35. THD+N vs Output Power with PVDD = 12 V Efficiency (%) 10 0.1 G007 Figure 34. Idle Channel Noise vs PVDD THD+N (%) 10k PVDD = 12 V, POSPK = 1 W Figure 33. THD+N vs Frequency 100 0 1k Frequency (Hz) G004 0.1 1 10 Output Power (W) 100 200 50 0 G013 Figure 36. THD+N vs Output Power with PVDD = 12 V 5 10 15 20 25 Total Output Power (W) 30 35 G015 Figure 37. Efficiency vs Output Power 8 Parameter Measurement Information All parameters are measured according to the conditions described in Specifications. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 21 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 9 Detailed Description 9.1 Overview The TAS5760L is a flexible and easy-to-use stereo class-D speaker amplifier with an I²S input serial audio port. The TAS5760L supports a variety of audio clock configurations via two speed modes. In Hardware Control mode, the device only operates in single-speed mode. When used in Software Control mode, the device can be placed into double speed mode to support higher sample rates, such as 88.2 kHz and 96 kHz. The outputs of the TAS5760L can be configured to drive two speakers in stereo Bridge Tied Load (BTL) mode or a single speaker in Parallel Bridge Tied Load (PBTL) mode. Only two power supplies are required for the TAS5760L. They are a 3.3-V power supply, called VDD, for the small signal analog and digital and a higher voltage power supply, called PVDD, for the output stage of the speaker amplifier. To enable use in a variety of applications, PVDD can be operated over a large range of voltages, as specified in the Recommended Operating Conditions. To configure and control the TAS5760L, two methods of control are available. In Hardware Control Mode, the configuration and real-time control of the device is accomplished through hardware control pins. In Software Control mode, the I²C control port is used both to configure the device and for real-time control. In Software Control Mode, several of the hardware control pins remain functional, such as the SPK_SD, SPK_FAULT, and SFT_CLIP pins. 9.2 Functional Block Diagram DVDD ANA_REG Internal Voltage Supplies AVDD Internal Reference Regulators GVDD_REG Internal Gate Drive Regulator Closed Loop Class D Amplifier SFT_CLIP MCLK SCLK LRCK SDIN PVDD Serial Audio Port Digital Boost & Volume Control Digital Clipper Digital to PWM Conversion Soft Clipper Analog Gain Gate Drives Gate Drives Full Bridge Power Stage A SPK_OUTA+ OverCurrent Protection Full Bridge Power Stage B SPK_OUTASPK_OUTB+ SPK_OUTB- Clock Monitoring Die Temp. Monitor Internal Control Registers and State Machines PBTL/ SPK_GAIN0 SPK_GAIN1 SPK_SD SPK_FAULT SPK_SLEEP/ FREQ/ ADR SDA SCL 9.3 Feature Description 9.3.1 Power Supplies The power supply requirements for the TAS5760L consist of one 3.3-V supply to power the low voltage analog and digital circuitry and one higher-voltage supply to power the output stage of the speaker amplifier. Several onchip regulators are included on the TAS5760L to generate the voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators which have been integrated are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the device. 22 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Feature Description (continued) 9.3.2 Speaker Amplifier Audio Signal Path Figure 38 shows a block diagram of the speaker amplifier of the TAS5760L. In Hardware Control mode, a limited subset of audio path controls are made available via external pins, which are pulled HIGH or LOW to configure the device. In Software Control Mode, the additional features and configurations are available. All of the available controls are discussed in this section, and the subset of controls that available in Hardware Control Mode are discussed in the respective section below. Digital Gain (GDIG) Analog Gain (GANA) Closed Loop Class D Amplifier HPF Serial Audio In Serial Audio Port Digital Boost & Volume Control Interpolation Filter 123456 Digital Clipper Digital to PWM Conversion 011010.. . Gate Drives Gate Drives Full Bridge Power Stage A Full Bridge Power Stage B PWM Audio Out SFT_CLIP Figure 38. Speaker Amplifier Audio Signal Path 9.3.2.1 Serial Audio Port (SAP) The serial audio port (SAP) receives audio in either I²S, Left Justified, or Right Justified formats. In Hardware Control mode, the device operates only in 32, 48 or 64 x fS I²S mode. In Software Control mode, additional options for left-justified and right justified audio formats are available. The supported clock rates and ratios for Hardware Control Mode and Software Control Mode are detailed in their respective sections below. The TAS5760L device supports SCLK to LRCK ratios of 32, 48, and 64. If SCLK is running at 64 × LRCK, MCLK can be tied directly to SCLK. Otherwise, MCLK must be driven externally. The valid MCLK to LRCK ratios are 64, 128, 192, 256, 384, and 512, as long as the frequency of MCLK is 25 MHz or less. 9.3.2.1.1 I²S Timing I²S timing uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is LOW for the left channel and HIGH for the right channel. A bit clock, called SCLK, runs at 32, 48, or 64 × fS and is used to clock in the data. There is a delay of one bit clock from the time the LRCK signal changes state to the first bit of data on the data lines. The data is presented in 2's-complement form (MSB-first) and is valid on the rising edge of bit clock. 9.3.2.1.2 Left-Justified Left-justified (LJ) timing also uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is HIGH for the left channel and LOW for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS5760L can accept digital words from 16 to 24 bits wide and pads any unused trailing data-bit positions in the L/R frame with zeros before presenting the digital word to the audio signal path. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 23 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Feature Description (continued) 9.3.2.1.3 Right-Justified Right-justified (RJ) timing also uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is HIGH for the left channel and LOW for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The TAS5760L pads unused leading data-bit positions in the left/right frame with zeros before presenting the digital word to the audio signal path. 9.3.2.2 DC Blocking Filter Excessive DC content in the audio signal can damage loudspeakers and even small amounts of DC offset in the signal path cause cause audible artifacts when muting and unmuting the speaker amplifier. For these reasons, the amplifier employs two separate DC blocking methods for the speaker amplifier. The first is a high-pass filter provided at the front of the data path to remove any DC from incoming audio data before it is presented to the audio path. The –3 dB corner frequencies for the filter are specified in the speaker amplifier electrical characteristics table. In Hardware Control mode, the DC blocking filter is active and cannot be disabled. In Software Control mode, the filter can be bypassed by writing a 1 to bit 7 of register 0x02. The second method is a DC detection circuit that will shutdown the power stage and issue a latching fault if DC is found to be present on the output due to some internal error of the device. This DC Error (DCE) protection is discussed in the Protection Circuitry section below. 9.3.2.3 Digital Boost and Volume Control Following the high-pass filter, a digital boost block is included to provide additional digital gain if required for a given application as well as to set an appropriate clipping point for a given GAIN[1:0] pin configuration when in Hardware Control mode. The digital boost block defaults to +6dB when the device is in Hardware Mode. In most use cases, the digital boost block will remain unchanged when operating the device in Software Control mode, as the volume control offers sufficient digital gain for most applications. The TAS5760L's digital volume control operates from Mute to 24 dB, in steps of 0.5 dB. The equation below illustrates how to set the 8-bit volume control register at address 0x04: DVC [Hex Value] = 0xCF + (DVC [dB] / 0.5 [dB] ) (1) Transitions between volume settings will occur at a rate of 0.5 dB every 8 LRCK cycles to ensure no audible artifacts occur during volume changes. This volume fade feature can be disabled via Bit 7 of the Volume Control Configuration Register. 9.3.2.4 Digital Clipper A digital clipper is integrated in the oversampled domain to provide a component-free method to set the clip point of the speaker amplifier. Through the "Digital Clipper Level x" controls in the I²C control port, the point at which the oversampled digital path clips can be set directly, which in turns sets the 10% THD+N operating point of the amplifier. This is useful for applications in which a single system is designed for use in several end applications that have different power rating specifications. Its place in the oversampled domain ensures that the digital clipper is acoustically appealing and reduces or eliminates tones which would otherwise foldback into the audio band during clipping events. Figure 39 shows a block diagram of the digital clipper. Digital Clipper Digital to PWM Conversion 22 Bit Audio Sample in Data Path Mux 20 Bit Digital Clipper Level in Control Port 011010.. . Digital Comparator Figure 39. Digital Clipper Simplified Block Diagram 24 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Feature Description (continued) As mentioned previously, the audio signature of the amplifier when the digital clipper is active is very smooth, owing to its place in the signal chain. Figure 40 shows the typical behavior of the clipping events. Figure 40. Digital Clipper Example Waveform for Various Settings of Digital Clip Level [19:0] It is important to note that the actual signal developed across the speaker will be determined not only by the digital clipper, but also the analog gain of the amplifier. Depending on the analog gain settings and the PVDD level applied, clipping could occur as a result of the voltage swing that is determined by the gain being larger than the available PVDD supply rail. The gain structures are discussed in detail below for both Hardware Control Mode and Software Control Mode. 9.3.2.5 Closed-Loop Class-D Amplifier Following the digital clipper, the interpolated audio data is next sent to the Closed-Loop Class-D amplifier, whose first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker amplifer. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D amplifier section of the device. The gain structures are discussed in detail below for both Hardware Control Mode and Software Control Mode. The switching rate of the amplifier is configurable in both Hardware Control Mode and Software Control Mode. In both cases, the PWM switching frequency is a multiple of the sample rate. This behavior is described in the respective Hardware Control Mode and Software Control Mode sections below. 9.3.3 Speaker Amplifier Protection Suite The speaker amplifier in the TAS5760L includes a robust suite of error handling and protection features. It is protected against Over-Current, Under-Voltage, Over-Voltage, Over-Temperature, DC, and Clock Errors. The status of these errors is reported via the SPK_FAULT pin and the appropriate error status register in the I²C Control Port. The error or handling behavior of the device is characterized as being either "Latching" or "NonLatching" depending on what is required to clear the fault and resume normal operation (that is playback of audio). For latching errors, the SPK_SD pin or the SPK_SD bit in the control port must be toggled in order to clear the error and resume normal operation. If the error is still present when the SPK_SD pin or bit transitions from LOW back to HIGH, the device will again detect the error and enter into a fault state resulting in the error status bit being set in the control port and the SPK_FAULT line being pulled LOW. If the error has been cleared (for example, the temperature of the device has decreased below the error threshold) the device will attempt to resume normal operation after the SPK_SD pin or bit is toggled and the required fault time out period (TSPK_FAULT ) has passed. If the error is still present, the device will once again enter a fault state and must be placed into and brought back out of shutdown in order to attempt to clear the error. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 25 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Feature Description (continued) For non-latching errors, the device will automatically resume normal operation (that is playback) once the error has been cleared. The non-latching errors, with the exception of clock errors will not cause the SPK_FAULT line to be pulled LOW. It is not necessary to toggle the SPK_SD pin or bit in order to clear the error and resume normal operation for non-latching errors. Table 1 details the types of errors protected by the TAS5760L's Protection Suite and how each are handled. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin) In both hardware and Software Control mode, the SPK_FAULT pin of the TAS5760L serves as a fault indicator to notify the system that a fault has occurred with the speaker amplifier by being actively pulled LOW. This pin is an open-drain output pin and, unless one is provided internal to the receiver, requires an external pullup to set the net to a known value. The behavior of this pin varies based upon the type of error which has occurred. In the case of a latching error, the fault line will remain LOW until such time that the TAS5760L has resumed normal operation (that is the SPK_SD pin has been toggled and TSPK_FAULT has passed). With the exception of clock errors, non-latching errors will not cause the SPK_FAULT pin to be pulled LOW. Once a non-latching error has been cleared, normal operation will resume. For clocking errors, the SPK_FAULT line will be pulled LOW, but upon clearing of the clock error normal operation will resume automatically, that is, with no TSPK_FAULT delay. One method which can be used to convert a latching error into an auto-recovered, non-latching error is to connect the SPK_FAULT pin to the SPK_SD pin. In this way, a fault condition will automatically toggle the SPK_SD pin when the SPK_FAULT pin goes LOW and returns HIGH after the TSPK_FAULT period has passed. Table 1. Protection Suite Error Handling Summary ERROR CAUSE FAULT TYPE ERROR IS CLEARED BY: Overvoltage Error (OVE) PVDD level rises above that specified by OVERTHRES(PVDD) Non-Latching (SPK_FAULT Pin is not pulled LOW) PVDD level returning below OVETHRES(PVDD) Undervoltage Error (UVE) PVDD voltage level drops below that specified by UVEFTHRES(SPK) Non-Latching (SPK_FAULT Pin is not pulled LOW) PVDD level returning above UVETHRES(PVDD) Non-Latching (SPK_FAULT Pin is pulled LOW) Clocks returning to valid state Speaker Amplifier output current has increased above the level specified by OCETHRES Latching TSPK_FAULT has passed AND SPK_SD Pin or Bit Toggle DC Detect Error (DCE) DC offset voltage on the speaker amplifier output has increased above the level specified by the DCETHRES Latching TSPK_FAULT has passed AND SPK_SD Pin or Bit Toggle Overtemperature Error (OTE) The temperature of the die has increased above the level specified by the OTETHRES Latching TSPK_FAULT has passed AND SPK_SD Pin or Bit Toggle AND the temperature of the device has reached a level below that which is dictated by the OTEHYST specification Clock Error (CLKE) Overcurrent Error (OCE) One or more of the following errors has occured: 1. Non-Supported MCLK to LRCK and/or SCLK to LRCK Ratio 2. Non-Supported MCLK or LRCK rate 3. MCLK, SCLK, or LRCK has stopped 9.3.3.2 DC Detect Protection The TAS5760L has circuitry which will protect the speakers from DC current which might occur due to an internal amplifier error. The device behavior in response to a DCE event is detailed in the table in the previous section. A DCE event occurs when the output differential duty-cycle of either channel exceeds 60% for more than 420 msec at the same polarity. The table below shows some examples of the typical DCE Protection threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents less than 2 Hz. 26 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 The minimum output offset voltages required to trigger the DC detect are listed in Table 2. The outputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect. Table 2. DC Detect Threshold PVDD [V] |VOS|- OUTPUT OFFSET VOLTAGE [V] 4.5 0.96 6 1.30 12 2.60 9.4 Device Functional Modes 9.4.1 Hardware Control Mode For systems which do not require the added flexibility of the I²C control port or do not have an I²C host controller, the TAS5760L can be used in Hardware Control Mode. In this mode of operation, the device operates in its default configuration and any changes to the device are accomplished via the hardware control pins, described below. The audio performance between Hardware and Software Control mode is identical, however more features and functionality are available when the device is operated in Software Control mode. The behavior of these Hardware Control Mode pins is described in the sections below. Several static I/O's are present on the TAS5760L which are meant to be configured during PCB design and not changed during normal operation. Some examples of these are the GAIN[1:0] and PBTL/SCL pins. These pins are often referred to as being tied or pulled LOW or tied or pulled HIGH. A pin which is tied or pulled LOW has been connected directly to the system ground. The TAS5760L is configured such that the most popular use cases for the device (that is BTL mode, 768-kHz switching frequency, and so forth) require the static I/O lines to be tied LOW. This ensures optimum thermal performance as well as BOM reduction. Device pins that need to be tied or pulled HIGH should be connected to DVDD. For these pins, a pull-up resistor is recommended to limit the slew rate of the voltage which is presented to the pin during power up. Depending on the output impedance of the supply, and the capacitance connected to the DVDD net on the board, slew rates of this node could be high enough to trigger the integrated ESD protection circuitry at high current levels, causing damage to the device. It is not necessary to have a separate pull-up resistor for each static digital I/O pin. Instead, a single resistor can be connected to DVDD and all static I/O lines which are to be tied HIGH can be connected to that pull-up resistor. This connectivity is shown in the Typical Application Circuits. These pullup resistors are not required when the digital I/O pins are driven by a controlled driver, such as a digital control line from a systems processor, as the output buffer in the system processor will ensure a controlled slew rate. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin) In both Hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into shutdown. Driving this pin LOW will place the device into shutdown, while pulling it HIGH (to DVDD) will bring the device out of shutdown. This is the lowest power consumption mode that the device can be placed in while the power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact may occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the SPK_SLEEP/ADR pin HIGH before pulling the SPK_SD low. 9.4.1.2 Serial Audio Port in Hardware Control Mode When used in Hardware Control Mode, the Serial Audio Port (SAP) accepts only I²S formatted data. Additionally, the device operates in Single-Speed Mode (SSM), which means that supported sample rates, MCLK rates, and SCLK rates are limited to those shown in the table below. Additional clocking options, including higher sample rates, are available when operating the device in Software Control Mode. Table 3 details the supported SCLK rates for each of the available sample rate and MCLK rate configurations. For each fS and MCLK rate, the supported SCLK rates are shown and are represented in multiples of the sample rate, which is written as "x fS". Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 27 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Device Functional Modes (continued) Table 3. Supported SCLK Rates in Hardware Control Mode (Single Speed Mode) MCLK Rate [x fS] Sample Rate [kHz] 128 192 12 N/S N/S 16 N/S N/S 24 N/S 32, 48, 64 32 32, 48, 64 256 384 512 N/S N/S 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 38 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 44.1 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 48 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin) The TAS5760L has a soft clipper that can be used to clip the output voltage level below the supply rail. When this circuit is active, the amplifier operates as if it was powered by a lower supply voltage, and thereby enters into clipping sooner than if the circuit was not active. The result is clipping behavior very similar to that of clipping at the PVDD rail, in contrast to the digital clipper behavior which occurs in the oversampled domain of the digital path. The point at which clipping begins is controlled by a resistor divider from GVDD_REG to ground, which sets the voltage at the SFT_CLIP pin. The precision of the threshold at which clipping occurs is dependent upon the voltage level at the SFT_CLIP pin. Because of this, increasing the precision of the resistors used to create the voltage divider, or using an external reference will increase the precision of the point at which the device enters into clipping. To ensure stability, and soften the edges of the clipping event, a capacitor should be connected from pin SFT_CLIP to ground. Figure 41. Soft Clipper Example Wave Form To move the output stage into clipping, the soft clipper circuit limits the duty cycle of the output PWM pulses to a fixed maximum value. After filtering this limit applied to the duty cycle resembles a clipping event at a voltage below that of the PVDD level. The peak voltage level attainable when the soft clipper circuit is active, called VP in the example below, is approximately 4 times the voltage at the SFT_CLIP pin, noted as VSFT_CLIP. This voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance, as shown in the equation below. POUT ææ ö ö RL çç ç ÷ ´ VP ÷÷ è RL + 2 ´ RS ø ø = è 2 ´ RL 2 for unclipped power (2) Where: RS is the total series resistance including RDS(on), and output filter resistance. RL is the load resistance. 28 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 VP is the peak amplitude achievable when the soft clipper circuit is active (As mentioned previously, VP = [4 x VSFT_CLIP], provided that [4 x VSFT_CLIP] < PVDD.) POUT (10%THD) ≈ 1.25 × POUT (unclipped) If the PVDD level is below (4 x VSFT_CLIP) clipping will occur due to clipping at PVDD before the clipping due to the soft clipper circuit becomes active. Table 4. Soft Clipper Example PVDD [V] SFT_CLIP Pin Voltage [V] Resistor to GND [kΩ] 12 GVDD 12 2.25 12 1.5 Resistor to GVDD [kΩ] Output Voltage [Vrms] (Open) 0 10.33 24 51 9.00 18 68 6.30 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin) In Hardware Control mode, the PWM switching frequency of the TAS5760L is configurable via the FREQ/SDA pin. When connected to the system ground, the pin sets the output switching frequency to 16 × fS. When connected to DVDD through a pull-up resistor, as shown in the Typical Application Circuits, the pin sets the output switching frequency to 8 × fS. More switching frequencies are available when the TAS5760L is used in Software Control Mode. 9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin) The TAS5760L can be configured to drive a single speaker with the two output channels connected in parallel. This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively reduces the output impedance of the amplifier in half, which in turn reduces the power dissipated in the device due to conduction losses through the output FETs. Additionally, since the output channels are working in parallel, it also doubles the amount of current the speaker amplifier can source before hitting the over-current error threshold. The device can be placed operated in PBTL mode in either Hardware Control Mode or in Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the I²C Control Port, see Software Control Mode. To place the TAS5760L into PBTL Mode when operating in Hardware Control Mode, the PBTL/SCL pin should be pulled HIGH (that is, connected to the DVDD supply through a pull-up resistor). If the device is to operate in BTL mode instead, the PBTL/SCL pin should be pulled LOW, that is connected to the system supply ground. When operated in PBTL mode, the output pins should be connected as shown in the Typical Application Circuit Diagrams. In PBTL mode, the amplifier selects its source signal from the right channel of the stereo signal presented on the SDIN line of the Serial Audio Port. To select the right channel of the stereo signal, the LRCK can be inverted in the processor that is sending the serial audio data to the TAS5760L. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin) In Hardware Control mode, pulling the SPK_SLEEP/ADR pin HIGH gracefully transitions the switching of the output devices to a non-switching state or "High-Z" state. This mode of operation is similar to mute in that no audio is present on the outputs of the device. However, unlike the 50/50 mute available in the I²C Control Port, sleep mode saves quiescent power dissipation by stopping the speaker amplifier output transitors from switching. This mode of operation saves quiescent current operation but keeps signal path blocks active so that normal operation can resume more quickly than if the device were placed into shutdown. It is recommended to place the device into sleep mode before stopping the audio signal coming in on the SDIN line or before bringing down the power supplies connected to the TAS5760L in order to avoid audible artifacts. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins) In Hardware Control Mode, a combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. The decode of the two pins "SPK_GAIN1" and "SPK_GAIN0" sets the gain of the speaker amplifier. Additionally, pulling both of the SPK_SPK_GAIN[1:0] pins HIGH places the device into software control mode. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 29 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com As seen in Figure 42, the audio path of the TAS5760L consists of a digital audio input port, a digital audio path, a digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds the output information back into the DPC block to correct for distortion sensed on the output pins. The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the analog gain from the input of the analog modulator GANA to the output of the speaker amplifier power stage. Digital Gain (GDIG) Analog Gain (GANA) Closed Loop Class D Amplifier HPF Serial Audio Port Serial Audio In Digital Boost & Volume Control Interpolation Filter Digital Clipper Digital to PWM Conversion 123456 Gate Drives Gate Drives 011010.. . Full Bridge Power Stage A Full Bridge Power Stage B PWM Audio Out SFT_CLIP Figure 42. Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins) As shown in Figure 42, the first gain stage for the speaker amplifier is present in the digital audio path. It consists of the volume control and the digital boost block. The volume control is set to 0dB by default and, in Hardware Control mode, it does not change. For all settings of the SPK_GAIN[1:0] pins, the digital boost block remains at +6 dB as analog gain block is transitioned through 19.2, 22.6, and 25 dBV. The gain configurations provided in Hardware Control mode were chosen to align with popular power supply levels found in many consumer electronics and to balance the trade-off between maximum power output before clipping and noise performance. These gain settings ensure that the output signal can be driven into clipping at those popular PVDD levels. If the power level required is lower than that which is possible with the PVDD level, a lower gain setting can be used. Additionally, if clipping at a level lower than the PVDD supply is desired, the digital clipper or soft clipper can be used. The values of GDIG and GANA for each of the SPK_GAIN[1:0] settings are shown in the table below. Additionally, the recommended PVDD level for each gain setting, along with the typical unclipped peak to peak output voltage swing for a 0dBFS input signal is provided. The peak voltage levels in the table below should only be used to understand the peak target output voltage swing of the amplifier if it had not been limited by clipping at the PVDD rail. Table 5. Gain Structure for Hardware Control Mode PVDD Level Recommended SPK_GAIN[1:0] Pins Setting Digital Boost [dB] A_GAIN [dBV] VPk Acheivable Voltage Swing (If output is not clipped at PVDD) 12 00 6 19.2 12.90 15 01 6 22.6 19.08 This setting is not recommended for voltages supported by the TAS5760L 10 6 25 This setting is not recommended for voltages supported by the TAS5760L - 11 30 (Gain is controlled via I²C Port) Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure Configuration of the gain of the amplifier is important to the overall noise and output power performance of the TAS5760L. Higher gain settings mean that more power can be driven from an amplifier before it becomes voltage limited. Moreover, when output clipping "at the rail" is desired, it becomes important that there be enough voltage gain in the signal path to drive the output signal above the PVDD level in order to "clip" the output signal at the PVDD level in the output stage. Another desirable aspect of higher gain settings is that the dynamic headroom of an amplifier is increased with higher gain settings, which increases the overall dynamic audio quality of the signal being amplified. With these advantages in mind, it may seem that setting the gain at the highest setting available would be appropriate. However, there are some drawbacks to having a gain that is set arbitrarily high. The first drawback is that a higher gain setting results in increased amplification of any noise that is present in the signal path. If the gain is set too high, and the speaker is sensitive enough, this may result in an audible "hiss" at the speakers when no audio is playing. Another consideration is that the speakers used in the system may not be rated for operation at the power levels which would be possible for the given PVDD supply that is present in the system. For this reason, it may be necessary to limit the voltage swing of the amplifier via a lower gain setting to reduce the voltage presented, and therefore, the power delivered, to the speaker. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode 1. Determine the maximum power target and the speaker impedance which is required for the application. 2. Calculate the required output voltage swing for the given speaker impedance which will deliver the target maximum power. 3. Chose the lowest gain setting via the SPK_GAIN[1:0] pins that produces an output voltage swing higher than the required output voltage swing for the target maximum power. NOTE A higher gain setting can be used, provided the noise performance is acceptable and the power delivered to the speaker remains within the safe operating area (SOA) of the speaker, using the soft clipper if necessary to set the clip point within the SOA of the speaker. 4. Characterize the clipping behavior of the system at the rated power. – If the system does not produce the target power before clipping that is required, increase the gain setting. – If the system meets the power requirements, but clipping is preferred at the rated power, use the soft clipper to set the clip point – If the system makes more power than is required but the noise performance is too high, consider reducing the gain. 5. Repeat Step 4 until the optimum balance of power, noise, and clipping behavior is achieved. 9.4.2 Software Control Mode The TAS5760L can be used in Hardware Control Mode or Software Control Mode. In order to place the device in software control mode, the two gain pins (GAIN[1:0]) should be pulled HIGH. When this is done, the PBTL/SCL and FREQ/SDA pins are allocated to serve as the clock and data lines for the I²C Control Port. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin) In both hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into shutdown. Driving this pin LOW will place the device into shutdown, while driving it HIGH (DVDD) will bring the device out of shutdown. This is the lowest power consumption mode that the device can be placed in while the power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact may occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the SPK_SLEEP/ADR pin HIGH before pulling the SPK_SD low. 9.4.2.2 Serial Audio Port Controls In Software Control mode, additional digital audio data formats and clock rates are made available via the I²C control port. With these controls, the audio format can be set to left justified, right justified, or I²S formatted data. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 31 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 9.4.2.2.1 Serial Audio Port (SAP) Clocking When used in Software Control mode, the device can be placed into double speed mode to support higher sample rates, such as 88.2 kHz and 96 kHz. The tables below detail the supported SCLK rates for each of the available sample rate and MCLK rate configurations. For each fS and MCLK Rate the support SCLK rates are shown and are represented in multiples of the sample rate, which is written as "x fS". Table 6. Supported SCLK Rates in Single-Speed Mode MCLK Rate [x fS] Sample Rate [kHz] 128 192 256 384 512 12 N/S N/S N/S N/S 32, 48, 64 16 N/S N/S 32, 48, 64 32, 48, 64 32, 48, 64 24 N/S 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 38 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 44.1 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 48 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 Table 7. Supported SCLK Rates in Double-Speed Mode MCLK Rate [x fS] Sample Rate [kHz] 128 192 256 88.2 32, 48, 64 32, 48, 64 32, 48, 64 96 32, 48, 64 32, 48, 64 32, 48, 64 9.4.2.3 Parallel Bridge Tied Load Mode via Software Control The TAS5760L can be configured to drive a single speaker with the two output channels connected in parallel. This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively reduces the on resistance of the amplifier in half, which in turn reduces the power dissipated in the device due to conduction losses through the output FETs. Additionally, since the output channels are working in parallel, it also doubles the amount of current the speaker amplifier can source before hitting the over-current error threshold. It should be noted that the device can be placed operated in PBTL mode in either Hardware Control Mode or in Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the PBTL/SCL Pin, see Hardware Control Mode. To place the TAS5760L into PBTL Mode when operating in Software Control Mode, the Bit 7 of the Analog Control Register (0x06) should be set in the control port. This bit is cleared by default to configure the device for BTL mode operation. An additional control available in software mode control is PBTL Channel Select, which selects which of the two channels presented on the SDIN line will be used for the input signal for the amplifier. This is found at Bit 1 of the Analog Control Register (0x06). When operated in PBTL mode, the output pins should be connected as shown in the Typical Application Circuit Diagrams. 9.4.2.4 Speaker Amplifier Gain Structure As shown in Figure 43, the audio path of the TAS5760L consists of a digital audio input port, a digital audio path, a digital to analog converter, an analog modulator, a gate driver stage, a Class D power stage, and a feedback loop which feeds the output information back into the analog modulator to correct for distortion sensed on the output pins. The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the analog gain from the input of the analog modulator GANA to the output of the speaker amplifier power stage. 32 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Digital Gain (GDIG) Analog Gain (GANA) Closed Loop Class D Amplifier HPF Serial Audio In Serial Audio Port Digital Boost & Volume Control Interpolation Filter Digital Clipper 123456 Gate Drives Digital to PWM Conversion Gate Drives 011010.. . Full Bridge Power Stage A Full Bridge Power Stage B PWM Audio Out SFT_CLIP Figure 43. Speaker Amplifier Gain Structure 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode The analog and digital gain are configured directly when operating in Software Control mode. It is important to note that the digital boost block is separate from the volume control. The digital boost block should be set before the speaker amplifier is brought out of mute and not changed during normal operation. In most cases, the digital boost can be left in its default configuration, and no further adjustment is necessary. As mentioned previously, the analog gain is directly set via the I²C control port in software control mode. 9.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure Configuration of the gain of the amplifier is important to the overall noise and output power performance of the TAS5760L. Higher gain settings mean that more power can be driven from an amplifier before it becomes voltage limited. Moreover, when output clipping "at the rail" is desired, it becomes important that there be enough voltage gain in the signal path to drive the output signal above the PVDD level in order to "clip" the output signal at the PVDD level in the output stage. Another desirable aspect of higher gain settings is that the dynamic headroom of an amplifier is increased with higher gain settings, which increases the overall dynamic audio quality of the signal being amplified. With these advantages in mind, it may seem that setting the gain at the highest setting available would be appropriate. However, there are some drawbacks to having a gain that is set arbitrarily high. The first drawback is that a higher gain setting results in increased amplification of any noise that is present in the signal path. If the gain is set too high, and the speaker is sensitive enough, this may result in an audible "hiss" at the speakers when no audio is playing. Another consideration is that the speakers used in the system may not be rated for operation at the power levels which would be possible for the given PVDD supply that is present in the system. For this reason it may be necessary to limit the voltage swing of the amplifier via a lower gain setting to reduce the voltage presented, and therefore the power delivered, to the speaker. 9.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode 1. Determine the maximum power target and the speaker impedance which is required for the application. 2. Calculate the required output voltage swing for the given speaker impedance which will deliver the target maximum power. 3. Chose the lowest analog gain setting via the A_GAIN[3:2] bits in the control port which will produce an output voltage swing higher than the required output voltage swing for the target maximum power. NOTE A higher gain setting can be used, provided the noise performance is acceptable and the power delivered to the speaker remains within the safe operating area (SOA) of the speaker, using the soft clipper if necessary to set the clip point within the SOA of the speaker. 4. Characterize the clipping behavior of the system at the rated power. – If the system does not produce the target power before clipping that is required, increase the analog gain. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 33 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com – If the system meets the power requirements, but clipping is preferred at the rated power, use the soft clipper or the digital clipper to set the clip point – If the system makes more power than is required but the noise performance is too high, consider reducing the analog gain. 5. Repeat Step 4 until the optimum balance of power, noise, and clipping behavior is achieved. 9.4.2.5 I²C Software Control Port The TAS5760L includes an I²C control port for increased flexibility and extended feature set. 9.4.2.5.1 Setting the I²C Device Address Each device on the I²C bus has a unique address that allows it to appropriately transmit and receive data to and from the I²C master controller. As part of the I²C protocol, the I²C master broadcast an 8-bit word on the bus that contains a 7-bit device address in the upper 7 bits and a read or write bit for the LSB. The TAS5760L has a configurable I²C address. The SPK_SLEEP/ADR can be used to set the device address of the TAS5760L. In Software Control mode, the seven bit I²C device address is configured as “110110x[R/W]”, where “x” corresponds to the state of the SPK_SLEEP/ADR pin at first power up sequence of the device. Upon application of the power supplies, the device latches in the value of the SPK_SLEEP/ADR pin for use in determining the I²C address of the device. If the SPK_SLEEP/ADR pin is tied LOW at power up (that is connected to the system ground), the device address will be set to 1101100[R/W]. If it is pulled HIGH (that is connected to the DVDD supply), the address will be set to 1101101[R/W] at power up. 9.4.2.5.2 General Operation of the I²C Control Port The TAS5760L device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status. The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a START condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate START and STOP conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 44. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5760L holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. SDA R/ A W 7-Bit Slave Address 7 6 5 4 3 2 1 0 8-Bit Register Address (N) 7 6 5 4 3 2 1 0 8-Bit Register Data For Address (N) A 7 6 5 4 3 2 1 8-Bit Register Data For Address (N) A 0 7 6 5 4 3 2 1 A 0 SCL Start Stop T0035-01 Figure 44. Typical I²C Sequence There is no limit on the number of bytes that can be transmitted between START and STOP conditions. When the last word transfers, the master generates a STOP condition to release the bus. A generic data transfer sequence is shown in Figure 44. 34 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 9.4.2.5.3 Writing to the I²C Control Port As shown in Figure 45, a single-byte data-write transfer begins with the master device transmitting a START condition followed by the I²C and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C and the read/write bit, the TAS5760L responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the TAS5760L register being accessed. After receiving the address byte, the TAS5760L again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5760L again responds with an acknowledge bit. Finally, the master device transmits a STOP condition to complete the single-byte data-write transfer. Start Condition Acknowledge A6 A5 A4 A3 A2 A1 Acknowledge R/W ACK A7 A0 A6 2 A5 A4 A3 A2 A1 Acknowledge A0 ACK D7 D6 D5 Subaddress I C Device Address and Read/Write Bit D4 D3 D2 D1 D0 ACK Stop Condition Data Byte T0036-01 Figure 45. Write Transfer 9.4.2.5.4 Reading from the I²C Control Port As shown in Figure 46, a data-read transfer begins with the master device transmitting a START condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5760L address and the read/write bit, TAS5760L responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another START condition followed by the TAS5760L address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5760L again responds with an acknowledge bit. Next, the TAS5760L transmits the data byte from the register being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a STOP condition to complete the data-read transfer. Repeat Start Condition Start Condition Acknowledge A6 A5 A1 Acknowledge A0 R/W ACK A7 A6 2 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 2 I C Device Address and Read/Write Bit Subaddress I C Device Address and Read/Write Bit Not Acknowledge Acknowledge D6 D1 D0 ACK Stop Condition Data Byte T0036-03 Figure 46. Read Transfer 9.5 Register Maps 9.5.1 Control Port Registers - Quick Reference Table 8. Control Port Quick Reference Table Adr. (Dec) Adr. (Hex) 0 0 Device Identification 1 1 Power Control Register Name Default (Binary) B7 B6 B5 0 0 0 B4 B3 B2 B1 B0 0 0 0 SPK_SL EEP SPK_SD 0 1 Default (Hex) Device Identification 0 0 DigClipLev[19:14] 1 1 1 1 1 1 0x00 0xFD Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 35 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Register Maps (continued) Table 8. Control Port Quick Reference Table (continued) Adr. (Dec) Adr. (Hex) 2 2 Default (Binary) Register Name Digital Control 3 3 Volume Control Configuration 4 4 5 6 B7 B6 HPF Bypass Reserved 0 0 Fade B5 Digital Boost 0 0 0 0 Left Channel Volume Control 1 1 0 0 5 Right Channel Volume Control 1 1 0 6 Analog Control PBTL Enable 1 8 Fault Configuration and Error Status 0 0 0 9 9 Reserved - - Reserved - Reserved - 11 Digital Clipper 1 1 1 0 0 Mute R Mute L 0 0 0 1 1 1 1 1 1 0x14 0x80 0xCF 1 0 0 0 0xCF PBTL Ch Reserved Sel A_GAIN Reserved 8 0 17 1 0 0 0 Reserved Reserved Digital Clipper 2 Serial Audio Input Format 0 PWM Rate Select Reserved 10 Default (Hex) B0 Volume Right 7 16 B1 Volume Left 7 F B2 SS/DS 1 1 ... B3 Reserved Reserved Reserved Reserved Reserved 0 15 B4 0 0 Reserved Reserved Reserved Reserved 0x00 0 0 0 0 CLKE OCE DCE OTE 0 0 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 0 0 Reserved 0 0x51 1 OCE Thres DigClipLev[13:6] 1 1 1 1 1 1 1 1 DigClipLev[5:0] 1 1 0x00 0xFF 0xFC 9.5.2 Control Port Registers - Detailed Description 9.5.2.1 Device Identification Register (0x00) Figure 47. Device Identification Register 7 6 5 4 3 Device Identification R 2 1 0 1 SPK_SLEEP R/W 0 SPK_SD R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9. Device Identification Register Field Descriptions Bit Field Type Reset Description 7:0 Device Identification R 0 Device Identification - TAS5760Lxx 9.5.2.2 Power Control Register (0x01) Figure 48. Power Control Register 7 6 5 4 DigClipLev[19:14] R/W 3 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 36 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Table 10. Power Control Register Field Descriptions Bit Field Type Reset Description 7:2 DigClipLev[19:14] R/W 1 The digital clipper is decoded from 3 registersDigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0]. DigClipLev[19:14], shown here, represents the upper 6 bits of the total of 20 bits that are used to set the Digital Clipping Threshold. SPK_SLEEP R/W 0 Sleep Mode 1 0: Device is not in sleep mode. 1: Device is placed in sleep mode (In this mode, the power stage is disabled to reduce quiescent power consumption over a 50/50 duty cycle mute, while low-voltage blocks remain on standby. This reduces the time required to resume playback when compared with entering and exiting full shut down.). 0 SPK_SD R/W 1 Speaker Shutdown 0: Speaker amplifier is shut down (This is the lowest power mode available when the device is connected to power supplies. In this mode, circuitry in both the DVDD and PVDD domain are powered down to minimize power consumption.). 1: Speaker amplifier is not shut down. 9.5.2.3 Digital Control Register (0x02) Figure 49. Digital Control Register 7 HPF Bypass R/W 6 Reserved R 5 4 3 SS/DS R/W Digital Boost R/W 2 1 Serial Audio Input Format R/W 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. Digital Control Register Field Descriptions Bit 7 Field Type Reset Description HPF Bypass R/W 0 High-Pass Filter Bypass 0: The internal high-pass filter in the digital path is not bypassed. 1: The internal high-pass filter in the digital path is bypassed. 6 5:4 Reserved R 0 This control is reserved and must not be changed from its default setting. Digital Boost R/W 01 Digital Boost 00: +0 dB is added to the signal in the digital path. 01: +6 dB is added to the signal in the digital path. (Default) 10: +12 dB is added to the signal in the digital path. 11: +18 dB is added to the signal in the digital path. 3 SS/DS R/W 0 Single Speed / Double Speed Mode Select 0: Serial Audio Port will accept single speed sample rates (that is 32 kHz, 44.1 kHz, 48 kHz) 1: Serial Audio Port will accept double speed sample rates (that is 88.2 kHz, 96 kHz) 2:0 Serial Audio Input Format R/W 100 Serial Audio Input Format 000: Serial Audio Input Format is 24 Bits, Right Justified 001: Serial Audio Input Format is 20 Bits, Right Justified 010: Serial Audio Input Format is 18 Bits, Right Justified 011: Serial Audio Input Format is 16 Bits, Right Justified 100: Serial Audio Input Format is I²S (Default) 101: Serial Audio Input Format is 16-24 Bits, Left Justified Settings above 101 are reserved and must not be used Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 37 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 9.5.2.4 Volume Control Configuration Register (0x03) Figure 50. Volume Control Configuration Register 7 Fade R/W 6 5 4 Reserved R 3 2 1 Mute R R/W 0 Mute L R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12. Volume Control Configuration Register Field Descriptions Bit Field Type Reset Description 7 Fade R/W 1 Volume Fade Enable 0: Volume fading is disabled. 1: Volume fading is enabled. 6:2 1 Reserved R 0 This control is reserved and must not be changed from its default setting. Mute R R/W 0 Mute Right Channel 0: The right channel is not muted 1: The right channel is muted (In software mute, most analog and digital blocks remain active and the speaker amplifier outputs transition to a 50/50 duty cycle.) 0 Mute L R/W 0 Mute Left Channel 0: The left channel is not muted 1: The left channel is muted (In software mute, most analog and digital blocks remain active and the speaker amplifier outputs transition to a 50/50 duty cycle.) 9.5.2.5 Left Channel Volume Control Register (0x04) Figure 51. Left Channel Volume Control Register 7 6 5 4 3 2 1 0 Volume Left R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13. Left Channel Volume Control Register Field Descriptions Bit Field Type Reset Description 7:0 Volume Left R/W 11001111 Left Channel Volume Control 11111111: Channel Volume is +24 dB 11111110: Channel Volume is +23.5 dB 11111101: Channel Volume is +23.0 dB ... 11001111: Channel Volume is 0 dB (Default) ... 00000111: Channel Volume is -100 dB Any setting less than 00000111 places the channel in Mute 9.5.2.6 Right Channel Volume Control Register (0x05) Figure 52. Right Channel Volume Control Register 7 6 5 4 3 2 1 0 Volume Right R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 38 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Table 14. Right Channel Volume Control Register Field Descriptions Bit Field Type Reset Description 7:0 Volume Right R/W 11001111 Right Channel Volume Control 11111111: Channel Volume is +24 dB 11111110: Channel Volume is +23.5 dB 11111101: Channel Volume is +23.0 dB ... 11001111: Channel Volume is 0 dB (Default) ... 00000111: Channel Volume is -100 dB Any setting less than 00000111 places the channel in Mute 9.5.2.7 Analog Control Register (0x06) Figure 53. Analog Control Register 7 PBTL Enable R/W 6 5 PWM Rate Select R/W 4 3 2 1 PBTL Ch Sel R/W A_GAIN R/W 0 Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15. Analog Control Register Field Descriptions Bit 7 Field Type Reset Description PBTL Enable R/W 0 PBTL Enable 0: Device is placed in BTL mode. 1: Device is placed in PBTL mode. 6:4 PWM Rate Select R/W 101 PWM Rate Select 000: Output switching rate of the Speaker Amplifier is 6 * LRCK. 001: Output switching rate of the Speaker Amplifier is 8 * LRCK. 010: Output switching rate of the Speaker Amplifier is 10 * LRCK. 011: Output switching rate of the Speaker Amplifier is 12 * LRCK. 100: Output switching rate of the Speaker Amplifier is 14 * LRCK. 101: Output switching rate of the Speaker Amplifier is 16 * LRCK. (Default) 110: Output switching rate of the Speaker Amplifier is 20 * LRCK. 111: Output switching rate of the Speaker Amplifier is 24 * LRCK. Note that all rates listed above are valid for single speed mode. For double speed mode, switching frequency is half of that represented above. 3:2 A_GAIN R/W 00 00: Analog Gain Setting is 19.2 dBV.(Default) 01: Analog Gain Setting is 22.6 dBV. 10: Analog Gain Setting is 25 dBV. 11: This setting is reserved and must not be used. 1 PBTL Ch Sel R/W 0 Channel Selection for PBTL Mode 0: When placed in PBTL mode, the audio information from the Right channel of the serial audio input stream is used by the speaker amplifier. 1: When placed in PBTL mode, the audio information from the Left channel of the serial audio input stream is used by the speaker amplifier. 0 Reserved R/W 1 This control is reserved and must not be changed from its default setting. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 39 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 9.5.2.8 Reserved Register (0x07) The controls in this section of the control port are reserved and must not be used. 9.5.2.9 Fault Configuration and Error Status Register (0x08) Figure 54. Fault Configuration and Error Status Register 7 6 Reserved R 5 4 3 CLKE R OCE Thres R/W 2 OCE R 1 DCE R 0 OTE R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16. Fault Configuration and Error Status Register Field Descriptions Bit Field Type Reset Description 7:6 Reserved R 0 This control is reserved and must not be changed from its default setting. 5:4 OCE Thres R/W 00 OCE Threshold 00: Threshold is set to the default level specified in the electrical characteristics table. (Default) 01: Threshold is reduced to 75% of the evel specified in the electrical characteristics table. 10: Threshold is reduced to 50% of the evel specified in the electrical characteristics table. 11: Threshold is reduced to 25% of the evel specified in the electrical characteristics table. 3 CLKE R 0 Clock Error Status 0: Clocks are valid and no error is currently detected. 1: A clock error is occuring (This error is non-latching, so intermittent clock errors will be cleared when clocks re-enter valid state and the device will resume normal operation automatically. This bit will likewise be cleared once normal operation resumes.). 2 OCE R 0 Over Current Error Status 0: The output current levels of the speaker amplifier outputs are below the OCE threshold. 1: The DC offset level of the outputs has exceeded the OCE threshold, causing an error (This is a latching error and SPK_SD must be toggled after an OCE event for the device to resume normal operation. This bit will remain HIGH until SPK_SD is toggled.). 1 DCE R 0 Output DC Error Status 0: The DC offset level of the speaker amplifier outputs are below the DCE threshold. 1: The DC offset level of the speaker amplifier outputs has exceeded the DCE threshold, causing an error (This is a latching error and SPK_SD must be toggled after an DCE event for the device to resume normal operation. This bit will remain HIGH until SPK_SD is toggled.). 0 OTE R 0 Over-Temperature Error Status 0: The temperature of the die is below the OTE threshold. 1: The temperature of the die has exceeded the level specified in the electrical characteristics table. (This is a latching error and SPK_SD must be toggled for the device to resume normal operation. This bit will remain HIGH until SPK_SD is toggled.). 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F) The controls in this section of the control port are reserved and must not be used. 9.5.2.11 Digital Clipper Control 2 Register (0x10) 40 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Figure 55. Digital Clipper Control 2 Register 7 6 5 4 3 DigClipLev[13:6] R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. Digital Clipper Control 2 Register Field Descriptions Bit Field Type Reset Description 7:0 DigClipLev[13:6] R/W 1 The digital clipper is decoded from 3 registersDigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0]. DigClipLev[13:6], shown here, represents the [13:6] bits of the total of 20 bits that are used to set the Digital Clipping Threshold. 9.5.2.12 Digital Clipper Control 1 Register (0x11) Figure 56. Digital Clipper Control 1 Register 7 6 5 4 3 2 1 DigClipLev[5:0] R/W 0 Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. Digital Clipper Control 1 Register Field Descriptions Bit Field Type Reset Description 7:2 DigClipLev[5:0] R/W 1 The digital clipper is decoded from 3 registersDigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0]. DigClipLev[5:0], shown here, represents the [5:0] bits of the total of 20 bits that are used to set the Digital Clipping Threshold. 1:0 Reserved R/W 0 These controls are reserved and should not be changed from there default values. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 41 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases. Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in all available modes of operation. Additionally, some of the application circuits are available as reference designs and can be found on the TI website. Also see the TAS5760L's product page for information on ordering the EVM. Not all configurations are available as reference designs; however, any design variation can be supported by TI through schematic and layout reviews. Visit support.ti.com for additional design assistance. Also, join the audio amplifier discussion forum at http://e2e.ti.com. 10.2 Typical Applications These application circuits detail the recommended component selection and board configurations for the TAS5760L device. Note that in Software Control mode, the clipping point of the amplifier and thus the rated power of the end equipment can be set using the digital clipper if desired. Additionally, if the sonic signature of the soft clipper is preferred, it can be used in addition to or in lieu of the digital clipper. The software control application circuit detailed in this section shows the soft clipper in its bypassed state, which results in a lower BOM count than when using the soft clipper. The trade-off between the sonic characteristics of the clipping events in the amplifier and BOM minimization can be chosen based upon the design goals related to the end product. 10.2.1 Stereo BTL Using Software Control VDD 1 1.0 µF 10 kΩ 2 1.0 µF 3 4 5 6 7 8 VDD 9 1.0 µF System Processor & Associated Passive R HIGH 1101101[ / W] LOW 1101100[ R/ W] 10 10 kΩ 11 12 13 14 15 16 Components 17 18 19 20 21 22 23 24 SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN LRCK DGND NC NC NC NC NC NC NC GVDD_REG GGND AVDD PVDD PVDD BSTRPA+ SPK_OUTA+ PGND SPK_OUTABSTRPABSTRPB+ SPK_OUTBPGND SPK_OUTB+ BSTRPBPVDD PVDD NC NC NC NC NC NC NC 1.0 µF PVDD 48 47 46 45 44 43 0.22 µF 0.1 µF LFILT 42 CFILT 41 40 39 38 CFILT 0.22 µF 0.22 µF LFILT 470 µF 37 LFILT CFILT 36 35 CFILT 0.22 µF 34 LFILT 33 32 31 0.1 µF 30 29 28 27 26 25 Figure 57. Stereo BTL Using Software Control 10.2.1.1 Design Requirements For this design example, use the parameters listed in Table 19 as the input parameters. 42 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Typical Applications (continued) Table 19. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V Host Processor I2C Compliant Master Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω I2S Compliant Master GPIO Control 10.2.1.2 Detailed Design Procedure 10.2.1.2.1 Startup Procedures- Software Control Mode 1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.) 2. Start with SPK_SD Pin = LOW 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port 6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH 7. Unmute the device via the control port 8. The device is now in normal operation NOTE Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.1.2.2 Shutdown Procedures- Software Control Mode 1. 2. 3. 4. 5. The device is in normal operation Mute via the control port Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off NOTE Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.1.2.3 Component Selection and Hardware Connections details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 43 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10.2.1.2.3.1 I²C Pullup Resistors It is important to note that when the device is operated in Software Control Mode, the customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification. 10.2.1.2.3.2 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.1.2.4 Recommended Startup and Shutdown Procedures The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below. 10.2.1.3 Application Curve Table 20. Relevant Performance Plots PLOT TITLE 44 PLOT NUMBER Figure 1. Output Power vs PVDD G001 Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024 Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027 Figure 7. Efficiency vs Output Power G030 Figure 8. Crosstalk vs Frequency G031 Figure 9. PVDD PSRR vs Frequency G019 Figure 10. DVDD PSRR vs Frequency G020 Figure 11. Idle Current Draw vs PVDD (Filterless) G042 Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023 Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022 Figure 14. Output Power vs PVDD G039 Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002 Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008 Figure 20. Efficiency vs Output Power G014 Figure 21. Crosstalk vs Frequency G018 Figure 22. PVDD PSRR vs Frequency G019 Figure 23. Idle Current Draw vs PVDD (Filterless) G045 Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044 Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 10.2.2 Stereo BTL Using Hardware Control RCLIP1 VDD 1.0 µF 1 RCLIP2 1.0 µF 2 1.0 µF 10 kΩ 3 4 5 VDD HIGH →f SPK_AMP = 8 * f S LOW →fSPK_AMP = 16 * f S 6 7 8 1.0 µF 9 10 Gain Set by Pin Decode System Processor & Associated Passive Components 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN LRCK DGND NC NC NC NC NC NC NC GVDD_REG GGND AVDD PVDD PVDD BSTRPA+ SPK_OUTA+ PGND SPK_OUTABSTRPABSTRPB+ SPK_OUTBPGND SPK_OUTB+ BSTRPBPVDD PVDD NC NC NC NC NC NC NC 1.0 µF PVDD 48 47 46 45 44 0.22 µF 0.1 µF L FILT 43 42 C FILT 41 C FILT 40 0.22 µF 0.22 µF 39 38 L FILT 470 µF 37 L FILT C FILT 36 35 C FILT 0.22 µF 34 L FILT 33 32 31 0.1 µF 30 29 28 27 26 25 Figure 58. Stereo BTL Using Hardware Control 10.2.2.1 Design Requirements For this design example, use the parameters listed in Table 21 as the input parameters. Table 21. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V I2S Compliant Master Host Processor GPIO Control Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω 10.2.2.2 Detailed Design Procedure 10.2.2.2.1 Startup Procedures- Hardware Control Mode 1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.) 2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH 6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW 7. The device is now in normal operation Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 45 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode 1. 2. 3. 4. 5. The device is in normal operation Pull SPK_SLEEP/ADR HIGH Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off 10.2.2.2.3 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.2.3 Application Curve Table 22. Relevant Performance Plots PLOT TITLE 46 PLOT NUMBER Figure 1. Output Power vs PVDD G001 Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024 Figure 4. Idle Channel Noise vs PVDD G026 Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027 Figure 7. Efficiency vs Output Power G030 Figure 8. Crosstalk vs Frequency G031 Figure 9. PVDD PSRR vs Frequency G019 Figure 10. DVDD PSRR vs Frequency G020 Figure 11. Idle Current Draw vs PVDD (Filterless) G042 Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023 Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022 Figure 14. Output Power vs PVDD G039 Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002 Figure 17. Idle Channel Noise vs PVDD G006 Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008 Figure 20. Efficiency vs Output Power G014 Figure 21. Crosstalk vs Frequency G018 Figure 22. PVDD PSRR vs Frequency G019 Figure 23. Idle Current Draw vs PVDD (Filterless) G045 Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044 Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 10.2.3 Mono PBTL Using Software Control VDD 1 1.0 µF 10 kΩ 2 1.0 µF 3 4 5 6 7 8 VDD 9 1.0 µF System Processor & Associated Passive Components R HIGH→ 1101101[ / W] R LOW → 1101100[ / W] 10 10 kΩ 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN LRCK DGND NC NC NC NC NC NC NC GVDD_REG GGND AVDD PVDD PVDD BSTRPA+ SPK_OUTA+ PGND SPK_OUTABSTRPABSTRPB+ SPK_OUTBPGND SPK_OUTB+ BSTRPBPVDD PVDD NC NC NC NC NC NC NC 1.0 µF PVDD 48 47 46 45 44 0.22 µF 0.1 µF L FILT 43 42 CFILT 41 40 0.22 µF 0.22 µF 39 38 470 µF 37 36 35 CFILT 0.22 µF 34 LFILT 33 32 31 0.1 µF 30 29 28 27 26 25 Figure 59. Mono PBTL Using Software Control 10.2.3.1 Design Requirements For this design example, use the parameters listed in Table 23 as the input parameters. Table 23. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V I2S Compliant Master Host Processor I2C Compliant Master Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω GPIO Control 10.2.3.2 Detailed Design Procedure 10.2.3.2.1 Startup Procedures- Software Control Mode 1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.) 2. Start with SPK_SD Pin = LOW 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port 6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH 7. Unmute the device via the control port 8. The device is now in normal operation Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 47 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com NOTE Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.3.2.2 Shutdown Procedures- Software Control Mode 1. 2. 3. 4. 5. The device is in normal operation Mute via the control port Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off NOTE Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.3.2.3 Component Selection and Hardware Connections above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. 10.2.3.2.3.1 I²C Pull-Up Resistors It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification. 10.2.3.2.3.2 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.3.3 Application Curve Table 24. Relevant Performance Plots PLOT TITLE 48 PLOT NUMBER Figure 27. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032 Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035 Figure 37. Efficiency vs Output Power G038 Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004 Figure 35. THD+N vs Output Power With PVDD = 12 V G011 Figure 7. Efficiency vs Output Power G015 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 10.2.4 Mono PBTL Using Hardware Control R CLIP1 VDD 1.0 µF 1 R CLIP2 1.0 µF 1.0 µF 10 kΩ 2 3 4 5 VDD HIGH→ f SPK_AMP = 8 * f S LOW → fSPK_AMP= 16 * f S 6 7 8 1.0 µF 10 kΩ 9 10 Gain Set by Pin Decode System Processor & Associated Passive 11 12 13 14 15 16 Components 17 18 19 20 21 22 23 24 SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN LRCK DGND NC NC NC NC NC NC NC GVDD_REG GGND AVDD PVDD PVDD BSTRPA+ SPK_OUTA+ PGND SPK_OUTABSTRPABSTRPB+ SPK_OUTBPGND SPK_OUTB+ BSTRPBPVDD PVDD NC NC NC NC NC NC NC 1.0 µF PVDD 48 47 46 45 44 0.1 µF 0.22 µF L FILT 43 42 C FILT 41 40 39 38 0.22 µF 0.22 µF 470 µF 37 36 35 C FILT 0.22 µF 34 LFILT 33 32 31 0.1 µF 30 29 28 27 26 25 Figure 60. Mono PBTL Using Hardware Control 10.2.4.1 Design Requirements For this design example, use the parameters listed in Table 25 as the input parameters. Table 25. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V I2S Compliant Master Host Processor GPIO Control Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω 10.2.4.2 Detailed Design Procedure 10.2.4.2.1 Startup Procedures- Hardware Control Mode 1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.) 2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH 6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW 7. The device is now in normal operation Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 49 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10.2.4.2.2 Shutdown Procedures- Hardware Control Mode 1. 2. 3. 4. 5. The device is in normal operation Pull SPK_SLEEP/ADR HIGH Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off 10.2.4.2.3 Component Selection and Hardware Connections details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. 10.2.4.2.4 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.4.3 Application Curve Table 26. Relevant Performance Plots PLOT TITLE 50 PLOT NUMBER Figure 32. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032 Figure 34. Idle Channel Noise vs PVDD G034 Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035 Figure 37. Efficiency vs Output Power G038 Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004 Figure 17. Idle Channel Noise vs PVDD G007 Figure 35. THD+N vs Output Power With PVDD = 12 V G011 Figure 7. Efficiency vs Output Power G015 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option PVDD VDD 1 2 1.0 …F 10 lQ 1.0 …F 3 4 5 6 7 8 VDD 9 1.0 …F System Processor & Associated Passive Components 10 11 R HIGH Æ 1101101[ /W] LOW Æ 1101100[R/W] 10 lQ 12 13 14 15 16 AVDD SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN GVDD_REG GGND BSTRPA+ SPK_OUTA+ PVDD PGND SPK_OUTABSTRPABSTRPBSPK_OUTBPGND PVDD SPK_OUTB+ BSTRPB+ DGND LRCK 1.0 …F 48 47 46 0.22…F 0.1 …F LFILT 31 CFILT 30 29 CFILT 28 27 26 0.22…F 0.22…F LFILT 470 …F LFILT 25 CFILT 24 23 CFILT 22 21 0.22…F LFILT 20 19 0.1 …F Figure 61. Stereo BTL using Software Control, 32-Pin DAP Package Option 10.2.5.1 Design Requirements For this design example, use the parameters listed in Table 27 as the input parameters. Table 27. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V I2S Compliant Master Host Processor I2C Compliant Master Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω GPIO Control 10.2.5.2 Detailed Design Procedure 10.2.5.2.1 Startup Procedures- Software Control Mode 1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.) 2. Start with SPK_SD Pin = LOW 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port 6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH 7. Unmute the device via the control port 8. The device is now in normal operation Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 51 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com NOTE Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.5.2.2 Shutdown Procedures- Software Control Mode 1. 2. 3. 4. 5. The device is in normal operation Mute via the control port Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off NOTE Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.5.2.3 Component Selection and Hardware Connections Figure 61 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. 10.2.5.2.3.1 I²C Pullup Resistors It is important to note that when the device is operated in Software Control Mode, the customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification. 10.2.5.2.3.2 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.5.2.4 Recommended Startup and Shutdown Procedures The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below. 10.2.5.3 Application Curve Table 28. Relevant Performance Plots PLOT TITLE 52 PLOT NUMBER Figure 1. Output Power vs PVDD G001 Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024 Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027 Figure 7. Efficiency vs Output Power G030 Figure 8. Crosstalk vs Frequency G031 Figure 22. PVDD PSRR vs Frequency G019 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Table 28. Relevant Performance Plots (continued) PLOT TITLE PLOT NUMBER Figure 10. DVDD PSRR vs Frequency G020 Figure 11. Idle Current Draw vs PVDD (Filterless) G042 Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023 Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022 Figure 14. Output Power vs PVDD G039 Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002 Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008 Figure 7. Efficiency vs Output Power G014 Figure 21. Crosstalk vs Frequency G018 Figure 22. PVDD PSRR vs Frequency G019 Figure 23. Idle Current Draw vs PVDD (Filterless) G045 Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044 Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 53 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option RCLIP1 1.0 …F PVDD RCLIP2 HIGH Æ fSPK_AMP = 8 * fS LOW Æ fSPK_AMP = 16 * fS VDD 1 2 1.0 …F 1.0 …F 10 lQ 3 4 5 6 7 VDD 8 9 1.0 …F System Processor & Associated Passive Components 10 11 Gain Set by Pin Decode 12 13 14 15 16 AVDD SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN GVDD_REG GGND BSTRPA+ SPK_OUTA+ PVDD PGND SPK_OUTABSTRPABSTRPBSPK_OUTBPGND PVDD SPK_OUTB+ BSTRPB+ DGND LRCK 1.0 …F 48 47 46 0.22…F 0.1 …F LFILT 31 CFILT 30 29 CFILT 28 27 26 0.22…F LFILT 470 …F 0.22…F LFILT 25 CFILT 24 23 CFILT 22 21 0.22…F LFILT 20 19 0.1 …F Figure 62. Stereo BTL using Hardware Control, 32-Pin DAP Package Option 10.2.6.1 Design Requirements For this design example, use the parameters listed in Table 29 as the input parameters. Table 29. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V I2S Compliant Master Host Processor GPIO Control Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω 10.2.6.2 Detailed Design Procedure 10.2.6.2.1 Startup Procedures- Hardware Control Mode 1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.) 2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH 6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW 7. The device is now in normal operation 10.2.6.2.2 Shutdown Procedures- Hardware Control Mode 1. The device is in normal operation 54 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com 2. 3. 4. 5. SLOS782C – JULY 2013 – REVISED MAY 2017 Pull SPK_SLEEP/ADR HIGH Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off 10.2.6.2.3 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.6.3 Application Curve Table 30. Relevant Performance Plots PLOT TITLE PLOT NUMBER Figure 1. Output Power vs PVDD G001 Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024 Figure 4. Idle Channel Noise vs PVDD G026 Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027 Figure 7. Efficiency vs Output Power G030 Figure 8. Crosstalk vs Frequency G031 Figure 22. PVDD PSRR vs Frequency G019 Figure 10. DVDD PSRR vs Frequency G020 Figure 11. Idle Current Draw vs PVDD (Filterless) G042 Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023 Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022 Figure 14. Output Power vs PVDD G039 Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002 Figure 17. Idle Channel Noise vs PVDD G006 Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008 Figure 7. Efficiency vs Output Power G014 Figure 21. Crosstalk vs Frequency G018 Figure 22. PVDD PSRR vs Frequency G019 Figure 23. Idle Current Draw vs PVDD (Filterless) G045 Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044 Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 55 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option PVDD VDD 1 2 1.0 …F 1.0 …F 10 lQ 3 4 5 6 7 System Processor & Associated Passive Components 8 VDD 9 1.0 …F HIGH Æ 1101101[R/W] LOW Æ 1101100[R/W] 10 11 10 lQ 12 13 14 15 16 AVDD SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN GVDD_REG GGND BSTRPA+ SPK_OUTA+ PVDD PGND SPK_OUTABSTRPABSTRPBSPK_OUTBPGND PVDD SPK_OUTB+ BSTRPB+ DGND LRCK 1.0 …F 48 47 46 0.22…F 0.1 …F LFILT 31 CFILT 30 29 28 27 26 0.22…F 470 …F 0.22…F 25 24 CFILT 23 22 21 LFILT 0.22…F 20 19 0.1 …F Figure 63. Mono PBTL using Software Control, 32-Pin DAP Package Option 10.2.7.1 Design Requirements For this design example, use the parameters listed in Table 31 as the input parameters. Table 31. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V Host Processor I2C Compliant Master Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω I2S Compliant Master GPIO Control 10.2.7.2 Detailed Design Procedure 10.2.7.2.1 Startup Procedures- Software Control Mode 1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.) 2. Start with SPK_SD Pin = LOW 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port 6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH 7. Unmute the device via the control port 8. The device is now in normal operation 56 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 NOTE Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.7.2.2 Shutdown Procedures- Software Control Mode 1. 2. 3. 4. 5. The device is in normal operation Mute via the control port Pull SPK_SD LOW The clocks can now be stopped and the power supplies brought down The device is now fully shutdown and powered off NOTE Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port. 10.2.7.2.3 Component Selection and Hardware Connections Figure 63 above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. 10.2.7.2.3.1 I²C Pull-Up Resistors It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification. 10.2.7.2.3.2 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.7.3 Application Curve Table 32. Relevant Performance Plots PLOT TITLE PLOT NUMBER Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032 Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035 Figure 7. Efficiency vs Output Power G038 Figure 16. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004 Figure 35. THD+N vs Output Power With PVDD = 12 V G011 Figure 31. Efficiency vs Output Power G015 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 57 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option RCLIP1 1.0 …F VDD PVDD RCLIP2 HIGH Æ fSPK_AMP = 8 * fS LOW Æ fSPK_AMP = 16 * fS 1 1.0 …F 2 1.0 …F 10 lQ 3 4 5 6 7 VDD 10 lQ 8 9 1.0 …F System Processor & Associated Passive Components 10 11 Gain Set by Pin Decode 12 13 14 15 16 AVDD SFT_CLIP ANA_REG VCOM ANA_REF SPK_FAULT SPK_SD FREQ/SDA PBTL/SCL DVDD SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR MCLK SCLK SDIN GVDD_REG GGND BSTRPA+ SPK_OUTA+ PVDD PGND SPK_OUTABSTRPABSTRPBSPK_OUTBPGND PVDD SPK_OUTB+ BSTRPB+ DGND LRCK 1.0 …F 48 0.1 …F 47 46 0.22…F LFILT 31 30 CFILT 29 28 27 26 0.22…F 470 …F 0.22…F 25 24 CFILT 23 22 21 0.22…F LFILT 20 19 0.1 …F Figure 64. Mono PBTL using Hardware Control, 32 Pin DAP Package Option 10.2.8.1 Design Requirements For this design example, use the parameters listed in Table 33 as the input parameters. Table 33. Design Parameters PARAMETER EXAMPLE Low Power Supply 3.3 V High Power Supply 5 V to 15 V I2S Compliant Master Host Processor GPIO Control Output Filters Inductor-Capacitor Low Pass Filter Speakers 4 Ω to 8 Ω 10.2.8.2 Detailed Design Procedure 10.2.8.2.1 Startup Procedures- Hardware Control Mode 1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.) 2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH 3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.) 4. Once power supplies are stable, start MCLK, SCLK, LRCK 5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH 6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW 7. The device is now in normal operation 10.2.8.2.2 Shutdown Procedures- Hardware Control Mode 1. The device is in normal operation 2. Pull SPK_SLEEP/ADR HIGH 58 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 3. Pull SPK_SD LOW 4. The clocks can now be stopped and the power supplies brought down 5. The device is now fully shutdown and powered off 10.2.8.2.3 Component Selection and Hardware Connections Figure 64 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. 10.2.8.2.4 Digital I/O Connectivity The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor. 10.2.8.3 Application Curve Table 34. Relevant Performance Plots PLOT TITLE PLOT NUMBER Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032 Figure 34. Idle Channel Noise vs PVDD G034 Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035 Figure 7. Efficiency vs Output Power G038 Figure 16. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004 Figure 17. Idle Channel Noise vs PVDD G007 Figure 35. THD+N vs Output Power With PVDD = 12 V G011 Figure 31. Efficiency vs Output Power G015 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 59 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com 11 Power Supply Recommendations The TAS5760L device requires two power supplies for proper operation. A high-voltage supply called PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low voltage power supply called DVDD is required to power the various low-power portions of the device. The allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating Conditions table. 11.1 DVDD Supply The DVDD supply required from the system is used to power several portions of the device it provides power to the DVDD pin and the DRVDD pin. Proper connection, routing, and decoupling techniques are highlighted in the TAS5760xx EVM User's Guide, SLOU371 (as well as the Application and Implementation section and Layout Example section) and must be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in the TAS5760xx EVM User's Guide, which followed the same techniques as those shown in the Application and Implementation section, may result in reduced performance, errant functionality, or even damage to the TTAS5760L device. Some portions of the device also require a separate power supply which is a lower voltage than the DVDD supply. To simplify the power supply requirements for the system, the TAS5760L device includes an integrated low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD supply and its output is presented on the ANA_REG pin, providing a connection point for an external bypass capacitor. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device. 11.2 PVDD Supply The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are highlighted in the TAS5760xx EVM and must be followed as closely as possible for proper operation and performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple the output power stages in the manner described in the TaS5760xx EVM User's Guide, SLOU371. The lack of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can damage the device. A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device. 12 Layout 12.1 Layout Guidelines 12.1.1 General Guidelines for Audio Amplifiers Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and the layout of the supporting components used around them. The system level performance metrics, including thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all affected by the device and supporting component layout. Ideally, the guidance provided in the applications section with regard to device and component selection can be followed by precise adherence to the layout guidance shown in Layout Example. These examples represent exemplary baseline balance of the engineering trade-offs involved with laying out the device. These designs can be modified slightly as needed to meet the needs of a given application. In some applications, for instance, solution size can be compromised in order to improve thermal performance through the use of additional contiguous copper near the device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start from the guidance shown in the Layout Example section and the TAS5760xx EVM, and work with TI field application engineers or through the E2E community in order to modify it based upon the application specific goals. 60 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Layout Guidelines (continued) 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. This applies to DVDD, DRVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5760L device deserve special attention. It is imperative that the small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible. Not only does placing these devices far away from the pins increase the electromagnetic interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these components too far from the TAS5760Ldevice may cause ringing on the output pins that can cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the device. For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD pins than what is shown in the example layouts in the Layout Example section. 12.1.3 Optimizing Thermal Performance Follow the layout examples shown in the Layout Example section of this document to achieve the best balance of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance may be required due to design constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device would prefer to travel away from the device and into the lower temperature structures around the device. 12.1.3.1 Device, Copper, and Component Layout Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures. These tips should be followed to achieve that goal: • Avoid placing other heat producing components or structures near the amplifier (including above or below in the end equipment). • If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5760Ldevice and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top and bottom layer. • Place the TTAS5760L device away from the edge of the PCB when possible to ensure that heat can travel away from the device on all four sides. • Avoid cutting off the flow of heat from the TAS5760Ldevice to the surrounding areas with traces or via strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular to the device. • Unless the area between two pads of a passive component is large enough to allow copper to flow in between the two pads, orient it so that the narrow end of the passive component is facing the TAS5760L device. • Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible. 12.1.3.2 Stencil Pattern The recommended drawings for the TAS5760L device PCB foot print and associated stencil pattern are shown at the end of this document in the package addendum. Additionally, baseline recommendations for the via arrangement under and around the device are given as a starting point for the PCB design. This guidance is provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this guidance may be too conservative and advanced PCB design techniques may be used to improve thermal performance of the system. It is important to note that the customer must verify that deviation from the guidance shown in the package addendum, including the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability goals. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 61 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Layout Guidelines (continued) 12.1.3.2.1 PCB Footprint and Via Arrangement The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the TAS5760Ldevice will be soldered to. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5760Ldevice, be made no smaller than what is specified in the package addendum. This ensures that the TAS5760L device has the largest interface possible to move heat from the device to the board. The via pattern shown in the package addendum provides an improved interface to carry the heat from the device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings) present a low thermalimpedance path from the device into the PCB. Once into the PCB, the heat travels away from the device and into the surrounding structures and air. By increasing the number of vias, as shown in Layout Example, this interface can benefit from improved thermal performance. NOTE Vias can obstruct heat flow if they are not constructed properly. • • • • • Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via. Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the additional cost of filled vias. The drill diameter should be no more than 8mils in diameter. Also, the distance between the via barrel and the surrounding planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases, minimum spacing should be determined by the voltages present on the planes surrounding the via and minimized wherever possible. Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding area. This arrangement is shown in the Layout Example section. Ensure that vias do not cut-off power current flow from the power supply through the planes on internal layers. If needed, remove some vias which are farthest from the TAS5760L device to open up the current path to and from the device. 12.1.3.2.1.1 Solder Stencil During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the thermal pad on the PCB is quite large and depositing a large, single deposition of solder paste would lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is called an aperture array, and is shown in the Layout Example section. It is important that the total area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the thermal pad itself. 62 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 12.2 Layout Example 10k 10 F 10 F 47 Ÿ 1 3232 2 3131 3 3030 4 2929 5 2828 6 2727 7 2626 8 2525 9 2424 10 2323 11 2222 0.22uF 10 F 10 F 12 2121 13 2020 14 1919 15 1818 16 1717 0.22uF 0.22uF 0.22uF TAS5760L System Processor Top Layer Ground and PowerPad Via to bottom Ground Plane Top Layer Ground Pour Via to PVDD Top Layer Signal Traces Figure 65. DAP Package PBTL Configuration Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 63 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Layout Example (continued) 10k 10 F 10 F 47 Ÿ 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 0.22uF 10 F 10 F 12 21 13 20 14 19 15 18 16 17 0.22uF 0.22uF 0.22uF TAS5760L System Processor Top Layer Ground and PowerPad Via to bottom Ground Plane Top Layer Ground Pour Via to PVDD Top Layer Signal Traces Figure 66. DAP Package BTL Configuration 64 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 Layout Example (continued) 10k 10 F 47 Ÿ 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 10 F 10 F 10 F 0.22uF 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 0.22uF 0.22uF 0.22uF 0.22uF 10 F TAS5760L System Processor Top Layer Ground and PowerPad Via to bottom Ground Plane Top Layer Ground Pour Via to PVDD Top Layer Signal Traces Figure 67. DCA Package PBTL Configuration Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 65 TAS5760L SLOS782C – JULY 2013 – REVISED MAY 2017 www.ti.com Layout Example (continued) 10k 10 F 47 Ÿ 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 10 F 10 F 10 F 0.22uF 0.22uF 0.22uF 0.22uF 10 F TAS5760L System Processor Top Layer Ground and PowerPad Via to bottom Ground Plane Top Layer Ground Pour Via to PVDD Top Layer Signal Traces Figure 68. DCA Package BTL Configuration 66 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L TAS5760L www.ti.com SLOS782C – JULY 2013 – REVISED MAY 2017 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation • TI FilterPro™ program available at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html • TAS5760xx EVM User's Guide, SLOU371 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided AS IS by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated Product Folder Links: TAS5760L 67 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TAS5760LDAP ACTIVE HTSSOP DAP 32 46 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 TAS5760L TAS5760LDAPR ACTIVE HTSSOP DAP 32 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 TAS5760L TAS5760LDCA ACTIVE HTSSOP DCA 48 40 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 TAS5760L TAS5760LDCAR ACTIVE HTSSOP DCA 48 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 TAS5760L (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of