TCA9539-Q1
SCPS254D – JANUARY 2014 – REVISED OCTOBER 2021
TCA9539-Q1 Automotive Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander
with Interrupt Output, Reset Pin, and Configuration Registers
1 Features
3 Description
•
The TCA9539-Q1 is a 24-pin device that provides
16 bits of general purpose parallel input and output
(I/O) expansion for the two-line bidirectional I2C bus
(or SMBus protocol). The device can operate with a
power supply voltage (VCC) range from 1.65 V to 3.6
V. The device supports 100 kHz (I2C Standard mode)
and 400 kHz (I2C Fast mode) clock frequencies. I/O
expanders such as the TCA9539-Q1 provide a simple
solution when additional I/Os are needed for switches,
sensors, push-buttons, LEDs, fans, and other similar
devices.
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AEC-Q100 (Grade 1): Qualified for automotive
applications
Functional Safety-Capable
– Documentation available to aid in functional
safety system design
I2C to parallel port expander
Open-drain active-low interrupt output
Active-low reset input
5 V tolerant input and output ports
Compatible with most microcontrollers
400 kHz Fast I2C bus
Polarity inversion register
Internal power-on reset
No glitch on power up
Address by two hardware address pins for use of
up to four devices
Latched outputs for directly driving LEDs
Latch-up performance exceeds 100 mA Per JESD
78, class II
ESD protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 1000-V Charged-device model (C101)
The features of the TCA9539-Q1 include an interrupt
that is generated on the INT pin whenever an
input port changes state. The A0 and A1 hardware
selectable address pins allow up to four TCA9539-Q1
devices on the same I2C bus. The device can be reset
to its default state by cycling the power supply and
causing a power-on reset. Also, the TCA9539-Q1 has
a hardware RESET pin that can be used to reset the
device to its default state.
The TCA9539-Q1 I2C I/O expander is qualified for
automotive applications.
2 Applications
Device Information
•
Automotive infotainment, advanced driver
assistance systems (ADAS), automotive body
electronics, HEV, EV and powertrain
• Industrial automation, factory automation, building
automation, test and measurement, EPOS
• I2C GPIO expansion
spacer
PART NUMBER
TCA9539-Q1
(1)
PACKAGE TYPE(1)
TSSOP (24)
BODY SIZE (NOM)
7.80 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
Peripheral Devices
SDA
SCL
INT
P00
P01
I2C or SMBus Controller
(e.g. Processor)
RESET
x
x
TCA9539-Q1
x
A0
/RESET,
ENABLE, or
control inputs
/INT or status
outputs
LEDs
P17
A1
GND
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9539-Q1
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SCPS254D – JANUARY 2014 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 I2C Interface Timing Requirements.............................6
6.7 RESET Timing Requirements..................................... 7
6.8 Switching Characteristics............................................7
6.9 Typical Characteristics................................................ 8
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................15
8.1 Overview................................................................... 15
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................18
8.5 Programming............................................................ 18
8.6 Register Maps...........................................................20
9 Power Supply Recommendations................................29
9.1 Power-On Reset Requirements................................ 29
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................33
11.1 Documentation Support.......................................... 33
11.2 Receiving Notification of Documentation Updates.. 33
11.3 Support Resources................................................. 33
11.4 Trademarks............................................................. 33
11.5 Electrostatic Discharge Caution.............................. 33
11.6 Glossary.................................................................. 33
4 Revision History
Changes from Revision C (December 2018) to Revision D (October 2021)
Page
• Added feature: Functional Safety-Capable ........................................................................................................1
• Globally changed instances of legacy terminology to controller and target where mentioned........................... 1
• Corrected the pin number for pins A0, SCL, SDA, and VCC in the TCA9539-Q1 Layout ............................... 32
Changes from Revision B (April 2016) to Revision C (December 2018)
Page
• Changed the appearance of the PW pinout image ............................................................................................3
• Removed (5 V) from the VCC label in Figure 9-1 ............................................................................................. 25
Changes from Revision A (September 2015) to Revision B (April 2016)
Page
• Changed device status from Product Preview to Production Data .................................................................... 1
Changes from Revision * (January 2014) to Revision A (September 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
2
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5 Pin Configuration and Functions
INT
1
24
VCC
A1
2
23
SDA
RESET
3
22
SCL
P00
4
21
A0
P01
5
20
P17
P02
6
19
P16
P03
7
18
P15
P04
8
17
P14
P05
9
16
P13
P06
10
15
P12
P07
11
14
P11
GND
12
13
P10
Not to scale
Figure 5-1. PW Package, 24-Pin TSSOP, Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
INT
O
Interrupt open-drain output. Connect to VCC through a pull-up resistor
2
A1
I
Address input. Connect directly to VCC or ground
3
RESET
I
Active-low reset input. Connect to VCC through a pull-up resistor if no active connection is used
4
P00
I/O
P-port input-output. Push-pull design structure. At power-on, P00 is configured as an input
5
P01
I/O
P-port input-output. Push-pull design structure. At power-on, P01 is configured as an input
6
P02
I/O
P-port input-output. Push-pull design structure. At power-on, P02 is configured as an input
7
P03
I/O
P-port input-output. Push-pull design structure. At power-on, P03 is configured as an input
8
P04
I/O
P-port input-output. Push-pull design structure. At power-on, P04 is configured as an input
9
P05
I/O
P-port input-output. Push-pull design structure. At power-on, P05 is configured as an input
10
P06
I/O
P-port input-output. Push-pull design structure. At power-on, P06 is configured as an input
11
P07
I/O
P-port input-output. Push-pull design structure. At power-on, P07 is configured as an input
12
GND
—
Ground
13
P10
I/O
P-port input-output. Push-pull design structure. At power-on, P10 is configured as an input
14
P11
I/O
P-port input-output. Push-pull design structure. At power-on, P11 is configured as an input
15
P12
I/O
P-port input-output. Push-pull design structure. At power-on, P12 is configured as an input
16
P13
I/O
P-port input-output. Push-pull design structure. At power-on, P13 is configured as an input
17
P14
I/O
P-port input-output. Push-pull design structure. At power-on, P14 is configured as an input
18
P15
I/O
P-port input-output. Push-pull design structure. At power-on, P15 is configured as an input
19
P16
I/O
P-port input-output. Push-pull design structure. At power-on, P16 is configured as an input
20
P17
I/O
P-port input-output. Push-pull design structure. At power-on, P17 is configured as an input
21
A0
I
Address input. Connect directly to VCC or ground
22
SCL
I
Serial clock bus. Connect to VCC through a pull-up resistor
23
SDA
I/O
Serial data bus. Connect to VCC through a pull-up resistor
24
VCC
—
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
3.6
V
–0.5
6
V
–0.5
6
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input-output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
Continuous current through GND
–250
Continuous current through VCC
160
Tj(MAX)
Maximum junction temperature
Tstg
Storage temperature
(1)
–65
mA
135
°C
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(2)
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
SCL, SDA, A0, A1, RESET, INT
VI/O
I/O ports voltage
(1)
For P00–P07, P10–P17 configured as outputs
For P00–P07, P10–P17 configured as
inputs(1)
VIH
High-level input voltage
SCL, SDA, A0, A1, RESET, P07–P00, P10–P17
VIL
Low-level input voltage
SCL, SDA, A0, A1, RESET, P07–P00, P10–P17
IOH
High-level output current
P00–P07, P10–P17
IOL
(2)
Low-level output current
P00–P07, P10–P17
4
Low-level output current
INT, SDA
MAX
3.6
V
–0.5
5.5
V
–0.5
3.6
V
–0.5
5.5
V
0.7 × VCC
0.3 × VCC
Tj ≤ 65°C
25
Tj = 85°C
18
Tj = 105°C
9
Tj = 125°C
4.5
Tj = 135°C
3.5
V
mA
mA
6
Tj = 105°C
3
Tj = 125°C
1.8
Tj = 135°C
1.5
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UNIT
V
–10
Tj ≤ 85°C
IOL (2)
MIN
1.65
mA
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
TA
(1)
(2)
Operating free-air temperature
MIN
MAX
UNIT
–40
125
°C
For voltages applied above VCC, an increase in ICC results.
The values shown apply to specific junction temperatures. See the Section 9.2.1.1 section on how to calculate the junction
temperature.
6.4 Thermal Information
TCA9539-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
ψJB
(1)
108.8
°C/W
54
°C/W
62.8
°C/W
Junction-to-top characterization parameter
11.1
°C/W
Junction-to-board characterization parameter
62.3
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
–1.2
VIK
Input diode clamp voltage
II = –18 mA
1.65 V to 3.6 V
VPORR
Power-on reset voltage, VCC
rising
VI = VCC or GND
1.65 V to 3.6 V
VPORF
Power-on reset voltage, VCC
falling
VI = VCC or GND
1.65 V to 3.6 V
0.75
1.65 V
1.2
2.3 V
1.8
3V
2.6
IOH = –8 mA
VOH
P-port high-level output voltage
(2)
IOH = –10 mA
SDA
IOL
P port (3)
INT
II
SCL, SDA
A0, A1, RESET
3.6 V
3.3
1
2.3 V
1.7
3V
2.5
3.6 V
3.2
VOL = 0.5 V
VOL = 0.7 V
MAX UNIT
V
1.2
1.65 V
VOL = 0.4 V
TYP (1)
1.5
V
1
V
V
3
1.65 V to 3.6 V
VOL = 0.4 V
8
mA
10
3
VI = VCC or GND
1.65 V to 3.6 V
±1
±1
µA
IIH
P port
VI = VCC
1.65 V to 3.6 V
1
µA
IIL
P port
VI = GND
1.65 V to 3.6 V
–1
µA
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6.5 Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Operating mode
TEST CONDITIONS
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz, no load
ICC
VI = VCC
Standby mode
IO = 0, I/O = inputs,
fSCL = 0 kHz, no load
VI = GND
Ci
SCL
Cio
(1)
(2)
(3)
VI = VCC or GND
SDA
P port
VIO = VCC or GND
VCC
MIN
TYP (1)
MAX UNIT
3.6 V
10
30
2.7 V
5
19
1.95 V
4
11
3.6 V
1.1
5
2.7 V
1
4.5
1.95 V
0.4
3.5
3.6 V
1.1
13
2.7 V
1
9.5
1.95 V
0.4
6.5
1.65 V to 3.6 V
1.65 V to 3.6 V
3
8
3
9.5
3.7
9.5
µA
pF
pF
All typical values are at nominal supply voltage (1.8 V, 2.5 V, or 3.3 V, VCC) and TA = 25°C.
Each I/O must be externally limited to the maximum allowed IOL, and each octal (P07–P00 and P17–P10) must be limited to a
maximum current of 100 mA, for a device total of 200 mA at Tj ≤ 85°C. See the Section 6.3 table for more information.
The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10) for Tj ≤ 85°C. See the
Section 6.3 table for more information.
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN
MAX
UNIT
0
100
kHz
I2C
BUS—STANDARD MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C
tsds
I2C serial-data setup time
tsdh
I2C
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time
tbuf
I2C
tsts
I2C start or repeated start condition setup
tsth
I2C
tsps
I2C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
3.45
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
3.45
µs
Cb
I2C bus capacitive load
400
pF
MIN
MAX
UNIT
0
400
kHz
clock high time
4
µs
4.7
µs
spike time
50
250
serial-data hold time
ns
0
input fall time
10 pF to 400 pF bus
bus free time between stop and start
start or repeated start condition hold
ns
ns
1000
ns
300
ns
300
ns
4.7
µs
4.7
µs
4
µs
4
µs
I2C BUS—FAST MODE
6
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
tscl
I2C
1.3
tsp
I2C spike time
clock low time
µs
µs
50
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MIN
MAX
UNIT
tsds
I2C serial-data setup time
tsdh
I2C
ticr
I2C input rise time
ticf
I2C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between stop and start
1.3
µs
tsts
I2C start or repeated start condition setup
0.6
µs
tsth
I2C
0.6
µs
tsps
I2C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
0.9
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.9
µs
Cb
I2C bus capacitive load
400
pF
MAX
UNIT
100
serial-data hold time
ns
0
10 pF to 400 pF bus
ns
20
300
ns
20 × (VCC /
5.5 V)
300
ns
20 × (VCC /
5.5 V)
300
ns
start or repeated start condition hold
0.6
µs
6.7 RESET Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-4)
MIN
tW
Reset pulse duration
tREC
Reset recovery time
tRESET
6
ns
0
ns
Time to reset; For VCC =2.3 V – 3.6 V
400
ns
Time to reset; For VCC = 1.65 V – 2.3 V
550
ns
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-2 and Figure
7-3)
PARAMETER
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid; For VCC = 2.3 V – 3.6 V
Output data valid; For VCC = 1.65 V – 2.3
V
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
SCL
INT
SCL
P port
MIN
MAX
UNIT
4
µs
4
µs
200
ns
300
ns
tps
Input data setup time
P port
SCL
150
ns
tph
Input data hold time
P port
SCL
1
µs
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6.9 Typical Characteristics
TA = 25°C (unless otherwise noted)
18
1.75
ICC - Supply Current (µA)
15
Vcc = 3.3 V
Vcc = 3.6 V
ICC - Standby Supply Current (µA)
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
12
9
6
3
0
-40
-25
-10
5
20 35 50 65 80
TA - Temperature (°C)
95
1.5
Figure 6-1. Supply Current vs Temperature for Different Supply
Voltage (VCC)
1
0.75
0.5
0.25
-40
-10
5
20 35 50 65 80
TA - Temperature (°C)
95
110 125
D002
30
-40 °C
25 °C
85 °C
125 °C
40qC
25qC
85qC
125qC
25
IOL - Sink Current (mA)
12
ICC - Supply Current (µA)
-25
Figure 6-2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC)
14
10
8
6
4
20
15
10
5
2
1.6
0
1.8
2
2.2 2.4 2.6 2.8
3
VCC - Supply Voltage (V)
3.2
3.4
3.6
0
0.1
D003
Figure 6-3. Supply Current vs Supply Voltage for Different
Temperature (TA)
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D004
Figure 6-4. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.65 V
35
55
40qC
25qC
85qC
125qC
25
40qC
25qC
85qC
125qC
50
45
IOL - Sink Current (mA)
30
IOL - Sink Current (mA)
Vcc = 3.3 V
Vcc = 3.6 V
1.25
110 125
D001
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
20
15
10
40
35
30
25
20
15
10
5
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
Figure 6-5. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 1.8 V
8
0
0.1
D005
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D006
Figure 6-6. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 2.5 V
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6.9 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
300
70
IOL - Sink Current (mA)
60
50
VOL - Output Low Voltage (mV)
40qC
25qC
85qC
125qC
40
30
20
10
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
50
-25
-10
5
20 35 50 65 80
TA - Temperature (°C)
95
110 125
D010
25
40qC
25qC
85qC
125qC
15
IOH - Source Current (mA)
IOH - Source Current (mA)
100
Figure 6-8. I/O Low Voltage vs Temperature for Different VCC
and IOL
20
10
5
0
40qC
25qC
85qC
125qC
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
0.1
D011
Figure 6-9. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D012
Figure 6-10. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
40
55
40qC
25qC
85qC
125qC
30
40qC
25qC
85qC
125qC
50
IOH - Source Current (mA)
35
IOH - Source Current (mA)
150
D007
Figure 6-7. I/O Sink Current vs Output Low Voltage for Different
Temperature (TA) for VCC = 3.3 V
3.3 V, 1mA
3.3 V, 10 mA
200
0
-40
0
1.8 V, 1 mA
1.8 V, 10 mA
250
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
0.1
D013
Figure 6-11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D014
Figure 6-12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
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6.9 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
15
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
350
12.5
300
Delta ICC (uA)
VCC - VOH - I/O High Voltage (mV)
400
250
200
-25
-10
5
20 35 50 65 80
TA - Temperature (°C)
95
110 125
5
0
-40
-20
D018
Figure 6-13. VCC – VOH Voltage vs Temperature for Different VCC
10
7.5
2.5
150
100
-40
10
1.65 V
1.8 V
1.95 V
2.5 V
2.7 V
3.3 V
3.6 V
0
20
40
60
Temperature (C)
80
100
120
D001
Figure 6-14. Δ ICC vs Temperature for Different VCC (VI = VCC –
0.6 V)
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
DUT
SDA
CL = 50 pF
(see Note A)
SDA Load Configuration
Stop
Condition
(P)
Start
Address
Address
Bit 7
Condition
Bit 6
(MSB)
(S)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tvd(ack)
tsp
tvd(data)
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
Voltage Waveforms
A.
B.
C.
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms
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VCC
RL = 4.7 kΩ
DUT
INT
CL = 100 pF
(see Note A)
Interrupt Load Configuration
1
SCL
2
3
4
5
6
7
8
Data From Port
Target Address
SDA
S
1
1
1
Start
Condition
0
1 A1 A0 1
R/W
Data 1
A
Data From Port
Data 4
A
NACK From
Stop
Controller Condition
ACK From
Controller
ACK From
Target
NA P
Read From
Port
Data Into
Port
Data 2
Data 3
tph
Data 4
Data 5
tps
INT
tiv
tir
0.7 × VCC
INT
SCL
0.3 × VCC
0.7 × VCC
R/W
tiv
0.3 × VCC
tir
Data Into
0.7 × VCC
Port (Pn)
0.3 × VCC
A.
B.
C.
A
0.7 × VCC
INT
0.3 × VCC
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 Hz, ZO = 50 Ω, tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Figure 7-2. Interrupt Load Circuit and Voltage Waveforms
12
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A.
B.
C.
D.
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CL includes probe and jig capacitance.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-3. P-Port Load Circuit and Voltage Waveforms
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V CC
DUT
500
Pn
R L = 1 kΩ
DUT
SDA
2 × V CC
C L = 50 pF
(see Note 1)
500 Ω
C L = 50 pF
(see Note 1)
SDA Load Configuration
P-Port Load Configuration
Start
SCL
ACK or Read Cycle
SDA
0.3
V CC
t RESET
RESET
V CC/2
t REC
tw
Px
(see Note 4)
A.
B.
C.
D.
E.
-VCC /2
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Figure 7-4. Reset Load Circuits and Voltage Waveforms
14
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8 Detailed Description
8.1 Overview
The TCA9539-Q1 is a 16-bit I/O expander for the two-line bidirectional bus (I2C) designed for 1.65 V to 3.6 V,
VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C
interface, serial clock (SCL) and serial data (SDA).
The TCA9539-Q1 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and
Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs.
The system controller can enable the I/Os as either inputs or outputs by writing to the configuration register
bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the
Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system
controller.
The system controller can reset the TCA9539-Q1 in the event of a time-out or other improper operation by
asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the
I2C-SMBus state machine. Asserting RESET causes the same reset-initialization to occur without depowering
the part.
The TCA9539-Q1 open-drain interrupt ( INT) output is activated when any input state differs from its
corresponding Input Port register state and is used to indicate to the system controller that an input state has
changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA9539-Q1 can remain a simple target device.
The TCA9539-Q1 is similar to the TCA9555, except for the removal of the internal I/O pull-up resistor, which
greatly reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different
address range. The TCA9539-Q1 is similar to the PCA9539 with lower voltage support (down to VCC = 1.65 V),
and also improved power-on reset circuitry for different application scenarios.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices
to share the same I2C bus or SMBus.
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8.2 Functional Block Diagram
TCA9539-Q1
INT
A0
A1
SCL
SDA
1
Interrupt
Logic
LP Filter
21
2
P07-P00
22
23
I2C Bus
Control
Input
Filter
Shift
Register
16 Bits
I/O
Port
P17-P10
RESET
VCC
GND
Write Pulse
3
24
12
Power-On
Reset
Read Pulse
Copyright © 2016, Texas Instruments Incorporated
Pin numbers shown are for PW package.
All I/Os are set to inputs at reset.
Figure 8-1. Logic Diagram (Positive Logic)
16
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Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
D
Q
FF
Write Configuration
Pulse
VCC
Q1
D
CLK Q
Q
FF
I/O Pin
CLK Q
Write Pulse
Output Port
Register
Q2
Input Port
Register
D
GND
Q
Input Port
Register Data
FF
Read Pulse
CLK Q
To INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
Copyright © 2016, Texas Instruments Incorporated
At power-on reset, all registers return to default values.
Figure 8-2. Simplified Schematic of P-Port I/Os
8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register.
In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
8.3.2 RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA9539-Q1 registers and
I2C-SMBus state machine are held in their default states until RESET is once again high. This input requires a
pull-up resistor to VCC, if no active connection is used.
8.3.3 Interrupt ( INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
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acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before
the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short)
because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and
is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pull-up resistor to VCC.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9539-Q1 in a reset condition
until VCC has reached VPORR. At that point, the reset condition is released and the TCA9539-Q1 registers and
I2C-SMBus state machine initialize to their default states. After that, VCC must be lowered to VPORF and then
back up to the operating voltage for a power-reset cycle. See Figure 8-3.
8.5 Programming
8.5.1 I2C Interface
The TCA9539-Q1 has a standard bidirectional I2C interface that is controlled by a controller device in order
to be configured or read the status of this device. Each target on the I2C bus has a specific device address
to differentiate between other target devices that are on the same I2C bus. Many target devices require
configuration upon startup to set the behavior of the device. This is typically done when the controller accesses
internal register maps of the target, which have unique register addresses. A device can have one or multiple
registers where data is stored, written, or read. For more information see Understanding the I2C Bus, SLVA704.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. For further details, see I2C Pull-up Resistor Calculation, SLVA689. Data transfer
may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a
STOP condition. See Table 8-1.
Figure 8-3 and Figure 8-4 show the general procedure for a controller to access a target device:
1. If a controller wants to send data to a target:
• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition.
2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter.
18
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•
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Controller-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 8-3. Definition of Start and Stop Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 8-4. Bit Transfer
Table 8-1 shows the interface definition.
Table 8-1. Interface Definition
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C target address
H
H
H
L
H
A1
A0
R/ W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
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8.6 Register Maps
8.6.1 Device Address
Figure 8-5 shows the address byte of the TCA9539-Q1.
R/W
Target Address
1
1
1
0
Fixed
1
A1 A0
Programmable
Figure 8-5. TCA9539-Q1 Address
Table 8-2 shows the address reference of the TCA9539-Q1.
Table 8-2. Address Reference
INPUTS
A1
I2C BUS TARGET ADDRESS
A0
L
L
116 (decimal), 74 (hexadecimal)
L
H
117 (decimal), 75 (hexadecimal)
H
L
118 (decimal), 76 (hexadecimal)
H
H
119 (decimal), 77 (hexadecimal)
The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.6.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus controller sends a command byte shown
in Table 8-3 that is stored in the control register in the TCA9539-Q1. Three bits of this data byte state the
operation (read or write) and the internal register (input, output, Polarity Inversion or Configuration) that is
affected. This register can be written or read through the I2C bus. The command byte is sent only during a write
transmission.
When a command byte has been sent, the register pair that was addressed continues to be accessed by reads
until a new command byte has been sent. Figure 8-6 shows the control register bits.
0
0
0
0
0
B2
B1
B0
Figure 8-6. Control Register Bits
Table 8-3. Command Byte
CONTROL REGISTER BITS
20
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0x00
Input Port 0
Read byte
xxxx xxxx
0
0
1
0x01
Input Port 1
Read byte
xxxx xxxx
0
1
0
0x02
Output Port 0
Read-write byte
1111 1111
0
1
1
0x03
Output Port 1
Read-write byte
1111 1111
1
0
0
0x04
Polarity Inversion Port 0
Read-write byte
0000 0000
1
0
1
0x05
Polarity Inversion Port 1
Read-write byte
0000 0000
1
1
0
0x06
Configuration Port 0
Read-write byte
1111 1111
1
1
1
0x07
Configuration Port 1
Read-write byte
1111 1111
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8.6.3 Register Descriptions
The Input Port registers (registers 0 and 1) shown in Table 8-4 reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on
read operation. Writes to these registers have no effect. The default value, X, is determined by the externally
applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next.
Table 8-4. Registers 0 And 1 (Input Port Registers)
Bit
I0.7
Default
Bit
Default
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
X
X
X
X
X
X
X
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) shown in Table 8-5 show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not
the actual pin value.
Table 8-5. Registers 2 And 3 (Output Port Registers)
Bit
O0.7
Default
Bit
Default
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
1
1
1
1
1
1
1
1
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 4 and 5) shown in Table 8-6 allow Polarity Inversion of pins defined
as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port
pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original
polarity is retained.
Table 8-6. Registers 4 And 5 (Polarity Inversion Registers)
Bit
Default
Bit
Default
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
0
0
0
0
0
0
0
0
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) shown in Table 8-7 configure the directions of the I/O pins. If a bit
in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver.
If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 8-7. Registers 6 And 7 (Configuration Registers)
Bit
Default
Bit
Default
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
1
1
1
1
1
1
1
1
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
1
1
1
1
1
1
1
1
8.6.3.1 Bus Transactions
Data is exchanged between the controller and the TCA9539-Q1 through write and read commands, and this is
accomplished by reading from or writing to registers in the target device.
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Registers are locations in the memory of the target which contain information, whether it be the configuration
information or some sampled data to send back to the controller. The controller must write information to these
registers in order to instruct the target device to perform a task.
8.6.3.1.1 Writes
To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as
well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the
controller then sends the register address of the register to which it wishes to write. The target acknowledges
again, letting the controller know it is ready. After this, the controller starts sending the register data to the target
until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller
terminates the transmission with a STOP condition.
See the Section 8.6.2 section to see list of the TCA9539-Q1s internal registers and a description of each one.
Figure 8-7 shows an example of writing a single byte to a target register.
Controller controls SDA line
Target controls SDA line
Write to one register in a device
Register Address N (8 bits)
Device (Target) Address (7 bits)
S
1
1
1
0
1
A1
START
A0
0
R/W=0
A
B7
B6
B5
B4
B3
B2
Data Byte to Register N (8 bits)
B1
B0
ACK
A
D7
D6
D5
D4
D3
D2
D1
D0
ACK
A
ACK
P
STOP
Figure 8-7. Write to Register
Figure 8-9 shows the Write to the Polarity Inversion Register.
Controller controls SDA line
Target controls SDA line
Register Address 0x01 (8 bits)
Device (Target) Address (7 bits)
S
1
1
1
0
1
A1
START
A0
0
R/W=0
A
0
0
0
0
ACK
0
1
Data Byte to Register 0x01 (8 bits)
0
0
A
D7
D6
D5
ACK
D4
D3
D2
D1
D0
A
ACK
P
STOP
Figure 8-8. Write to the Polarity Inversion Register
Figure 8-9 shows the Write to Output Port Registers
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SCL
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2
3
4
5
6
7
8
9
Command Byte
Target Address
SDA
S
1
1
1
0
1
A1 A0
0
A
0
0
0
0
0
0
Data to Port 0
1
0
A 0.7
R/W Acknowledge
From Target
Start Condition
Data to Port 1
0.0
Data 0
A 1.7
Acknowledge
From Target
1.0
Data 1
A
P
Acknowledge
From Target
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 8-9. Write to Output Port Registers
8.6.3.1.2 Reads
Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target,
the controller must first instruct the target which register it wishes to read from. This is done by the controller
starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to
0 (signifying a write), followed by the register address it wishes to read from. When the target acknowledges this
register address, the controller sends a START condition again, followed by the target address with the R/ W
bit set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases
the SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller
becomes the controller-receiver, and the target becomes the target-transmitter.
The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit
data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it
is ready for more data. When the controller has received the number of bytes it is expecting, it sends a NACK,
signaling to the target to halt communications and release the bus. The controller follows this up with a STOP
condition.
If a read is requested by the controller after a POR without first setting the command byte via a write, the device
NACKs until a command byte-register address is set as described above.
See the Section 8.6.2 section to see list of the TCA9539-Q1s internal registers and a description of each one.
Figure 8-10 shows an example of reading a single byte from a target register.
Controller controls SDA line
Target controls SDA line
Read from one register in a device
Device (Target) Address (7 bits)
S
1
START
1
1
0
1
A1
Register Address N (8 bits)
A0
0
R/W=0
A
B7
B6
ACK
B5
B4
B3
B2
Data Byte from Register N (8 bits)
Device (Target) Address (7 bits)
B1
B0
A
ACK
Sr
1
1
1
0
1
A1
Repeated START
A0
1
R/W=1
A
ACK
D7
D6
D5
D4
D3
D2
D1
D0
NA
NACK
P
STOP
Figure 8-10. Read from Register
When a restart occurs after a single write request to a register, the requested register is used for the read
request. Note that when reading multiple bytes of data. Data is clocked into the register on the rising edge of the
ACK clock pulse before data is sent. The internal register value is also changed to the other register of the pair
on the rising edge of the ACK clock pulse before data is sent. After the first byte is read, additional bytes may be
read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read,
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the next byte read is Input Port 0. If a restart occurs during a read, the data is lost because the internal register
already has been changed to the next register in the pair.
There is no limitation on the number of data bytes received in one read transmission, but when the final byte
is received, the bus controller must not acknowledge the data. Figure 8-11 and Figure 8-12 show two different
scenarios of Read Input Port Register.
1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
1
1
1
0
1
A1
1
A0
A
7
R/W
6
5
4
3
I1.x
2
1
0
A
7
6
5
4
3
Acknowledge
From Controller
Acknowledge
From Target
I0.x
2
1
0
A
7
6
5
4
3
I1.x
2
1
0
A
7
6
5
4
3
2
Acknowledge
From Controller
Acknowledge
From Controller
1
0
1
P
No Acknowledge
From Controller
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
tiv
tir
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is
valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).
This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual
data transfer from the P port (see the Section 8.6.3.1.2 section for these details).
Figure 8-11. Read Input Port Register, Scenario 1
1
SCL
2
3
4
5
6
7
8
9
10.x
SDA
S
1
1
1
0
1
A1
A0
1
R/W
A
00
Acknowledge
From Target
11.x
A
10
10.x
A
11.x
03
A
Acknowledge
From Controller
Acknowledge
From Controller
tps
tph
11
1
P
Acknowledge
From Controller
No Acknowledge
From Controller
t ph
Read From Port 0
Data Into Port 0
Data 00
Data 01
t iv
Data 02
Data 03
tph
Read From Port 1
Data 10
Data Into Port 1
Data 11
Data 12
tir
INT
tiv
t iv
t ir
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is
valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).
This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual
data transfer from the P port (see the Section 8.6.3.1.2 section for these details).
Figure 8-12. Read Input Port Register, Scenario 2
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Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9539-Q1 has this device connected as a target to an I2C controller (processor), and the
I2C bus may contain any number of other target devices. The TCA9539-Q1 is typically in a remote location from
the controller, placed close to the GPIOs to which the controller needs to monitor or control.
IO Expanders such as the TCA9539-Q1 are typically used for controlling LEDs (for feedback or status lights),
controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.
9.2 Typical Application
Figure 9-1 shows an application in which the TCA9539-Q1 can be used.
Subsystem 1
(e.g., Temperature
Sensor)
INT
VCC
10 kΩ
VCC
10 kΩ
10 kΩ
SCL
Controller SDA
INT
GND
24
10 kΩ
22
23
2 kΩ
VCC
SCL
SDA
1
3 INT
RESET
4
P00
5
P01
6
P02
7
P03
8
P04
9
P05
Subsystem 2
(e.g., Counter)
100 kΩ
100 kΩ
100 kΩ
RESET
A
ENABLE
B
TCA9539-Q1
P06
P07
P10
P11
2
A1
P12
P13
21
A0
P14
P15
P16
GND P17
12
10
11
13
14
15
16
17
18
19
20
VCC
Controlled Switch
(e.g., CBT Device)
ALARM
Keypad
Subsystem 3
(e.g., Alarm)
Device address is configured as 1110100 for this example.
P00, P02, and P03 are configured as outputs.
P01 and P04 to P17 are configured as inputs.
Pin numbers shown are for the PW package.
Figure 9-1. Application Schematic
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9.2.1 Design Requirements
9.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with the TCA9539-Q1, it is important that the Section 6.3 not be violated. Many of the
parameters of this device are rated based on junction temperature, so junction temperature must be calculated
in order to verify that safe operation of the device is met. The basic equation for junction temperature is shown in
Equation 1.
Tj = TA + (qJA ´ Pd )
(1)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Section 6.4
table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
(
Pd » ICC _ STATIC ´ VCC
) + å Pd _ PORT _ L + å Pd _ PORT _ H
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high,
or outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied
by the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3
to calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd _ PORT _ L = (IOL ´ VOL )
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
(
)
Pd _ PORT _H = IOH ´ (VCC - VOH )
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
9.2.1.2 Minimizing ICC When I/Os Control LEDs
When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 9-1).
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in the Section 6.5 table show how ICC increases as VIN becomes lower than VCC. For battery-powered
applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the LED is off, to
minimize current consumption.
Figure 9-2 shows a high-value resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional
supply-current consumption when the LED is off.
Take care to make sure that the recommended maximum IOL through the ports not be violated based upon
junction temperature. See the Section 6.3 for more information.
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VCC
LED
100 kΩ
VCC
Pn
Figure 9-2. High-Value Resistor In Parallel With LED
3.3 V
VCC
5V
LED
Pn
Figure 9-3. Device Supplied By Lower Voltage
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all targets on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 5.
Rp(min) =
VCC - VOL(max)
IOL
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb as shown in Equation 6.
Rp(max) =
tr
0.8473 ´ Cb
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9539-Q1, Ci for
SCL or Cio for SDA, the capacitance of wires, connections, traces, and the capacitance of additional targets on
the bus.
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9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC 2 V
Figure 9-5. Minimum Pull-Up Resistance (Rp(min))
vs Pull-Up Reference Voltage (VCC)
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9 Power Supply Recommendations
9.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9539-Q1 can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
The voltage waveform for a power-on reset is shown in Figure 9-1.
VCC
Ramp-Up
Ramp-Down
VCC_TRR
VCC drops below VPORF – 50 mV
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 9-1. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC
Table 9-1 specifies the performance of the power-on reset feature for TCA9539-Q1.
Table 9-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall rate
See Figure 9-1
0.1
ms
VCC_RT
Rise rate
See Figure 9-1
0.1
ms
VCC_TRR
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or
when VCC drops to GND)
See Figure 9-1
2
μs
VCC_GH
The level (referenced to VCC) that VCC can glitch down to, but
not cause a functional disruption when VCC_GW
See Figure 9-2
VCC_MV
The minimum voltage that VCC can glitch down to without
causing a reset (VCC_GH must not be violated)
See Figure 9-2
VCC_GW
Glitch width that does not cause a functional disruption
See Figure 9-2
VPORF
Voltage trip point of POR on falling VCC
VPORR
Voltage trip point of POR on rising VCC
(1)
1.2
1.5
V
10
0.75
V
1
1.2
μs
V
1.5
V
TA = –40°C to +125°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 9-2 and Table 9-1 provide more
information on how to measure these specifications.
VCC
VCC_GH
VCC_MV
Time
VCC_GW
Figure 9-2. Glitch Width, Glitch Height, and Minimum Glitch Voltage
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VPOR is critical to the power-on reset. VPOR R is the voltage level at which the reset condition is released and all
the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs
based on the VCC being lowered to or from 0. Figure 9-3 and Table 9-1 provide more details on this specification.
VCC
VPORR
VPORF
Time
POR
Time
Figure 9-3. VPOR
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10 Layout
10.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9539-Q1, common PCB layout practices must be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power
in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the TCA9539-Q1 as possible. These best practices are shown in Figure
10-1.
For the layout example provided in Figure 10-1, it would be possible to fabricate a PCB with only 2 layers
by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground
(GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB,
it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and
ground, vias are placed directly next to the surface mount component pad which must attach to VCC or GND
and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when
a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in
Figure 10-1.
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10.2 Layout Example
LEGEND
Partial view of plane
(inner layer)
Via to power plane
Via to GND plane
C
To processor
VC
By-pass/de-coupling
capacitors
C
VC
23
To I/Os
To I/Os
22
G
ND
Figure 10-1. TCA9539-Q1 Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Understanding the I2C Bus, SLVA704
• I2C Pull-up Resistor Calculation, SLVA689
• Introduction to Logic, SLVA700
• Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695
• I2C Bus Pull-Up Resistor Calculation, SLVA689
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCA9539QPWRQ1
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TCA539Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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