TCAN1044-Q1, TCAN1044V-Q1
SLLSF17B – AUGUST 2019 – REVISED OCTOBER 2021
TCAN1044V-Q1 Automotive Fault-Protected CAN FD Transceiver
With 1.8-V I/O Support
1 Features
3 Description
•
The TCAN1044-Q1 is a high speed controller area
network (CAN) transceiver that meets the physical
layer requirements of the ISO 11898-2:2016 highspeed CAN specification.
•
•
•
•
•
•
•
•
•
•
AEC-Q100: Qualified for automotive applications
– Temperature grade 1: –40°C to 125°C TA
Meets the requirements of ISO 11898-2:2016 and
ISO 11898-5:2007 physical layer standards
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Support of classical CAN and optimized CAN FD
performance at 2, 5, and 8 Mbps
– Short and symmetrical propagation delays for
enhanced timing margin
– Higher data rates in loaded CAN networks
I/O voltage range supports 1.7 V to 5.5 V
– Support for 1.8-V, 2.5-V, 3.3-V, and 5-V
applications
Protection features:
– Bus fault protection: ±58 V
– Undervoltage protection
– TXD-dominant time-out (DTO)
• Data rates down to 9.2 kbps
– Thermal-shutdown protection (TSD)
Operating modes:
– Normal mode
– Low power standby mode supporting remote
wake-up request
Optimized behavior when unpowered
– Bus and logic pins are high impedance (no load
to operating bus or application)
– Hot-plug capable: power up/down glitch free
operation on bus and RXD output
Junction temperatures from: –40°C to 150°C
Receiver common mode input voltage: ±12 V
Available in SOIC (8), SOT23 (8) packages
(2.9 mm x 1.60 mm) and leadless VSON (8)
packages (3.0 mm x 3.0 mm) with improved
automated optical inspection (AOI) capability
The TCAN1044-Q1 transceiver supports both
classical CAN and CAN FD networks up to 8
megabits per second (Mbps). The TCAN1044-Q1
includes internal logic level translation via the VIO
terminal to allow for interfacing the transceiver I/Os
directly to 1.8 V, 2.5 V, 3.3 V, or 5 V logic I/Os. The
transceiver supports a low-power standby mode and
wake over CAN compliant to the ISO 11898-2:2016
defined wake-up pattern (WUP). The TCAN1044-Q1
transceiver also includes protection and diagnostic
features supporting thermal-shutdown (TSD), TXDdominant time-out (DTO), supply undervoltage
detection, and bus fault protection up to
±58 V.
Device Information
PART NUMBER
TCAN1044-Q1
TCAN1044V-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOT (DDF) (8)
2.90 mm x 1.60 mm
VSON (DRB) (8)
3.00 mm x 3.00 mm
SOIC (D) (8)
4.90 mm x 3.91 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
Automotive and Transportation
– Body control modules
– Automotive gateway
– Advanced driver assistance system (ADAS)
– Infotainment
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN1044-Q1, TCAN1044V-Q1
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SLLSF17B – AUGUST 2019 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 ESD Ratings............................................................... 4
6.4 Recommended Operating Conditions.........................4
6.5 Thermal Characteristics.............................................. 5
6.6 Supply Characteristics................................................ 5
6.7 Dissipation Ratings..................................................... 6
6.8 Electrical Characteristics.............................................6
6.9 Switching Characteristics............................................8
6.10 Typical Characteristics............................................ 10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................20
9 Application and Implementation.................................. 23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
9.3 System Examples..................................................... 26
10 Power Supply Recommendations..............................26
11 Device and Documentation Support..........................28
11.1 Receiving Notification of Documentation Updates.. 28
11.2 Support Resources................................................. 28
11.3 Trademarks............................................................. 28
11.4 Electrostatic Discharge Caution.............................. 28
11.5 Glossary.................................................................. 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2019) to Revision B (October 2021)
Page
• Added Feature "Functional Safety-Capable"...................................................................................................... 1
• Changed the Simplified Schematic image.......................................................................................................... 1
• Changed Figure 9-2 .........................................................................................................................................24
Changes from Revision * (August 2019) to Revision A (December 2019)
Page
• First public release of the data sheet .................................................................................................................1
• Added SAE j2962-2 ESD....................................................................................................................................4
• Changed footnote to Tested according to IEC 62228-3:2019 CAN Transceivers, Section 6.3; standard pulses
parameters defined in ISO 7637-2 (2011)...........................................................................................................4
2
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5 Pin Configuration and Functions
TX D
1
8
STB
TX D
1
8
STB
GND
2
7
CA NH
GND
2
7
CA NH
VCC
3
6
CA NL
VCC
3
6
CA NL
RX D
4
5
NC, VIO
RX D
4
5
NC, VIO
No t to scale
No t to scale
DDF Package TCAN1044(V)-Q1, 8-Pin SOT, Top
View
TXD
1
GND
2
VCC
3
RXD
4
D Package TCAN1044(V)-Q1, 8-Pin SOIC, Top View
Thermal
Pad
8
STB
7
CANH
6
CANL
5
NC,VIO
Not to scale
DRB Package TCAN1044(V)-Q1, 8-Pin VSON , Top View
Pin Functions
Pins
Name
No.
TXD
1
GND
2
VCC
3
RXD
4
NC
VIO
5
Type
Description
Digital Input CAN transmit data input
GND
Ground connection
Supply
5-V supply voltage
Digital Output CAN receive data output, tri-state when powered off
—
No Connect (not internally connected); Devices without VIO
Supply
I/O supply voltage
CANL
6
Bus IO
Low-level CAN bus input/output line
CANH
7
Bus IO
High-level CAN bus input/output line
STB
8
Thermal Pad (VSON only)
Digital Input Standby input for mode control, integrated pull up
—
Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB)
ground plane for thermal relief
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
VCC
Supply voltage
–0.3
6
V
VIO
Supply voltage I/O level shifter
–0.3
6
V
VBUS
CAN Bus IO voltage CANH and CANL
–58
58
V
VDIFF
Max differential voltage between CANH and CANL
–45
45
V
VLogic_Input
Logic input terminal voltage
–0.3
6
V
VRXD
RXD output terminal voltage range
–0.3
6
V
IO(RXD)
RXD output current
–8
8
mA
TJ
Operating virtual junction temperature range
–40
150
°C
TSTG
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, except differential IO bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
Human-body model (HBM), per AEC Q100-002(1)
VESD
Electrostatic discharge
VALUE
UNIT
HBM classification level 3A for
all pins
±3000
V
HBM classification level 3B for
global pins CANH & CANL
±10000
V
±750
V
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings
System Level Electro-Static Discharge (ESD)(3)
VESD
CAN bus terminals (CANH, CANL) to GND
ISO 7637 ISO Pulse Transients(1)
VTran
CAN bus terminals (CANH, CANL)
ISO 7637 Slow transients pulse(2)
(1)
(2)
(3)
CAN bus terminals (CANH, CANL) to GND
VALUE
UNIT
SAE J2962-2 per ISO 10650
Powered Contact Discharge
±8000
V
SAE J2962-2 per ISO 10650
Powered Air Discharge
±15000
V
Pulse 1
–100
V
Pulse 2a
75
V
Pulse 3a
–150
V
Pulse 3b
100
V
DCC slow transient pulse
±85
V
Tested according to IEC 62228-3:2019 CAN Transceivers, Section 6.3; standard pulses parameters defined in ISO 7637-2 (2011)
Tested according to ISO 7637-3 (2017); Electrical transient transmission by capacitive and inductive coupling via lines other than
supply lines
Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed
by OEM approved independent 3rd party, EMC report available upon request.
6.4 Recommended Operating Conditions
4
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIO
Supply voltage for I/O level shifter
1.7
IOH(RXD)
RXD terminal high level output current
–2
IOL(RXD)
RXD terminal low level output current
TA
Operating ambient temperature
–40
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5.5
UNIT
V
V
mA
2
mA
125
℃
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6.5 Thermal Characteristics
TCAN1044x-Q1
THERMAL METRIC(1)
D (SOIC)
DDF (SOT)
UNIT
DRB (VSON)
RΘJA
Junction-to-ambient thermal resistance
128.1
119.9
49.9
℃/W
RΘJC(top)
Junction-to-case (top) thermal resistance
68.3
61.8
58.2
℃/W
RΘJB
Junction-to-board thermal resistance
71.6
39.7
23.9
℃/W
ΨJT
Junction-to-top characterization parameter
19.7
2.1
1.7
℃/W
ΨJB
Junction-to-board characterization parameter
70.8
39.5
23.8
℃/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
-
–
6.4
℃/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Supply Characteristics
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TYP
MAX
TXD = 0 V, STB = 0 V, RL = 60 Ω, CL =
open
See Figure 7-1
TEST CONDITIONS
45
70
mA
TXD = 0 V, STB = 0 V, RL = 50 Ω, CL =
open
See Figure 7-1
49
80
mA
Recessive
TXD = VCC, STB = 0 V, RL = 50 Ω, CL =
open
See Figure 7-1
4.5
7.5
mA
Dominant with
bus fault
TXD = 0 V, STB = 0 V, CANH = CANL =
±25 V, RL = open, CL = open
See Figure 7-1
130
mA
1
µA
14.5
µA
Dominant
ICC
Supply current
Normal mode
MIN
UNIT
ICC
Supply current
Standby mode
Devices with VIO
TXD = STB = VIO, RL = 50 Ω, CL = open
See Figure 7-1
ICC
Supply current
Standby mode
Devices without VIO
TXD = STB = VCC, RL = 50 Ω, CL = open
See Figure 7-1
IIO
I/O supply current
Normal mode
Dominant
TXD = 0 V, STB= 0 V
RXD floating
125
300
µA
IIO
I/O supply current
Normal mode
Recessive
TXD = 0 V, STB = 0 V
RXD floating
25
48
µA
IIO
I/O supply current
Standby mode
TXD = 0 V, STB = VIO
RXD floating
8.5
13.5
µA
UVVCC
Rising under voltage detection on VCC for protected mode
4.2
4.4
V
UVVCC
Falling under voltage detection on VCC for protected mode
4
4.25
V
UVVIO
Rising under voltage detection on VIO (Devices with VIO)
1.56
1.65
V
UVVIO
Falling under voltage detection on VIO (Devices with VIO)
1.51
1.59
V
0.2
3.5
1.4
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6.7 Dissipation Ratings
PARAMETER
TEST CONDITIONS
Average power dissipation
Normal mode
PD
TTSD
Thermal shutdown temperature
TTSD_HYS
Thermal shutdown hysteresis
MIN
TYP
MAX
UNIT
VCC = 5 V, VIO = 1.8 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle square
wave, CL_RXD = 15 pF
110
mW
VCC = 5 V, VIO = 3.3 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle square
wave, CL_RXD = 15 pF
110
mW
VCC = 5 V, VIO = 5 V, TJ= 27°C, RL = 60Ω, TXD
input = 250 kHz 50% duty cycle square wave,
CL_RXD = 15 pF
110
mW
VCC = 5.5 V, VIO = 1.8 V, TA= 125°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
120
mW
VCC = 5.5 V, VIO = 3.3 V, TA= 125°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
120
mW
VCC = 5.5 V, VIO = 5 V, TA= 125°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
120
mW
192
°C
10
6.8 Electrical Characteristics
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TXD = 0 V, STB = 0 V , 50 Ω ≤ RL ≤ 65 Ω,
CL = open, RCM = open
See Figure 7-2 and Figure 8-3,
2.75
4.5
V
0.5
2.25
V
3
V
Driver Electrical Characteristics
VO(DOM)
Dominant output voltage
Normal mode
CANH
CANL
TXD = VIO, STB = 0 V , RL = open (no
load), RCM = open
See Figure 7-2 and Figure 8-3
VO(REC)
Recessive output voltage
Normal mode
VSYM
Driver symmetry
(VO(CANH) + VO(CANL))/VCC
STB = 0 V , RL = 60 Ω, CSPLIT = 4.7 nF,
CL = open, RCM = open, TXD = 250 kHz, 1
MHz, 2.5 MHz
See Figure 7-2 and Figure 9-2
VSYM_DC
DC output symmetry
(VCC - VO(CANH) - VO(CANL))
STB = 0 V , RL = 60 Ω, CL = open
See Figure 7-2 and Figure 8-3
VOD(DOM)
VOD(REC)
Differential output voltage
Normal mode
Dominant
Differential output voltage
Normal mode
Recessive
CANH and CANL
CANH - CANL
CANH - CANL
VO(STB)
CANL
1.1
V/V
–400
400
mV
TXD = 0 V, STB = 0 V , 50 Ω ≤ RL ≤ 65 Ω,
CL = open
See Figure 7-2 and Figure 8-3
1.5
3
V
TXD = 0 V, STB = 0 V , 45 Ω ≤ RL ≤ 70 Ω,
CL = open
See Figure 7-2 and Figure 8-3
1.4
3.3
V
TXD = 0 V, STB = 0 V , RL = 2240 Ω, CL =
open
See Figure 7-2 and Figure 8-3
1.5
5
V
TXD = VIO, STB = 0 V , RL = 60 Ω, CL =
open
See Figure 7-2 and Figure 8-3
–120
12
mV
TXD = VIO, STB = 0 V , RL = open, CL =
open
See Figure 7-2 and Figure 8-3
–50
50
mV
-0.1
0.1
V
-0.1
0.1
V
-0.2
0.2
V
STB = VIO , RL = open (no load)
See Figure 7-2 and Figure 8-3
CANH - CANL
6
0.5 VCC
0.9
CANH
Bus output voltage
Standby mode
2
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
IOS(SS_DOM)
IOS(SS_REC)
Short-circuit steady-state output current,
dominant
Normal mode
Short-circuit steady-state output current,
recessive
Normal mode
TEST CONDITIONS
MIN
STB = 0 V , V(CANH) = -15 V to 40 V, CANL
= open, TXD = 0 V
See Figure 7-7 and Figure 8-3
–115
TYP
MAX UNIT
mA
STB = 0 V , V(CAN_L) = -15 V to 40 V,
CANH = open, TXD = 0 V
See Figure 7-7 and Figure 8-3
115
mA
STB = 0 V , –27 V ≤ VBUS ≤ 32 V, where
VBUS = CANH = CANL, TXD = VIO
See Figure 7-7 and Figure 8-3
–5
5
mA
Receiver Electrical Characteristics
VIT
Input threshold voltage
Normal mode
STB = 0 V , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
500
900
mV
VIT(STB)
Input threshold
Standby mode
STB = VIO , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
400
1150
mV
VDOM
Dominant state differential input voltage range
Normal mode
STB = 0 V , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
0.9
9
V
VREC
Recessive state differential input voltage range
Normal mode
STB = 0 V , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
-4
0.5
V
VDOM(STB)
Dominant state differential input voltage range
Standby mode
STB = VIO , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
1.15
9
V
VREC(STB)
Recessive state differential input voltage range
Standby mode
STB = VIO , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
-4
0.4
V
VHYS
Hysteresis voltage for input threshold
Normal mode
STB = 0 V , -12 V ≤ VCM ≤ 12 V
See Figure 7-3, Table 7-1, and Table 8-6
VCM
Common mode range
Normal and standby modes
See Figure 7-3 and Table 8-6 Table 8-6
ILKG(IOFF)
Unpowered bus input leakage current
CANH = CANL = 5 V, VCC = VIO = GND
CI
Input capacitance to ground (CANH or CANL)
CID
Differential input capacitance
RID
Differential input resistance
RIN
Single ended input resistance
(CANH or CANL)
RIN(M)
Input resistance matching
[1 – (RIN(CANH) / RIN(CANL))] × 100 %
100
–12
TXD = VIO(1)
TXD = VIO(1), STB = 0 V , -12 V ≤ VCM ≤
12 V
V(CAN_H) = V(CAN_L) = 5 V
mV
12
V
5
µA
20
pF
10
pF
40
90
kΩ
20
45
kΩ
–1
1
%
TXD Terminal (CAN Transmit Data Input)
VIH
High-level input voltage
Devices without VIO
0.7 VCC
VIH
High-level input voltage
Devices with VIO
0.7 VIO
V
VIL
Low-level input voltage
Devices without VIO
VIL
Low-level input voltage
Devices with VIO
0.3 VIO
V
IIH
High-level input leakage current
TXD = VCC = VIO = 5.5 V
–2.5
0
1
µA
IIL
Low-level input leakage current
TXD = 0 V, VCC = VIO = 5.5 V
–200
-100
–20
µA
ILKG(OFF)
Unpowered leakage current
TXD = 5.5 V, VCC = VIO = 0 V
–1
0
1
µA
CI
Input Capacitance
VIN = 0.4×sin(2×π×2×106×t)+2.5 V
V
0.3 VCC
5
V
pF
RXD Terminal (CAN Receive Data Output)
VOH
High-level output voltage
IO = –2 mA, Devices without VIO
See Figure 7-3
0.8 VCC
V
VOH
High-level output voltage
IO = –2 mA, Devices with VIO
See Figure 7-3
0.8 VIO
V
VOL
Low-level output voltage
IO = 2 mA, Devices without VIO
See Figure 7-3
0.2 VCC
V
VOL
Low-level output voltage
IO = –2 mA, Devices with VIO
See Figure 7-3
0.2 VIO
V
ILKG(OFF)
Unpowered leakage current
RXD = 5.5 V, VCC = VIO = 0 V
1
µA
–1
0
STB Terminal (Standby Mode Input)
VIH
High-level input voltage
Devices without VIO
0.7 VCC
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH
High-level input voltage
Devices with VIO
VIL
Low-level input voltage
Devices without VIO
0.3 VCC
VIL
Low-level input voltage
Devices with VIO
0.3 VIO
V
IIH
High-level input leakage current
VCC = VIO = STB = 5.5 V
2
µA
IIL
Low-level input leakage current
VCC = VIO = 5.5 V, STB = 0 V
–20
–2
µA
ILKG(OFF)
Unpowered leakage current
STB = 5.5V, VCC = VIO = 0 V
–1
1
µA
(1)
0.7 VIO
V
–2
0
V
VIO = VCC in non-V variants of device
6.9 Switching Characteristics
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device Switching Characteristics
tPROP(LOOP1)
Total loop delay, driver input (TXD) to receiver
output (RXD), recessive to dominant
Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
VIO = 2.8 V to 5.5 V
See Figure 7-4
125
210
ns
tPROP(LOOP1)
Total loop delay, driver input (TXD) to receiver
output (RXD), recessive to dominant
Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
VIO = 1.7 V
See Figure 7-4
165
255
ns
tPROP(LOOP2)
Total loop delay, driver input (TXD) to receiver
output (RXD), dominant to recessive
Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
VIO = 2.8 V to 5.5 V
See Figure 7-4
150
210
ns
tPROP(LOOP2)
Total loop delay, driver input (TXD) to receiver
output (RXD), dominant to recessive
Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
VIO = 1.7 V
See Figure 7-4
180
255
ns
tMODE
Mode change time, from normal to standby or from
standby to normal
See Figure 7-5
20
µs
tWK_FILTER
Filter time for a valid wake-up pattern
See Figure 8-5
0.5
1.8
µs
tWK_TIMEOUT
Bus wake-up timeout
See Figure 8-5
0.8
6
ms
Driver Switching Characteristics
tpHR
Propagation delay time, high TXD to driver
recessive (dominant to recessive)
tpLD
Propagation delay time, low TXD to driver dominant
(recessive to dominant)
STB = 0 V , RL = 60 Ω, CL = 100 pF
See Figure 7-2 and Figure 7-6
80
ns
70
ns
20
ns
ns
tsk(p)
Pulse skew (|tpHR - tpLD|)
tR
Differential output signal rise time
30
tF
Differential output signal fall time
50
tTXD_DTO
Dominant timeout
1.2
ns
4.0
ms
Receiver Switching Characteristics
tpRH
Propagation delay time, bus recessive input to high
output (dominant to recessive)
tpDL
Propagation delay time, bus dominant input to low
output (recessive to dominant)
tR
tF
90
ns
65
ns
RXD output signal rise time
10
ns
RXD output signal fall time
10
ns
STB = 0 V , CL(RXD) = 15 pF
See Figure 7-3
FD Timing Characteristics
8
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6.9 Switching Characteristics (continued)
Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
450
530
ns
155
210
ns
400
550
ns
120
220
ns
Receiver timing symmetry
tBIT(TXD) = 500 ns
-50
20
ns
Receiver timing symmetry
tBIT(TXD) = 200 ns
-45
15
ns
tBIT(BUS)
Bit time on CAN bus output pins
tBIT(TXD) = 500 ns
tBIT(BUS)
Bit time on CAN bus output pins
tBIT(TXD) = 200 ns
tBIT(RXD)
Bit time on RXD output pins
tBIT(TXD) = 500 ns
tBIT(RXD)
Bit time on RXD output pins
tBIT(TXD) = 200 ns
tREC
tREC
STB = 0 V, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 7-4
MIN
TYP
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6.10 Typical Characteristics
4
3
3.5
2.5
3
VOD(DOM) (V)
VOD(DOM) (V)
2
2.5
2
1.5
1.5
1
1
0.5
0.5
0
-40
-25
-10
5
20
35
50
65
80
95
110
VCC = 5 V
0
4.5
125
Temperature (qC)
4.6
4.7
4.8
4.9
VIO = 3.3 V
5
5.1
5.2
5.3
5.4
5.5
VCC (V)
VOD(
VOD(
Temp = 25°C
RL = 60 Ω
RL = 60 Ω
Figure 6-2. VOD(DOM) vs VCC
Figure 6-1. VOD(DOM) vs Temperature
1
15
0.9
0.8
13
0.7
11
IIO (PA)
ICC (PA)
0.6
0.5
0.4
9
0.3
0.2
7
0.1
0
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (qC)
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 6-3. ICC Standby vs Temperature
10
5
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (qC)
D_IC
VCC = 5 V
VIO = 3.3 V
D_II
RL = 60 Ω
Figure 6-4. IIO Standby vs Temperature
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7 Parameter Measurement Information
CANH
TXD
CL
RL
CANL
Figure 7-1. ICC Test Circuit
RCM
CANH
50%
TXD
50%
TXD
RL
CL
VOD
VCM
VCC
VO(CANH)
tpHR
tpLD
CANL
90%
RCM
0V
0.9V
VO(CANL)
VOD
0.5V
10%
tR
tF
Figure 7-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
CANL
CL_RXD
VOH
VO
90%
VO(RXD)
50%
10%
VOL
tR
tF
Figure 7-3. Receiver Test Circuit and Measurement
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Table 7-1. Receiver Differential Input Voltage Threshold Test
Input (See Figure 7-3)
Output
VCANH
VCANL
|VID|
-11.5 V
-12.5 V
1000 mV
12.5 V
11.5 V
1000 mV
-8.55 V
-9.45 V
900 mV
9.45 V
8.55 V
900 mV
-8.75 V
-9.25 V
500 mV
9.25 V
8.75 V
500 mV
-11.8 V
-12.2 V
400 mV
12.2 V
11.8 V
400 mV
Open
Open
X
RXD
Low
VOL
High
VOH
TXD
VI
70%
tLOOP2
30%
30%
CANH
0V
VI
TXD
RL
5 x tBIT(TXD)
CL
tBIT(TXD)
CANL
0V
STB
tBIT(BUS)
900mV
500mV
RXD
VDIFF
VO
CL_RXD
RXD
VOH
70%
30%
tBIT(RXD)
VOL
tLOOP1
Figure 7-4. Transmitter and Receiver Timing Test Circuit and Measurement
12
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CANH
0V
VIH
TXD
CL
RL
STB
CANL
VI
50%
STB
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
Figure 7-5. tMODE Test Circuit and Measurement
VIH
CANH
TXD
TXD
CL
RL
0V
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Figure 7-6. TXD Dominant Timeout Test Circuit and Measurement
CANH
200 s
IOS
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 7-7. Driver Short-Circuit Current Test and Measurement
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8 Detailed Description
8.1 Overview
The TCAN1044-Q1 meets or exceeds the specifications of the ISO 11898-2:2016 high speed CAN (Controller
Area Network) physical layer standard. The device has been certified to the requirements of ISO 11898-2:2016
and ISO 11898-5:2007 physical layer requirements according to the GIFT/ICT high speed CAN test specification.
The transceiver provides a number of different protection features making it ideal for the stringent automotive
system requirements while also supporting CAN FD data rates up to 8 Mbps.
The TCAN1044-Q1 conforms to the following CAN standards:
•
CAN transceiver physical layer standards:
– ISO 11898-2:2016 High speed medium access unit
– ISO 11898-5:2007 High speed medium access unit with low-power mode
– SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125 kbps
– SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps
– SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps
– SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 2 Mbps
– SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 5 Mbps
– ARINC 825-4 General Standardization of CAN (Controller Area Network) Bus Protocol For Airborne Use
•
EMC requirements:
– VeLIO (Vehicle LAN Interoperability and Optimization) CAN and CAN-FD Transceiver Requirements
– SAE J2962-2 Communication Transceivers Qualification Requirements – CAN
•
Conformance test requirements:
– ISO 16845-2 Road vehicles – Controller area network (CAN) conformance test plan Part 2: High-speed
medium access unit conformance test plan
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8.2 Functional Block Diagram
Figure 8-1. Block Diagram
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8.3 Feature Description
8.3.1 Pin Description
8.3.1.1 TXD
The TXD input is a logic-level signal, referenced to either VCC or VIO from a CAN controller to the TCAN1044-Q1
transceivers.
8.3.1.2 GND
GND is the ground pin of the transceiver, it must be connected to the PCB ground.
8.3.1.3 VCC
VCC provides the 5-V power supply to the CAN transceiver.
8.3.1.4 RXD
The RXD output is a logic-level signal, referenced to either VCC or VIO, from the TCAN1044-Q1 transceivers to
the CAN controller. RXD is only driven once VIO is present.
When a wake event takes place RXD is driven low.
8.3.1.5 VIO
The VIO pin provides the digital I/O voltage to match the CAN controller voltage thus avoiding the requirement for
a level shifter. It supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.
8.3.1.6 CANH and CANL
These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transceiver
and the low-voltage WUP CAN receiver.
8.3.1.7 STB (Standby)
The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either
the system processor or from a static system voltage source. If normal mode is the only intended mode of
operation than the STB pin can be tied directly to GND.
8.3.2 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 8-2 and Figure 8-3.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and
RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input
resistors RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than
the differential voltage of a single driver.
The TCAN1044-Q1 transceiver implements a low-power standby (STB ) mode which enables a third bus state
where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See
Figure 8-2 and Figure 8-3.
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Normal Mode
Standby Mode
Typical Bus Voltage
CANH
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
Figure 8-2. Bus States
CANH
2.5V
A
RXD
Bias
Unit
B
GND
CANL
A.
B.
Normal Mode
Standby Mode
Figure 8-3. Simplified Recessive Common Mode Bias Unit and Receiver
8.3.3 TXD Dominant Timeout (DTO)
During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising
edge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for
communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is
seen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to VCC/2 and
the RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimum
transmitted data rate may be calculated using Equation 1.
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
(1)
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Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Normal CAN communication
Driver disabled freeing bus for other nodes
%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH ZKROH QHWZRUN EXW 7;' '72
prevents this and frees the bus for communication after the time tTXD_DTO.
CAN Bus Signal
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
Figure 8-4. Example Timing Diagram for TXD Dominant Timeout
8.3.4 CAN Bus Short Circuit Current Limiting
The TCAN1044-Q1 has several protection features that limit the short circuit current when a CAN bus line is
shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant
state timeout which prevents permanently having the higher short circuit current of a dominant state in case of
a system fault. During CAN communication the bus switches between the dominant and recessive states, thus
the short circuit current may be viewed as either the current during each bus state or as a DC average current.
When selecting termination resistors or a common mode choke for the CAN design the average power rating,
IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has
forced state changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure
there is a minimum amount of recessive time on the bus even if the data field contains a high percentage of
dominant bits.
The average short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated using Equation 2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC]
(2)
Where:
• IOS(AVG) is the average short circuit current
• % Transmit is the percentage the node is transmitting CAN messages
• % Receive is the percentage the node is receiving CAN messages
• % REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• % DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
This short circuit current and the possible fault cases of the network should be taken into consideration when
sizing the power supply used to generate the transceivers VCC supply.
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8.3.5 Thermal Shutdown (TSD)
If the junction temperature of the TCAN1044-Q1 exceeds the thermal shutdown threshold, TTSD, the device turns
off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared
when the junction temperature of the device drops below TTSD. The CAN bus pins are biased to VCC/2 during a
TSD fault and the receiver to RXD path remains operational. The TCAN1044-Q1 TSD circuit includes hysteresis
which prevents the CAN driver output from oscillating during a TSD fault.
8.3.6 Undervoltage Lockout
The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
Table 8-1. Undervoltage Lockout - TCAN1044-Q1
(1)
VCC
DEVICE STATE
BUS
RXD PIN
> UVVCC
Normal
Per TXD
Mirrors bus
< UVVCC
Protected
High impedance
Weak pull-down to ground(1)
High impedance
VCC = GND, see ILKG(OFF)
Table 8-2. Undervoltage Lockout - TCAN1044-Q1V
(1)
(2)
VCC
VIO
DEVICE STATE
BUS
RXD PIN
> UVVCC
> UVVIO
Normal
Per TXD
Mirrors bus
< UVVCC
> UVVIO
> UVVCC
< UVVIO
Protected
< UVVCC
< UVVIO
Protected
VIO: Remote wake request(2)
STB = VIO: standby mode
STB = GND: Protected
High impedance
Weak pull-down to
ground(1)
Recessive
High impedance
High impedance
VCC = GND, see ILKG(OFF)
See Section 8.4.3.1
Once the undervoltage condition is cleared and tMODE has expired the TCAN1044-Q1 transitions to normal mode
and the host controller can send and receive CAN traffic again.
8.3.7 Unpowered Device
The TCAN1044-Q1 is designed to be an ideal passive or no load to the CAN bus if the device is unpowered.
The bus pins were designed to have low leakage currents when the device is unpowered, so they do not load
the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational.
The logic pins also have low leakage currents when the device is unpowered, so they do not load other circuits
which may remain powered.
8.3.8 Floating pins
The TCAN1044-Q1 has internal pull-ups on critical pins which place the device into known states if the pin floats.
This internal bias should not be relied upon by design though, especially in noisy environments, but instead
should be considered a failsafe protection feature.
When a CAN controller supporting open-drain outputs is used an adequate external pull-up resistor must be
chosen. This ensures that the TXD output of the CAN controller maintains acceptable bit time to the input of the
CAN transceiver. See Table 8-3 for details on pin bias conditions.
Table 8-3. Pin Bias
Pin
Pull-up or Pull-down
TXD
Pull-up
Comment
Weakly biases TXD towards recessive to prevent bus blockage or
TXD DTO triggering
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Table 8-3. Pin Bias (continued)
Pin
Pull-up or Pull-down
STB
Comment
Weakly biases STB towards low-power standby mode to prevent
excessive system power
Pull-up
8.4 Device Functional Modes
8.4.1 Operating Modes
The TCAN1044-Q1 has two main operating modes; normal mode and standby mode. Operating mode selection
is made by applying a high or low level to the STB pin on the TCAN1044-Q1.
Table 8-4. Operating Modes
STB
Device Mode
Driver
Receiver
RXD Pin
High
Low current standby mode with
bus wake-up
Disabled
Low-power receiver and bus
monitor enable
High (recessive) until valid WUP
is received
See section 8.3.3.1
Low
Normal Mode
Enabled
Enabled
Mirrors bus state
8.4.2 Normal Mode
This is the normal operating mode of the TCAN1044-Q1. The CAN driver and receiver are fully operational and
CAN communication is bi-directional. The driver is translating a digital input on the TXD input to a differential
output on the CANH and CANL bus pins. The receiver is translating the differential signal from CANH and CANL
to a digital output on the RXD output.
8.4.3 Standby Mode
This is the low-power mode of the TCAN1044-Q1. The CAN driver and main receiver are switched off and
bi-directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled
to allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Figure
8-5. The local CAN protocol controller should monitor RXD for transitions (high-to-low) and reactivate the device
to normal mode by pulling the STB pin low . The CAN bus pins are weakly pulled to GND in this mode; see
Figure 8-2 and Figure 8-3.
In standby mode, only the VIO supply is required therefore the VCC may be switched off for additional system
level current savings.
8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
The TCAN1044-Q1 supports a remote wake-up request that is used to indicate to the host controller that the bus
is active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to
qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a
falling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN1044-Q1.
The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
For a dominant or recessive to be considered filtered, the bus must be in that state for more than the
tWK_FILTER time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be
generated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is always generated. See Figure 8-5 for the timing diagram of the wake-up pattern.
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The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers the
filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this
section. See Figure 8-5 for the timing diagram of the wake-up pattern with wake timeout feature.
Bus Wake via RXD
Request
Wake Up Pattern (WUP) received in t < tWK_Timeout
Filtered
Dominant
Waiting for
Filtered
Recessive
Filtered
Recessive
Waiting for
Filtered
Dominant
Filtered
Dominant
Bus
Bus VDiff
• tWK_FILTER
• tWK_FILTER
• tWK_FILTER
RXD
• tWK_FILTER
Filtered Dominant RXD Output
Bus Wake Via RXD Requests
Figure 8-5. Wake-Up Pattern (WUP) with tWK_TIMEOUT
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8.4.4 Driver and Receiver Function
The digital logic input and output levels for the TCAN1044-Q1 are CMOS levels with respect to either VCC for 5 V
systems or VIO for compatible with MCUs having 1.8 V, 2.5 V, 3.3 V, or 5 V systems.
Table 8-5. Driver Function Table
Device Mode
Normal
CANH
Driven Bus State(2)
CANL
Low
High
Low
Dominant
High or open
High impedance
High impedance
Biased recessive
X
High impedance
High impedance
Biased to ground
Standby
(1)
(2)
Bus Outputs
TXD Input(1)
X = irrelevant
For bus state and bias see Figure 8-2 and Figure 8-3
Table 8-6. Receiver Function Table Normal and Standby Mode
Device Mode
CAN Differential Inputs
VID = VCANH – VCANL
VID ≥ 0.9 V
Dominant
Low
Normal
0.5 V < VID < 0.9 V
Undefined
Undefined
Standby
Any
22
Bus State
RXD Pin
VID ≤ 0.5 V
Recessive
High
VID ≥ 1.15 V
Dominant
0.4 V < VID < 1.15 V
Undefined
VID ≤ 0.4 V
Recessive
High
Low if a remote wake event
occurred
See Figure 8-5
Open (VID ≈ 0 V)
Open
High
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
The TCAN1044-Q1 transceiver can be used in applications with a host controller or FPGA that includes the link
layer portion of the CAN protocol. Figure 9-1 shows a typical configuration for 5 V controller applications. The
bus termination is shown for illustrative purposes.
VIN
VIN
VOUT
5V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VDD
3
Port x
7
STB 8
CANH
TCAN1044
CAN FD Controller
RXD
RXD
TXD
TXD 1
4
CANL
5
NC
6
2
GND
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
Figure 9-1. Transceiver Application Using 5 V I/O Connections
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9.2.1 Design Requirements
9.2.1.1 CAN Termination
Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used,
see Figure 9-2. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines.
Standard Termination
Split Termination
CANH
CANH
RTERM/2
TCAN Transceiver
RTERM
TCAN Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 9-2. CAN Bus Termination Concepts
9.2.2 Detailed Design Procedures
9.2.2.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1044-Q1.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output must
be greater than 1.5 V. The TCAN1044-Q1 family is specified to meet the 1.5 V requirement down to 50 Ω and is
specified to meet 1.4 V differential output at 45Ω bus load. The differential input resistance of the TCAN1044-Q1
is a minimum of 40 kΩ. If 100 TCAN1044-Q1 transceivers are in parallel on a bus, this is equivalent to a 400-Ω
differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of approximately
52 Ω. Therefore, the TCAN1044-Q1 family theoretically supports over 100 transceivers on a single bus segment.
However, for a CAN network design margin must be given for signal loss across the system and cabling,
parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum
number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design
and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km
with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility,
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
24
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Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN Controller
CAN Controller
CAN Controller
TCAN1044-Q1
TCAN1042-Q1
TCAN1043-Q1
Node n
(with termination)
MCU or DSP
CAN Controller
TCAN1044V-Q1
RTERM
RTERM
Figure 9-3. Typical CAN Bus
9.2.3 Application Curves
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 9-4. tPROP(LOOP1)
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 9-5. tPROP(LOOP2)
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9.3 System Examples
The TCAN1044-Q1 CAN transceiver is typically used in applications with a host controller or FPGA that includes
the link layer portion of the CAN protocol. A 1.8 V, 2.5 V, or 3.3 V application is shown in Figure 9-6. The bus
termination is shown for illustrative purposes.
Figure 9-6. Typical Transceiver Application Using 1.8 V, 2.5 V, 3.3 V IO Connections
10 Power Supply Recommendations
The TCAN1044-Q1 transceiver is designed to operate with a main VCC input voltage supply range between
4.5 V and 5.5 V. The TCAN1044-Q1V implements an IO level shifting supply input, VIO, designed for a range
between 1.8 V and 5.5 V. Both supply inputs must be well regulated. A decoupling capacitance, typically 100 nF,
should be placed near the CAN transceiver's main VCC supply pin in addition to bypass capacitors. A decoupling
capacitor, typically 100 nF, should be placed near the CAN transceiver's VIO supply pin in addition to bypass
capacitors.
26
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Layout
Robust and reliable CAN node design may require special layout techniques depending on the application
and automotive design requirements. Since transient disturbances have high frequency content and a wide
bandwidth, high-frequency layout techniques should be applied during PCB design.
11.1 Layout Guidelines
•
•
•
•
Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and
noise from propagating onto the board. This layout example shows an optional transient voltage suppression
(TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of
the transceiver. This example also shows optional bus filter capacitors C4 and C5.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
Note
High frequency current follows the path of least impedance and not the path of least resistance.
•
•
•
•
This layout example shows how split termination could be implemented on the CAN node. The termination
is split into two resistors, R6 and R7, with the center or split tap of the termination connected to ground
via capacitor C3. Split termination provides common mode filtering for the bus. See Section 9.2.1.1, Section
8.3.4, and Equation 2 for information on termination concepts and power ratings needed for the termination
resistor(s).
To limit current of digital lines series resistors may be used. Examples are R2, R3 and R4.
Pin 1 is shown for the TXD input of the device with R1 as an optional pull-up resistor. If an open drain host
controller is used this is mandatory to ensure the bit timing into the device is met.
Pin 8 is shown with R4 assuming the mode pin STB, is used. If the device is used in normal mode only, R4 is
not needed and the pads of C4 could be used for the pull down resistor R5 to GND.
11.2 Layout Example
STB
R4
VCC or VIO
R5
R1
GND
R2
TXD
GND
C4
R6
GND
C3
VCC
J1
D1
C2
C1
U1
U1
TCAN1044(V)
R7
C5
GND
RXD
VIO
R3
C7
C6
GND
Figure 11-1. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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18-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCAN1044DRBRQ1
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1044
TCAN1044DRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1044
TCAN1044VDDFRQ1
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
26SF
TCAN1044VDRBRQ1
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1044V
TCAN1044VDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1044V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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