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TCAN4420
SLLSF19 – DECEMBER 2017
TCAN4420 CAN Transceiver with Polarity Control
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
Meets the Requirements of the ISO 11898-2
(2016) Physical Layer Standard
External Polarity Control Through SW (switch) Pin
– Can be Used to Switch Polarity to Normal
(Default) or Reverse Configuration of CAN Bus
Dual Power Supplies
– 5-V VCC Pin for CAN Driver and Receiver
– 2.8-V to 5-V VIO Pin for Powering RXD, TXD
and SW pins
Wide Operating Ranges
– ±46-V Bus Fault Protection
– ±12-V Common Mode
– –40°C to 125°C Ambient Temperature
Protection Feature
– HBM ESD Protection up to ±12 kV
– Under Voltage Protection on VCC and VIO
Supplies
– TXD Dominant Time Out (TXD DTO) –
Supports Data Rates Down to 9.2 kbps
– Thermal Shutdown Protection (TSD)
Optimized Behavior when Unpowered
– Bus and Logic Terminals are High Impedance
(No Load to Operating Bus or Application)
– Power Up and Down Glitch Free Operation
Fast Loop Times: 150 ns
Building Automation
– Building Security Gateway
– HVAC Gateway and System Controller
– Elevator Main Panel
3 Description
The TCAN4420 is a high-speed Controller Area
Network (CAN) transceiver that meets the
specifications of the ISO 11898-2 (2016) physical
layer standard requirements. The device also allows
the CAN bus polarity to be controlled externally by a
microcontroller through the SW pin. The TCAN4420
includes many protection features providing device
and CAN network robustness. Support for 2.8 V to 5
V MCUs and I/Os is included through the VIO pin.
Device Information(1)
PART NUMBER
TCAN4420
PACKAGE
SOIC (D) (8)
BODY SIZE (NOM)
4.90 mm x 3.91 mm
(1) For all available variants, see the orderable addendum at the
end of the data sheet.
Functional Block Diagram
VIO
TXD
Dominant
Time Out
1
SW 8
4
RXD
GND
VCC
DRIVER
Mode and
Control Logic
Polarity
Control
Under
Voltage
VIO
VCC
VCC
VIO
3
Bias Unit
5
VCC
7
CANH
6 CANL
Over
Temp.
VCC
Logic
Output
2
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN4420
SLLSF19 – DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
ESD Ratings Specifications ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Supply Characteristics ...................................
AC and DC Electrical Characteristics .......................
Timing Requirements ...............................................
Typical Characteristics ..............................................
8.2 Functional Block Diagrams ..................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
8.1 Overview ................................................................. 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2017
*
Initial release.
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
TXD
1
8
SW
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
VIO
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
TXD
1
Logic Input
GND
2
Ground
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
Ground connection
VCC
3
Power
5 V ±10% supply voltage
RXD
4
Logic Output
VIO
5
Power
Transceiver I/O level shifting supply voltage
CANL
6
Bus I/O
Low level CAN bus input/output line
CANH
7
Bus I/O
High level CAN bus input/output line
SW
8
Logic Input
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
Polarity switch pin. Set to low for normal polarity (default), and high to reverse the polarity of
the CAN pins
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
VCC
Supply voltage
–0.3
6
VIO
Supply voltage select for I/O level shifter
–0.3
6
VBUS
CAN Bus I/O voltage (CANH, CANL)
–46
46
VLogic_Input
Logic input terminal voltage
–0.3
6
VRXD
RXD output terminal voltage range
–0.3
6
IO(RXD)
RXD output current
TJ
Operating virtual junction temperature range, packaged units
–40
150
TA
Ambient temperature
–40
125
TSTG
Storage temperature
–65
150
(1)
(2)
8
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002
All pins
Charged-device model (CDM), per AEC
Q100-011
All pins (2)
(1)
UNIT
±4000
V
±750
Tested in accordance to AEC-Q100-002.
Tested in accordance to AEC-Q100-011.
6.3 ESD Ratings Specifications
Electrostatic discharge
V(ESD)
(1)
(2)
(3)
(4)
(5)
4
Human bodt model (HBM)
IEC 61400-4-2 according to IBEE CAN
EMC test spec (2)
CANH and CANL terminals to GND (3)
(4)
IEC 61400-4-2 Air Discharge (2)
CANH and CANL terminals to GND (3)
(4)
ISO7637 Transients according to IBEE
CAN EMC test spec (5)
(1)
CAN bus terminal
(CANH, CANL)
CAN bus terminals (CANH, CANL)
VALUE
UNIT
±12000
V
±8000
V
±15000
V
Pulse 1
–100
V
Pulse 2
75
V
Pulse 3a
–150
V
System level ESD test, results given here were performed at the system level with appropriate external components such TVS diodes.
Different system level configurations may lead to different results.
IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations may lead to different results.
IEC 61000-4-2 is a system level ESD test. Results given here were performed at the system level with appropriate external components
such TVS diodes. Different system level configurations may lead to different results.
Testing performed in accordance with 3rd party IBEE Zwickau test method.
ISO7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations may lead to different results.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5
5.5
VCC
Supply voltage
4.5
VIO
Supply Voltage for I/O Level Shifter
2.8
IOH(RXD)
RXD terminal HIGH level output current
–2
IOL(RXD)
RXD terminal LOW level output current
TA
Operational free-air temperature (see Thermal Characteristics
table)
UNIT
V
5.5
V
mA
–40
2
mA
125
°C
6.5 Thermal Information
TCAN4420
THERMAL METRIC (1)
SOIC
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
114
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.2
°C/W
RθJB
Junction-to-board thermal resistance
59.2
°C/W
ΨJT
Junction-to-top characterization parameter
9.5
°C/W
ΨJB
Junction-to-board characterization parameter
58.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC
Supply Current Normal
Mode
TEST CONDITIONS
MAX
Dominant
55
70
Dominant
See Figure 6, TXD = 0 V, RL = 50 Ω, CL
= open,
60
80
Dominant with
bus Fault
See Figure 6, TXD = 0 V, STBx = 0 V,
CANH = –25 V, RL = open, CL = open
100
180
Recessive
See Figure 6, TXD = VCC, RL = 60 Ω, CL
= open, RCM = open, S or STB = 0 V
10
20
Under voltage detection on VCC for protected mode
UVVCC
MIN
3.5
Average Power
Dissapation
4.4
200
Under voltage detection on VIO for protected mode
UNIT
mA
Hysteresis voltage
UVVIO
PD
TYP
See Figure 6, TXD = 0 V, RL = 60 Ω, CL
= open,
1.3
2.7
VCC = VIO= 5 V, TJ = 25℃, RL = 60 Ω, Input to TXD at 250
kHz, 25% duty cycle square wave, CL_RXD = 15 pF. Typical
CAN operating conditions at 500 kbps with 25% transmission
(domiant) rate.
115
VCC = VIO= 5.5 V, TJ = 150℃, RL = 50 Ω. Input to TXD at
500 kHz, 50% duty cycle square wave, CL_RXD = 15 pF.
Typical high load CAN operating conditions at 1 Mbps with
50% transmission (domiant) rate and loaded network.
268
V
mV
V
mW
Thermal Shutdown Temperature
185
Thermal Shutdown Hysterisis
℃
15
6.7 AC and DC Electrical Characteristics
All typical values are at 25°C and supply voltages of VCC = 5 V. RL = 60 Ω over operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 8 and Figure 9, TXD = 0 V, RL
= 60 Ω, CL = open, RCM = open
2.75
4.5
V
0.5
2.25
V
3
V
Driver Electrical Characteristics
VO(D)
VO(R)
VOD(D)
VOD(R)
Bus output voltage
(dominant)
CANH
CANL
Bus output voltage (recessive)
Differential output voltage (dominant)
Differential output voltage (recessive)
VSYM
Output symmetry (dominant or recessive)
(VCC - VO(CANH) - VO(CANL))
IOS(DOM)
Short-circuit steady-state output current,
Dominant
IOS(REC)
Short-circuit steady-state output current,
Recessive
See Figure 6 and Figure 9, TXD = VCC,
RL = open (no load), RCM = open
2
0.5 x VCC
See Figure 6 and Figure 9, TXD = 0 V, 50
Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open
4.75 V ≤ VCC ≤ 5.25 V
1.5
3
V
See Figure 6 and Figure 9, TXD = 0 V, 50
Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open
4.5 V ≤ VCC ≤ 5.5 V
1.3
3.2
V
–120
12
mV
SeeFigure 6 and Figure 9,TXD = VCC, RL
= open, CL = open, RCM = open
–50
50
mV
See Figure 6 and Figure 9, RL = 60 Ω, CL
= open, RCM = open
–400
400
mV
See Figure 6 and Figure 12, V(CAN_H) ≤ –5
V, CANL = open, TXD = 0 V
–115
See Figure 6 and Figure 9, TXD = VCC,
RL = 60 Ω, CL = open, RCM = open
mA
See Figure 6 and Figure 12, V(CAN_L) = 40
V, CANH = open, TXD = 0 V
See Figure 6 and Figure 12, –27 V ≤
VBUS ≤ 32 V, VBUS = CANH = CANL
–5
115
mA
5
mA
900
mV
Receiver Electrical Characteristics
VIT
Input threshold voltage
VHYS
Hysteresis voltage for input threshold
VCM
Common Mode Range
IIOFF(LKG)
Power-off (unpowered) bus input leakage
current
6
500
See Figure 10
120
–12
CANH = CANL = 5 V, VCC to GND via 0
Ω
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12
5
V
µA
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AC and DC Electrical Characteristics (continued)
All typical values are at 25°C and supply voltages of VCC = 5 V. RL = 60 Ω over operating free-air temperature range (unless
otherwise noted)
PARAMETER
CI
Input capacitance to ground (CANH or
CANL)
CID
Differential input capacitance
RID
Differential input resistance
RIN
Single Ended Input resistance
(CANH or CANL)
RIN(M)
Input resistance matching:
[1 – (RIN(CANH) / RIN(CANL))] × 100 %
TEST CONDITIONS
MIN
TYP
MAX
UNIT
40
pF
20
TXD = VCC = VIO
V(CAN_H) = V(CAN_L) = 5 V
pF
20
80
kΩ
10
40
kΩ
–1%
1%
VIO PIN
VIO
Supply voltage on VIO pin
IIO
Supply current on VIO pin
2.8
RXD pin floating, TXD = 0 V
RXD pin floating, TXD = 5
5.5
V
350
µA
50
µA
TXD Terminal (CAN Transmit Data Input)
VIH
High-level input voltage
VIL
Low-level input voltage
0.7VIO
IIH
High-level input leakage current
VTXD = VIO = VCC = 5.5 V
–2.5
IIL
Low-level input leakage current
VTXD = 0 V, VCC = 5.5 V
–200
ILKG(OFF)
Unpowered leakage current
VTXD = 5.5 V, VIO = VCC = 0 V
CI
Input Capacitance
VIN = 0.4 x sin(2 x M x 2 x 106 x t) + 2.5
V
0
–1
0
0.3VIO
V
1
µA
–6
µA
1
µA
20
pF
RXD Pin (CAN Receive Data Output)
VOH
High-level input voltage
See Figure 10, IO = –2 mA
VOL
Low-level input voltage
See Figure 10, IO = –2 mA
ILKG(OFF)
Unpowered leakage current
VRXD = 5.5 V, VIO = VCC = 0 V
0.8VIO
V
–1
0
0.2VIO
V
1
µA
SW Pin (Polarity Switch Input)
VIH
High-level input voltage
VIL
Low-level input voltage
0.7VIO
IIH
High-level input leakage current
SW = VIO = VCC = 5.5 V
0.5
IIL
Low-level input leakage current
SW = 0 V, VCC = 5.5 V
–1
ILKG(OFF)
Unpowered leakage current
SW = 5.5 V, VIO = VCC = 0 V
–1
V
0
0.3VIO
V
20
µA
1
µA
1
µA
6.8 Timing Requirements
MIN
NOM
MAX
UNIT
Switching Characteristics
tpHR
Propagation delay time,
high TXD to Driver Recessive
tpLD
Propagation delay time,
low TXD to Driver Dominant
tsk(p)
Pulse skew (|tpHR - tpLD|)
10
tR
Differential output signal rise time
25
tF
Differential output signal fall time
tTXD_DTO
(1)
Dominant time out (1)
50
See Figure 9,
Typical Conditions for DS: RL =
60 Ω, CL = 100 pF, RCM = open
40
ns
25
See Figure 13, RL = 60 Ω, CL =
open
1.2
4
ms
The TXD dominant time out (tTXD_DTO) disables the driver of the transceiver once the TXD has been dominant longer than tTXD_DTO,
which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it
limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst
case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps.
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Timing Requirements (continued)
MIN
tpRH
Propagation delay time, bus recessive input
to high RXD_INT output
tpDL
Propagation delay time, bus dominant input
to RXD low output
tR
Differential output signal rise time
tF
Differential output signal fall time
NOM
MAX
UNIT
50
See Figure 10 CL(RXD) = 15 pF
Typical Conditions for DS: CANL
= 1.5 V, CANH = 3.5 V
50
ns
8
8
Device Switching Characteristics
t(LOOP1)
t(LOOP2)
Total loop delay, driver input (TXD) to
receiver output (RXD), recessive to
dominant (2)
See Figure 10 Typical Conditions:
RL = 60 Ω, CL = 100 pF, CL(RXD) =
15 pF
Total loop delay, driver input (TXD) to
receiver output (RXD), dominant to
receissive (2)
See Figure 10 Typical Conditions:
RL = 60 Ω, CL = 100 pF, CL(RXD) =
15 pF
tMODE
Mode change time from normal
configuration to reverse
tUV_RE-ENABLE
Re-enable time after UV event
(2)
8
See Figure 10. Time for device to
return to normal operation from
UVVCC and UVVIO under voltage
event
150
ns
150
300
µs
300
µs
Time span from signal edge on TXD input to next signal edge with same polarity on RXD output, the maximum of delay of both signal
edges is to be considered.
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6.9 Typical Characteristics
3
3
VOD vs T ; SW = 0
VOD vs T ; SW = 1
2.5
2.5
2
VOD(D) (V)
VOD(D) (V)
2
1.5
1.5
1
1
0.5
0.5
VOD vs VCC : SW = 0
VOD vs VCC : SW = 1
0
-50
0
50
Temperature (qC)
VCC = 5 V
CL = Open
100
0
4.5
150
VIO = 5 V
RCM = Open
RL= 60Ω
SW = 0 / 1
4.7
4.8
4.9
SW = 0 / 1
CL = Open
Figure 1. VOD(D) over Temperature
5
5.1
VCC (V)
5.2
5.3
5.4
5.5
SLLS
VIO = 5 V
RCM = Open
RL= 60Ω
Temp = 25°C
Figure 2. VOD(D) over VCC Supply Voltage
13.4
100
ICC Recessive : SW = 0
ICC Recessive : SW = 1
13.3
90
13.2
TLOOP (D2R) (ns)
ICC Recessive (mA)
4.6
SLLS
13.1
13
12.9
80
70
60
12.8
50
12.7
12.6
-40
SW=0
SW=1
-20
0
VCC = 5 V
CL = Open
20
40
60
80
Temperature (qC)
100
120
40
-50
140
0
SLLS
VIO = 5 V
RCM = Open
RL= 60Ω
SW = 0 / 1
Figure 3. ICC over Temperature
50
Temperature (qC)
VCC = 5 V
CL = Open
VIO = 5 V
RCM = Open
100
150
SLLS
RL= 60Ω
SW = 0 / 1
Figure 4. Dominant to Recessive TLOOP over Temperature
80
75
TLOOP (R2D) (ns)
70
65
60
55
50
45
SW = 0
SW = 1
40
-50
0
VCC = 5 V
CL = Open
50
Temperature (qC)
100
VIO = 5 V
RCM = Open
150
SLLS
RL= 60 Ω
SW = 0 / 1
Figure 5. Recessive to Dominant TLOOP vs Temperature
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4
3
CANH
2
VOD(D)
VOD(R)
CANL
1
Typical Bus Voltage (V)
7 Parameter Measurement Information
Time, t
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Figure 6. Bus States (Physical Bit Representation)
10
CANH
VCC / 2
RXD
10
CANL
Figure 7. Common Mode Bias Unit and Receiver
CANH
TXD
RL
CL
CANL
Figure 8. Supply Test Circuit
10
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Parameter Measurement Information (continued)
RCM
CANH
VCC
50%
TXD
50%
TXD
RL
CL
VOD
0V
VCM
VO(CANH)
tpHR
tpLD
CANL
90%
RCM
0.9 V
VO(CANL)
VOD
0.5 V
10%
tR
tF
Figure 9. Driver Test Circuit and Measurement
CANH
1.5 V
RXD
0.9 V
VID
IO
0.5 V
0V
VID
tpDL
tpRH
CANL
VOH
VO
CL_RXD
90%
70%
VO(RXD)
30%
10%
VOL
tF
tR
Figure 10. Receiver Test Circuit and Measurement
CANH
TXD
R
0V
CL
5V
4.4 V
VSUP
L
3.8V
tUV_RE-ENABLE
CANL
STB
0V
70%
RXD VO
RXD
30%
Hi Z
VO
CL_RXD
Figure 11. UV Re-enable Time after UV Event
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Parameter Measurement Information (continued)
CANH
VI
TXD
VI
CL
RL
tLOOP
Falling
edge
70%
TXD
STB
30%
30%
CANL
0V
0V
5 x tBIT(TXD)
tBIT(TXD)
RXD
tBIT(Bus)
VO
CL_RXD
900 mV
VDiff
500 mV
VOH
70%
RXD
30%
tLOOP
rising
edge
VOL
tBIT(RXD)
Figure 12. Transmitter and Receiver Timing Behavior Test Circuit and Measurement
CANH
VIH
TXD
TXD
RL
CL
30%
VOD
0V
VOD(D)
CANL
0.9 V
VOD
0.5 V
0V
tTXD_DTO
Figure 13. TXD_INT Dominant Time Out Test Circuit and Measurement
12
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Parameter Measurement Information (continued)
CANH
200 s
IOS
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 14. Driver Short-Circuit Current Test and Measurement
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8 Detailed Description
8.1 Overview
The TCAN4420 is a high-speed CAN transceiver that meets the specifications of the ISO 11898-2 (2016) High
Speed CAN (Controller Are Network) physical layer standards. It includes many protection features providing
device and CAN network robustness. It also allows for the polarity of the CAN pins to be controlled externally by
a micro-controller through the use of the polarity switch pin, SW.
The CAN bus has two logical states during operation: recessive and dominant. See Figure 6 and Figure 7.
A recessive bus state occurs when the bus is biased to a common mode of VCC/2 via the receivers bias unit.
Recessive is equivalent to logic high on the TXD pin and is typically a differential voltage on the bus of
approximately 0 V.
A dominant bus state occurs when the bus is driven differentially by one or more drivers. The driver produces a
current which flows through the termination resistors on the bus and generates a differential voltage. Dominant is
equivalent to logic low on the TXD pin and is a differential voltage on the bus greater than the minimum required
threshold for a CAN dominant.
The host microprocessor of the CAN node uses the TXD terminal, pin 1, to drive the bus and receives data from
the bus via the RXD terminal, pin 4. The TCAN4420 integrates level shifting capabilities into the RXD output via
the VIO pin. This feature eliminates the need for an additional level shifter between the host microprocessor and
the RXD output of the CAN transceiver.
8.2 Functional Block Diagrams
VIO
TXD
Dominant
Time Out
1
SW 8
Under
Voltage
VIO
4
GND
VCC
DRIVER
Mode and
Control Logic
Polarity
Control
RXD
VCC
VCC
VIO
3
Bias Unit
5
VCC
7
CANH
6 CANL
Over
Temp.
VCC
Logic
Output
2
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8.3 Feature Description
8.3.1 TXD Dominant Time Out (DTO)
The TXD DTO circuit prevents the local node from blocking network communication in event of a hardware or
software failure where TXD is held dominant longer than the time out period tTXD_DTO. The DTO circuit timer
starts on a falling edge on TXD. The DTO circuit disables the CAN bus driver if no rising edge is seen before the
timeout period expires. This frees the bus for communication between other nodes on the network. The CAN
driver is re-activated when a recessive signal is seen on the TXD terminal, thus clearing the TXD DTO condition.
The receiver and RXD terminal still reflect activity on the CAN bus, and the bus terminals are biased to the
recessive level during a TXD dominant timeout.
14
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Feature Description (continued)
8.3.2 CAN Bus Short Circuit Current Limiting
The TCAN4420 has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include CAN driver current limiting (dominant and recessive). During CAN communication the bus
switches between dominant and recessive states, thus the short circuit current may be viewed either as the
current during each bus state or as a DC average current. For system current and power considerations in the
termination resistors and common mode choke ratings the average short circuit current should be used. The
percentage dominant is limited by the TXD dominant time out and CAN protocol which has forced state changes
and recessive bits such as bit stuffing, control fields, and inter frame space. These ensure there is a minimum
recessive amount of time on the bus even if the data field contains a high percentage of dominant bits.
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short
circuit currents. The average short circuit current may be calculated using Equation 1.
IOS(AVG) = %Transmit x [(%REC_Bits x IOS(SS)_REC) + (%DOM_Bits x IOS(SS)_DOM)] + [%Receive x IOS(SS)_REC]
(1)
Where:
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages,
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current.
NOTE
The short circuit current and possible fault cases of the network should be taken into
consideration when sizing the power ratings of the termination resistance, other network
components, and the power supply used to generate VCC.
8.3.3 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold of 170ºC the device turns off
the CAN driver circuitry thus blocking the TXD to bus transmission path. The shutdown condition is cleared when
the junction temperature of the device drops below the thermal shutdown temperature of the device. If the fault
condition that caused the thermal shutdown is still present, the temperature may rise again and the device enters
thermal shut down again. Prolonged operation with thermal shutdown conditions may affect device reliability. The
thermal shutdown circuit includes hysteresis to avoid oscillation of the driver output.
NOTE
During thermal shutdown the CAN bus driver is turned off thus no transmission is possible
from TXD to the bus. The CAN bus terminals are biased to recessive level during a
thermal shutdown, and the receiver to RXD path remains operational.
8.3.4 Under Voltage Lockout (UVLO) and Unpowered Device
The VCC and VIO supply terminals have under voltage detection circuitry which places the device in a protected
mode if an under voltage fault occurs. This protects the bus during an under voltage event on these terminals. If
VIO is under voltage the RXD terminal is tri-stated (high impedance) and the device does not pass any signals
from the bus. If VCC supply is lost, or has a brown out that triggers the UVLO, the device transitions to a
protected mode. See Table 1.
If VIO drops below UVVIO under voltage detection, the transceiver switches off and disengage from the bus until
VIO has recovered.
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Feature Description (continued)
The device is designed to be an "ideal passive" or “no load” to the CAN bus if the device is unpowered. The bus
terminals (CANH, CANL) have extremely low leakage currents when the device is unpowered, so they do not
load the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational. Logic terminals also have low leakage currents when the device is unpowered, so they do not load
other circuits which may remain powered.
Table 1. Under Voltage Lockout Protection
VCC
VIO
DEVICE STATE
BUS
RXD
> UVVCC
> UVVIO
Normal
Per TXD
Mirrors Bus
< UVVCC
> UVVIO
Protected
High Impedance
High (Recessive)
> UVVCC
< UVVIO
Protected
High Impedance
High Impedance
< UVVCC
< UVVIO
Protected
High Impedance
High Impedance
space
NOTE
Once an under voltage condition is cleared and the VCC supply has returned to valid level
the device typically needs tMODE to transition to normal operation. The host processor
should not attempt to send or receive messages until this transition time has expired.
8.3.4.1 VIO Supply PIN
A separate VIO supply pin is supported on this device. This pin should be connected to the supply voltage of the
microcontroller, see Figure 17 and Figure 18. This sets the signal levels for TXD, RXD and SW pins to the I/O
level of the microcontroller.
8.4 Device Functional Modes
8.4.1 Polarity Configuration
The device supports two polarity configurations on the CAN pins. For a conventional (normal) CAN connection,
connect SW pin to GND. Allow for a time interval equal to tMODE after changing the SW pin, before reading the
bus or the RXD pin. To support a reverse connection of the CAN pins, connect the SW pin to VIO. This approach
enables compatibility with existing boards that already use this pin (pin 8) to be connected to GND for normal
operation. See Table 2.
Table 2. Polarity Configurations
SW Pin
Device Polarity
VOD(TX) or VID (RX)
LOW
Normal
= CANH-CANL
HIGH
Reverse
= CANL-CANH
8.4.2 Normal Polarity Mode
This is the normal configuration of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH
and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.
Normal Mode is enabled when there is a logic low on the SW pin.
8.4.3 Reverse Polarity Mode
The TCAN4420 supports a reverse polarity configuration when the SW pin is connected to supply. In this
configuration, both the driver and receiver remain fully operational, the key difference being that both VOD and VID
are now defined as the difference between CANL and CANH pins as indicated in Table 2. Also see Table
Table 3 and Table 4 for the pin voltage levels in this configuration.
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8.4.4 Driver and Receiver Function
The digital logic input and output levels for these devices are TTL levels with respect to VIO for compatibility with
protocol controllers having 2.8 V to 5 V logic or I/O.
Table 3 and Table 4 provide the states of the CAN driver and CAN receiver in each mode.
Table 3. Driver Function Table
DEVICE MODE
Normal
Reverse
(1)
(2)
(3)
BUS OUTPUTS (2)
TXD INPUT (1)
CANH
CANL
DRIVEN BUS
STATE (3)
L
H
L
Dominant
H or Open
Z
Z
Biased Recessive
L
L
H
Dominant
H or Open
Z
Z
Biased Recessive
H = high level, L = low level
H = high level, L = low level, Z = high Z receiver bias
For Bus state and bias see Figure 7
Table 4. Receiver Function Table
DEVICE MODE
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL
VID ≥ 0.9 V
Dominant
L
Normal: VID = VCANH – VCANL
Reverse: VID = VCANL – VCANH
0.5 V < VID < 0.9 V
Undefined
Undefined
VID ≤ 0.5 V
Recessive
H
(1)
BUS STATE
RXD TERMINAL (1)
H = high level, L = low level
8.4.5 Floating Terminals
The TCAN4420 has internal pull ups and pull downs on critical terminals to place the device into known states if
the terminal floats. See Table 5 for details on terminal bias conditions
Table 5. Terminal Bias
TERMINAL
PULL UP or PULL DOWN
TXD
Pull up
SW
Pull down
COMMENT
Weakly biases TXD toward recessive to prevent bus blockage or
TXD DTO triggering
Weakly biases SW terminal towards GND to use the default (normal)
polarity configuration
space
NOTE
The internal bias should not be relied upon as only termination, especially in noisy
environments but should be considered a failsafe protection. Special care needs to be
taken when the device is used with MCUs which implement open drain outputs. TXD is
weakly internally pulled up. The TXD pull up strength and CAN bit timing require special
consideration when this device is used with an open drain TXD output on the
microprocessor CAN controller. An adequate external pull up resistor must be used to
ensure that the TXD output of the microprocessor maintains adequate bit timing input to
the CAN transceiver.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the
data link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V
microprocessor applications. The bus termination is shown for illustrative purposes.
9.2 Typical Application
Figure 15. Typical CAN Bus Application
9.2.1 Design Requirements
9.2.1.1 Bus Loading, Length and Number of Nodes
A typical CAN application can have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A high number of nodes require a transceiver with high input impedance such as the TCAN4420 transceiver.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original
ISO11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic
loading of the bus. Examples of these CAN systems level specifications are ARINC825, CANopen, DeviceNet,
SAE J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In ISO 11898-2 the driver differential output is specified
with a 60-Ω bus load where the differential output must be greater than 1.5 V. The TCAN4420 is specified to
meet the 1.5 V requirement across this load and is specified to meet 1.3-V differential output at 50-Ω bus load.
The differential input resistance of this family of transceiver is a minimum of 20 kΩ. If 67 of these transceivers are
in parallel on a bus, this is equivalent to an 300-Ω differential load in parallel with the 60 Ω bus termination which
gives a total bus load of 50 Ω. Therefore, this family theoretically supports over 67 transceivers on a single bus
segment with margin to the 0.9-V minimum differential input voltage requirement at each receiving node.
However, for network design, margin must be given for signal loss across the system and cabling, parasitic
loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of
nodes is much lower. Bus length may also be extended beyond 40 meters by careful system design and data
rate tradeoffs. For example CANopen network design guidelines allow the network to be up to 1 km with changes
in the termination resistance, cabling, less than 64 nodes on the bus, and significantly lowered data rate.
18
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Typical Application (continued)
This flexibility in network design is one of its key strengths allowing for these system level network extensions
and additional standards to build on the typical CAN bus length parameters. However, when using this flexibility
the network system designer must take the responsibility of good network design to ensure robust network
operation.
9.2.2 Detailed Design Procedure
9.2.2.1 CAN Termination
The ISO 11898 standard specifies the interconnect to be a twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line must be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines, stubs, connecting nodes
to the bus must be kept as short as possible to minimize signal reflections. The termination may be on the cable
or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that it is not
removed from the bus
Termination may be a single 120-Ω resistor at the end of the bus either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used,
see Figure 16. Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages.
Split Termination
Standard Termination
CANH
CANH
RTERM/2
CAN
Transceiver
RTERM
CAN
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 16. CAN Bus Termination Concepts
The TCAN4420 transceiver supports both 5-V only applications and applications where level shifting is needed
for a 3.3-V microcontroller. See Figure 17 and Figure 18 for application examples.
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Typical Application (continued)
5-V Voltage
Regulator
(e.g. TPSxxxx)
VIN
VOUT
VCC
VCC
VIO
3
GPIO1
SW
5-V MCU
RXD
TXD
RXD
TXD
5
CANH
7
8
TCAN4420 CAN
Transceiver
4 With Polarity
Control
1
CANL
6
2
Optional:
Terminating
Node
GND
Optional:
Filtering,
Transient and ESD
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Figure 17. Typical CAN Bus Application Using TCAN4420 with 5 V µC
VIN
VIN
3-V Voltage
Regulator
(e.g. TPSxxxx)
VOUT
5-V Voltage
Regulator
(e.g. TPSxxxx)
VOUT
VCC
VCC
VIO
3
GPIO1
SW
3-V MCU
RXD
TXD
RXD
TXD
5
7
8
CANH
TCAN4420 CAN
Transceiver
4 With Polarity
Control
1
6
2
GND
CANL
Optional:
Terminating
Node
Optional:
Filtering,
Transient and ESD
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Figure 18. Typical CAN Application Using TCAN4420 with 3.3 V µC
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Typical Application (continued)
9.2.3 Application Curves
70
ICC Dominant (mA)
60
50
40
30
20
10
0
4.5
ICC Dominant vs VCC : SW = 0
ICC Dominant vs VCC : SW = 1
4.6
4.7
4.8
4.9
5
5.1
VCC (V)
5.2
5.3
5.4
5.5
SLLS
Figure 19. ICC Dominant Current over VCC Supply Voltage
10 Power Supply Recommendations
The TCAN4420 device is designed to operate with a main VCC input voltage supply range between 4.5 V and
5.5 V. The device also has an IO level shifting supply input, VIO, designed for a range between 2.8 V and
5.5 V. To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a
100-nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage
ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance
and inductance of the PCB power planes.
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11 Layout
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
11.1 Layout Guidelines
•
•
•
Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and
noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,
D1, has been used for added protection. The production solution can be either bi-directional TVS diode or
varistor with ratings matching the application requirements. This example also shows optional bus filter
capacitors C3 and C4. Additionally (not shown) a series common mode choke (CMC) can be placed on the
CANH and CANL lines between the TCAN4420 transceiver and connector J1.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
Use supply (VCC) and ground planes to provide low inductance.
NOTE
High-frequency currents follows the path of least impedance and not the path of least
resistance.
•
•
•
•
•
•
•
22
Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
Bypass capacitors should be placed as close as possible to the supply terminals of transceiver, examples are
C1 on the VCC supply and C5 on the VIO supply.
Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C2. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination. See the application section for information on power ratings needed
for the termination resistor(s).
To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not
required.
Pin 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used, this is
mandatory to ensure the bit timing into the device is met.
Pin 5: A bypass capacitor should be placed as close to the pin as possible (example C5). A voltage must be
applied to the VIO for normal operation.
Pin 8: is shows the SW terminal with R4 and R5 as optional resistors. The SW terminal can also be tied to an
IO for soft polarity configuration.
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11.2 Layout Example
Figure 20. Example Layout
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12 Device and Documentation Support
12.1 Device Support
This device will conform to the following CAN standards. The core of what is needed is covered within this
system specifications; however, reference should be made to these standards and any discrepancies pointed out
and discussed. This document should provide all the basics of what is needed. However, for a full understanding
of CAN including the protocol these additional sources will be helpful as the scope of CAN protocol in detail is
outside the scope of this physical layer (transceiver) specifications.
12.1.1 Device Nomenclature
CAN Transceiver Physical Layer Standards:
• ISO11898-2 High speed medium access unit (original High Speed CAN transceiver standard)
• ISO11898-5 High speed medium access unit with low power mode (super sets -2 standard electrically in
several specs and adds the original wake up capability via the bus in low power mode).
Conformance Test requirements:
• A Comprehensible Guide to Controller Area Network”, Wilfried Voss, Copperhill Media Corporation
• "CAN System Engineering: From Theory to Practical Applications”, 2nd Edition, 2013; Dr. Wolfhard Lawrenz,
Springer.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
SYMM
5
4
5
4
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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Product Folder Links: TCAN4420
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCAN4420DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4420
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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