TDP158
SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
TDP158 6-Gbps, AC-Coupled to TMDS™ or HDMI ™ Level Shifter Redriver
1 Features
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3 Description
AC-coupled TMDS or DisplayPort™ dual-mode
physical layer input to HDMI 2.0b TMDS physical
layer output supporting up to 6 Gbps data rate,
compatible with HDMI 2.0b electrical parameters
Supporting DisplayPort dual-mode standard
version 1.1
Support 4k2k60p and up to WUXGA 16-bit color
depth or 1080p with higher refresh rates
Programmable fixed receiver equalizer up to
15.5 dB
Global or independent high speed lane control,
pre-emphasis and transmit swing, and slew rate
control
I2C or pin strap programmable
Configurable as a DisplayPort redriver through the
I2C
Full lane swap on main lanes
Low power consumption
– –200 mW active at 6-Gbps and –8 mW at
shutdown state
40-pin, 0.4 mm Pitch, 5 mm × 5 mm, WQFN
package, pin compatible to the SN75DP159RSB
retimer
2 Applications
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The TDP158 device is an AC-coupled HDMI signal
to transition-minimized differential signal (TMDS)
Redriver supporting digital video interface (DVI) 1.0
and high-definition multimedia interface (HDMI) 1.4b
and 2.0b output signals. The TDP158 supports four
TMDS channels and Digital Display Control (DDC)
interfaces. The TDP158 supports signaling rates up to
6 Gbps to allow for the highest resolutions of 4k2k60p
24 bits per pixel and up to WUXGA 16-bit color depth
or 1080p with higher refresh rates. The TDP158 can
be configured to support the HDMI 2.0 standard.
The TDP158 supports dual power supply rails of
1.1 V on VDD and 3.3 V on VCC for power reduction.
Several methods of power management are
implemented to reduce overall power consumption.
TDP158 supports fixed receiver EQ gain using I2C
or pin strap to compensate for different lengths input
cable or board traces.
Device Information(1)
PART NUMBER
TDP158
(1)
PACKAGE
BODY SIZE (NOM)
WQFN (40)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Notebook, desktop, all-in-ones, tablet, gaming and
industrial PC
Audio or video equipment
Blu-ray™ DVD
Gaming systems
HDMI adaptor or dongle
Docking station
TDP158
DP++ TX
Or
AC Coupled
HDMI TX
IN_D2p/n
OUT_D2p/n
IN_D1p/n
OUT_D1p/n
IN_D0p/n
OUT_D0p/n
D P1
IN_CLKp/n
GPU
5V
SCL_SRC
58
T
TDP158
OUT_CLKp/n
HDMI
Connector
Display
SDA_SRC
SCL_SNK
DDC
SDA_SNK
HPD
3.3 V
HPD_SRC
HPD_SNK
OE
I2C
SCL_CTL
VSADJ
SDA_CTL
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TDP158
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SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics, Power Supply.................... 8
6.6 Electrical Characteristics, Differential Input................ 9
6.7 Electrical Characteristics, TMDS Differential
Output............................................................................9
6.8 Electrical Characteristics, DDC, I2C, HPD, and
ARC...............................................................................9
6.9 Electrical Characteristics, TMDS Differential
Output in DP-Mode......................................................10
6.10 Switching Characteristics, TMDS............................10
6.11 Switching Characteristics, HPD.............................. 10
6.12 Switching Characteristics, DDC and I2C................. 11
6.13 Typical Characteristics............................................ 12
7 Parameter Measurement Information.......................... 13
8 Detailed Description......................................................19
8.1 Overview................................................................... 19
8.2 Functional Block Diagram......................................... 20
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................27
8.5 Register Maps...........................................................28
9 Application and Implementation.................................. 39
9.1 Application Information............................................. 39
9.2 Typical Application.................................................... 39
10 Power Supply Recommendations..............................45
10.1 Power Management................................................45
10.2 Standby Power........................................................45
11 Layout........................................................................... 46
11.1 Layout Guidelines................................................... 46
11.2 Layout Example...................................................... 47
12 Device and Documentation Support..........................48
12.1 Documentation Support.......................................... 48
12.2 Receiving Notification of Documentation Updates..48
12.3 Support Resources................................................. 48
12.4 Trademarks............................................................. 48
12.5 Electrostatic Discharge Caution..............................48
12.6 Glossary..................................................................48
13 Mechanical, Packaging, and Orderable
Information.................................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2020) to Revision E (July 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added inclusive terminology throughout the data sheet..................................................................................... 1
• Updated the TDP158 in Source Side Application figure with ESD between device and receptacle.................39
• Updated the TDP158 Source Side Application with DDC Snoop figure with ESD between device and
receptacle......................................................................................................................................................... 43
• Updated the TDP158 in Dual Role Source Side Application figure with ESD between device and receptacle....
44
Changes from Revision C (October 2019) to Revision D (March 2020)
Page
• Changed HDMI 2.0a to HDMI 2.0b ....................................................................................................................1
Changes from Revision B (June 2017) to Revision C (October 2019)
Page
• Deleted Feature: Both Extended Commercial and Industrial Temperature Device Options............................... 1
• Changed Feature: From: Pin Compatible to the SN65DP159RSB and SN75DP159RSB Retimer To: Pin
Compatible to the SN75DP159RSB Retimer......................................................................................................1
• Deleted TDP158I from the Device Information table.......................................................................................... 1
• Changed the TJ MIN value From: –40°C To: 0°C in the Recommended Operating Conditions table................ 6
• Deleted TA for TDP158I in the Recommended Operating Conditions table....................................................... 6
• Changed the last sentence of the Overview section to remove the TDP158I device....................................... 19
Changes from Revision A (January 2017) to Revision B (June 2017)
Page
• Changed the title From: "HDMI ™ Redriver" To: "HDMI ™ Level Shifter Redriver"............................................1
• Changed the Features List................................................................................................................................. 1
• Changed the Applications List............................................................................................................................ 1
2
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SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
Added text to pins 17, 23, 34, 16 in the Pin Functions table: "For pin control, Low = 1 kΩ pulldown resistor to
GND, High = 1 kΩ pullup resistor to VCC, NC = Floating" ................................................................................ 4
Added text to pin NC in the Pin Functions table: "Optionally connect 0.1 μF to GND to reduce noise"............. 4
VSADJ: Added Note "Reducing resistor ..", and Changed values in the Recommended Operating Conditions
table.................................................................................................................................................................... 6
Changed Rvsdj max value to 8 kΩ in Figure 6-1 ............................................................................................. 12
Changed the paragraph in the Operation Timing section................................................................................. 21
Added column Pin Number to Table 8-2, Changed IN_CLK → OUT_CLK To: IN_D2 → OUT_D2 in the last
row of the SWAP column.................................................................................................................................. 22
Changed Note 1 of Table 8-3 ...........................................................................................................................23
Changed the last two sentences of the paragraph in the pre-emphasis section.............................................. 26
Changed the title of Figure 8-6 From: 3.5 dB pre-emphasis in Normal Operation To: 6 dB pre-emphasis
Setting in Normal Operation............................................................................................................................. 26
Changed From: Reg0Ch[1:0] = 01 To: Reg0Ch[1:0] = 10 in Figure 8-7 .......................................................... 26
Changed the Default setting in Table 8-9 From: TBD To: 00000001................................................................ 30
Added paragraph to the Application and Implementation section: "TDP158 is designed ..."........................... 39
Changed the Application Information paragraph.............................................................................................. 39
Changed From: 0 Ω resistors To: 1 kΩ resistors, and a noise filter (capacitor) for the no connect in Figure 9-1
..........................................................................................................................................................................39
Added text "1 kΩ pulldown resistor " to the Connect values in Table 9-1 ........................................................ 40
Changed text in the second paragraph of the Source Side HDMI Application section From: "Control pins can
be tied directly to VCC, GND or left floating." To: "Control pins should be tied to 1 kΩ pullup to VCC, 1 kΩ
pulldown to GND, or left floating.".....................................................................................................................43
Changed From: 0 Ω resistors To: 1 kΩ resistors, and a noise filter (capacitor) for the no connect in Figure 9-5
..........................................................................................................................................................................43
Changed From: 0 Ω resistors To: 1 kΩ resistors, and a noise filter (capacitor) for the no connect in Figure 9-6
..........................................................................................................................................................................44
Changed From: 0 Ω resistors To: 1 kΩ resistors, and a noise filter (capacitor) for the no connect in Figure 11-2
..........................................................................................................................................................................47
Changes from Revision * (December 2016) to Revision A (January 2017)
Page
• Changed From: Preview To: Production data .................................................................................................... 1
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SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
VDD
SDA_SRC
SCL_SRC
VCC
OE
GND
SLEW
SDA_SNK
SCL_SNK
VDD
40
39
38
37
36
35
34
33
32
31
5 Pin Configuration and Functions
IN_D2p/n
1
30
OUT_D2n/p
IN_D2p/n
2
29
OUT_D2n/p
HPD_SRC
3
28
HPD_SNK
IN_D1p/n
4
27
OUT_D1n/p
IN_D1p/n
5
26
OUT_D1n/p
IN_D0p/n
6
25
OUT_D0n/p
IN_D0p/n
7
24
OUT_D0n/p
I2C_EN
8
23
A1/EQ2
IN_CLKp/n
9
22
OUT_CLKn/p
IN_CLKp/n
10
21
OUT_CLKn/p
11
12
13
14
15
16
17
18
19
20
VCC
VDD
SCL_CTL/SWAP
SDA_CTL/PRE
GND
TERM
A0/EQ1
VSADJ
NC
VDD
GND
Not to scale
Figure 5-1. RSB Package, 40-Pin WQFN (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
SUPPLY AND GROUND PINS
VCC
11, 37
P
3.3 V Power Supply
VDD
12,20,31,40
P
1.1 V Power Supply
GND
15, 35
Thermal Pad
G
Ground
MAIN LINK INPUT PINS
IN_D2p/n
1, 2
I
Channel 2 Differential Input
IN_D1p/n
4, 5
I
Channel 1 Differential Input
IN_D0p/n
6, 7
I
Channel 0 Differential Input
IN_CLKp/n
9, 10
I
Clock Differential Input
OUT_D2n/p
29, 30
O
TMDS Data 2 Differential Output
OUT_D1n/p
26, 27
O
TMDS Data 1 Differential Output
OUT_D0n/p
24, 25
O
TMDS Data 0 Differential Output
OUT_CLKn/p
21, 22
O
TMDS Data Clock Differential Output
MAIN LINK OUTPUT PINS (FAIL SAFE)
4
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Table 5-1. Pin Functions (continued)
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
HOT PLUG DETECT AND DDC PINS
HPD_SRC
3
O
Hot Plug Detect Output to source side
HPD_SNK
SDA_SNK
28
I
Hot Plug Detect Input from sink side
33
I/O
Sink Side Bidirectional DDC Data Line
SCL_SNK
32
I/O
Sink Side Bidirectional DDC Clock Line
SDA_SRC
39
I/O
Source Side Bidirectional DDC Data Line
SCL_SRC
38
I/O
Source Side Bidirectional DDC Clock Line
CONTROL PINS
OE
36
I
Operation Enable/Reset Pin
OE = L: Power Down Mode
OE = H: Normal Operation
Internal weak pullup: Resets device when transitions from H to L
I2C_EN
8
I
I2C_EN = High; Puts Device into I2C Control Mode
I2C_EN = Low; Puts Device into Pin Strap Mode
SDA_CTL/PRE
14
I/0
I2C Data Signal: When I2C_EN = High;
Pre-emphasis: When I2C_EN = Low: See Section 8.3.11
DE = L: None 0 dB
DE = H: 3.5 dB
SCL_CTL/SWAP
13
I
I2C Clock Signal: When I2C_EN = High;
Lane SWAP: When I2C_EN = Low: See Section 8.3.4 HDMI Mode Only
SWAP = L: Normal Operation
SWAP = H: Lane Swap
VSADJ
18
I
TMDS Compliant Voltage Swing Control (Nominal 6 kΩ for HDMI and DP combination;
6.49 kΩ for HDMI only)
A0/EQ1
17
I
3 Level
Address Bit 1 for I2C Programming when I2C_EN = High
EQ1 Pin Setting when I2C_EN = Low; Works in conjunction with A1/EQ2; See Section
8.3.5 for settings. For pin control, Low = 1 kΩ pulldown resistor to GND, High = 1 kΩ
pullup resistor to VCC, NC = Floating.
23
I
3 Level
Address Bit 2 for I2C Programming when I2C_EN = High
EQ2 Pin Setting when I2C_EN = Low; Works in conjunction with A0/EQ1; See Section
8.3.5 for settings. For pin control, Low = 1 kΩ pulldown resistor to GND, High = 1 kΩ
pullup resistor to VCC, NC = Floating.
I
3 Level
Clock Slew Rate Control: See Section 8.3.10
SLEW = L: Slowest ≅ 203 ps
SLEW = NC (Default): Mid-range 1 ≅ 180 ps
SLEW = H: Fastest ≅ 122 ps
For pin control, L = 1 kΩ pulldown resistor to GND, H = 1 kΩ pullup resistor to VCC, NC =
Floating.
Source Termination Cotnrol: See Section 8.3.8
TERM = H, 75 Ω ≅ 150 Ω
TERM = L, Transmit Termination impedance in 150 Ω ≅ 300 Ω
TERM = NC, No transmit Termination
Note: When TMDS_CLOCK_RATIO_STATUS bit = 1 the TDP158 sets source termination
to 75 Ω ≅ 150 Ω Automatically
For pin control, L = 1 kΩ pulldown resistor to GND, H = 1 kΩ pullup resistor to VCC, NC =
Floating.
A1/EQ2
SLEW
34
TERM
16
I
3 Level
NC
19
NA
(1)
No Connect. Optionally connect 0.1 μF to GND to reduce noise.
I= Input, O = Output, P = Power, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
Supply Voltage Range(3)
MIN
MAX
UNIT
VCC
–0.3
4
V
VDD
–0.3
1.4
V
0
1.56
V
Main Link Input Single Ended on Pin
–0.3
1.4
V
TMDS Output ( OUT_Dx)
–0.3
4
V
HPD_SRC, VSADJ, SDA_CTL/PRE, OE,
A1/EQ2, A0/EQ1, TERM, I2C_EN, SLEW,
SCL_CTL/SWAP, SDA_SRC, SCL_SRC
–0.3
4
V
HDP_SNK, SDA_SNK, SCL_SNK
–0.3
6
V
Main Link Input Differential Voltage (IN_Dx)
Voltage Range
Continuous power dissipation
See Section 6.4
Storage temperature, Tstg
(1)
(2)
(3)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply Voltage Nominal Value 3.3 V for DP mode
Supply Voltage Nominal Value 3.3 V for HDMI mode
NOM
MAX
UNIT
3
3.6
V
3.13
3.47
V
VDD
Supply Voltage Nominal Value 1.1 V
1
1.27
V
TJ
Junction temperature
0
105
°C
TA
Operating free-air temperature (TDP158)
0
85
°C
MAIN LINK DIFFERENTIAL PINS
VID(EYE)
Peak-to-peak input differential voltage See Figure 7-14
VID(DC)
The input differential voltage Peak-to peak DC level, See Figure 7-14
VIC
Input Common Mode Voltage (Internally Biased)
dR
Data rate
VSADJ
TMDS compliant swing voltage bias resistor (Nominal 6 kΩ for HDMI and
DP combination; 6.49 kΩ for HDMI only)(1)
75
1200
mV
200
1200
mV
0.5
0.9
0.25
6
Gbps
8
kΩ
5.5
V
3.6
V
4.5
V
DDC, I2C, HPD, AND CONTROL PINS
VI(DC)
DC Input Voltage
HDP_SNK, SDA_SNK, SCL_SNK,
SDA_SRC, SCL_SRC; All other Local I2C, and
control pins
6
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–0.3
–0.3
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SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VIL
NOM
MAX
UNIT
Low-level input voltage at DDC
0.3 x VCC
V
Low-level input voltage at HPD
0.8
V
Low-level input voltage at SDA_CTL/PRE, OE, A1/EQ2, A0/EQ1, TERM,
I2C_EN, SLEW, SCL_CTL/SWAP pins only
0.3
V
1.6
V
VIM
Mid-Level input voltage at A1/EQ2, A0/EQ1, TERM, SLEW pins only
VIH
High-level input voltage at OE, A1/EQ2, A0/EQ1, TERM, I2C_EN, SLEW
pins only
0.7 x VCC
High-level input voltage at SDA_SRC, SCL_SRC, SDA_CTL/PRE,
SCL_CTL/SWAP
0.7 x VCC
High-level input voltage at SDA_SNK, SCL_SNK
High-level input voltage at HPD
VOL
Low-level output voltage
VOH
High-level output voltage
fSCL
1.2
V
V
3.2
V
2
V
0.4
V
SCL clock frequency fast I2C mode for local I2C control
400
kHz
C(bus,DDC)
Total capacitive load for each bus line supporting 400 kHz (DDC terminals)
400
pF
C(bus,I2C)
Total capacitive load for each bus line (local I2C terminals)
100
pF
dR(DDC)
DDC Data rate
400
Kbps
IIH
High level input current
–30
30
µA
IIM
Mid level input current
–20
20
µA
IIL
Low level input current
–10
10
µA
IOZ
High impedance outpupt current
10
µA
R(OEPU)
Pull up resistance on OE pin
150
250
kΩ
(1)
2.4
V
Reducing resistor in VSADJ will increase VOD, care should be taking since resistors below ≅6 kΩ may lead to compliance failures.
6.4 Thermal Information
TDP158
THERMAL METRIC(1)
RSB (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
3.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.1
°C/W
RθJB
Junction-to-board thermal resistance
9.9
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
3.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
6.5 Electrical Characteristics, Power Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP(2)
MAX(1)
UNIT
200
350
mW
330
680
mW
PD1
Device power Dissipation
OE = H,VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
IN_Dx: VID_PP = 1200 mV, 6 Gbps
TMDS pattern, VI = 3.3 V, I2C_EN = L,
SDA_CTL/PRE = L, EQ1/EQ2 = H
PD2
Device power Dissipation in DPMode
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
IN_Dx: VID_PP = 400 mV, 5.4 Gbps DP
pattern, I2C_EN = H, VOD = 400 mV PRE
= 0 dB
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V , HPD = H, No input Signal: Stage 1 See
Section 10.2
34
mW
Stage 1: Standby Power
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/
1.27 V , HPD = H, Noise on input Signal:
Stage 2 See Section 10.2
60
mW
Stage 2: Standby Power
P(SD1)
Device power in PowerDown
OE = L, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
8
34
mW
P(SD2)
Device power in PowerDown in DPMode
OE = L, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
8
34
mW
8
20
mA
VCC Supply current
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS
pattern
I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2
= H,
45
110
mA
VCC Supply current in DP-Mode
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
IN_Dx: VID_PP = 400 mV, 5.4 Gbps DP
pattern, I2C_EN = H, VOD = 400 mV PRE
= 0 dB
160
220
mA
VDD Supply current
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS
pattern
I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2
=H
160
220
mA
VDD Supply current DP-Mode
OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27
V
IN_Dx: VID_PP = 400 mV, 5.4 Gbps DP
pattern, I2C_EN = H, VOD = 40 mV PRE =
dB
Stage 1: Standby current See
Section 10.2
OE = H, VCC = 3.3 V/3.6 V,
VDD = 1.1 V/1.27 V , HPD =
H: No signal on IN_CLK
3.3 V Rail
7
mA
1.1 V Rail
7
mA
OE = H, VCC = 3.3 V/3.6
V, VDD = 1.1 V/1.27 V ,
HPD = H: No valid signal on
IN_CLK
3.3 V Rail
Stage 2: Standby current See
Section 10.2
I(SD11)
PowerDown current – HDMI Mode
OE = L, VCC = 3.3 V/3.6 V,
3.3 V Rail
VDD = 1.1 V/1.27 V , or OE =
1.1 V Rail
H, HPD = L
I(SD2)
PowerDown current in DP-Mode
OE = L, VCC = 3.3 V/3.6 V,
VDD = 1.1 V/1.27 V
P(STBY1)
ICC1
ICC2
IDD1
IDD2
I(STBY1)
(1)
(2)
8
TEST CONDITIONS
7
mA
27
mA
1
7
mA
4
7
mA
3.3 V Rail
1
7
mA
1.1 V Rail
4
7
mA
1.1 V Rail
The maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted.
The typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted.
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6.6 Electrical Characteristics, Differential Input
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DR(RX_DATA)
TMDS data lanes data rate
DR(RX_CLK)
TMDS clock lanes clock rate
tRX_DUTY
Input clock duty circle
R(INT)
Input differential termination
impedance
V(TERM)
Input Common Mode Voltage
(1)
(2)
TEST CONDITIONS
MAX(1)
UNIT
0.25
6
Gbps
25
340
Mhz
MIN
TYP(2)
40%
50%
60%
80
100
120
OE = H
0.7
Ω
V
The maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted.
The typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted.
6.7 Electrical Characteristics, TMDS Differential Output
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOD(PP)
Output differential voltage before preemphasis; See Section 8.3.11
VOD(SS)
Steady state output differential voltage
See Section 8.3.11
IOS
Short circuit current limit
R(TERM)
Source Termination resistance for HDMI
2.0
TEST CONDITIONS
MIN
TYP(2)
MAX(1)
UNIT
VSADJ = 6 kΩ; SDA_CTL/PRE = H:
See Figure 7-4
600
1400
mV
VSADJ = 6 kΩ; SDA_CTL/PRE = H,
See Figure 7-4
350
720
mV
VSADJ = 5.5 kΩ; SDA_CTL/PRE = L,
See Figure 7-3
350
1000
mV
50
mA
150
Ω
Main link output shorted to GND
75
6.8 Electrical Characteristics, DDC, I2C, HPD, and ARC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(2)
MAX(1)
UNIT
DDC and I2C
VIL
SCL/SDA_CTL, SCL/SDA_SRC low
level input voltage
0.3 x VCC
V
VIH
SCL/SDA_CTL, input voltage
VCC + 0.5
V
VOL
SCL/SDA_CTL, SCL/SDA_SRC low
level output voltage
IO = 3 mA and VCC > 2 V
0.4
V
IO = 3 mA and VCC > 2 V
0.2 x VCC
V
VIH
High-level input voltage
HPD_SNK
VIL
Low-level input voltage
HPD_SNK
VOH
High-level output voltage
IOH = –500 µA; HPD_SRC,
VOL
Low-level output voltage
IOL = 500 µA; HPD_SRC,
Failsafe condition leakage current
VCC = 0 V; VDD = 0 V;
HPD_SNK = 5 V;
0.7 x VCC
HPD
ILKG
IH(HPD)
High level input current
R(pdHPD)
HPD input termination to GND
(1)
(2)
2.1
V
0.8
V
2.4
3.6
V
0
0.4
V
40
μA
Device powered; VIH = 5 V; IH(HPD)
includes R(pdHPD) resistor current
40
μA
Device powered; VIL = 0.8 V; IL(HPD)
includes R(pdHPD) resistor current
30
μA
220
kΩ
VCC = 0 V
150
190
The maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted.
The typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted.
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6.9 Electrical Characteristics, TMDS Differential Output in DP-Mode
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(1)
UNIT
V(TX_DIFFPP_LVL0)
Differential peak-to-peak output
voltage level 0
Based on default state of
V0_P0_VOD register
415
V
V(TX_DIFFPP_LVL1)
Differential peak-to-peak output
voltage level 1
Based on default state of
V1_P0_VOD register
660
V
V(TX_DIFFPP_LVL2)
Differential peak-to-peak output
voltage level 2
Based on default state of
V2_P0_VOD register
880
V
ΔVOD(L1L2)
Output peak-to-peak differential
voltage delta
ΔVODn = 20×log(VODL(n+1) /
VODL(n)) measured in compliance
with latest PHY CTS 1.2
V(TX_PRE_RATIO_0)
Pre-emphasis level 0
RBR, HBR and HBR2
V(TX_PRE_RATIO_1)
Pre-emphasis level 1
RBR, HBR and HBR2
2
4.2
dB
V(TX_PRE_RATIO_2)
Pre-emphasis level 2
RBR, HBR and HBR2
5
7.2
dB
ΔVPRE(L1L0)
Pre-emphasis delta
Measured in compliance with
latest PHY CTS 1.2
2
dB
1.6
dB
ΔVOD(L0L1)
ΔVPRE(L2L1)
(1)
1
6
dB
1
5
dB
0
dB
Does not support Level 3 swing or pre-emphasis.
6.10 Switching Characteristics, TMDS
PARAMETER
dR
Data rate
tT(DATA)
tT(CLOCK)
(1)
(2)
TEST CONDITIONS
Transition time (rise and fall time);
measured at 20% and 80%.
SDA_CTL = L, OE = H, All Data
Rates
Note: Data lane control by I2C only:
See Section 8.3.10
MIN
TYP(2)
250
MAX(1)
UNIT
6000
Mbps
Reg0Ah[1:0] = 11 (default)
60
ps
Reg0Ah[1:0] = 10
80
ps
Reg0Ah[1:0] = 01
95
ps
Reg0Ah[1:0] = 00
110
ps
TERM = H; Reg0Bh[7:6] = 11
122
ps
Reg0Bh[7:6] = 10
150
ps
TERM = L; Reg0Bh[7:6] = 00
180
ps
TERM = NC; Reg0Bh[7:6] = 01
203
ps
The maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted.
The typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted.
6.11 Switching Characteristics, HPD
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPD(HPD)
Propagation delay from HPD_SNK to
see Figure 7-8; not valid during
HPD_SRC; rising edge and falling
switching time
edge
tT(HPD)
HPD logical disconnected timeout
(1)
(2)
10
see Figure 7-9
MIN
TYP(2)
MAX(1)
40
120
2
UNIT
ns
ms
The Maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted
The Typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted
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6.12 Switching Characteristics, DDC and I2C
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Rise time of both SDA and SCL
signals
VCC = 3.3 V; See Figure 7-12
300
ns
tf
Fall time of both SDA and SCL
signals
See Figure 7-12
300
ns
tHIGH
Pulse duration , SCL high
See Figure 7-11
tLOW
Pulse duration , SCL low
tSU1
Setup time, SDA to SCL
tST, STA
tHD,STA
tHD,DAT
Data Hold Time
0
ns
tVD,DAT
Data valid time
0.9
µs
tVD,ACK
Data valid acknowledge time
0.9
µs
tST,STO
Setup time, SCL to stop condition
See Figure 7-10
0.6
μs
t(BUF)
Bus free time between stop and start
See Figure 7-10
condition
1.3
μs
0.6
μs
See Figure 7-11
1.3
μs
See Figure 7-11
100
ns
Setup time, SCL to start condition
See Figure 7-11
0.6
μs
Hold time, start condition to SCL
See Figure 7-10
0.6
μs
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900
180
800
160
700
140
600
120
Current (mA)
VOD (mV)
6.13 Typical Characteristics
500
400
300
1.1 V (mA)
3.3 V (mA)
100
80
60
200
40
100
20
0
0
4
5
6
Rvsadj (k:)
7
0
8
0.5
1
1.5
2
D001
Figure 6-1. VOD Swing vs VASDJ Resistor Value
2.5 3 3.5 4
Date Rate (Gbps)
4.5
5
5.5
6
D002
Figure 6-2. HDMI Current vs Data Rate
180
160
Current (mA)
140
120
100
80
60
40
20
0
1.4
2
2.6
3.2
3.8
Data Rate (Gbps)
4.4
5
5.4
D003
Figure 6-3. DisplayPort Current vs Data Rate
12
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7 Parameter Measurement Information
VTERM
3.3 V
50 Ÿ
50 Ÿ
75-200 nF
D+
VD+
50 Ÿ
50 Ÿ
0.5 pF
Receiver
VID
Y
Driver
VY
D75-200 nF
VD-
Z
VID = VD+ - VD-
VOD = VY - VZ
VICM = (VD+ + VD-)
2
VOC = (VY + VZ)
2
VZ
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. TMDS Main Link Test Circuit
4.0 V
Vcc
VID
2.6 V
VID+
VID(pp)
0V
VIDtPHL
tPLH
80%
80%
VOD
VOD(pp)
0V
20%
tf
20%
tr
Figure 7-2. Input or Output Timing Measurements
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VOD(SS)
PRE = L
Figure 7-3. Output Differential Waveform
PRE = L
PRE = H
VOD(PP)
VOD(SS)
Figure 7-4. Output Differential Waveform with De-Emphasis
14
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Avcc(4)
RT
Data +
Data -
Parallel (6)
BERT
Coax
Coax
SMA
RX
+EQ
SMA
FR4 PCB trace(1) &
AC coupling Caps
[No Preemphasis]
Clk+
Coax
Clk-
Coax
Coax
SMA
Coax
Device
Jitter Test
Instrument (2,3)
FR4 PCB trace
AVcc
RT
RX
+EQ
RT(5)
REF
Cable
EQ
OUT
SMA
SMA
SMA
SMA
Coax
SMA
Coax
OUT
RT
REF
Cable
EQ
Jitter Test
Instrument (2,3)
TTP1
TTP2
TTP4_EQ
TTP4
TTP3
TTP2_EQ
Copyright © 2016, Texas Instruments Incorporated
A.
B.
C.
D.
The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap, connector and another 1-8” of FR4.
Trace width – 4 mils. 100 Ω differential impedance.
All Jitter is measured at a BER of 109
Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP
AVCC = 3.3 V
E.
F.
RT = 50 Ω
The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.
Figure 7-5. HDMI Output Jitter Measurement
V
0
H
0
0.5
Figure 7-6. Output Eye Mask at TTP4_EQ for HDMI 2.0
TMDS Data Rate (Gbps)
H (Tbit)
3.4 < DR < 3.712
0.6
3.712 < DR < 5.94
–0.0332Rbit2
5.94 ≤ DR ≤ 6.0
V (mV)
335
–19.66Rbit2
+ 0.2312 Rbit + 0.1998
0.4
150
HPD Input
190 k
+ 106.74Rbit + 209.58
HPD Output
100 k
Figure 7-7. HPD Test Circuit
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VCC
HPD_SNK
50%
0V
tPD(HPD)
VCC
HPD_SRC
50%
0V
Figure 7-8. HPD Timing Diagram No. 1
Vcc
HPD_SNK
50%
0V
HPD_SRC
HPD Logical disconnect
Timeout
tT(HPD)
Vcc
0V
Device Logically
Connected
Logically
Disconnected
Figure 7-9. HPD Logic Disconnect Timeout
16
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tHD,STA
tf
tr
SCL
tST,STO
SDA
t(BUF)
START
STOP
Figure 7-10. Start and Stop Condition Timing
tHIGH
tLOW
SCL
tST,STA
SDA
tSU1
Figure 7-11. SCL and SDA Timing
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SDA_SRC/SCL_SRC
INPUT
½ VCC
tPLH1
tPHL1
SDA_SNK/SCL_SNK
OUTPUT
80%
½ VCC
20
%
tf
tr
Figure 7-12. DDC Propagation Delay – Source to Sink
SDA_SNK/SCL_SNK
INPUT
½ Vcc
tPHL2
tPLH2
80%
SDA_SRC/SCL_SRC
OUTPUT
20%
tf
½ Vcc
tr
Figure 7-13. DDC Propagation Delay – Sink to Source
VID(DC)
VID(EYE)
Figure 7-14. VID(DC) and VID(EYE)
18
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8 Detailed Description
8.1 Overview
The TDP158 is an AC-coupled digital video interface (DVI) or high-definition multimedia interface (HDMI) signal
input to Transition Minimized Differential Signal (TMDS) level shifting Redriver. The TDP158 supports four TMDS
channels, Hot Plug Detect, and a Digital Display Control (DDC) interfaces. The TDP158 supports signaling rates
up to 6 Gbps to allow for the highest resolutions of 4k2k60p 24 bits per pixel and up to WUXGA 16-bit color
depth or 1080p with higher refresh rates. For passing compliance and reducing system level design issues,
several features have been included such as TMDS output amplitude adjust using an external resistor on the
VSADJ pin, source termination selection, pre-emphasis, and output slew rate control. Device operation and
configuration can be programmed by pin strapping or I2C. Four TDP158 devices can be used on one I2C bus
when I2C_EN is high with device address set by A0/A1.
To reduce active power the TDP158 supports dual power supply rails of 1.1 V on VDD and 3.3 V on VCC. There
are several methods of power management such as going into power down mode using three methods:
1. HPD is low
2. Writing a 1 to register 09h[3]
3. De-asserting OE
De-asserting OE clears the I2C registers, thus once re-asserted, the device must be reprogrammed if I2C was
used for device setup. The TDP158 requires the source to write a 1 to the TMDS_CLOCK_RATIO_STATUS
register for the TDP158 to resume 75 Ω to 150 Ω source termination upon return to normal active operation
from re-asserted, OE, or re-asserted HPD. If this bit is already set as a one during the source to sink read, then
the TDP158 automatically sets this bit to 1. The SIG_EN register enables the signal detect circuit that provides
an automatic power-management feature during normal operation. When no valid signal is present on the clock
input, the device enters Standby mode. DDC link supports the HDMI 2.0b SCDC communication, 100 Kbps data
rate default and 400 Kbps adjustable by software.
TDP158 supports fixed EQ gain control to compensate for different lengths of input cables or board traces. The
EQ gain can be software adjusted by I2C control or pin strapping EQ1 and EQ2 pins. Customers can use the
TERM to change to one of three source termination impedances for better output performance when working in
HDMI 1.4b or HDMI 2.0b. When the TMDS_CLOCK_RATIO_STATUS bit is set to 1, the TDP158 automatically
switches in 75 Ω to 150 Ω source termination. To assist in ease of implementation, the TDP158 supports lanes
swapping, see Section 8.3.3. The device's available extended commercial temperature range is 0°C to 85°C.
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8.2 Functional Block Diagram
HPD_SRC
HPD_SNK
190 k
SIGNAL
DETECT
VBIAS
50
SIG_DET_
OUT
VSADJ
50
OUT_CLKp
TMDS
EQ
TERM
IN_CLKp
OUT_CLKn
IN_CLKn
VBIAS
50
50
IN_D[2:0]p
TMDS
IN_D[2:0]n
OUT_D[2:0]n
Enable
I2C_EN
EQ_CTL
EQ1
A0/EQ1
EQ2
A1/EQ2
TERM
OUT_D[2:0]p
EQ
Control Block, I2C Registers
MODE_TERM
SLEW
DE
Enable
SIG_DET_OUT
A0
A1
SDA
SDA_CTL/PRE
SCL
SCL_CTL/SWAP
PRE
OE
Local
I2C
Control
SLEW
TERM
DDC Snoop Block
SWAP
SDA_SRC
SDA_SNK
ACTIVE DDC BLOCK
SCL_SRC
SCL_SNK
1.1 V
VREG 3.3 V
VDD
VCC
GND
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Reset Implementation
When OE is low, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical
to transition the OE from a low level to high after the VCC supply has reached the minimum recommended
operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor connected
between OE and GND. To ensure the TDP158 is properly reset, the OE pin must be de-asserted for at least 100
μs before being asserted. When OE is re-asserted the TDP158 must be reprogrammed if it was programmed by
I2C and not pin strapping. When implementing the external capacitor, the size of the external capacitor depends
on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor.
Refer to the latest reference schematic for TDP158; consider approximately 0.1 µF capacitor as a reasonable
first estimate for the size of the external capacitor. Both OE implementations are shown in Figure 8-1 and Figure
8-2.
20
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OE
RRST = 200 k
C
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. External Capacitor Controlled OE
GPO
OE
C
Copyright © 2016, Texas Instruments Incorporated
Figure 8-2. OE Input from Active Controller
8.3.2 Operation Timing
TDP158 starts to operate after the OE signal is properly set after power up timing is complete. See Figure 8-3
and Table 8-1. Keeping OE low until VDD and VCC becomes stable avoids any timing requirements as shown in
Figure 8-3.
Control Signal
Td2
OE
Td1
Vdd
Vcc
Figure 8-3. Power Up Timing for TDP158
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Table 8-1. Power Up and Operation Timing Requirements
PARAMETER
DESCRIPTION
td1
VCC stable before VDD
td1
MIN
0
TYP
MAX
UNIT
200
µs
VDD and VCC stable before OE de-assertion
100
VDD(ramp)
VDD supply ramp up requirements
0.2
100
ms
µs
VCC(ramp)
VCC supply ramp up requirements
0.2
100
ms
8.3.3 Lane Control
The TDP158 has various lane control features. By default the high speed lanes are globally controlled. Pin
strapping can globally control features like receiver equalization, VOD swing and pre-emphasis. I2C programming
performs the same global programming using default configurations. Through I2C a method to control receive
equalization, transmitter swing (VOD) and pre-emphasis on each individual lane. Setting reg09h[5] = 1 puts the
device into independent lane configuration mode.
Reg31h[7:3] controls the clock lane, reg32h[7:3] controls lane D0, reg33h[7:3] controls lane D1 and reg34h[7:3]
controls lane D2 while Reg4E and Reg4F control the individual lane EQ control.
Note
If the swap function is enabled and individual lane control has been implemented, then it is
recommended to reprogram the lanes to make sure they match the expected results. Registers are
mapped to the pin name convention.
8.3.4 Swap
TDP158 incorporates a swap function which can swap the lanes, see Figure 8-4. The EQ, Pre-emphasis,
termination, and slew setup will follow the new mapping. This function can be used with the SCL_CTL/SWAP pin
13 when I2C_EN pin 8 is low or can be implemented using control the register 0x09h bit 7 and is only valid for
HDMI mode.
Table 8-2. Swap Functions
22
Normal Operation
SWAP = L or CSR 0x09h bit 7 is 1’b1
Pin Numbers
IN_D2 → OUT_D2
IN_CLK → OUT_CLK
[1, 2] → [30, 29]
IN_D1 → OUT_D1
IN_D0 → OUT_D0
[4, 5] → [27, 26]
IN_D0 → OUT_D0
IN_D1 → OUT_D1
[6, 7] → [25, 24]
IN_CLK → OUT_CLK
IN_D2 → OUT_D2
[9, 10] → [22, 21]
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DATA LANE2
SLLSEX2E – DECEMBER 2016 – REVISED JULY 2022
IN_D2p
CLOCK LANE
IN_D2p
1
30
OUT_D2p
2
29
OUT_D2n
IN_D2n
2
29
OUT_D2n
HPD_SRC
3
28
HPD_SNK
HPD_SRC
3
28
HPD_SNK
IN_D1p
4
27
OUT_D1p
IN_D1p
4
27
OUT_D1p
IN_D1n
5
26
OUT_D1n
IN_D0p
6
25
OUT_D0p
DATA LANE0
IN_D1n
DATA LANE0
OUT_D2p
CLOCK LANE
IN_D2n
DATA LANE1
30
1
IN_D0p
5
26
OUT_D1n
6
25
OUT_D0p
DATA LANE1
IN_D0n
7
24
OUT_D0n
IN_D0n
7
24
OUT_D0n
I2C_EN
8
23
A1/EQ2
I2C_EN
8
23
A1/EQ2
IN_CLKp
9
22
OUT_CLKp
IN_CLKp
9
22
OUT_CLKp
IN_CLKn
10
21
OUT_CLKn
DATA LANE2
IN_CLKn
10
21
OUT_CLKn
In Normal Working
Lane Swap
Figure 8-4. TDP158 Swap Function
8.3.5 Main Link Inputs
Standard Dual Mode DisplayPort terminations are integrated on all inputs with expected AC coupling capacitors
on board prior to input pins. External terminations are not required. Each input data channel contains an
equalizer to compensate for cable or board losses. The voltage at the input pins must be limited under the
absolute maximum ratings.
8.3.6 Receiver Equalizer
The equalizer is used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board
traces or cables. TDP158 supports fixed receiver equalizer by setting the A0/EQ1 and A1/EQ2 pins or through
I2C. Table 8-3 shows the pin strap settings and EQ values.
Table 8-3. Receiver EQ Programming and Values
Global
RX EQ
(dB)
Pin Control (1)
Independent Lane Control
I2C Control (2)
I2C Control
D1
P0_Reg4E[7:4]
D3
P0_Reg4F[3:0]
CLK(2) (3)
P0_Reg4F[7:4]
{EQ2,EQ1}
P0_Reg0D[6:3]
D2
P0_Reg4E[3:0]
2
2’b00
4’b0000
4’b0000
4’b0000
4’b0000
4’b0000
3
2’b0Z
4’b0001
4’b0001
4’b0001
4’b0001
4’b0001
4’b0010
4’b0010
4’b0010
4’b0010
4’b0010
4
5
2’b01
4’b0011
4’b0011
4’b0011
4’b0011
4’b0011
6.5
2’bZ0
4’b0100
4’b0100
4’b0100
4’b0100
4’b0100
4’b0101
4’b0101
4’b0101
4’b0101
4’b0101
4’b0110
4’b0110
4’b0110
4’b0110
4’b0110
4’b0111
4’b0111
4’b0111
4’b0111
4’b0111
7.5
8.5
2’bZZ
9
10
2’bZ1
4’b1000
4’b1000
4’b1000
4’b1000
4’b1000
11
2’b10
4’b1001
4’b1001
4’b1001
4’b1001
4’b1001
12
4’b1010
4’b1010
4’b1010
4’b1010
4’b1010
13
4’b1011
4’b1011
4’b1011
4’b1011
4’b1011
14
4’b1100
4’b1100
4’b1100
4’b1100
4’b1100
4’b1101
4’b1101
4’b1101
4’b1101
4’b1101
14.5
2’b1Z
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Table 8-3. Receiver EQ Programming and Values (continued)
RX EQ
(dB)
Global
Independent Lane Control
Pin Control (1)
I2C Control
I2C Control (2)
{EQ2,EQ1}
P0_Reg0D[6:3]
D2
P0_Reg4E[3:0]
D1
P0_Reg4E[7:4]
D3
P0_Reg4F[3:0]
CLK(2) (3)
P0_Reg4F[7:4]
4’b1110
4’b1110
4’b1110
4’b1110
4’b1110
4’b1111
4’b1111
4’b1111
4’b1111
4’b1111
15
15.5
(1)
(2)
(3)
2’b11
For Pin Control 0 = 1 kΩ pulldown resistor to GND, 1 = 1 kΩ pullup resistor to VCC, Z = Floating (No Connect)
Individual Lane control is based upon the pin names with no swap
The CLK EQ in HDMI mode is controlled by register P0_Reg0D[2:1]
8.3.7 Input Signal Detect Block
When SIG_EN is enabled through I2C the receiver looks for a valid HDMI clock signal input and is fully functional
when a valid signal is detected. If no valid HDMI clock signal is detected, then the device enters standby mode
waiting for a valid signal at the clock input. All of the TMDS outputs and IN_D[0:2] are in high-Z status. HDMI
signal detect circuit is default enabled. If there is a loss of signal, then reg20h[5] can be read to determine if the
TDP158 has detected a valid signal or not.
8.3.8 Transmitter Impedance Control
HDMI 2.0 standard requires a source termination impedance in the 75 Ω to 150 Ω range for data rates > 3.4
Gbps. HDMI 1.4b requires no source termination but has a provision for using 150 Ω to 300 Ω for higher data
rates. The TDP158 has three termination levels that are selectable using pin 16 when programming through pin
strapping or when using I2C programming through reg0Bh[4:3]. When the TMDS_CLOCK_RATIO_STATUS bit,
reg0Bh[1] = 1 the TDP158 automatically turns on the 75 Ω to 150 Ω source termination otherwise the termination
must be selected. See Table 8-4.
Table 8-4. Source Termination Control Table
Pin 16
Reg0Bh[4:3]
Source Termination
TERM = L
00
150 Ω ≅ 300 Ω
TERM = NC
01
None
10
Automatic set based upon TMDS_CLOCK_RATIO_STATUS bit
11
75 Ω ≅ 150 Ω
TERM = H
Note
If the TMDS_CLOCK_RATIO_STATUS bit = 1, then the TDP158 automatically switches in 75 Ω ≅ 150
Ω termination.
24
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8.3.9 TMDS Outputs
A 1% precision resistor, connected from VSADJ pin to ground is recommended to allow the differential output
swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current sink
capability, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor.
VCC
AVCC
TDP158
Zo = RT
Zo = RT
Figure 8-5. TMDS Driver and Termination Circuit
Referring to Figure 8-5, if VCC (TDP158 supply) and AVCC (sink termination supply) are both powered, the
TMDS output signals are high impedance when OE = low. Both supplies being active is the normal operating
condition. A total of approximately 33-mW of power is consumed by the terminations independent of the OE
logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed.
When the power source of the device is off and the power source to termination is on, the IO(off), output leakage
current, specification ensures the leakage current is limited 45-μA or less. The clock and data lanes VOD can be
changed through I2C reg0Ch[7:2], VSWING_DATA and VSWING_CLK.
8.3.10 Slew Rate Control
As the clock signal tends to be a primary source of EMI, the TDP158 provides the ability to slow down the TMDS
output edge rates. There are two ways of changing the slew rate, Pin strapping for clock lane and I2C for both
clock and data lanes. Refer to Section 6.10
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8.3.11 Pre-Emphasis
The TDP158 provides pre-emphasis on the data lanes allowing the output signal pre-conditioning to offset
interconnect losses between the TDP158 outputs and a TMDS receiver. Pre-emphasis is not implemented on
the clock lane unless the TDP158 is in DP mode; at which time, it becomes a data lane. The default value
for pre-emphasis is 0 dB. There are two methods to implement pre-emphasis, pin strapping or through I2C
programming. When using pin strapping, the SDA_CTL/PRE pin controls global pre-emphasis values of 0 dB or
3.5 dB. Through I2C, reg0Ch[1:0] pre-emphasis values are 0 dB, 3.5 dB, and 6 dB. The 6 dB value has different
meanings when the device is in normal operational mode (reg09h[5] = 0) or when the TDP158 has been put into
DP-mode (reg09h[5] = 1). As Figure 8-6 shows, the 6 dB pre-emphasis setting will result in an output of 3 dB
of pre-emphasis with 3 dB of de-emphasis when device is in normal HDMI operation. As Figure 8-7 shows, the
output will be about 5 dB pre-emphasis with a 1 db de-emphasis when selecting 6 dB pre-emphasis setting for
DP-mode. VOD(PP) value will not go above 1 V.
Reg0Ch[1:0] = 00
Reg0Ch[1:0] = 10
VOD(PP)
VOD(SS)
Figure 8-6. 6 dB Pre-Emphasis Setting in Normal Operation
Reg0Ch[1:0] = 00
Reg0Ch[1:0] = 10
VOD(PP)
VOD(SS)
Figure 8-7. 6 dB Pre-Emphasis in DP-Mode
26
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Table 8-5. Swing and Pre-Emphasis Programming Based Upon 6 kΩ VSADJ Resistor
Global Control
Mode
Reg09h[6]
Lane CTL
Reg09[5]
Mode CTL
Independent Lane Control
P0_Reg0C[7:0]
Reg09h[6]
Lane CTL
Reg09[5]
Mode CTL
P0_Reg0C[7:0]
8’h00
HDMI
0
0
8’h00
1
0
DP SWG0, PRE0
0
1
8’h80
1
1
8’h80
DP SWG0, PRE1
0
1
8’hC1
1
1
8’hC1
DP SWG0, PRE2
0
1
8’h42
1
1
8’h42
DP SWG1, PRE0
0
1
8’hC0
1
1
8’hA0
DP SWG1, PRE1
0
1
8’hF1
1
1
8’h21
DP SWG1, PRE2
0
1
8’h52
1
1
8’h62
DP SWG2, PRE0
0
1
8’h20
1
1
8’h00
DP SWG2, PRE1
0
1
8’h51
1
1
8’h61
8.3.12 DP-Mode Description
The TDP158 has the ability to perform as a DisplayPort redriver under the right conditions. The TDP158 is put
into this mode by setting reg09h[5] to 1. The device is now programmable through I2C only. As the transmitter
is a DC coupled transmitter supporting TMDS some external circuits are required to level shift the signal to an
AC-coupled DisplayPort signal, see Figure 9-6. Note that the AUX lines bypass the TDP158. To set the device
up correctly during link training, the TDP158 must be programmed using I2C. When this bit is set, the TDP158
does the following:
• Ignore SWAP function
• Ignore SIG_EN function
• Enable all four lanes and set to support 5.4 Gbps data rate
• Sets VOD swing to the lowest level based on a 6 kΩ VSADJ resistor value
• Sets pre-emphasis to 0 dB
• Defaults to global lane control
• Can be set to independent lane control by setting P0_Reg09[6] to a 1. This should be done after
implementing DP mode. Individual Lane control starts on P0_Reg30 through P0_Reg34 and also P0_Reg4E
and 4F
For the system implementer to configure the TDP158 output to the properly requested levels during link training,
the following registers are used.
• Reg0Ch[7:5] is a global VOD swing control for all four lanes, see Table 8-5
• Reg0Ch[1:0] is a global Pre-emphasis control for all four lanes, see Table 8-5. This register works with
Reg30h[7:6]
• Reg0D[6:3] is a global EQ control for all four lanes
• Reg30h[7:6] is to let the TDP158 know what the data rate is. This is used for the delay component for
pre-emphasis signal.
• Reg30h[5:2] is used to turn on or off individual lanes
Power down states while in DP-Mode are implemented the same as if in normal operation. See the Section 6.7
for the outputs based upon the VSADJ 6 kΩ VSADJ resistor.
8.4 Device Functional Modes
8.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
As part of discovery, the source reads the sink E-EDID information to understand the sink’s capabilities.
The supported data rate comes from the HDMI Forum Vendor Specific Data Block (HF-VSDB)
MAX_TMDS_Character_Rate byte. Depending upon the value, the source will write to target address 0xA8
offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The TDP158 snoops the DDC link to determine the TMDS
clock ratio status and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a ‘1’ is written by the
source the TMDS clock is 1/40 of TMDS bit period. If a ‘0’ is written, then the TMDS clock is 1/10 of TMDS bit
period.
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The TDP158 will always default to 1/10 of TMDS bit period unless a ‘1’ is written to address 0xA8 offset 0x20
bit 1 or during a read by the source this bit is set. This helps determine source termination when automatic
source termination select is enabled. Otherwise this bit has no other impact on the TDP158. When HPD_SNK is
de-asserted this bit is reset to default values of 0 if this feature is enabled. If the source does not write this bit to
the sink or during the read the bit is not set the TDP158 will not set the output termination to 75 Ω to 150 Ω in
support of HDMI 2.0. If the TDP158 has entered a power down state using HDP_SNK = low or OE = low this bit
is cleared and will be set on a read or write where this bit is set. When DDC_TRAIN_SETDISABLE is 1’b0 the
TMDS_CLOCK_RATIO_STATUS bit will reflect the value of the DDC snoop. When DDC_TRAIN_SETDISABLE
is 1’b1 the TMDS_CLOCK_RATIO_STATUS bit is set by I2C and DDC snoop is ignored and thus automatic
TERM control is ignored and must be manually set. To go back to snoop and automatic TERM control the
DDC_TRAIN_SETDISABLE bit has to be cleared and TERM set back to automatic control.
8.4.2 DDC Functional Description
The TDP158 solves sink/source level issues by implementing a controller/target control mode for the DDC
bus. When the TDP158 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC it transfers
the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the
feedback from the downstream device, the TDP158 pulls up or pulls down the SDA_SRC bus and delivers the
signal to the source.
The DDC link defaults to 100 Kbps but can be set to various values including 400 Kbps by setting the correct
value to address 22h through the I2C interface. The HPD goes to high impedance when VCC is under low power
conditions, < 1.5 V.
Note
The TDP158 uses clock stretching for DDC transactions. As there are sources and sinks that
do not perform this function correctly, a system may not work correctly as DDC transactions
are incorrectly transmitted/received. To overcome this, a snoop configuration can be implemented
where the SDA/SCL from the source is connected directly to the SDA/SCL pins. The TDP158
needs the SDA_SNK and SCL_SNK pins connected to the sink DDC pins so that the
TMDS_CLOCK_RATIO_STATUS bit can be automatically set; otherwise, it will have to be set through
I2C. For best noise immunity, the SDA_SRC and SCL_SRC pins should be connected to GND. Care
must be taken when this configuration is being implemented as the voltage level for DDC between the
source and sink may be different, 3.3 V versus 5 V.
8.5 Register Maps
The TDP158 local I2C interface is enabled when I2C_EN is high. The SCL_CTL and SDA_CTL terminals are
used for I2C clock and data respectively. The TDP158 I2C interface conforms to the two-wire serial interface
defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to
400 Kbps. The device address byte is the first byte received following the START condition from the controller
device. The 7 bit device address for TDP158 decides by the combination of A0/EQ1 and A1/EQ2. Table 8-6
clarifies the TDP158 target address.
Table 8-6. TDP158 I2C Device Address Description
A1/A0
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
HEX
00
1
0
1
1
1
1
0
0/1
BC/BD
01
1
0
1
1
1
0
1
0/1
BA/BB
10
1
0
1
1
1
0
0
0/1
B8/B9
11
1
0
1
1
0
1
1
0/1
B6/B7
The local I2C is 5-V tolerant, and no additional circuitry required. Local I2C buses run at 400 kHz supporting
fast-mode I2C operation.
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The following procedure is followed to write to the TDP158 I2C registers:
1. The controller initiates a write operation by generating a start condition (S), followed by the TDP158 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TDP158 acknowledges the address cycle.
3. The controller presents the sub-address (I2C register within TDP158) to be written, consisting of one byte of
data, MSB-first.
4. The TDP158 acknowledges the sub-address cycle.
5. The controller presents the first byte of data to be written to the I2C register.
6. The TDP158 acknowledges the byte transfer.
7. The controller may continue presenting additional bytes of data to be written, with each byte transfer
completing with an acknowledge from the TDP158.
8. The controller terminates the write operation by generating a stop condition (P).
The following procedure is followed to read the TDP158 I2C registers:
1. The controller initiates a read operation by generating a start condition (S), followed by the TDP158 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The TDP158 acknowledges the address cycle.
3. The TDP158 transmit the contents of the memory registers MSB-first starting at register 00h.
4. The TDP158 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller
after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
5. If an ACK is received, the TDP158 transmits the next byte of data.
6. The controller terminates the read operation by generating a stop condition (P).
Note
Upon reset, the TDP158 sub-address will always be set to 0x00. When no sub-address is included
in a read operation, the TDP158 sub-address will increment from previous acknowledged read or
write data byte. If it is required to read from a sub-address that is different from the TDP158 internal
sub-address, a write operation with only a sub-address specified is needed before performing the read
operation.
Refer to Section 8.5.1 for TDP158 local I2C register descriptions. Reads from reserved fields or addresses that
are not specified return zeros. The value written to reserved fields must match the value read from the reserved
field to not impact device features or performance.
8.5.1 Local I2C Control BIT Access TAG Convention
Reads from reserved fields shall return zero, and writes to read-only reserved registers shall be ignored. Writes
to reserved register which are marked with ‘W’ will produce unexpected behavior. All addresses not defined by
this specification shall be considered reserved. Reads from these addresses shall return zero and writes shall be
ignored.
8.5.2 BIT Access Tag Conventions
A table of bit descriptions is typically included for each register description that indicates the bit field name, field
description, and the field access tags. The field access tags are described in Table 8-7.
Table 8-7. Field Access Tags
Access Tag
Name
R
Read
The field shall be read by software
W
Write
The field shall be written by software
S
Set
C
Clear
U
Update
NA
No Access
DESCRIPTION
The field shall be set by a write of one. Writes of Zero to the field have no effect
The field shall be cleared by a write of one. Writes of Zero to the field have no effect
Hardware may autonomously update this field
Not accessible or not applicable
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8.5.3 CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
Figure 8-8. DEVICE_ID
7
6
5
4
3
2
1
0
DEVICE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-8. DEVICE_ID Field Descriptions
Bit
Field
Type
7:0
Default
Description
These fields return a string of ASCII characters “TDP158”
followed by one space characters
TDP158: Address 0x00 – 0x07 = {- 0x54”T”, 0x44”D”, 0x50”P”,
0x31”1”, 0x35”5”, 0x38”8, 0x20, 0x20
R
8.5.4 CSR Bit Field Definitions, REV_ID (address = 08h )
Figure 8-9. REV_ID Field Descriptions
7
6
5
4
3
2
1
0
REV_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-9. REV_ID
Bit
Field
Type
Default
Description
7:0
REV_ID
R
00000001
This field identifies the device revision.
00000001 – TDP158 Revision
8.5.5 CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
Figure 8-10. MISC CONTROL 09h Field Descriptions
7
6
5
4
3
2
1
LANE_SWAP
Lane Control
DP-Mode
SIG_EN
PD_EN
HPD_AUTO_P
WRDWN_DISA
BLE
R/W
R/W
R/W
R/W
R/W
R/W
0
I2C_DR_CTL
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-10. MISC CONTROL 09h
Bit
7
6
5
30
Field
LANE_SWAP
Lane Control
DP-Mode
Type
R/W
R/W
R/W
Default
Description
1’b0
This field Swaps the input lanes as per Figure 8-4 and Section
8.3.4 and valid when in HDMI mode only.
0 − Disable (default) No Lane Swap
1 − Enable: Swaps both Input and Output Lanes
1’b0
See Section 8.3.3
0 – Global (Default)
1 – Independent
Note: In default mode reg0C and reg0D control all lanes. When
set to 1 each lane can be individually controlled for Swing, EQ,
Pre-emphasis.
1’b0
See Section 8.3.12
0 – Normal DP158 Operation (Default)
1 – All lanes behave as data lanes and full control through I2C
only
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Table 8-10. MISC CONTROL 09h (continued)
Bit
Field
Type
Default
Description
4
SIG_EN
R/W
1’b1
This field enables the clock lane activity detect circuitry. See
Section 8.3.7
0 – Disable Clock detector circuit closed and receiver always
works in normal operation.
1 – Enable (default), Clock detector circuit will make the receiver
automatically enter the standby state when no valid data detect.
3
PD_EN
R/W
1’b0
0 – Normal working (default)
1 – Forced Power down by I2C, Lowest Power state
2
HPD_AUTO_PWRDWN_DISABL
R/W
1’b0
0 – Automatically enters Power Down mode based on
HPD_SNK (default)
1 – Will not automatically enter Power Down mode
2’b10
I2C data rate supported for configuring device.
00 – 5 Kbps
01 – 10 Kbps
10 – 100 Kbps( Default )
11 – 400 Kbps
1:0
I2C_DR_CTL
R/W
8.5.6 CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
Figure 8-11. MISC CONTROL 0Ah Field Descriptions
7
6
Reserved
HPDSNK_GAT
E_EN
5
4
Reserved
3
2
SLEW_CTL_DATA
1
0
R
R/W
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-11. MISC CONTROL 0Ah
Bit
7
6
5:2
1:0
Field
Type
Default
Description
Reserved
R
1’b0
Reserved
HPDSNK_GATE_EN
R/W
1’b0
The field set the HPD_SNK signal pass through to HPD_SRC or
not and HPD_SRC whether held in the de-asserted state.
0 – HPD_SNK passed through to the HPD_SRC (default)
1 – HPD_SNK will not pass through to the HPD_SRC.
Reserved
R
4’b0000
Reserved
2’b11
See Section 8.3.10
00 – Slowest ≅ 110
01 – Mid-Range 1 ≅ 95
10 – Mid-Range 2 ≅ 80 ps
11 – Fastest (Default) ≅ 60 ps
Values are typical
SLEW_CTL_DATA
R/W
8.5.7 CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
Figure 8-12. MISC CONTROL 0Bh Field Descriptions
7
6
SLEW_CTL_CLK
5
4
3
2
Reserved
TERM
DDC_DR_SEL
R
R/W
R/W
R/W
1
0
TMDS_CLOCK DDC_TRAIN_S
_RATIO_STATU ETDISABLE
S
R/W/U
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-12. MISC CONTROL 0Bh
Bit
Field
7:6
5
4:3
2
1
Type
Description
SLEW_CTL_CLK
R/W
2’b01
See Section 8.3.10
00 – Slowest ≅ 215 ps
01 – Mid-Range 1 (Default) ≅ 185 ps
10 – Mid-Range 2 ≅ 155 ps
11 – Fastest ≅ 125 ps
Values are typical
Reserved
R
1’b0
Reserved
TERM
R/W
2’b10
Controls termination for HDMI TX. See Section 8.3.8
00 – 150 to 300 Ω
01 – No termination
10 – Follows TMDS_CLOCK_RATIO_STATUS bit (default).
When = 1 termination value is 75 to 150 Ω:
When = 0 No termination
11 – 75 to 150 Ω:
Note: When TMDS_CLOCK_RATIO_STATUS bit reg0Bh[1] = 1
this register will automatically be set to 11 for 75 to 150 Ω but
can be overwritten using this address
DDC_DR_SEL
R/W
1’b0
Defines the DDC output speed for DDC bridge
0 – 100 Kbps (default)
1 – 400 Kbps
1’b0
This field is updated from snoop of I2C write to target
address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/
SCL_SRC interface. When bit 1 of address 0xA8 offset 0x20 is
written to a 1’b1 or read as a 1’b1, then this field will be set to a
1’b1. When bit 1 of address 0xA8 offset 0x20 is written to a 1’b0,
then this field will be set to a 1’b0. This field is reset to default
value whenever HPD_SNK is de-asserted for greater than 2 ms.
The main function of this bit is to automatically set the proper TX
termination when value = 1.
0 – HDMI 1.4b (default)
1 – HDMI 2.0
Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 this bit will
reflect the value of the DDC snoop.
Note 2. When DDC_TRAIN_SETDISABLE is 1’b1 this bit is set
by I2C and DDC snoop is ignored. If this bit was set to 1 during
snoop prior to the DDC_TRAIN_SETDISABLE being set to 1 it
will be cleared to 0.
1’b0
This field indicate the DDC training block function status.
0 – DDC training enable (default)
1 – DDC training disable –DDC snoop disabled
Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 the
TMDS_CLOCK_RATIO_STUATU bit will reflect the value of the
DDC snoop.
Note 2. When DDC_TRAIN_SETDISABLE is 1’b1, this bit is
set by I2C and DDC snoop is ignored and thus automatic
TERM control is ignored and must be manually set and
TMDS_CLOCK_RATIO_STATUS bit will be cleared.
Note 3. To go back to snoop and automatic TERM control this bit
has to be cleared and TERM set back to automatic control.
TMDS_CLOCK_RATIO_STATUS
0
Reset
DDC_TRAIN_SETDISABLE
R/W/U
R/W
8.5.8 CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
Figure 8-13. MISC CONTROL 0Ch Field Descriptions
7
6
5
4
3
2
1
0
VSWING_DATA
VSWING_CLK
HDMI _TWPST1[1:0]
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
32
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Table 8-13. MISC CONTROL 0Ch
Bit
Field
7:5
Type
VSWING_DATA
4:2
R/W
VSWING_CLK
1:0
R/W
HDMI _TWPST1[1:0]
R/W
Reset
Description
3’b000
Data Output Swing Control
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%
3’b000
Clock Output Swing Control: Default is set by Vsadj resistor
value and the value of reg0Dh[0].
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 14% 011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%
2’b00
HDMI Pre-emphasis
00 – No Pre-emphasis (default)
01 – 3.5 dB 10 – 6 dB
11 – Reserved
NOTE: See Pre-emphasis Section for 6 dB explanation during
normal operation supporting HDMI
8.5.9 CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
Figure 8-14. Equalization Control Register
7
6
5
4
3
2
1
Reserved
Data Lane Fixed EQ Values
Clock EQ Values
R
R/W
R/W
0
DIS_HDMI
2_SWG
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-14. Equalization Control Register Field Descriptions
Bit
7
6:3
2:1
0
Field
Type
Reset
Description
Reserved
R
1’b0
Reserved
Data Lane Fixed EQ Values
R/W
4’b0000
(Section Section 8.3.6 and Table 8-3 for values)
0000 – 0 dB (default)
2’b00
00 – 0 dB (default)
01 – 1.5 dB
10 – 3 dB
11 – 4.5 dB
1’b0
Disables halving the clock output swing when entering HDMI 2.0
mode from TMDS_CLOCK_RATIO_STATUS.
0 – Disables TMDS_CLOCK_RATIO_STATUS control of the
clock VOD so output swing is at full swing (default)
1 – Clock VOD is half of set values when
TMDS_CLOCK_RATIO_STATUS states in HDMI 2.0 mode
Clock EQ Values
DIS_HDMI 2_SWG
R/W
R/W
8.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
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Figure 8-15. POWER MODE STATUS
7
6
5
Power Down
Status Bit
Standby Status
Bit
Loss of Signal
Status Bit –
LOS
4
3
Reserved
2
1
R/U
R/U
R/U
R
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-15. POWER MODE STATUS Field Descriptions
Bit
Field
Type
Reset
Description
7
Power Down Status Bit
R/U
1’b0
0 – Normal Operation
1 – Device in Power Down Mode.
6
Standby Status Bit
R/U
1’b0
0 – Normal Operation
1 – Device in Standby Mode
5
Loss of Signal Status Bit – LOS
R/U
1’b0
0 – Clock present
1 – No Clock present
Reserved
R
5’b00000
Reserved
4:0
8.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
See Section 8.3.12 and Section 8.3.3. Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set
to one.
Figure 8-16. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
Data Rate Select
R/W
R/W
5
4
3
2
Clock Lane
Lane D0
Lane D1
Lane D2
1
Reserved
0
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-16. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Data Rate Select
R/W
2’b00
00 – 5.4 Gbps (default)
01 – 2.7 Gbps
10 – 1.62 Gbps
11 - Reserved
5
Clock Lane
R/W
1’b1
0 – Disabled
1 – Enabled (default)
4
Lane D0
R/W
1’b1
0 – Disabled
1 – Enabled (default)
3
Lane D1
R/W
1’b1
0 – Disabled
1 – Enabled (default)
2
Lane D2
R/W
1’b1
0 – Disabled
1 – Enabled (default)
1:0
Reserved
R
2’b00
Reserved
8.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one.
Figure 8-17. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
VOD Swing Adjust for CLK Lane
34
5
4
3
Pre-emphasis Adjust for CLK
Lane
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1
0
Reserved
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Figure 8-17. DP-Mode and INDIVIDUAL LANE CONTROL (continued)
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-17. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
7:5
Type
VOD Swing Adjust for CLK Lane
R/W
Reset
Description
3’b000
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%
Note: reg09h[6] = 1 otherwise all lanes are global control.
4:3
Pre-emphasis Adjust for CLK Lane
R/W
2’b00
00 – No Pre-emphasis (default)
01 – 3.5 dB Pre-emphasis.
10 – 6 dB Pre-emphasis
11 – Reserved
Note 1. reg09h[6] = 1 otherwise all lanes are global control.
Note 2. If in HDMI mode writes will be ignored and reg09h[7]
SWAP = 0. No pre-emphasis on clock.
2:0
Reserved
R/W
3’b000
Reserved
8.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one
Figure 8-18. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
VOD Swing Adjust for D0 Lane
Pre-emphasis Adjust for D0 Lane
Reserved
R/W
R/W
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
7:5
Field
VOD Swing Adjust for D0 Lane
Type
R/W
Reset
Description
3’b000
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
11 – Decrease by 7%
Note: reg09h[6] = 1 otherwise all lanes are global control.
4:3
Pre-emphasis Adjust for D0 Lane
R/W
2’b00
00 – No Pre-emphasis (default)
01 – 3.5 dB Pre-emphasis.
10 – 6 dB Pre-emphasis
11 – Reserved
Note: reg09h[6] = 1 otherwise all lanes are global control.
2:0
Reserved
R/W
3’b000
Reserved
8.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one
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Figure 8-19. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
VOD Swing Adjust for D1 Lane
Pre-emphasis Adjust for D1 Lane
Reserved
R/W
R/W
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
7:5
Type
VOD Swing Adjust for D1 Lane
R/W
Reset
Description
3’b000
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
11 – Decrease by 7%
Note: reg09h[6] = 1 otherwise all lanes are global control.
4:3
Pre-emphasis Adjust for D1 Lane
R/W
2’b00
00 – No Pre-emphasis (default)
01 – 3.5 dB Pre-emphasis.
10 – 6 dB Pre-emphasis
11 – Reserved
Note: reg09h[6] = 1 otherwise all lanes are global control.
2:0
Reserved
R/W
3’b000
Reserved
8.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one
Figure 8-20. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
VOD Swing Adjust for D2 Lane
Pre-emphasis Adjust for D2 Lane
Reserved
R/W
R/W
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-20. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
7:5
36
Field
VOD Swing Adjust for D2 Lane
Type
R/W
Reset
Description
3’b000
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
11 – Decrease by 7%
Note: reg09h[6] = 1 otherwise all lanes are global control.
4:3
Pre-emphasis Adjust for D2 Lane
R/W
2’b00
00 – No pre-emphasis (default)
01 – 3.5 dB pre-emphasis
10 – 6 dB pre-emphasis
11 – Reserved
Note 1. reg09h[6] = 1 otherwise all lanes are global control.
Note 2. If in HDMI mode writes will be ignored and reg09h[7]
SWAP = 1. No pre-emphasis on clock.
2:0
Reserved
R/W
3’b000
Reserved
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8.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one
Figure 8-21. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-21. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
‘h00
Reserved
8.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one
Figure 8-22. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-22. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
‘h00
Reserved
8.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
See Section Section 8.3.12 and Section 8.3.3 Note: DP-Mode is valid only when DP-Mode Register
P0_Reg09[5] is set to one
Figure 8-23. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
Data Lane 1 Fixed EQ Values
Data Lane 2 Fixed EQ Values
R/W
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
Type
Reset
Description
7:4
Data Lane 1 Fixed EQ Values
R/W
4’b0000
Section 8.3.6 and Table 8 2 for values
0000 – 0 dB (default)
3:0
Data Lane 2 Fixed EQ Values
R/W
4’b0000
Section 8.3.6 and Table 8 2 for values
0000 – 0 dB (default)
8.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
See Section 8.3.12 and Section 8.3.3. Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set
to one
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Figure 8-24. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
CLK Lane Fixed EQ Values
Data Lane 0 Fixed EQ Values
R/W
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
38
Bit
Field
Type
Reset
Description
7:4
CLK Lane Fixed EQ Values
R/W
4’b0000
Section 8.3.6 and Table 8 2 for values
0000 – 0 dB (default)
3:0
Data Lane 0 Fixed EQ Values
R/W
4’b0000
Section 8.3.6 and Table 8 2 for values
0000 – 0 dB (default)
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TDP158 was designed to work mainly in source applications such as Blu-Ray DVD players, gaming
systems, desktops, notebooks, or AVRs. The following sections provide design consideration for various types of
applications.
9.2 Typical Application
Figure 9-1 provides a schematic representation of what is considered a standard implementation.
0.1 µF
4
0.1 µF
5
IN_D2n
ML1p
OUT_D2n
27
OUT_D1p
IN_D1p
ML1n
0.1 µF
6
ML2p
26
0.1 µF
IN_D0n
0.1 µF
24
9
OUT_CLKp
3
38
39
DDC_SCL
DDC_SCL
DDC_SDA
DDC_SCA
2 k
GND5
TMDS_D0n
GND6
14
17
CEC
20
CASE_GND1
21
15
SCL_SNK
33
DDC_SCL
28
DDC_SCA
SDA_SNK
SDA_SRC
TMDS_D0p
11
13
CEC
32
SCL_SRC
GND4
TMDS_CLKn
2 k
HPD_SRC
GND3
TMDS_D1n
TMDS_CLKp
5V
IN_CLKn
HPD
TMDS_D1p
5
8
12
OUT_CLKn
10
ML3n
GND2
10
21
IN_CLKp
0.1 µF
7
22
9
ML3p
25
OUT_D0n
7
ML2n
TMDS_D2n
6
OUT_D0p
IN_D0p
GND1
4
OUT_D1n
IN_D1n
2
TMDS_D2p
3
29
ESD
2
OUT_D2p
ESD
0.1 µF
1
30
IN_D2p
ML0n
Dual Mode GPU/DP TX
or AC coupled HDMI TX
HDMI/DVI Receptacle
1
DDC_SCL
CASE_GND2
DDC_SDA
CASE_GND3
16
ESD
0.1 µF
ML0p
22
19
23
HPD
HPD_SNK
CASE_GND4
VCC_3.3 V
VCC_3.3 V
0.01 µF
CAD_DET
2 k
2 k
13
SCL_CTL/SWAP
I2C_SCL
0
0
0 kΩ
14
I2C_SDA
I2C_EN
NOTE: Connector side DDC is 5 V
while GPU may require 3.3 V DDC so
a level shifter may need here
8
16
SDA_CTL/PRE
TERM
Optional
17
EQ1/A0
VCC_3.3 V
23
36
0.1 µF
EQ2/A1
34
OE
CEC
0.1 µF
SLEW
18
0
VSADJ
CEC
1 M
0 kΩ
100 k
0.1 µF
10 µF
0
6 k
1%
VDD_1.1 V
15
35
GND
THERMAL PAD
GND
19
12
20
31
VDD_1.1 V
40
VCC
11
0.1 µF
0.1 µF
0.1 µF
0.01 µF
0.01 µF
10 µF
VCC
VDD
VDD
VDD
VDD
Populated only when using Pin Strapping
NC
0.1 µF
Populated only when using I2C
37
VCC_3.3 V
Figure 9-1. TDP158 in Source Side Application
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9.2.1 Design Requirements
The TDP158 can be designed into many different applications. In all the applications there are certain
requirements for the system to work properly. Two voltage rails are required to support the lowest power
consumption possible. The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a
processor but the pin needs to change states after the voltage rails have stabilized. Using the I2C is the best
way to configure the device, but pin strapping is also provided as I2C, which is not available in all cases. As
sources may have many different naming conventions, it is necessary to confirm that the link between the
source and the TDP158 are correctly mapped. A swap function is provided for the input pins in case signaling
is reversed between source and the device. The following control pin values are based upon driving pins with
a microcontroller; otherwise, the shown pullup/down configuration meets the device levels. The following table
provides information on the expected values to perform properly.
For this design, use the parameters shown in Table 9-1.
Table 9-1. Design Parameters
Design Parameter
Value
VCC
3.3 V
VDD
1.1 V
Main Link Input Voltage
VID = 0.15 to 1.4 Vpp
Control Pin Max Voltage for Low
Connect to 1 kΩ pulldown resistor to GND
Control Pin Voltage Range Mid
Connect to 1 kΩ pulldown resistor to GND
Control Pin Min Voltage for High
Connect to 1 kΩ pullup resistor to VCC
R(VSADJ) Resistor
6.49 kΩ 1%
9.2.2 Detailed Design Procedure
9.2.2.1 Source Side
The TDP158 is a signal conditioning device that provides several forms of signal conditioning to support
compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished using
receive equalization, retiming, and output driver configurability. The transmitter will drive 1”– 2” of board trace
and connector when compliance is required at the connector.
To design in the TDP158 the following need to be understood for a source side application:
•
•
•
•
•
•
•
40
Determine the loss profile between the GPU/chipset and the HDMI /DVI connector.
Based upon this loss profile and signal swing determine optimal location for the TDP158, to pass source
electrical compliance. Usually within 1”– 2” of the connector.
Use the typical application Figure 9-1 for information on control pin resistors.
The TDP158 has a receiver equalizer but can also be configured using EQ1 and EQ2 control pins.
Set the VOD, pre-emphasis, termination, and edge rate levels appropriately to support compliance by using
the appropriate VSADJ resistor value and setting SDA_CTL/PRE, TERM and SLEW control pins.
The thermal pad must be connected to ground.
See schematics in Figure 9-1 on recommended decouple caps from VCC pins to ground.
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9.2.2.2 DDC Pull Up Resistors
This section is for information only and subject to change depending upon system implementation. The pull-up
resistor value is determined by two requirements:
1. The maximum sink current of the I2C buffer:
The maximum sink current is 3 mA or slightly higher for an I2C driver supporting standard-mode I2C
operation.
V CC
R UP(min)
I sink
(1)
2. The maximum transition time on the bus:
The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pull-up resistor
value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by solving
for t, the times at which certain voltage thresholds are reached. Different input threshold combinations
introduce different values of t. Table 9-2 summarizes the possible values of k under different threshold
combinations.
T k u RC
(2)
t
V(t) V DD u (1
e RC )
(3)
Table 9-2. Value k upon Different Input Threshold Voltages
Vth-\Vth+
0.7 VCC
0.65 VCC
0.6 VCC
0.55 VCC
0.5 VCC
0.45 VCC
0.4 VCC
0.35 VCC
0.3 VCC
0.1 VCC
1.0986
0.9445
0.8109
0.6931
0.5878
0.4925
0.4055
0.3254
0.2513
0.15 VCC
1.0415
0.8873
0.7538
0.6360
0.5306
0.4353
0.3483
0.2683
0.1942
0.2 VCC
0.9808
0.8267
0.6931
0.5754
0.4700
0.3747
0.2877
0.2076
0.1335
0.25 VCC
0.9163
0.7621
0.6286
0.5108
0.4055
0.3102
0.2231
0.1431
0.0690
0.3 VCC
0.8473
0.6931
0.5596
0.4418
0.3365
0.2412
0.1542
0.0741
From Equation 1, Rup(min) = 5.5 V/3 mA = 1.83 kΩ to operate the bus under a 5-V pull-up voltage and provide
less than 3 mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA,
is allowed, Rup(min) can be as low as 1.375 kΩ.
If DDC working at standard mode of 100 Kbps, the maximum transition time T is fixed, 1 μs, and using the k
values from Table 9-2, the recommended maximum total resistance of the pull-up resistors on an I2C bus can be
calculated for different system setups. If DDC working in fast mode of 400 Kbps, the transition time should be set
at 300 ns according to I2C specification.
To support the maximum load capacitance specified in the HDMI spec, C(cable)(max) = 700 pF, C(source) = 50 pF,
CI = 50 pF, R(max) can be calculated as shown in Table 9-3.
Table 9-3. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads
Vth-\Vth+
0.7 VCC
0.65 VCC
0.6 VCC
0.55 VCC
0.5 VCC
0.45 VCC
0.4 VCC
0.35 VCC
0.3 VCC
UNIT
0.1 VCC
1.14
1.32
1.54
1.8
2.13
2.54
3.08
3.84
4.97
kΩ
0.15 VCC
1.2
1.41
1.66
1.97
2.36
2.87
3.59
4.66
6.44
kΩ
0.2 VCC
1.27
1.51
1.8
2.17
2.66
3.34
4.35
6.02
9.36
kΩ
0.25 VCC
1.36
1.64
1.99
2.45
3.08
4.03
5.6
8.74
18.12
kΩ
0.3 VCC
1.48
1.8
2.23
2.83
3.72
5.18
8.11
16.87
—
kΩ
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To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support
a maximum 800-pF load capacitance for a standard-mode I2C bus.
9.2.3 Application Curves
Figure 9-2. High Loss Input Eye −20” 4 mil Trace at Figure 9-3. Output Eye from High Loss Input Eye at
TDP158 Pin
TDP158 Pin
Figure 9-4. HDMI 2 Compliance Eye from High Loss Input Eye
42
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9.2.4 Application with DDC Snoop
9.2.4.1 Source Side HDMI Application
In source side applications, the TDP158 takes an AC-coupled HDMI signal and provides signal conditioning and
level shifting to support TMDS signaling. Figure 9-5 provides an example of a DDC snoop version. Notes in both
schematics provide important system design considerations. To help reduce overall EMI in a system the VCC
and VDD decoupling caps need to be as close to the pins as possible. The drawings shown one set but multiple
sets may be needed for each pin.
Control pins should be tied to 1 kΩ pullup to VCC, 1 kΩ pulldown to GND, or left floating. Drawings show 0-Ω
resistors as this provides flexibility. In noisy systems a 0.1-µF capacitor to GND may reduce glitches on these
pins and are not shown in the drawings. As Figure 9-5 shows, connect the DDC source and sink pins to GND as
the SCL/SDA_SRC if an application requires the DDC source and sink pins to be completely bypassed. If this is
done, then the TX termination must be controlled by the TERM pin or through I2C.
HDMI/DVI Receptacle
1
2
0.1 µF
4
0.1 µF
5
ML0n
OUT_D2n
27
OUT_D1p
IN_D1p
ML1n
0.1 µF
6
ML2p
26
0.1 µF
IN_D0n
0.1 µF
3
2 k
DDC_SCL
39
DDC_SDA
33
16
GND6
17
21
DDC_SCL
CASE_GND2
DDC_SDA
CASE_GND3
22
23
HPD
HPD_SNK
SDA_SRC
20
19
28
SCL_SRC
TMDS_D0n
14
CASE_GND1
15
SDA_SNK
38
GND5
CEC
32
SCL_SNK
2 k
TMDS_D0p
11
13
CEC
ESD
2 k
GND4
TMDS_CLKn
2 k
VCC_3.3 V
GND3
TMDS_D1n
TMDS_CLKp
5V
HPD_SRC
TMDS_D1p
5
8
12
21
IN_CLKn
HPD
GND2
10
OUT_CLKn
10
ML3n
Dual Mode GPU/DP TX
or AC coupled HDMI TX
9
OUT_CLKp
IN_CLKp
0.1 µF
7
24
22
9
ML3p
25
OUT_D0n
7
ML2n
TMDS_D2n
6
OUT_D0p
IN_D0p
GND1
4
OUT_D1n
IN_D1n
TMDS_D2p
3
29
IN_D2n
ML1p
2
OUT_D2p
ESD
0.1 µF
1
30
IN_D2p
ESD
0.1 µF
ML0p
CASE_GND4
VCC_3.3 V
VCC_3.3 V
0.01 µF
CAD_DET
1 M
0 kΩ
100 k
2 k
2 k
13
SCL_CTL/SWAP
I2C_SCL
0
0
0 kΩ
14
I2C_SDA
I2C_EN
8
VCC_3.3 V
16
SDA_CTL/PRE
TERM
Optional
0.1 µF
17
0.1 µF
10 µF
EQ1/A0
23
36
0.1 µF
EQ2/A1
34
OE
SLEW
18
0
VSADJ
CEC
CEC
0
6 k
1%
AUXp
VDD_1.1 V
15
35
GND
THERMAL PAD
GND
19
12
20
31
VDD_1.1 V
40
VCC
11
0.1 µF
0.1 µF
0.1 µF
0.01 µF
0.01 µF
10 µF
VCC
VDD
VDD
VDD
VDD
Populated only when using Pin Strapping
NC
0.1 µF
Populated only when using I2C
37
VCC_3.3 V
Figure 9-5. TDP158 Source Side Application with DDC Snoop
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9.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
The TDP158 has a special mode that will allow the device to support either HDMI or DP applications. The device
is put into this mode by setting reg09h[5] to 1. The device will self-configure with the following settings and
become I2C programmable only. The TDP158 does not support automatic Link Training for DisplayPort. AUX
channel bypasses device.
• All four lanes are turned on and configured for 5.4 Gbps data rate.
• Sets VOD swing to ≅ 410 mV (This value is based upon a VSADJ value of 6 kΩ).
• Reg0Ch[7:5] is used to control VOD swing for all lanes.
• Reg0Ch[1:0] is used to control pre-emphasis for all lanes.
• Reg30h[7:2] is used to turn on or off individual lanes as well as informing the TDP158 what the data rate is.
This is used for the delay component for pre-emphasis signal.
For DisplayPort the link is AC coupled. This shows
one way of doing this otherwise the capacitors
could be moved to a dongle or the end equipment.
0.1 µF
2
ML0n
OUT_D2p
IN_D2n
0.1 µF
4
0.1 µF
5
ML1n
0.1 µF
6
0.1 µF
0.1 µF
0.1 µF
0.1 µF
7
24
0.1 µF
9
22
0.1 µF
38
DDC_SCL
39
33
16
13
SCL_CTL/SWAP
14
I2C_SDA
Optional
36
0.1 µF
I2C_EN
CEC
AUXp
AUXp
AUXn
AUXn
21
CASE_GND2
DDC_SDA
CASE_GND3
22
23
CASE_GND4
0
8
AUXp
AUXp
AUXn
AUXn
0.01 µF
1 M
VCC_3.3 V
16
SDA_CTL/PRE
TERM
0.1 µF
17
0.1 µF
10 µF
EQ1/A0
OE
23
EQ2/A1
18
34
SLEW
VSADJ
CEC
20
DDC_SCL
HPD
0
2 k
17
VCC_3.3 V
100 k
2 k
GND6
19
HPD_SNK
SDA_SRC
VCC_3.3 V
I2C_SCL
TMDS_D0n
14
CASE_GND1
15
28
SCL_SRC
GND5
CEC
32
SDA_SNK
DDC_SDA
CAD_DET
2 k
CEC
ESD
2 k
2 k
TMDS_D0p
11
13
0.1 µF
SCL_SNK
VCC_3.3 V
GND4
TMDS_CLKn
2 k
HPD_SRC
GND3
TMDS_D1n
TMDS_CLKp
5V
IN_CLKn
3
TMDS_D1p
5
8
12
OUT_CLKn
10
HPD
GND2
10
0.1 µF
21
TMDS_D2n
6
25
OUT_CLKp
IN_CLKp
ML3n
Dual Mode GPU/DP TX
or AC coupled HDMI TX
26
GND1
4
OUT_D0n
9
0.1 µF
0.1 µF
OUT_D0p
IN_D0p
IN_D0n
ML3p
27
2
TMDS_D2p
3
OUT_D1n
7
ML2n
0.1 µF
OUT_D1p
IN_D1n
ML2p
29
OUT_D2n
IN_D1p
ML1p
1
30
IN_D2p
ML0p
HDMI/DVI Receptacle or
DP Receptacle
ESD
1
ESD
0.1 µF
6 k
1%
0
0
I2C Programming
only so these can
be left floating
15
GND
35
VDD_1.1 V
GND
THERMAL PAD
19
NC
12
20
31
VDD_1.1 V
40
VCC
11
0.1 µF
0.1 µF
0.1 µF
0.01 µF
0.01 µF
10 µF
VCC
VDD
VDD
VDD
VDD
0.1 µF
37
VCC_3.3 V
Figure 9-6. TDP158 in Dual Role Source Side Application
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10 Power Supply Recommendations
10.1 Power Management
To minimize the power consumption of customer application, TDP158 used the dual power supply. VCC is 3.3 V
with 10% range to support the I/O voltage. The VDD is 1.1 V with ≅ 5% range to supply the internal digital control
circuit. TDP158 operates in 3 different working states.
• Power Down mode:
– When OE = Low, the device will put itself into the lowest power state by shutting down all function blocks.
• OE re-asserted means the pin transitions from low to high. Transitioning the OE pin from L → H
creates a reset. If the device is programmed through I2C, then it must be reprogrammed.
– Writing a 1 to register 09h[3].
– OE = High, HPD_SNK = Low for > 2 ms
• Standby mode:
– HPD_SNK = High but no valid clock signal detect on clock lane.
• Normal operation:
– When HPD assert, the device output will enable based on the signal detector circuit result.
– HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when VCC over 3 V.
Note
When the TDP158 is put into a power down state the I2C registers are cleared. This is important as
the TMDS_CLOCK_RATIO_STATUS bit will be cleared. If cleared and HDMI 2.0 resolutions are to be
supported the TDP158 expects the source to write a 1 to this bit location. If the read has the bit set,
the TDP158 will set this bit; otherwise, the source termination must be set manually.
10.2 Standby Power
The TDP158/I implement a two stage standby power process.
Stage 1: If there is no signal on the clock line, then the maximum IVCC ≅ 7 mA and maximum IVDD ≅ 7 mA.
Stage 2: If a signal (like a noise or clock signal) is on the clock line, then the TDP158 investigates the clock line
for 3 μs to 5 μs and detects if a signal is present.
• If a clock is detected, then the TDP158 will go into normal operation.
• If it is determined that no clock is present, then the TDP158 will re-enter stage 1.
In stage 2; maximum IVCC ≅ 7 mA and maximum IVDD ≅ 27 mA.
Table 10-1. Power Modes
INPUTS
STATUS
OE
HPD_SNK
Reg09[2]
IN_CLK
HPD_SRC
IN_Dx
SDA/SCL_CTL
OUT_Dx
OUT_CLK
DDC
Mode
L
X
X
X
H
High-Z
Disable
High-Z
Disabled
Power Down
Mode
H
X
1
X
HPD_SNK
RX Active
Active
TX Active
Active
Normal
operation
H
X
1
No Valid TMDS
Clock
HPD_SNK
D0-D2 Disabled
IN_CLK Active
Active
High-Z
Active
Standby Mode
(Squelch
waiting)
H
X
1
Valid TMDS
Clock
HPD_SNK
RX Active
Active
TX Active
Active
Normal
operation
H
H
0
No Valid TMDS
Clock
HPD_SNK
D0-D2 Disabled
IN_CLK Active
Active
High-Z
Active
Standby Mode
(Squelch
waiting)
H
H
0
Valid TMDS
Clock
HPD_SNK
RX Active
Active
TX Active
Active
Normal
operation
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11 Layout
11.1 Layout Guidelines
For the TDP158 on a high-K board, it is required to solder the PowerPAD™ onto the thermal land to ground.
A thermal land is the area of solder-tinned-copper underneath the PowerPAD™ package. On a high-K board
the TDP158 can operate over the full temperature range by soldering the PowerPAD™ onto the thermal land.
On a low-K board, for the device to operate across the temperature range on a low-K board, a 1-oz Cu trace
connecting the GND pins to the thermal land must be used. A simulation shows RθJA = 100.84°C/W allowing 545
mW power dissipation at 70°C ambient temperature. A general PCB design guide for PowerPAD packages is
provided in the document SLMA002. TI recommends using a four layer stack up at a minimum to accomplish a
low-EMI PCB design. TI recommends six layers as the TDP158 is a two voltage rail device.
•
•
•
•
•
Routing the high-speed TMDS traces on the top layer avoids the use of vias, avoids the introduction of
their inductances, and allows for clean interconnects from the HDMI connectors to the Redriver inputs and
outputs. It is important to match the electrical length of these high speed traces to minimize both inter-pair
and intra-pair skew.
Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for
transmission link interconnects and provides an excellent low –inductance path for the return current flow.
Placing a power plane next to the ground plane creates and additional high-frequency bypass capacitance.
Routing slower seed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to
the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be place closer together, thus increasing the high
frequency bypass capacitance significantly.
Layer 1: TMDS signal layer
5 to 10
mils
Layer 1: TMDS signal layer
Layer 2: Ground Plane
Layer 2: Ground Plane
Layer 3: VCC Power Plane
20 to 40
mils
Layer 3: Power Plane
Layer 4: VDD Power Plane
Layer 5: Ground Plane
5 to 10
mils
Layer 4: Control signal layer
Layer 6: Control signal layer
Figure 11-1. Recommended 4 – or 6 – Layer PCB Stack
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11.2 Layout Example
VCC
SCL_SRC
GND
GND
SLEW
5V SDA_SNK
VCC
2kQ
2kQ
5V
Match High Speed traces
length as close as possible to
minimize Ske
100nF
100nF
Match High Speed traces
length as close as possible to
minimize Ske
HPD_SRC
OUT_D2p/n
HPD_SNK
100nF
IN_D1p/n
From Source
1
OUT_D1p/n
100nF
GND
100nF
IN_D0p/n
VCC
I2C_EN
OUT_D0p/n
100nF
GND
1lQ
1lQ
1lQ
VCC
1lQ
GND
To Connector
IN_D2p/n
SCL_SNK
VDD
VCC
VDD
SDA_SRC
1lQ
2kQ
1lQ
2kQ
100nF
VCC
A1/EQ2
OUT_CLKp/n
100nF
IN_CLKp/n
NC
1lQ
1lQ
6.49 kQ
VCC
GND
GND
GND
2kO/1lQ
1lQ
DE
2kO/1lQ
VCC
1lQ
SDA_CTL
VCC
1lQ
For I2C only Pop pull up and
use 2 lQ
VCC
SCL_CTL
VDD
1lQ
VDD
SWAP
GND
VCC
100nF
Place VCC and VDD decoupling
caps as close to VCC and VDD
pins as possible
VSADJ
GND
For DE and SWAP only Pop pull up
or pull down and use 65 lQ
TERM A0/EQ1
The differential input lanes and differential output lanes should be separated as close to the TDP158 as feasible to minimize crosstalk.
Adding a ground flood plain between each differential lane further reduces crosstalk and thus improves signal integrity at high speed
data rates.
Figure 11-2. Example Layout for Source Side Application
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, PowerPAD Thermally Enhanced Package
• [HDMI ] High-definition Multimedia Interface CTS Version 1.4b October, 2011
• [HDMI ] High-definition Multimedia Interface CTS Version 2.0o June 2016
• [HDMI ] High-definition Multimedia Interface Specification Version 1.4b October, 2011
• [HDMI ] High-definition Multimedia Interface Specification Version 2.0 September 4, 2013
• [I2C] The I2C-Bus specification version 2.1 January 2000
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TMDS™ is a trademark of Wabtec Holding Corp.
HDMI ™ is a trademark of HDMI Licensing Administrator, Inc.
DisplayPort™ is a trademark of Video Electronics Standards Association.
Blu-ray™ is a trademark of Blu-ray Disc Accociation.
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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1-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TDP158RSBR
ACTIVE
WQFN
RSB
40
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 85
TDP158
TDP158RSBT
ACTIVE
WQFN
RSB
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 85
TDP158
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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