THS1009IDA

 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 
   
   
     
 
 
 FEATURES D Simultaneous Sampling of Two Single-Ended Signals or One Differential Signals or Combination of Both D Signal-to-Noise and Distortion Ratio: 59 dB D D D D D D D D at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1 LSB Auto-Scan Mode for Two Inputs programming the ADC into the desired mode. The THS1009 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The THS1009C is characterized for operation from 0°C to 70°C, and the THS1009I is characterized for operation from –40°C to 85°C. 3-V or 5-V Digital Interface Compatible DA PACKAGE (TOP VIEW) Low Power: 216 mW Max at 5 V Power Down: 1 mW Max 5-V Analog Single Supply Operation Internal Voltage References . . . 50 PPM/°C and ±5% Accuracy D Glueless DSP Interface D Parallel µC/DSP Interface APPLICATIONS D Radar Applications D Communications D Control Applications D High-Speed DSP Front-End D Automotive Applications DESCRIPTION The THS1009 is a CMOS, low-power, 10-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for D0 D1 D2 D3 D4 D5 BVDD BGND D6 D7 D8 D9 RA0 RA1 CONV_CLK SYNC 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 NC RESET AINP AINM REFIN REFOUT REFP REFM AGND AVDD CS0 CS1 WR (R/W) RD DVDD DGND ORDERING INFORMATION PACKAGED DEVICE TA TSSOP (DA) 0°C to 70°C THS1009CDA –40°C to 85°C THS1009IDA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 
 
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 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNITS Supply Su ly voltage range DGND to DVDD –0.3 V to 6.5 V BGND to BVDD –0.3 V to 6.5 V AGND to AVDD –0.3 V to 6.5 V Analog input voltage range AGND –0.3 V to AVDD + 1.5 V –0.3 V + AGND to AVDD + 0.3 V Reference input voltage Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V Operating virtual junction temperature range, TJ –40°C to 150°C THS1009C Operating free-air free air temperature range, range TA 0 to 70°C THS1009I –40°C to 85°C Storage temperature range, Tstg –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS POWER SUPPLY Supply y voltage g MIN NOM MAX AVDD DVDD 4.75 5 5.25 4.75 5 5.25 BVDD 3 ANALOG AND REFERENCE INPUTS Analog input voltage in single-ended configuration Common-mode input voltage VCM in differential configuration NOM MAX VREFM 1 VREFP 4 V 2.5 3.5 AVDD–1.2 V 1.4 Input voltage difference, REFP – REFM DIGITAL INPUTS MIN High level input voltage, High-level voltage VIH BVDD = 3.3 V BVDD = 5.25 V Low level input voltage, Low-level voltage VIL BVDD = 3.3 V BVDD = 5.25 V Input CONV_CLK frequency CONV_CLK pulse duration, clock high, tw(CONV_CLKH) CONV_CLK pulse duration, clock low, tw(CONV_CLKL) Operating free-air free air temperature, temperature TA 2 V 5.25 MIN External reference voltage,VREFP (optional) External reference voltage, VREFM (optional) UNIT UNIT V 1.5 V 2 V NOM MAX UNIT 2 V 2.6 V 0.6 0.6 V DVDD = 4.75 V to 5.25 V DVDD = 4.75 V to 5.25 V 0.1 62 62 5000 ns DVDD = 4.75 V to 5.25 V THS1009CDA 62 62 5000 ns THS1009IDA 8 V 0 70 –40 85 MHz °C 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal voltage (unless otherwise noted) DIGITAL SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital inputs IIH IIL High-level input current Low-level input current DVDD = digital inputs Digital input = 0 V –50 50 µA –50 50 µA Ci Input capacitance Digital outputs 5 VOH VOL High-level output voltage Low-level output voltage IOH = –50 µA, IOL = 50 µA, BVDD = 3.3 V, 5 V BVDD = 3.3 V, 5 V IOZ CO High-impedance-state output current CS1 = DGND, CS0 = DVDD CL Load capacitance at databus D0 – D9 pF BVDD–0.5 V –10 Output capacitance 0.4 V 10 µA 5 pF 30 pF ELECTRICAL CHARACTERISTICS over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.3 V, fs = 8 MSPS, VREF = internal voltage (unless otherwise noted) DC SPECIFICATIONS PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 10 UNIT Bits Accuracy Integral nonlinearity, INL ±1 LSB Differential nonlinearity, DNL ±1 LSB ±5 After calibration in single-ended mode Offset error After calibration in differential mode Gain error LSB –10 10 LSB –10 10 LSB Analog input Input capacitance Input leakage current 15 VAIN = VREFM to VREFP pF ±10 µA V Internal voltage reference Accuracy, VREFP 3.3 3.5 3.7 Accuracy, VREFM 1.4 1.5 1.6 Temperature coefficient 50 Reference noise µV 100 Accuracy, REFOUT 2.475 V PPM/°C 2.5 2.525 V Power supply IDDA IDDD Analog supply current AVDD = DVDD = 5 V, BVDD =3.3 V AVDD = DVDD = 5 V, BVDD = 3.3 V 36 40 mA 0.5 3 mA IDDB Buffer supply current AVDD = DVDD = 5 V, BVDD = 3.3 V AVDD = DVDD = 5 V, BVDD = 3.3 V 1.5 4 mA Power dissipation 186 216 mW Power dissipation in power down with conversion clock inactive AVDD = DVDD = 5 V, BVDD = 3.3 V 0.25 mW Digital supply current 3 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating conditions, VREF = internal voltage, fs = 8 MSPS, fI = 2 MSPS at –1 dB (unless otherwise noted) AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF PARAMETER SINAD Signal to noise ratio + distortion Signal-to-noise SNR Signal to noise ratio Signal-to-noise THD Total harmonic distortion ENOB Effective number of bits SFDR Spurious free dynamic range MIN TYP Differential mode TEST CONDITIONS 56 59 Single-ended mode 55 58 Differential mode 59 61 Single-ended mode 58 60 Differential mode –64 Single-ended mode –63 Differential mode 9 9.5 8.85 9.35 Differential mode 61 65 Single-ended mode 60 64 Single-ended mode MAX UNIT dB dB dB Bits dB Analog Input Full-power bandwidth with a source impedance of 150 Ω in differential configuration. Full scale sinewave, –3 dB 96 MHz Full-power bandwidth with a source impedance of 150 Ω in single-ended configuration. Full scale sinewave, –3 dB 54 MHz Small-signal bandwidth with a source impedance of 150 Ω in differential configuration. 100 mVpp sinewave, –3 dB 96 MHz Small-signal bandwidth with a source impedance of 150 Ω in single-ended configuration. 100 mVpp sinewave, –3 dB 54 MHz TIMING REQUIREMENTS AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal voltage, CL < 30 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONV CLK tpipe Latency tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) Setup time, CONV_CLK low before CS valid 10 Setup time, CS invalid to CONV_CLK low 20 td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH) Delay time, CONV_CLK low to SYNC low 10 ns Delay time, CONV_CLK low to SYNC high 10 ns 4 5 ns ns 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AINP 30 I Analog input, single-ended or positive input of differential channel A AINM 29 I Analog input, single-ended or negative input of differential channel A AVDD AGND 23 I Analog supply voltage 24 I Analog ground BVDD BGND 7 I Digital supply voltage for buffer 8 I Digital ground for buffer CONV_CLK 15 I Digital input. This input is the conversion clock input. CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) SYNC 16 O Synchronization output. This signal indicates in a multichannel operation that data of channel A is brought to the digital output and can therefore be used for synchronization. DGND 17 I Digital ground. Ground reference for digital circuitry. DVDD D0 – D9 18 I Digital supply voltage 1–6, 9–12 I/ O/Z RA0 13 I Digital input. RA0 is used as an address line (RA0) for the control register. This is required for writing to control register 0 and control register 1. See Table 7. RA1 14 I Digital input. RA1 is used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 7. NC 32 O Not connected REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 8. REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 8. RESET 31 I Hardware reset of the THS1009. Sets the control register to default values. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires a capacitor of 10 µF to AGND for filtering and stability. RD(1) 19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. WR (R/W)(1) 20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a write-only input (WR), which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section. Digital input, output; D0 = LSB (1) The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC. 5 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD 3.5 V REFP 1.5 V 2.5 V 1.225 V REF REFOUT REFM REFP REFIN S/H AINP AINM Single-Ended and/or Differential MUX + – REFM BVDD 10-Bit Pipeline ADC 10 S/H Buffers CONV_CLK CS0 CS1 RD Logic and Control Control Register BGND WR (R/W) SYNC RESET AGND 6 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 RA0 RA1 DGND 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) 80 SINAD – Signal-to-Noise and Distortion – dB 65 THD – Total Harmonic Distortion – dB 75 70 65 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 60 55 50 45 40 60 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 55 50 45 40 0 1 2 3 4 5 6 7 8 9 0 1 fs – Sampling Frequency – MHz 2 Figure 1 4 5 6 7 8 9 Figure 2 SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (SINGLE-ENDED) SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (SINGLE-ENDED) 65 90 85 80 SNR – Signal-to-Noise – dB SFDR – Spurious Free Dynamic Range – dB 3 fs – Sampling Frequency – MHz 75 70 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 65 60 55 60 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 55 50 45 50 45 40 40 0 1 2 3 4 5 6 7 fs – Sampling Frequency – MHz Figure 3 8 9 0 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz Figure 4 7 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) 85 SINAD – Signal-to-Noise and Distortion – dB 65 THD – Total Harmonic Distortion – dB 80 75 70 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 65 60 55 50 45 40 60 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 55 50 45 40 0 1 2 3 4 5 6 7 8 9 0 1 fs – Sampling Frequency – MHz 2 Figure 5 5 6 7 8 9 SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (DIFFERENTIAL) 65 90 85 80 SNR – Signal-to-Noise – dB SFDR – Spurious Free Dynamic Range – dB 4 Figure 6 SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (DIFFERENTIAL) 75 70 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 65 60 55 60 55 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 50 45 50 45 40 40 0 1 2 3 4 5 6 7 fs – Sampling Frequency – MHz Figure 7 8 3 fs – Sampling Frequency – MHz 8 9 0 1 2 3 4 5 6 7 fs – Sampling Frequency – MHz Figure 8 8 9 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) 80 SINAD – Signal-to-Noise and Distortion – dB 65 THD – Total Harmonic Distortion – dB 75 70 65 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 60 55 50 45 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 60 55 50 45 40 0.0 4.0 AVDD = 5 V, DVDD = BVDD = 3 V, fs= 8 MSPS, AIN = –1 dB FS 0.5 fi – Input Frequency – MHz 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz Figure 9 Figure 10 SIGNAL-TO-NOISE vs INPUT FREQUENCY (SINGLE-ENDED) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (SINGLE-ENDED) 80 90 85 75 80 SNR – Signal-to-Noise – dB SFDR – Spurious Free Dynamic Range – dB 1.0 75 70 65 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 60 55 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS 70 65 60 55 50 50 45 45 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 fi – Input Frequency – MHz Figure 11 3.5 4.0 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 fi – Input Frequency – MHz 3.5 4.0 Figure 12 9 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) 65 SINAD – Signal-to-Noise and Distortion – dB THD – Total Harmonic Distortion –dB 80 75 70 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 800 MSPS, AIN = –1 dB FS 65 60 55 50 45 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 60 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 55 50 45 40 0.0 4.0 fi – Input Frequency – MHz 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz Figure 13 Figure 14 SIGNAL-TO-NOISE vs INPUT FREQUENCY (DIFFERENTIAL) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (DIFFERENTIAL) 65 85 80 75 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 70 65 60 55 60 55 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 50 45 50 45 40 0.0 40 0.0 0.5 1.0 1.5 2.0 2.5 fi – Input Frequency – MHz Figure 15 10 SNR – Signal-to-Noise – dB SFDR – Spurious Free Dynamic Range – dB 90 3.0 3.5 4.0 0.5 1.0 1.5 2.0 2.5 3.0 fi – Input Frequency – MHz Figure 16 3.5 4.0 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs SAMPLING RATE (DIFFERENTIAL) EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (SINGLE-ENDED) 11.0 10.5 10.5 ENOB – Effective Number of Bits – dB ENOB – Effective Number of Bits – Bits 11.0 10.0 9.5 9.0 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 8.5 8.0 7.5 7.0 6.5 10.0 9.5 9.0 8.5 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dB FS 8.0 7.5 7.0 6.5 6.0 0 6.0 0 1 2 3 4 5 6 7 fs – Sampling Frequency – MHz 8 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz 9 Figure 18 Figure 17 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (DIFFERENTIAL) 11.0 11.0 10.5 10.5 10.0 10.0 ENOB – Effective Number of Bits – dB ENOB – Effective Number of Bits – dB EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (SINGLE-ENDED) 9.5 9.0 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 8.5 8.0 7.5 7.0 6.5 6.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 fi – Input Frequency – MHz Figure 19 3.5 4.0 9.5 9.0 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dB FS 8.5 8.0 7.5 7.0 6.5 6.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz Figure 20 11 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs ADC CODE 1.0 0.8 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS 0.6 0.4 0.2 –0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 256 512 768 1024 ADC Code Figure 21 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs ADC CODE 1.0 0.8 0.6 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS 0.4 0.2 –0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 256 512 ADC Code Figure 22 12 768 1024 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM (4096 Points) (SINGLE-ENDED) vs FREQUENCY 0 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MHz, AIN = –1 dB FS, fIN = 1.25 MHz Magnitude – dB –20 –40 –60 –80 –100 –120 –140 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 4000000 f – Frequency – Hz Figure 23 FAST FOURIER TRANSFORM (4096 Points) (DIFFERENTIAL) vs FREQUENCY 0 Magnitude – dB –20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MHz, AIN = –0.5 dB FS, fIN = 1.25 MHz –40 –60 –80 –100 –120 –140 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 4000000 f – Frequency – Hz Figure 24 13 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 DETAILED DESCRIPTION Reference Voltage The THS1009 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. Analog Inputs The THS1009 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed. Converter The THS1009 uses a 10-bit pipelined multistaged architecture which achieves a high sample rate with low power consumption. The THS1009 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples. Conversion An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. The conversion values are available at the output with a latency of 5 clock cycles. SYNC In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK after a SYNC reset. This is due to the latency of the pipeline architecture of the THS1009. Sampling Rate The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate for the different combinations. Table 1. Maximum Conversion Rate in Continuous Conversion Mode NUMBER OF CHANNELS MAXIMUM CONVERSION RATE PER CHANNEL 1 single-ended channel 1 8 MSPS 2 single-ended channels 2 4 MSPS 1 differential channel 1 8 MSPS CHANNEL CONFIGURATION The maximum conversion rate per channel, fc, is given by: fc + 8 MSPS # channels Continuous Conversion Mode During conversion the ADC operates with a free running external clock signal applied to the input CONV_CLK. With every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding read signal. The THS1009 offers up to two analog inputs to be selected. It is important to provide the channel information to the system; this means knowing which channel is available to the databus. To maintain this channel integrity, the THS1009 has an output signal SYNC, which is always active low if the data of channel 1 is applied to the databus. 14 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Figure 25 shows the timing of the conversion when one analog input channel is selected. The maximum throughput rate is 8 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information is not required for one analog input. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 26 and the timing specification. A more detailed description of the timing is given in the section timing and signal description of the THS1009. Sample N+1 Channel 1 Sample N Channel 1 Sample N+2 Channel 1 Sample N+3 Channel 1 Sample N+4 Channel 1 Sample N+5 Channel 1 Sample N+6 Channel 1 Sample N+7 Channel 1 Sample N+8 Channel 1 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) CONV_CLK tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) READ† Data N–4 Channel 1 Data N–3 Channel 1 Data N–2 Channel 1 Data N–1 Channel 1 Data N Channel 1 Data N+1 Channel 1 Data N+2 Channel 1 †READ is the logical combination from CS0, CS1 and RD Figure 25. Conversion Timing in 1-Channel Operation Figure 27 shows the conversion timing when two analog input channels are selected. The maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is available to the data bus. This can be seen in Figure 26 and Table 2. A more detailed description of the timing is given in the section timing and signal description of the THS1009. Sample N Channel 1, 2 Sample N+1 Channel 1, 2 Sample N+2 Channel 1, 2 Sample N+3 Channel 1, 2 Sample N+4 Channel 1, 2 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) CONV_CLK tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) READ† tsu(CONV_CLKL-SYNCH) tsu(CONV_CLKL-SYNCL) SYNC Data N–2 Channel 1 Data N–2 Channel 2 Data N–1 Channel 1 Data N–1 Channel 2 Data N Channel 1 Data N Channel 2 Data N+1 Channel 1 †READ is the logical combination from CS0, CS1 and RD Figure 26. Conversion Timing in 2-Channel Operation 15 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 DIGITAL OUTPUT DATA FORMAT The digital output data format of the THS1009 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 2. Binary Output Format for Single-Ended Configuration SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP AIN = (VREFP + VREFM)/2 3FFh AIN = VREFM 000h 200h Table 3. Twos Complement Output Format for Single-Ended Configuration SINGLE-ENDED, TWOS COMPLEMENT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP AIN = (VREFP + VREFM)/2 1FFh AIN = VREFM 200h 000h Table 4. Binary Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP – AINM VREF = VREFP – VREFM Vin = VREF 3FFh Vin = 0 Vin = –VREF 200h 000h Table 5. Twos Complement Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP – AINM VREF = VREFP – VREFM Vin = VREF Vin = 0 1FFh Vin = –VREF 200h 000h ADC CONTROL REGISTER The THS1009 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 6. Table 6. Bit Definitions of Control Register CR0 and CR1 16 REG BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RES VREF CR1 RESERVED OFFSET BIN/2’s R/W RES RES RES RES SRST RESET 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Writing to Control Register 0 and Control Register 1 The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper bits RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 7 shows the addressing of each control register. Table 7. Control Register Addressing D0 – D9 RA0 RA1 Addressed Control Register Desired register value 0 0 Control register 0 Desired register value 1 0 Control register 1 Desired register value 0 1 Reserved for future Desired register value 1 1 Reserved for future INITIALIZATION OF THE THS1009 The initialization of the THS1009 should be done according to the configuration flow shown in Figure 27. Start Use Default Values? No Yes Write 0x401 to THS1009 (Set Reset Bit in CR1) Clear RESET By Writing 0x400 to CR1 Write 0x401 to THS1009 (Set Reset Bit in CR1) Clear RESET By Writing 0x400 to CR1 Write the User Configuration to CR0 Write The User Configuration to CR1 ( Must Exclude RESET) Continue Figure 27. THS1009 Configuration Flow 17 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 ADC CONTROL REGISTERS Control Register 0, Write Only (see Table 8) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RES VREF Table 8. Control Register 0 Bit Functions BITS RESET VALUE NAME 0 0 VREF Vref select: Bit 0 = 0 → The internal reference is used Bit 0 = 1 → The external reference voltage is used for the ADC 1 0 RES Reserved 2 0 PD 3, 4 0,0 CHSEL0, CHSEL1 5,6 1,0 DIFF0, DIFF1 7 0 SCAN Autoscan enable Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 9. 8,9 0,0 TEST0, TEST1 Test input enable Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation. FUNCTION Power down. Bit 2 = 0 → The ADC is active Bit 2 = 1 → Power down The reading and writing to and from the digital outputs is possible during power down. Channel select Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 9. Number of differential channels Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 9. Refer to Table 10 for selection of the three different test voltages. 18 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 ANALOG INPUT CHANNEL SELECTION The analog input channels of the THS1009 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 9 shows the possible selections. Table 9. Analog Input Channel Configurations BIT 7 SCAN BIT 6 DIFF1 BIT 5 DIFF0 BIT 4 CHSEL1 BIT 3 CHSEL0 0 0 0 0 0 Analog input AINP (single ended) 0 0 0 0 1 Analog input AINM (single ended) 0 0 0 1 0 Reserved 0 0 0 1 1 Reserved 0 0 1 0 0 Differential channel (AINP–AINM) 0 0 1 0 1 Reserved 1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, … 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 1 Reserved 1 0 1 1 0 Reserved 1 1 0 0 1 Reserved 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved 1 0 0 0 0 Reserved 1 0 1 0 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved DESCRIPTION OF THE SELECTED INPUTS Test Mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 10. Table 10. Test Mode BIT 9 TEST1 BIT 8 TEST0 OUTPUT RESULT 0 0 Normal mode 0 1 1 0 VREFP ((VREFM)+(VREFP))/2 1 1 VREFM Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor. 19 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Control Register 1, Write Only (see Table 11) BIT11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 RESERVED OFFSET BIN/2s R/W RES RES RES RES SRST RESET Table 11. Control Register 1 Bit Functions BITS RESET VALUE NAME 0 0 RESET FUNCTION Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. To bring the device out of RESET, a 0 has to be written into this bit. 1 0 SRST Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the configuration cycle. 2, 3 0,0 RES Reserved 4 1 RES Reserved 5 1 RES Reserved 6 0 R/W R/W, RD/WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR becomes a write input. 7 0 BIN/2s Complement select If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5. 8 0 OFFSET Offset cancellation mode Bit 8 = 0 → normal conversion mode Bit 8 = 1 → offset calibration mode If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error. 9 20 0 RESERVED Always write 0. 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 TIMING AND SIGNAL DESCRIPTION OF THE THS1009 The reading from the THS1009 and writing to the THS1009 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs can be used to interface easily to a processor. Reading from the THS1009 takes place by an internal RDint signal, which is generated from the logical combination of the external signals CS0, CS1 and RD (see Figure 28). This signal is then used to strobe out the words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active while the write input (WR) is inactive. The first of those external signals switching to its inactive state deactivates RDint again. Writing to the THS1009 takes place by an internal WRint signal, which is generated from the logical combination of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input (RD) is inactive. The first of those external signals going to its inactive state deactivates WRint again. CS0 RDint CS1 RD WRint WR Control/Data Registers Data Bits Figure 28. Logical Combination of CS0, CS1, RD, and WR 21 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Read Timing (using RD, RD-controlled) Figure 29 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0, CS1, and RD which becomes valid. CS0 CS1 tsu(CS) ÓÓÓÓÓ ÓÓÓÓÓ th(CS) ÔÔÔÔ ÔÔÔÔ WR tw(RD) 10% RD 10% ta th 90% 90% D(0–9) td(CSDAV) 90% DATA_AV Figure 29. Read Timing Diagram Using RD (RD-controlled) Read Timing Parameter (RD-controlled) PARAMETER MIN TYP MAX UNIT tsu(CS) ta Setup time, RD low to last CS valid 0 Access time, last CS valid to data valid 0 td(CSDAV) th Delay time, last CS valid to DATA_AV inactive Hold time, first CS invalid to data invalid 0 th(CS) tw(RD) Hold time, RD change to first CS invalid 5 ns 10 ns 22 Pulse duration, RD active ns 10 12 ns ns 5 ns 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Write Timing (using WR, WR-controlled) Figure 30 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR which becomes valid. CS0 CS1 tsu(CS) th(CS) tw(WR) WR RD 10% 10% ÓÓÓÓ ÓÓÓÓ tsu ÔÔÔÔ ÔÔÔÔ th 90% 90% D(0–9) DATA_AV ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ Figure 30. Write Timing Diagram Using WR (WR-controlled) Write Timing Parameter Using WR (WR-controlled) PARAMETER MIN TYP MAX UNIT tsu(CS) tsu Setup time, CS stable to last WR valid 0 ns Setup time, data valid to first WR invalid 5 ns th th(CS) Hold time, WR invalid to data invalid 2 ns 5 ns tw(WR) Pulse duration, WR active 10 ns Hold time, WR invalid to CS change 23 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Read Timing (using R/W, CS0-controlled) Figure 31 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 31. tsu(CONV_CLKL–CSOL) CONV_CLK tsu(CSOH–CONV_CLKL) 10% 10% 90% tw(CS) CS0 10% 10% CS1 R/W ÓÓÓ ÓÓÓ ÔÔÔÔ ÔÔÔÔ th(R/W) tsu(R/W) 90% 90% RD ta th 90% 90% D(0–11) Figure 31. Read Timing Diagram Using R/W (CS0-controlled) Read Timing Parameter (CS0-controlled) PARAMETER MIN TYP MAX UNIT tsu(CONV_CLKL–CSOL) tsu(CSOH–CONV_CLKL) Setup time, CONV_CLK low before CS valid 10 ns Setup time, CS invalid to CONV_CLK low 20 ns tsu(R/W) ta Setup time, R/W high to last CS valid 0 ns Access time, last CS valid to data valid 0 10 ns th th(R/W) Hold time, first CS invalid to data invalid 0 5 ns tw(CS) Pulse duration, CS active 24 Hold time, first external CS invalid to R/W change 5 ns 10 ns 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 Write Timing (using R/W, CS0-controlled) Figure 32 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1009 can be performed irrespective of the conversion clock signal CONV_CLK. tw(CS) CS0 90% 10% 10% CS1 R/W ÔÔÔ ÔÔÔ ÔÔÔ tsu(R/W) ÓÓÓÓ ÓÓÓÓ ÓÓÓÓ th(R/W) 10% 10% RD tsu th 90% 90% D(0–11) Figure 32. Write Timing Diagram Using R/W (CS0-controlled) Write Timing Parameter (CS0-controlled) PARAMETER MIN TYP MAX UNIT tsu(R/W) tsu Setup time, R/W stable to last CS valid 0 ns Setup time, data valid to first CS invalid 5 ns th th(R/W) Hold time, first CS invalid to data invalid 2 ns Hold time, first CS invalid to R/W change 5 ns tw(CS) Pulse duration, CS active 10 ns 25 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE The THS1009 features two analog input channels. These can be configured for either single-ended or differential operation. Figure 33 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference voltage). The analog input voltage range is between VREFM to VREFP. This means that VREFM defines the minimum voltage and VREFP defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V (see also section Reference Voltage). The resulting analog input voltage swing of 2 V can be expressed by: V REFM v AINP v V (1) REFP VREFP 10-Bit ADC AINP VREFM Figure 33. Single-Ended Input Stage A differential operation is desired for many applications due to better signal-to-noise ration. Figure 34 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The differential operation mode provides in terms of performance benefits over the single-ended mode and is therefore recommended for best performance. The THS1009 offers 1 differential analog input and in the single-ended mode 2 analog inputs. If the analog input architecture is differential, common-mode noise and common-mode voltages can be rejected. Additional details for both modes are given below. VREFP AINP + Σ VADC 10-Bit ADC – AINM VREFM Figure 34. Differential Input Stage In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the input of the ADC is the difference between the input AINP and AINM. The voltage VADC can be calculated as follows: V ADC + ABS(AINP–AINM) (2) An advantage to single-ended operation is that the common-mode voltage V CM + AINM ) AINP 2 (3) can be rejected in the differential configuration, if the following condition for the analog input voltages is true: AGND v AINM, AINP v AV 1VvV 26 CM v4V DD (4) (5) 
 www.ti.com SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002 SINGLE-ENDED MODE OF OPERATION The THS1009 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the THS1009 should be driven from an operational amplifier that does not degrade the ADC performance. Because the THS1009 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc- and ac-coupling. DC COUPLING An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS1009. The analog input voltage range of the THS1009 goes from 1.5 V to 3.5 V. An operational amplifier can be used as shown in Figure 35. Figure 35 shows an example with the analog input signal in the range between –1 V and 1 V. The signal is shifted by an operational amplifier to the analog input range of the THS1009 (1.5 V to 3.5 V). The operational amplifier is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS1009 by using a resistor divider. Therefore, the operational amplifier output voltage is centered at 2.5 V. The 10 µF tantalum capacitor is required for bypassing REFOUT. REFIN of the THS1009 must be connected directly to REFOUT in single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors. 3.5 V 2.5 V 1.5 V R1 5V 1V 0V –1 V R1 _ THS1009 RS AINP 1.25 V + C REFIN REFOUT + R2 10 µF R2 Figure 35. Level-Shift for DC-Coupled Input DIFFERENTIAL MODE OF OPERATION For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode. Mini Circuits T4–1 49.9 Ω THS1009 R AINP 200 Ω C R AINM C 10 µF + REFOUT Figure 36. Transformer Coupled Input 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS1009IDA ACTIVE TSSOP DA 32 46 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS1009I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of