DGN-8
DGK-8
D-8
THS4271
THS4275
DRB-8
www.ti.com
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE
VOLTAGE FEEDBACK AMPLIFIER
Check for Samples: THS4271 THS4275
FEATURES
1
•
•
23
•
•
•
•
•
•
DESCRIPTION
Unity Gain Stability
Low Voltage Noise
– 3 nV/√Hz
High Slew Rate: 1000 V/μs
Low Distortion
– –92 dBc THD at 30 MHz
Wide Bandwidth: 1.4 GHz
Supply Voltages
– +5 V, ±5 V
Power Down Functionality (THS4275)
Evaluation Module Available
The THS4271 and THS4275 are low-noise, high slew
rate, unity gain stable voltage-feedback amplifiers
designed to run from supply voltages as low as 5 V
and as high as ±5 V. The THS4275 offers the same
performance as the THS4271 with the addition of a
power-down capability. The combination of low-noise,
high slew rate, wide bandwidth, low distortion, and
unity gain stability make the THS4271 and THS4275
high performance devices across multiple ac
specifications.
APPLICATIONS
•
•
•
•
•
High Linearity ADC Preamplifier
Wireless Communication Receivers
Differential to Single-Ended Conversion
DAC Output Buffer
Active Filtering
Low-Noise, Low-Distortion, Wideband Application Circuit
Designers using the THS4271 are rewarded with
higher dynamic range over a wider frequency band
without the stability concerns of decompensated
amplifiers. The devices are available in SOIC, MSOP
with PowerPAD™, and leadless MSOP with
PowerPAD™ packages.
The THS4271 and THS4275 may have low-level
oscillation when the die temperature (also known as
the junction temperature) exceeds +60°C. For more
information, see Maximum Die Temperature to
Prevent Oscillation.
RELATED DEVICES
+5 V
50 Ω Source
50 Ω
+
49.9 Ω
VI
VO
THS4271
_
DEVICE
DESCRIPTION
THS4211
1-GHz voltage-feedback amplifier
THS4503
Wideband, fully-differential amplifier
THS3202
Dual, wideband current feedback amplifier
249 Ω
249 Ω
NOTE: Power supply decoupling capacitors not shown
THS4271
NC
IN−
IN+
VS−
1
8
2
7
3
6
4
5
NC
VS+
VOUT
NC
Harmonic and Intermodulation Distortion − dB
-5 V
HARMONIC AND INTERMODULATION
DISTORTION
vs
FREQUENCY
−40
Gain = 2
Rf = 249 Ω
RL = 150 Ω
VO = 2 VPP
VS = ±5 V
−50
−60
IMD3
200 kHz Tone Spacing
VO = 2 VPP Envelope
−70
−80
HD2
−90
HD3
−100
1
10
f − Frequency − MHz
100
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2009, Texas Instruments Incorporated
THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
ORDERABLE PACKAGE AND NUMBER
PLASTIC
SMALL OUTLINE (D)
(1)
LEADLESS
MSOP 8 (3)
PLASTIC MSOP
PowerPAD
(2)
PLASTIC MSOP
(2)
(DRB)
(DGN)
THS4271D
THS4271DRBT
THS4271DGN
THS4271DR
THS4271DRBR
THS4271DGNR
THS4275D
THS4275DRBT
THS4275DGN
THS4275DR
THS4275DRBR
THS4275DGNR
PACKAGE MARKING
PACKAGE
MARKING
(DGK)
THS4271DGK
BFQ
BEY
THS4271DGKR
THS4275DGK
BFR
(2)
BJD
THS4275DGKR
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
All packages are available taped and reeled. The R suffix standard quantity is 2500 (for example, THS4271DGNR).
All packages are available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250 (for example,
THS4271DRBT).
(2)
(3)
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted (1)
UNIT
VS
Supply voltage
VI
IO
16.5 V
Input voltage
(2)
±VS
Output current
100 mA
Continuous power dissipation
TJ
See Dissipation Ratings Table
Maximum junction temperature
+150°C
+125°C
TJ
(2)
Maximum junction temperature, continuous operation long term reliability
TJ
(3)
Maximum junction temperature to prevent oscillation
Tstg
+60°C
Storage temperature range
–65°C to +150°C
HBM
3000 V
ESD ratings CDM
1500 V
MM
(1)
(2)
(3)
1000 V
The absolute maximum temperature under any condition is limited by the constraints of the silicon process. Stresses above these
ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not
implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet.
PACKAGE DISSIPATION RATINGS
PACKAGE
θJC
(°C/W)
θJA (1)
(°C/W)
D (8 pin)
38.3
97.5
DGN (8 pin) (2)
4.7
58.4
DGK (8 pin)
54.2
260
5
45.8
DRB (8 pin)
(1)
(2)
2
(2)
These data were taken using the JEDEC standard High-K test PCB.
The THS4271/5 may incorporate a PowerPAD™ on the underside of the chip. This feature acts as a
heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction temperature which could permanently damage
the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
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Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
THS4271
THS4275
www.ti.com
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
RECOMMENDED OPERATING CONDITIONS
Dual supply
Supply voltage (VS+ and VS–)
Single supply
Input common-mode voltage range
MIN
MAX
±2.5
±5
5
10
VS- + 1.4
VS+ – 1.4
UNIT
V
V
PIN ASSIGNMENTS
(TOP VIEW)
D, DRB, DGN, DGK
(TOP VIEW)
THS4271
NC
ININ+
VS-
1
8
2
7
3
6
4
5
D, DRB, DGN, DGK
THS4275
NC
VS+
VOUT
NC
REF
ININ+
VS-
1
8
2
7
3
6
4
5
PD
VS+
VOUT
NC
NC - No internal connection
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
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3
THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
+25°C
OVER TEMPERATURE
+25°C
0°C to
+70°C
–40°C to
+85°C
(1)
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
G = 1, VO = 100 mVPP, RL = 150 Ω
1.4
GHz
Typ
G = –1, VO = 100 mVPP
400
MHz
Typ
G = 2, VO = 100 mVPP
390
MHz
Typ
G = 5, VO = 100 mVPP
85
MHz
Typ
G = 10, VO = 100 mVPP
40
MHz
Typ
0.1-dB flat bandwidth
G = 1, VO = 100 mVPP, RL = 150 Ω
200
MHz
Typ
Gain bandwidth product
G > 10, f = 1 MHz
400
MHz
Typ
Full-power bandwidth
G = –1, VO = 2 Vp
80
MHz
Typ
G = 1, VO = 2 V Step
950
V/μs
Typ
Small-signal bandwidth
Slew rate
G = –1, VO = 2 V Step
1000
V/μs
Typ
Settling time to 0.1%
G = –1, VO = 4 V Step
25
ns
Typ
Settling time to 0.01%
G = –1, VO = 4 V Step
38
ns
Typ
Harmonic distortion
G = 1, VO = 1 VPP, f = 30 MHz
RL = 150 Ω
-92
dBc
Typ
RL = 499 Ω
-80
dBc
Typ
RL = 150 Ω
-95
dBc
Typ
RL = 499 Ω
-95
dBc
Typ
RL = 150 Ω
-65
dBc
Typ
RL = 499 Ω
-70
dBc
Typ
RL = 150 Ω
-80
dBc
Typ
RL = 499 Ω
-90
dBc
Typ
Third-order intermodulation (IMD3)
G = 2, VO = 2 VPP, RL = 150 Ω,
f = 70 MHz
-60
dBc
Typ
Third-order output intercept (OIP3)
G = 2, VO = 2 VPP, RL = 150Ω,
f = 70 MHz
35
dBm
Typ
Differential gain (NTSC, PAL)
G = 2, RL = 150 Ω
0.007%
Differential phase (NTSC, PAL)
G = 2, RL = 150 Ω
0.004
°
Typ
Input voltage noise
f = 1 MHz
3
nV/√Hz
Typ
Input current noise
f = 1 MHz
3
pA√Hz
Typ
Open-loop voltage gain (AOL)
VO = ± 50 mV, RL = 499 Ω
75
65
dB
Min
Input offset voltage
VCM = 0 V
5
10
Max
Average offset voltage drift
VCM = 0 V
Input bias current
VCM = 0 V
Average bias current drift
VCM = 0 V
Input offset current
VCM = 0 V
Average offset current drift
VCM = 0 V
Second harmonic distortion
Third harmonic distortion
Harmonic distortion
Second harmonic distortion
Third harmonic distortion
G = 2, VO = 2 VPP, f = 30 MHz
Typ
DC PERFORMANCE
6
15
1
6
60
60
12
12
mV
±10
±10
μV/°C
Typ
18
18
μA
Max
±10
±10
nA/°C
Typ
8
8
μA
Max
±10
±10
nA/°C
Typ
Min
INPUT CHARACTERISTICS
Common-mode input range
±4
±3.6
±3.5
±3.5
V
Common-mode rejection ratio
VCM = ± 2 V
72
67
65
65
dB
Min
Input resistance
Common-mode
5
MΩ
Typ
Input capacitance
Common-mode / differential
0.4/0.8
pF
Typ
(1)
4
See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet.
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
THS4271
THS4275
www.ti.com
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
(1)
UNITS
MIN/
TYP/
MAX
OUTPUT CHARACTERISTICS
Output voltage swing
G = +2
±4
±3.8
±3.7
±3.7
V
Min
Output current (sourcing)
RL = 10 Ω
160
120
110
110
mA
Min
Output current (sinking)
RL = 10 Ω
80
60
50
50
mA
Min
Output impedance
f = 1 MHz
0.1
Ω
Typ
POWER SUPPLY
Specified operating voltage
±5
±5
±5
±5
V
Max
Maximum quiescent current
22
24
27
28
mA
Max
Minimum quiescent current
22
20
18
15
mA
Min
Power-supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 5 V
85
75
70
70
dB
Min
Power-supply rejection (-PSRR)
VS+ = 5 V, VS– = -5.5 V to -4.5 V
75
65
60
60
dB
Min
REF+1.8
V
Min
Power down
REF+1
V
Max
Enable
REF–1
V
Min
REF–1.7
V
Max
POWER-DOWN CHARACTERISTICS (THS4275 Only)
REF = 0 V or VS–
Power-down voltage level (2)
REF = VS+ or Floating
Power-down quiescent current
Enable
Power down
PD = Ref +1.0 V,
Ref = 0 V
875
1000
1100
1200
μA
Max
PD = Ref –1.7 V,
Ref = VS+
650
800
900
1000
μA
Max
Turn-on time delay [t(ON)]
50% of final supply current value
4
μs
Typ
Turn-off time delay [t(OFF)]
50% of final supply current value
3
μs
Typ
Input impedance
f = 1 MHz
4
GΩ
Typ
200
kΩ
Typ
Output impedance
(2)
For detailed information on the power-down circuit, see the Power-Down section in the Application Information of this data sheet.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
Submit Documentation Feedback
5
THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = 5 V
At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
+25°C
OVER TEMPERATURE
+25°C
0°C to
+70°C
–40°C to
+85°C
(1)
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
G = 1, VO = 100 mVPP, RL = 150 Ω
1.2
GHz
Typ
G = –1, VO = 100 mVPP
380
MHz
Typ
G = 2, VO = 100 mVPP
360
MHz
Typ
G = 5, VO = 100 mVPP
80
MHz
Typ
G = 10, VO = 100 mVPP
35
MHz
Typ
0.1-dB flat bandwidth
G = 1, VO = 100 mVPP, RL = 150 Ω
120
MHz
Typ
Gain bandwidth product
G > 10, f = 1 MHz
350
MHz
Typ
Full-power bandwidth
G = –1, VO = 2 Vp
60
MHz
Typ
G = 1, VO = 2 V Step
700
V/μs
Typ
Small-signal bandwidth
Slew rate
G = –1, VO = 2 V Step
750
V/μs
Typ
Settling time to 0.1%
G = –1, VO = 2 V Step
18
ns
Typ
Settling time to 0.01%
G = –1, VO = 2 V Step
66
ns
Typ
Harmonic distortion
G = 1, VO = 1 VPP, f = 30 MHz
RL = 150 Ω
75
dBc
Typ
RL = 499 Ω
72
dBc
Typ
RL = 150 Ω
-70
dBc
Typ
RL = 499 Ω
70
dBc
Typ
G = 2, VO = 1 VPP, RL = 150Ω,
Third-order intermodulation (IMD3)
f = 70 MHz
-65
dBc
Typ
Third-order output intercept (OIP3)
G = 2, VO = 1 VPP, RL = 150Ω,
f = 70 MHz
32
dBm
Typ
Input voltage noise
f = 1 MHz
3
nV/√Hz
Typ
Input current noise
f = 10 MHz
3
pA/√Hz
Typ
Open-loop voltage gain (AOL)
VO = ± 50 mV, RL = 499 Ω
68
63
60
60
dB
Min
Input offset voltage
VCM = VS/2
5
10
12
12
mV
Max
Average offset voltage drift
VCM = VS/2
±10
±10
μV/°C
Typ
Input bias current
VCM = VS/2
6
15
18
18
μA
Max
Average bias current drift
VCM = VS/2
±10
±10
nA/°C
Typ
Input offset current
VCM = VS/2
Average offset current drift
VCM = VS/2
Second harmonic distortion
Third harmonic distortion
DC PERFORMANCE
1
6
8
8
μA
Max
±10
±10
nA/°C
Typ
Min
INPUT CHARACTERISTICS
Common-mode input range
1/4
1.3/3.7
1.4/3.6
1.5/3.5
V
Common-mode rejection ratio
VCM = ± 0.5 V, VO = 2.5 V
72
67
65
65
dB
Min
Input resistance
Common-mode
5
MΩ
Typ
Input capacitance
Common-mode / differential
0.4/0.8
pF
Typ
Output voltage swing
G = +2
1.2/3.8
1.4/3.6
1.5/3.5
1.5/3.5
V
Min
Output current (sourcing)
RL = 10 Ω
120
100
90
90
mA
Min
Output current (sinking)
RL = 10 Ω
65
50
40
40
mA
Min
Output impedance
f = 1 MHz
0.1
Ω
Typ
OUTPUT CHARACTERISTICS
(1)
6
See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet.
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
THS4271
THS4275
www.ti.com
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
Specified operating voltage
5
10
10
Maximum quiescent current
20
22
25
(1)
UNITS
MIN/
TYP/
MAX
10
V
Max
27
mA
Max
–40°C to
+85°C
POWER SUPPLY
Minimum quiescent current
20
18
16
14
mA
Min
Power-supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 0 V
85
75
62
62
dB
Min
Power-supply rejection (-PSRR)
VS+ = 5 V, VS– = –0.5 V to 0.5 V
75
65
60
60
dB
Min
POWER-DOWN CHARACTERISTICS (THS4275 Only)
REF = 0 V, or VS–
Power-down voltage level (2)
REF = VS+ or Floating
Power-down quiescent current
Enable
REF+1.8
V
Min
Power-down
REF+1
V
Max
Enable
REF–1
V
Min
V
Max
PD = Ref +1.0 V, Ref = 0 V
Power-down
650
REF–1.7
800
900
1000
μA
Max
PD = Ref –1.7 V, Ref = VS+
650
800
900
1000
μA
Max
Turn-on time delay [t(ON)]
50% of final value
4
μs
Typ
Turn-off time delay [t(OFF)]
50% of final value
3
μs
Typ
Input impedance
f = 1 MHz
6
GΩ
Typ
100
kΩ
Typ
Output impedance
(2)
For detail information on the power-down circuit, see the Power-Down section in the Application Information of this data sheet.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
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THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small-signal unity gain frequency response
1
Small-signal frequency response
2
0.1-dB gain flatness frequency response
3
Large-signal frequency response
4
Slew rate
vs Output voltage
5
Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
Third-order intermodulation distortion
vs Frequency
14, 16
Third-order intercept point
vs Frequency
15, 17
Voltage and current noise
vs Frequency
18
Differential gain
vs Number of loads
19
Differential phase
vs Number of loads
20
6, 7, 8, 9
10, 11, 12, 13
Settling time
21
Quiescent current
vs Supply voltage
22
Output voltage
vs Load resistance
23
Frequency response
vs Capacitive load
24
Open-loop gain and phase
vs Frequency
25
Open-loop gain
vs Supply voltage
26
Rejection ratios
vs Frequency
27
Rejection ratios
vs Case temperature
28
Common-mode rejection ratio
vs Input common-mode range
29
Input offset voltage
vs Case temperature
30
Input bias and offset current
vs Case temperature
31
Small-signal transient response
32
Large-signal transient response
33
Overdrive recovery
34
Closed-loop output impedance
vs Frequency
35
Power-down quiescent current
vs Supply voltage
36
Power-down output impedance
vs Frequency
37
Turn-on and turn-off delay times
8
Submit Documentation Feedback
38
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
THS4271
THS4275
www.ti.com
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
Table of Graphs (5 V)
FIGURE
Small-signal unity gain frequency response
39
Small-signal frequency response
40
0.1-dB gain flatness frequency response
41
Large-signal frequency response
42
Slew rate
vs Output voltage
Harmonic distortion
vs Frequency
44, 45, 46, 47
Harmonic distortion
vs Output voltage swing
48, 49, 50, 51
Third-order intermodulation distortion
vs Frequency
52, 54
Third-order intercept point
vs Frequency
53, 55
Voltage and current noise
vs Frequency
56
Settling time
43
57
Quiescent current
vs Supply voltage
58
Output voltage
vs Load resistance
59
Frequency response
vs Capacitive load
60
Open-loop gain and phase
vs Frequency
61
Open-loop gain
vs Case temperature
62
Rejection ratios
vs Frequency
63
Rejection ratios
vs Case temperature
64
Common-mode rejection ratio
vs Input common-mode range
65
Input offset voltage
vs Case temperature
66
Input bias and offset current
vs Case temperature
67
Small-signal transient response
68
Large-signal transient response
69
Overdrive recovery
70
Closed-loop output impedance
vs Frequency
71
Power-down quiescent current
vs Supply voltage
72
Power-down output impedance
vs Frequency
73
Turn-on and turn-off delay times
74
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
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THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL UNIT GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL
FREQUENCY RESPONSE
22
2
1
0
−1
−2
0
Gain = 10
18
Small Signal Gain − dB
16
Gain = 5
14
RL = 499 Ω
Rf = 249 Ω
VO = 100 mVPP
VS = ±5 V
12
10
8
6
Gain = 2
4
2
−3
−4
100 k
1M
10 M
1G
100 M
Gain = −1
−2
−4
100 k
1M
10 G
f − Frequency − Hz
10 M
100 M
f − Frequency − Hz
10 M
100 M
−50
10
8
6
800
Rise
600
400
Gain = −1
RL = 499 Ω
Rf = 249 Ω
VS = ±5 V
Gain = 2
200
0
100 k
Harmonic Distortion − dBc
1000
RL = 499 Ω
Rf = 249 Ω
VO = 1 VPP
VS = ±5 V
Gain = 1
VO = 1 VPP
VS = ±5 V
10 M
100 M
0
1G
−60
−70
HD3, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 150Ω
HD2, RL = 499Ω
−90
−100
0
1M
f − Frequency − Hz
0.5
1
1.5
2
2.5
3
3.5
4 4.5
5
1
VO − Output Voltage − V
10
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−50
−50
Harmonic Distortion − dBc
Gain = 1
VO = 2 VPP
VS = ±5 V
HD2, RL = 150Ω
HD3, RL = 499Ω
−80
HD3, RL = 150Ω
HD2, RL = 499Ω
−100
Figure 7.
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100
100
−50
Gain = 2
Rf = 249 Ω
VO = 1 VPP
VS = ±5 V
−60
−70
HD3, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 499Ω
HD2, RL = 150Ω
−90
−100
10
f − Frequency − MHz
1G
f − Frequency − Hz
Fall
SR − Slew Rate − V/ µ s
Large Signal Gain − dB
1M
HARMONIC DISTORTION
vs
FREQUENCY
2
Harmonic Distortion − dBc
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = ±5 V
SLEW RATE
vs
OUTPUT VOLTAGE
12
1
−0.7
LARGE-SIGNAL
FREQUENCY RESPONSE
14
−90
−0.6
Figure 3.
Gain = 5
−70
−0.5
Figure 2.
Gain = 10
−60
−0.4
−1
100 k
1G
1200
4
−0.3
−0.9
20
16
−0.2
Figure 1.
22
18
−0.1
−0.8
0
Harmonic Distortion − dBc
Small Signal Gain − dB
3
0.1
20
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = ±5 V
Small Signal Gain − dB
4
10
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
Gain = 2
Rf = 249 Ω
VO = 2 VPP
VS = ±5 V
HD3, RL = 499Ω
−60
−70
HD2, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 150Ω
−90
−100
1
f − Frequency − MHz
10
f − Frequency − MHz
Figure 8.
Figure 9.
10
100
1
100
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−50
−50
−60
Harmonic Distortion − dBc
Gain = 1
f= 8 MHz
VS = ±5 V
HD3, RL = 150Ω
−70
HD3, RL = 499Ω
−80
HD2, RL = 499Ω
HD2, RL = 150Ω
−90
−60
Gain = 1
f= 32 MHz
VS = ±5 V
−70
HD2, RL = 150Ω
Gain = 2
Rf = 249 Ω
f = 8 MHz
VS = ±5 V
HD2, RL = 499Ω
Harmonic Distortion − dBc
−50
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HD3, RL = 150Ω
−80
−90
−60
HD3, RL = 499Ω
−70
HD2, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 150Ω
−90
HD3, RL = 499Ω
−100
0
5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
VO − Output Voltage Swing − ±V
5
Figure 12.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
Gain = 2
Rf = 249 Ω
f = 32 MHz
HD2, RL = 499Ω
VS = ±5 V
HD2, RL = 150Ω
−60
−70
−80
HD3,
RL = 150Ω
−90
HD3,
RL = 499Ω
−100
0
1
2
3
4
VO − Output Voltage Swing − ±V
55
−40
Gain = 1
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
−50
Third-Order Output Intersept Point − dBm
Third-Order Intermodulation Distortion − dBc
Figure 11.
−60
−70
VO = 2 VPP
−80
−90
VO = 1 VPP
−100
5
10
Gain = 1
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
50
VO = 2 VPP
45
VO = 1 VPP
40
35
30
100
0
20
40
60
f − Frequency − MHz
f − Frequency − MHz
80
100
Figure 13.
Figure 14.
Figure 15.
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
50
−60
VO = 2 VPP
−70
−80
VO = 1 VPP
−90
−100
10
100
45
40
Gain = 2
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
VO = 1 VPP
35
30
0
20
40
60
f − Frequency − MHz
f − Frequency − MHz
Figure 16.
Figure 17.
80
100
Hz
−50
100
VO = 2 VPP
Hz
Gain = 2
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
Vn − Voltage Noise − nV/
−40
Third-Order Output Intersept Point − dBm
Harmonic Distortion − dBc
1
2
3
4
VO − Output Voltage Swing − ±V
Figure 10.
−50
Third-Order Intermodulation Distortion − dBc
−100
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VO − Output Voltage Swing − ±V
100
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Vn
10
10
In
1
100
1k
10 k
100 k
1M
10 M
I n − Current Noise − pA/
−100
1
100 M
f − Frequency − Hz
Figure 18.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.015
Gain = 2
Rf = 1.3 kΩ
VS = ±5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.09
°
Differential Phase −
0.020
3
NTSC
0.010
0.08
0.07
Rising Edge
2
VO − Output Voltage − V
Gain = 2
Rf = 1.3 kΩ
VS = ±5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.025
Differential Gain − %
SETTLING TIME
0.10
0.030
0.06
0.05
PAL
0.04
0.03
NTSC
0.02
PAL
0.005
1
Gain = −1
RL = 499 Ω
Rf = 249 Ω
f= 1 MHz
VS = ±5 V
0
−1
Falling Edge
−2
0.01
0
0
1
2
3
4
5
6
7
0
8
−3
0
Number of Loads − 150 Ω
1
2
3
4
5
6
7
8
0
Figure 21.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
25
20
TA = −40°C
15
10
5
0
VS = ±5 V
TA = −40 to 85°C
3
2
Normalized Gain - dB
VO − Output Voltage − V
Quiescent Current − mA
TA = 25°C
1
0
−1
−2
3
3.5
4
4.5
10
5
R(ISO) = 25 W, CL = 10 pF
-1
R(ISO) = 15 W, CL = 50 pF
-1.5
R(ISO) = 10 W, CL = 100 pF
-2
-2.5
−5
2.5
-0.5
−3
−4
0
VS − Supply Voltage − ±V
100
1k
RL − Load Resistance − Ω
RL = 499 W
VS = ±5 V
-3
1M
10 k
10 M
100 M
Capacitive Load - Hz
Figure 22.
Figure 23.
Figure 24.
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
SUPPLY VOLTAGE
REJECTION RATIOS
vs
FREQUENCY
0
VS = ±5 V
Gain
60
80
40
80
30
100
Phase
120
Phase − °
60
20
TA = 85°C
65
60
0
160
55
180
1G
50
1M
10 M
100 M
f − Frequency − Hz
Figure 25.
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PSRR+
80
70
140
100 k
TA = 25°C
75
10
−10
10 k
TA = −40°C
40
50
VS = ±5 V
90
20
Open-Loop Gain − dB
70
100
85
Rejection Ratios − dB
80
25
0.5
5
4
Open-Loop Gain − dB
20
Figure 20.
TA = 85°C
12
10
15
t − Time − ns
Figure 19.
30
2
5
Number of Loads − 150 Ω
70
PSRR−
60
50
CMRR
40
30
20
10
0
2.5
3
3.5
4
4.5
5
Supply Voltage − ±VS
Figure 26.
10 k
100 k
1M
10 M
f − Frequency − Hz
100 M
Figure 27.
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS: ±5 V (continued)
COMMON-MODE REJECTION RATIOS
vs
INPUT COMMON-MODE RANGE
VS = ±5 V
PSRR+
100
Rejection Ratios − dB
PSRR−
80
60
CMMR
40
20
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
100
5
90
VOS − Input Offset Voltage − mV
120
CMRR − Common-Mode Rejection Ratio − dB
REJECTION RATIOS
vs
FREQUENCY
80
70
60
50
40
30
20
VS = ±5 V
TA = 25°C
10
0
−6
−4
Case Temperature − °C
−2
0
2
4
1
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
6
TC − Case Temperature − °C
Figure 29.
Figure 30.
INPUT BIAS AND OFFSET
CURRENT
vs
CASE TEMPERATURE
SMALL-SIGNAL TRANSIENT
RESPONSE
LARGE-SIGNAL TRANSIENT
RESPONSE
1.17
0.3
1.5
IOS
1.15
0.2
1
1.14
5
IIB+
4
1.13
3
1.12
2
1.11
1
1.1
0.1
0
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = ±5 V
−0.1
−0.2
1.09
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
VO − Output Voltage − V
6
VO − Output Voltage − V
1.16
IIB−
I OS − Input Offset Current − µ A
7
0.5
0
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = ±5 V
−0.5
−1
−1.5
−0.3
0
TC − Case Temperature − °C
2
4
6
8
10
12
14 16
0
2
t − Time − ns
4
6 8 10 12 14
t − Time − ns
16 18
Figure 31.
Figure 32.
Figure 33.
OVERDRIVE RECOVERY
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
6
1000
4
2
3
1.5
2
1
1
0.5
0
0
−1
−0.5
−2
−1
−3
−1.5
−4
−2
−5
−2.5
VI − Input Voltage − V
2.5
Closed-Loop Output Impedance − Ω
3
VS = ±5 V
−3
−6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
100
1200
Gain = 1
RL = 499 Ω
PIN = −1 dBm
VS = ±5 V
10
1
0.1
0.01
0.001
100 k
1
t − Time − µs
Power-down Quiescent Current − µ A
I IB − Input Bias Current − µ A
VS = ±5 V
2
Input Common-Mode Range − V
VS = ±5 V
Single-Ended Output Voltage − V
VS = 5 V
3
Figure 28.
8
5
4
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 34.
Figure 35.
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TA = 85°C
1000
TA = 25°C
800
TA = −40°C
600
400
200
0
2.5
3
3.5
4
4.5
5
VS − Supply Voltage − ±V
Figure 36.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
POWER-DOWN OUTPUT
IMPEDANCE
vs
FREQUENCY
Power-down Output Impedance − Ω
1M
Gain = 1
RL = 150 Ω
VIN = 1 dBm
VS = ±5 V
100 k
10 k
100
1
100 k
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 37.
TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNIT GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL UNIT GAIN
FREQUENCY RESPONSE
20
0
−1
−2
−3
−4
100 k
1M
0.1
Gain = 10
18
10 M
100 M
1G
16
Gain = 5
14
RL = 499 Ω
Rf = 249 Ω
VO = 100 mVPP
VS = 5 V
12
10
8
6
Gain = 2
4
2
0
Gain = −1
−2
−4
100 k
1M
10 G
f − Frequency − Hz
−0.4
−0.5
−0.6
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = 5 V
−0.7
−0.8
−0.9
10 M
100 M
f − Frequency − Hz
−1
100 k
1G
1M
10 M
100 M
LARGE-SIGNAL FREQUENCY
RESPONSE
HARMONIC DISTORTION
DISTORTION
vs
FREQUENCY
1000
16
14
12
10
Gain = 1
RL = 499 Ω
Rf = 249 Ω
VS = 5 V
900
Gain = 5
RL = 499 Ω
Rf = 249 Ω
VO = 1 VPP
VS = 5 V
6
Gain = 2
800
700
600
−50
Fall
Harmonic Distortion − dBc
Gain = 10
1G
f − Frequency − Hz
SLEW RATE
vs
FREQUENCY
SR − Slew Rate − V/ µ s
Large Signal Gain − dB
−0.3
Figure 41.
18
Rise
500
400
300
200
Gain = 1
VO = 1 VPP
RL = 150 Ω
VS = 5 V
−60
−70
−80
HD3
HD2
−90
100
2
0
100 k
−100
0
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 42.
14
−0.2
Figure 40.
20
4
0
−0.1
Figure 39.
22
8
Small Signal Gain − dB
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = 5 V
Small Signal Gain − dB
Small Signal Gain − dB
1
0.2
22
3
2
0.1-dB GAIN FLTANESS
FREQUENCY RESPONSE
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0
0.5
1
1.5
2
VO − Output Voltage −V
2.5
1
10
100
f − Frequency − MHz
Figure 43.
Figure 44.
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−50
−20
−30
Harmonic Distortion − dBc
Gain = 1
VO = 2 VPP
RL = 150 Ω
VS = 5 V
−40
−50
HD3
−60
−70
HD2
−80
0
Gain = 2
Rf = 249 Ω
RL = 249 Ω
VO = 1 VPP
VS = 5 V
−60
−70
−80
HD3
−90
HD2
1
10
−100
−30
−40
−50
HD2
−60
−70
HD3
−80
100
−100
1
f − Frequency − MHz
10
f − Frequency − MHz
1
100
10
100
f − Frequency − MHz
Figure 45.
Figure 46.
Figure 47.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−50
−40
Gain = 1
f= 8 MHz
VS = 5 V
−50
Harmonic Distortion − dBc
−60
HD3,
RL = 499Ω
−70
HD3,
RL = 150Ω
−80
HD2, RL
= 499Ω
−90
Gain = 1
f= 32 MHz
VS = 5 V
HD2, RL = 150Ω
−60
HD3,
RL = 499Ω
Harmonic Distortion − dBc
−50
Harmonic Distortion − dBc
−20
−90
−90
−100
Gain = 2
Rf = 249 Ω
RL = 150 Ω
VO = 2 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
0
−10
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
HD3,
RL = 150Ω
−70
HD2, RL = 150Ω
−80
HD2, RL = 499Ω
Gain = 2
Rf = 249 Ω
f = 8 MHz
VS = 5 V
−60
HD3, RL = 150Ω
HD2, RL = 150Ω
−70
−80
HD2, RL = 499Ω
−90
−90
HD3, RL = 499Ω
−100
0
0.5
1
1.5
2
−100
−100
2.5
0
VO − Output Voltage Swing − V
0
2.5
0.5
1
1.5
2
VO − Output Voltage Swing − V
2.5
Figure 48.
Figure 49.
Figure 50.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
−40
−50
HD3, RL = 150Ω
HD2, RL = 150Ω
−60
HD3,
RL = 499Ω
−70
HD2, RL = 499Ω
−80
−90
−100
0
0.5
1
1.5
2
VO − Output Voltage Swing − V
2.5
Figure 51.
45
−40
Third-Order Output Intersept Point − dBm
Gain = 2
Rf = 249 Ω
f = 32 MHz
VS = 5 V
Third-Order Intermodulation Distortion − dBc
−30
Harmonic Distortion − dBc
0.5
1
1.5
2
VO − Output Voltage Swing − V
Gain = 1
RL = 150 Ω
VO = 1 VPP
VS = 5 V
200 kHz Tone
Spacing
−50
−60
−70
−80
−90
−100
10
100
40
35
30
Gain = 1
RL = 150 Ω
VO = 1 VPP
VS = 5 V
200 kHz Tone Spacing
25
20
0
20
40
60
f − Frequency − MHz
f − Frequency − MHz
Figure 52.
Figure 53.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
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15
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TYPICAL CHARACTERISTICS: 5 V (continued)
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
−70
−80
−90
−100
10
40
35
30
0
20
40
100
Hz
1k
10 k
100 k
1M
10 M
1
100 M
f − Frequency − Hz
Figure 54.
Figure 55.
Figure 56.
SETTLING TIME
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
30
2
TA = 85°C
Rising Edge
1.5
25
1
0
−0.5
Falling Edge
VO − Output Voltage − V
Gain = −1
RL = 499 Ω
Rf = 249 Ω
f= 1 MHz
VS = 5 V
0.5
TA = 25°C
Quiescent Current − mA
20
TA = −40°C
15
10
−1
5
−1.5
0
1
VS = 5 V
TA = −40 to 85°C
0.5
0
−0.5
−1
−1.5
0 2
4
6
8
10 12 14 16 18 20 22 24
−2
2
2.5
3
3.5
4
4.5
VS − Supply Voltage − ±V
t − Time − ns
Figure 58.
Figure 59.
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
80
−1
R(ISO) = 15 Ω, CL = 50 pF
−1.5
R(ISO) = 10 Ω, CL = 100 pF
−2
RL = 499 Ω
VS = 5 V
−3
10
Capacitive Load − MHz
Figure 60.
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100
50
60
40
80
30
100
20
Phase
120
10
140
0
160
−10
10 k
180
100 k
80
1M
10 M
TA = −40°C
TA = 25°C
40
100 M
Open-Loop Gain − dB
R(ISO) = 25 Ω, CL = 10 pF
Open-Loop Gain − dB
−0.5
20
Gain
60
10 k
85
0
VS = 5 V
70
0
1
100
1k
RL − Load Resistance − Ω
Figure 57.
0.5
−2.5
10
5
Phase − °
VO − Output Voltage − V
80
f − Frequency − MHz
1.5
Frequency Response − dB
60
10
In
1
100
25
100
Vn
10
I n − Current Noise − pA/
−60
100
Hz
−50
100
Gain = 2
RL = 150 Ω
VO = 2 VPP
VS = 5 V
200 kHz Tone Spacing
Vn − Voltage Noise − nV/
Gain = 2
RL = 150 Ω
VO = 2 VPP
VS = 5 V
200 kHz Tone Spacing
f − Frequency − MHz
16
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
45
−40
Third-Order Output Intersept Point − dBm
Third-Order Intermodulation Distortion − dBc
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
75
70
TA = 85°C
65
60
55
50
1G
f − Frequency − Hz
2.5
3
3.5
4
4.5
5
Case Temperature − °C
Figure 61.
Figure 62.
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Product Folder Link(s): THS4271 THS4275
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THS4275
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS: 5 V (continued)
REJECTION RATIOS
vs
CASE TEMPERATURE
100
120
VS = 5 V
90
PSRR+
70
PSRR−
60
CMRR
50
PSRR+
100
PSRR−
Rejection Ratios − dB
40
30
80
60
CMMR
40
20
20
VS = 5 V
10
0
10 k
100 k
1M
10 M
f − Frequency − Hz
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
100 M
VS = 5 V
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
Input Common-Mode Voltage Range − V
Figure 63.
Figure 64.
Figure 65.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
INPUT BIAS AND OFFSET
CURRENT vs
CASE TEMPERATURE
SMALL-SIGNAL TRANSIENT
RESPONSE
8
VS = ±5 V
2
1
6
IOS
5
1.14
4
1.13
IIB+
3
1.12
2
1.11
1
1.1
Figure 66.
LARGE-SIGNAL TRANSIENT
RESPONSE
1.5
Single-Ended Output Voltage − V
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = 5 V
−0.5
−1
1
2
3 4
5
6
7
8 9
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = 5 V
−0.1
−0.2
−0.3
0
Figure 69.
6
8
10
12
OVERDRIVE RECOVERY
CLOSED-LOOP OUTPUT
IMPEDANCE vs
FREQUENCY
14
16
1000
1.5
2
1
1
0.5
0
0
−1
−0.5
−2
−1
−1.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
t − Time − ns
4
t − Time − ns
VS = 5 V
0
10 11
2
Figure 68.
−3
−1.5
0
0
Figure 67.
3
0
0.1
TC − Case Temperature − °C
TC − Case Temperature − °C
0.5
0.2
1.09
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1
1.15
Figure 70.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
Closed-Loop Output Impedance − Ω
VS = 5 V
3
1.16
IIB−
VO − Output Voltage − V
I IB − Input Bias Current − µ A
7
4
0.3
1.17
VS = 5 V
I OS − Input Offset Current − µ A
5
VOS − Input Offset Voltage − mV
100
Case Temperature − °C
VI − Input Voltage − V
Rejection Ratios − dB
80
VO − Output Voltage − V
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
CMRR − Common-Mode Rejection Ratio − dB
REJECTION RATIOS
vs
FREQUENCY
100
Gain = 1
RL = 499 Ω
VIN = 1 dBm
VS = 5 V
10
1
0.1
0.01
0.001
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 71.
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17
THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN OUTPUT
IMPEDANCE vs
FREQUENCY
1M
TA = 85°C
1000
TA = 25°C
800
TA = −40°C
600
400
200
0
2.5
3
3.5
4
4.5
VS − Supply Voltage − ±V
Figure 72.
18
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5
6.5
45
Input
Gain = 1
RL = 150 Ω
PIN = −1 dBm
VS = 5 V
I O− Output Current Level − mV
Power-down Output Impedance − Ω
Power-down Quiescent Current − µ A
1200
TURN-ON AND TURN-OFF TIME vs
DELAY TIME
10 k
100
40
5
35
3.5
30
2
25
0.5
20
−1
15
10
0.5
Gain = −1
RL = 150 Ω
VS = 5 V
0
1
100 k
0
10 M
100 M
1M
f − Frequency − Hz
1G
V I − Input Voltage Level − V
POWER-DOWN QUIESCENT
CURRENT vs
SUPPLY VOLTAGE
10
20
30
40
50
60
70
t − Time − µs
Figure 73.
Figure 74.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
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THS4275
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
APPLICATION INFORMATION
MAXIMUM DIE TEMPERATURE TO PREVENT
OSCILLATION
The THS4271 and THS4275 may have low-level
oscillation when the die temperature (also called
junction temperature) exceeds +60°C.
The oscillation is a result of the internal design of the
bias circuit, and external configuration is not expected
to mitigate or reduce the problem. This problem
occurs randomly because of normal process
variations and normal testing cannot identify problem
units.
The THS4211 and THS4215 are recommended
replacement devices.
The die temperature depends on the power
dissipation and the thermal resistance of the device.
space
The die temperature can be approximated with the
following formula:
Die Temperature = PDISS × θJA + TA
Where:
PDISS = (VS+– VS–) × (IQ + ILOAD) – (VOUT × ILOAD)
Table 1 shows the estimated the maximum ambient
temperature (TA max) in degrees Celsius for each
package option of the THS4271 and THS4275 using
the thermal dissipation rating given in the Dissipation
Ratings table for a JEDEC standard High-K test PCB.
For each case shown, RL = 499 Ω to ground and the
quiescent current = 27 mA (the maximum over the
0°C to +70°C temperature range). The last entry for
each package option (shaded cells) lists the
worst-case scenario where the power supply is
single-supply 10 V and ground and the output voltage
is 5 V DC.
Table 1. Estimated Maximum Ambient Temperature Per Package Option
PACKAGE
DEVICE
VS+
VS–
SOIC
THS4271D
THS4271DR
5V
–5 V
THS4275D
10 V
0V
VSON
THS4271DRBT
THS4271DRBR
5V
–5 V
θJA
TA max
0V
33.7°C
2 VPP
32.4°C
4 VPP
6 VPP
THS4275DR
Worst Case
VOUT
97.5°C/W
31.3°C
30.4°C
8 VPP
29.7°C
5 DC
28.8°C
0V
47.6°C
2 VPP
47.0°C
4 VPP
45.8°C/W
46.5°C
THS4275DRBT
6 VPP
THS4275DRBR
8 VPP
45.8°C
Worst Case
5 DC
45.3°C
PowerPad™ MSOP
0V
44.2°C
THS4271DGN
2 VPP
43.5°C
THS4271DGNR
10 V
0V
46.1°C
5V
–5 V
4 VPP
58.4°C/W
42.8°C
THS4275DGN
6 VPP
THS4275DGNR
8 VPP
41.9°C
5 DC
41.3°C
0V
–10.2°C
2 VPP
–13.6°C
Worst Case
10 V
0V
MSOP
THS4271DGK
THS4271DGKR
5V
–5 V
4 VPP
260°C/W
42.3°C
–16.5°C
THS4275DGK
6 VPP
THS4275DGKR
8 VPP
–20.8°C
5 DC
–23.2°C
Worst Case
10 V
0V
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–18.9°C
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19
THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
HIGH-SPEED OPERATIONAL AMPLIFIERS
WIDEBAND, NONINVERTING OPERATION
The THS4271 and the THS4275 operational
amplifiers set new performance levels, combining low
distortion, high slew rates, low noise, and a unity-gain
bandwidth in excess of 1 GHz. To achieve the full
performance of the amplifier, careful attention must
be paid to printed-circuit board (PCB) layout and
component selection.
The THS4271 and the THS4275 are unity gain
stable,
1.4-GHz
voltage-feedback
operational
amplifiers, with and without power-down capability,
designed to operate from a single 5-V to 15-V power
supply.
The THS4275 provides a power-down mode,
providing the ability to save power when the amplifier
is inactive. A reference pin is provided to allow the
user the flexibility to control the threshold levels of the
power-down control pin.
Applications Section Contents
• Wideband, Noninverting Operation
• Wideband, Inverting Gain Operation
• Single-Supply Operation
• Saving Power with Power-Down Functionality and
Setting Threshold Levels with the Reference Pin
• Power Supply Decoupling Techniques and
Recommendations
• Using the THS4271 as a DAC Output Buffer
• Driving an ADC With the THS4271
• Active Filtering With the THS4271
• Building a Low-Noise Receiver with the THS4271
• Linearity:
Definitions,
Terminology,
Circuit
Techniques and Design Tradeoffs
• An Abbreviated Analysis of Noise in Amplifiers
• Driving Capacitive Loads
• Printed Circuit Board Layout Techniques for
Optimal Performance
• Power Dissipation and Thermal Considerations
• Performance vs Package Options
• Evaluation
Fixtures,
Spice
Models,
and
Applications Support
• Additional Reference Material
• Mechanical Package Drawings
Figure 75 is the noninverting gain configuration of 2
V/V used to demonstrate the typical performance
curves. Most of the curves were characterized using
signal sources with 50-Ω source impedance, and with
measurement equipment presenting a 50-Ω load
impedance. In Figure 75, the 49.9-Ω shunt resistor at
the VIN terminal matches the source impedance of the
test generator. The total 499-Ω load at the output,
combined with the 498-Ω total feedback network load,
presents the THS4271 and THS4275 with an
effective output load of 249 Ω for the circuit of
Figure 75.
Voltage feedback amplifiers, unlike current feedback
designs, can use a wide range of resistors values to
set their gain with minimal impact on their stability
and frequency response. Larger-valued resistors
decrease the loading effect of the feedback network
on the output of the amplifier, but this enhancement
comes at the expense of additional noise and
potentially lower bandwidth. Feedback resistor values
between 249 Ω and 1 kΩ are recommended for most
situations.
5 V +V
S
+
100 pF
50 Ω Source
0.1 µF 6.8 µF
+
VI
VO
THS4271
49.9 Ω
_
Rf
249 Ω
499 Ω
249 Ω
Rg
0.1 µF 6.8 µF
100 pF
+
space
space
−5 V
−VS
space
Figure 75. Wideband, Noninverting
Gain Configuration
space
20
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
WIDEBAND, INVERTING GAIN OPERATION
Since
the
THS4271
and
THS4275
are
general-purpose,
wideband
voltage-feedback
amplifiers, several familiar operational amplifier
applications circuits are available to the designer.
Figure 76 shows a typical inverting configuration
where the input and output impedances and noise
gain from Figure 75 are retained in an inverting circuit
configuration. Inverting operation is one of the more
common
requirements
and
offers
several
performance benefits. The inverting configuration
shows improved slew rates and distortion due to the
pseudo-static voltage maintained on the inverting
input.
5 V +V
S
+
100 pF
0.1 µF
6.8 µF
+
RT
130 Ω
CT
0.1 µF
VO
THS4271
_
499 Ω
50 Ω Source
VI
Rg
Rf
249 Ω
RM
61.9 Ω
249 Ω
0.1 µF
The next major consideration is that the signal source
impedance becomes part of the noise gain equation
and hence influences the bandwidth. For example,
the RM value combines in parallel with the external
50-Ω source impedance (at high frequencies),
yielding an effective source impedance of 50 Ω ||
61.9Ω = 27.7 Ω. This impedance is then added in
series with Rg for calculating the noise gain. The
result is 1.9 for Figure 76, as opposed to the 1.8 if RM
is eliminated. The bandwidth is lower for the gain of
–2 circuit, Figure 76 (NG=+1.9), than for the gain of
+2 circuit in Figure 75.
+
100 pF
−5 V
6.8 µF
must be taken when dealing with low inverting gains,
as the resulting feedback resistor value can present a
significant load to the amplifier output. For an
inverting gain of 2, setting Rg to 49.9 Ω for input
matching eliminates the need for RM but requires a
100-Ω feedback resistor. This has an advantage of
the noise gain becoming equal to 2 for a 50-Ω source
impedance—the same as the noninverting circuit in
Figure 75. However, the amplifier output now sees
the 100-Ω feedback resistor in parallel with the
external load. To eliminate this excessive loading, it is
preferable to increase both Rg and Rf, values, as
shown in Figure 76, and then achieve the input
matching impedance with a third resistor (RM) to
ground. The total input impedance becomes the
parallel combination of Rg and RM.
−VS
Figure 76. Wideband, Inverting Gain
Configuration
In the inverting configuration, some key design
considerations must be noted. One is that the gain
resistor (Rg) becomes part of the signal channel input
impedance. If the input impedance matching is
desired (which is beneficial whenever the signal is
coupled through a cable, twisted pair, long PCB
trace, or other transmission line conductors), Rg may
be set equal to the required termination value and Rf
adjusted to give the desired gain. However, care
The last major consideration in inverting amplifier
design is setting the bias current cancellation resistor
on the noninverting input. If the resistance is set
equal to the total dc resistance looking out of the
inverting terminal, the output dc error, due to the input
bias currents, is reduced to (input offset current)
multiplied by Rf in Figure 76, the dc source
impedance looking out of the inverting terminal is 249
Ω || (249Ω + 27.7 Ω) = 130 Ω. To reduce the
additional high-frequency noise introduced by the
resistor at the noninverting input, and power-supply
feedback, RT is bypassed with a capacitor to ground.
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THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
SINGLE-SUPPLY OPERATION
The THS4271 is designed to operate from a single
5-V to 15-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to allow for the maximum output voltage swing. The
circuits shown in Figure 77 demonstrate methods to
configure an amplifier in a manner conducive for
single-supply operation.
+VS
50 Ω Source
+
VI
49.9 Ω
RT
THS4271
VO
_
499 Ω
+VS
2
+VS
2
Power-Down Reference Pin Operation
249 Ω
In addition to the power-down pin, the THS4275 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. Operation of the
reference pin as it relates to the power-down pin is
described below.
Rf
249 Ω
VS
50 Ω Source
Rg
61.9 Ω
+VS
2
249 Ω
RT
_
THS4271
+
VO
499 Ω
+VS
2
Figure 77. DC-Coupled Single-Supply Operation
Saving Power with Power-Down Functionality and
Setting Threshold Levels with the Reference Pin
The THS4275 features a power-down pin (PD) which
lowers the quiescent current from 22 mA down to 700
μA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
Enable Threshold Voltage, the device is on. Below
the Disable Threshold Voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
22
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
Rf
Rg
249 Ω
VI
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
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In most split-supply applications, the reference pin is
connected to ground. In some cases, the user may
want to connect it to the negative or positive supply
rail. In either case, the user needs to be aware of the
voltage level thresholds that apply to the power-down
pin. Table 2 and Table 3 show examples and
illustrate the relationship between the reference
voltage and the power-down thresholds.
Table 2. Power-Down Threshold Voltage Levels
(REF ≤ MIDRAIL)
SUPPLY
VOLTAGE
(V)
REFERENCE
PIN VOLTAGE
(V)
±5
5
ENABLE
LEVEL
(V)
DISABLE
LEVEL
(V)
GND
≥ 1.8
≤1
-2.5
≥ -0.7
≤ –1.5
-5
≥ -3.2
≤ -4
GND
≥ 1.8
≤1
1
≥ 2.8
≤2
2.5
≥ 4.3
≤ 3.5
In Table 2, the threshold levels are derived by the
following equations:
REF + 1.8 V for enable
REF + 1 V for disable
Note that in order to maintain these threshold levels,
the reference pin can be any voltage between VS– or
GND up to Vs/2 (midrail).
Copyright © 2002–2009, Texas Instruments Incorporated
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THS4275
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
Table 3. Power-Down Threshold Voltage Levels
(REF > MIDRAIL)
SUPPLY
VOLTAGE
(V)
REFERENCE
PIN VOLTAGE
(V)
ENABLE
LEVEL
(V)
DISABLE
LEVEL
(V)
Floating or 5
≥4
≤ 3.3
2.5
≥ 1.5
≤ 0.8
1
≥0
≤ -0.7
Floating or 5
≥ 3.3
≤ 3.3
4
≥3
≤ 2.3
3.5
≥ 2.5
≤ 1.8
±5
5
In Table 3, the threshold levels are derived by the
following equations:
REF - 1 V for enable
REF - 1.7 V for disable
Note that in order to maintain these threshold levels,
the reference pin can be any voltage between (VS+/2)
+ 1 V to VS+.
The recommended mode of operation is to tie the
reference pin to midrail, thus setting the threshold
levels to midrail +1 V and midrail +1.8 V.
A 100-pF capacitor can be used across the
supplies as well for extremely high-frequency
return currents, but often is not required.
APPLICATION CIRCUITS
Driving an Analog-to-Digital Converter With the
THS4271
The THS4271 can be used to drive high-performance
analog-to-digital converters. Two example circuits are
presented below.
The first circuit uses a wideband transformer to
convert a single-ended input signal into a differential
signal. The differential signal is then amplified and
filtered by two THS4271 amplifiers. This circuit
provides low intermodulation distortion, suppressed
even-order distortion, 14 dB of voltage gain, a 50-Ω
input impedance, and a single-pole filter at 100 MHz.
For applications without signal content at dc, this
method of driving ADCs can be very useful. Where dc
information content is required, the THS4500 family
of fully differential amplifiers may be applicable.
5V
NO. OF CHANNELS
PACKAGES
Single (8-pin)
THS4275D, THS4275DGN, and
THS4275DRB
Power-Supply Decoupling Techniques and
Recommendations
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance.
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths, with the
exception of the areas underneath the input and
output pins.
4. Recommended
values
for
power-supply
decoupling include a bulk decoupling capacitor
(6.8 μF to 22 μF), a mid-range decoupling
capacitor (0.1 μF) and a high frequency
decoupling capacitor (1000 pF) for each supply.
VCM
+
THS4271
_
50 Ω
(1:4 Ω)
Source 1:2
100 Ω
-5 V
249 Ω
24.9 Ω
ADS5422
22 pF
14-Bit, 62 Msps
22 pF
100 Ω
24.9 Ω
249 Ω
_
THS4271
VCM
+
Figure 78. A Linear, Low-Noise, High-Gain
ADC Preamplifier
The second circuit depicts single-ended ADC drive.
While not recommended for optimum performance
using converters with differential inputs, satisfactory
performance can sometimes be achieved with
single-ended input drive. An example circuit is shown
here for reference.
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Product Folder Link(s): THS4271 THS4275
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23
THS4271
THS4275
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
50 Ω
Source
www.ti.com
THS4271
+5 V
+
VI
49.9 Ω
RT
THS4271
_
-5 V
100 Ω
ADS807
100 Ω
12-Bit,
Rf
1.82 kΩ
249 Ω
100 Ω
249 Ω
14-Bit,
400 MSps
249 Ω
1 nF
IF+
DAC5675
0.1 µF
CF
1 nF
CM 53 Msps
IN
249 Ω
Rg
_
IN
68 pf
16.5 Ω
+
3.3 V 3.3 V
0.1 µF
RISO
249 Ω
49.9 Ω
249 Ω
49.9 Ω
RF(out)
IF1 nF
1 nF
_
For best performance, high-speed ADCs should be driven
differentially. See the THS4500 family of devices for more
information.
+
Figure 79. Driving an ADC With a
Single-Ended Input
THS4271
Figure 81. Differential Mixer Drive Circuit
Using the DAC5675 and the THS4271
Using the THS4271 as a DAC Output Buffer
Two example circuits are presented here showing the
THS4271 buffering the output of a digital-to-analog
converter. The first circuit performs a differential to
single-ended
conversion
with
the
THS4271
configured as a difference amplifier. The difference
amplifier can double as the termination mechanism
for the DAC outputs as well.
3.3 V 3.3 V
100 Ω
Active Filtering With the THS4271
High-frequency active filtering with the THS4271 is
achievable due to the amplifier high slew-rate, wide
bandwidth, and voltage-feedback architecture.
Several options are available for high-pass, low-pass,
bandpass, and bandstop filters of varying orders. A
simple two-pole low pass filter is presented here as
an example, with two poles at 100 MHz.
249 Ω
100 Ω
6.8
pF
+5 V
DAC5675
14-Bit,
400 MSps
CF
249 Ω
124 Ω
_
50 Ω Source
49.9 Ω
THS4271
VI
+
249 Ω
-5 V
249 Ω
249 Ω
RF
LO
249 Ω
61.9 Ω
5V
_
THS4271
+
49.9 Ω
VO
33 pF
−5 V
Figure 80. Differential to Single-Ended
Conversion of a High-Speed DAC Output
Figure 82. A Two-Pole Active Filter With Two
Poles Between 90 MHz and 100 MHz
For cases where a differential signaling path is
desirable, a pair of THS4271 amplifiers can be used
as output buffers. The circuit depicts differential drive
into a mixer IF inputs, coupled with additional signal
gain and filtering.
24
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THS4271
THS4275
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
A Low-Noise Receiver With the THS4271
THEORY AND GUIDELINES
A combination of two THS4271 amplifiers can create
a high-speed, low-distortion, low-noise differential
receiver circuit as depicted in Figure 83. With both
amplifiers operating in the noninverting mode of
operation, the circuit presents a high load impedance
to the source. The designer has the option of
controlling the impedance through termination
resistors if a matched termination impedance is
desired.
100 Ω
VI+
+
49.9 Ω
VO+
_
249 Ω
499 Ω
100 Ω
249 Ω
_
VI−
49.9 Ω
+
Figure 83. A High Input Impedance, Low-Noise,
Differential Receiver
A modification on this circuit to include a difference
amplifier turns this circuit into a high-speed
instrumentation amplifier, as shown in Figure 84.
Equation 1 calculates the output voltage for this
circuit.
100 Ω
+
VI-
Rg2
The
THS4271
provides
excellent
distortion
performance into a 150-Ω load. Relative to alternative
solutions, it provides exceptional performance into
lighter loads, as well as exceptional performance on a
single 5-V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the second harmonic dominates the total harmonic
distortion with a negligible third harmonic component.
Focusing then on the second harmonic, increasing
the load impedance improves distortion directly. The
total load includes the feedback network; in the
noninverting configuration (Figure 75) this is the sum
of Rf and Rg, while in the inverting configuration
(Figure 76), only Rf needs to be included in parallel
with the actual load.
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
VO−
100 Ω
Distortion Performance
The
THS4271
features
excellent
distortion
performance for monolithic operational amplifiers.
This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of operational
amplifiers to desired linearity specifications in RF
receiver chains.
Amplifiers are generally thought of as linear devices.
The output of an amplifier is a linearly-scaled version
of the input signal applied to it. However, amplifier
transfer functions are nonlinear. Minimizing amplifier
nonlinearity is a primary design goal in many
applications.
Rf2
THS4271
_
Rf1
Rg1
_
100 Ω
_
Rf1
THS4271
+
49.9 Ω
VO
THS4271
Rg2
+
49.9 Ω
Rf2
VI+
Figure 84. A High-Speed Instrumentation
Amplifier
ǒ
Ǔ
ǒ Ǔ
2R f1
ǒV i)–V i–Ǔ R f2
VO + 1 1 )
2
Rg1
Rg2
(1)
space
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THS4275
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Intercept points are specifications long used as key
design criteria in the RF communications world as a
metric for the intermodulation distortion performance
of a device in the signal chain (e.g., amplifiers,
mixers, etc.). Use of the intercept point, rather than
strictly the intermodulation distortion, allows simpler
system-level calculations. Intercept points, like noise
figures, can be easily cascaded back and forth
through a signal chain to determine the overall
receiver chain intermodulation distortion performance.
The relationship between intermodulation distortion
and intercept point is depicted in Figure 85 and
Figure 86.
PO
PO
Power
∆fc = fc - f1
∆fc = f2 - fc
IMD3 = PS - PO
PS
fc - 3∆f
f2
However, with an operational amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to their outputs regardless of the impedance present,
it is important to comprehend this when evaluating
the intercept point of an operational amplifier. The
THS4271 yields optimum distortion performance
when loaded with 150 Ω to 1 kΩ, very similar to the
input impedance of an analog-to-digital converter
over its input frequency band.
As a result, terminating the input of the ADC to 50Ω
can actually be detrimental to systems performance.
The discontinuity between open-loop, class-A
amplifiers and closed-loop, class-AB amplifiers
becomes apparent when comparing the intercept
points of the two types of devices. Equation 2 and
Equation 3 give the definition of an intercept point,
relative to the intermodulation distortion.
ŤIMD 3Ť
OIP 3 + P O )
where
2
(2)
PS
f1 fc
Due to the intercept point ease of use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related
design decisions. Traditionally, these systems use
primarily class-A, single-ended RF amplifiers as gain
blocks. These RF amplifiers are typically designed to
operate in a 50-Ω environment. Giving intercept
points in dBm, implies an associated impedance (50
Ω).
fc + 3∆f
ǒ
f - Frequency - MHz
ǒ
Figure 85.
P O + 10 log
Ǔ
Ǔ
V 2P
2RL 0.001
(3)
NOTE: PO is the output power of a single tone, RL
is the load resistance, and VP is the peak
voltage for a single tone.
POUT
(dBm)
1X
NOISE ANALYSIS
OIP3
PO
IIP3
IMD3
3X
PIN
(dBm)
High slew rate, unity gain stable, voltage-feedback
operational amplifiers usually achieve the slew rate at
the expense of a higher input noise voltage. The
3-nV/√Hz input voltage noise for the THS4271 and
THS4275 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the
two input-referred current noise terms (3 pA/√Hz),
combine to give low output noise under a wide variety
of operating conditions. Figure 87 shows the amplifier
noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
PS
Figure 86.
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Product Folder Link(s): THS4271 THS4275
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SLOS397F – JULY 2002 – REVISED OCTOBER 2009
THS4271/THS4275
ENI
+
RS
IBN
ERS
EO
_
4kTRS
ERF
Rf
Rg
4kT
Rg
4kTRf
IBI
4kT = 1.6E-20J
at 290K
Figure 87. Noise Analysis Model
The total output spot noise voltage can be computed
as the square of all square output noise voltage
contributors. Equation 4 shows the general form for
the output noise voltage using the terms shown in
Figure 87:
EO +
Ǹǒ
2
Ǔ
2
ENI 2 ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRfǓ ) 4kTRfNG
(4)
Dividing this expression by the noise gain [NG=(1+
Rf/Rg)] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
EO +
Ǹ
E NI
2
2
ǒ Ǔ ) 4kTR
NG
2
I R
) ǒI BNRSǓ ) 4kTR S ) BI f
NG
f
additional pole in the signal path that can decrease
the phase margin. When the primary considerations
are frequency response flatness, pulse response
fidelity, or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4271. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4271 output pin (see the Board Layout
Guidelines section).
The criterion for setting this R(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load. For a gain of +2, the frequency response at the
output pin is already slightly peaked without the
capacitive load, requiring relatively high values of
R(ISO) to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
(5)
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4271 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier open-loop output resistance is
considered, this capacitive load introduces an
0.5
0
Normalized Gain - dB
Evaluation of these two equations for the circuit and
component values shown in Figure 75 will give a total
output spot noise voltage of 12.2 nV/√Hz and a total
equivalent input spot noise voltage of 6.2 nV/√Hz.
This includes the noise added by the resistors. This
total input-referred spot noise voltage is not much
higher than the 3-nV/√Hz specification for the
amplifier voltage noise alone.
-0.5
-1
-1.5
R(ISO) = 25 Ω CL = 10 pF
R(ISO) = 15 Ω CL = 100 pF
R(ISO) = 10 Ω CL = 50 pF
-2
-2.5
-3
1M
RL = 499 Ω
VS =±5 V
10 M
100 M
f - Frequency - Hz
Figure 88. Isolation Resistor Diagram
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THS4275
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BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the THS4271 requires
careful attention to board layout parasitics and
external component types.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-μF
de-coupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (2.2-μF to 6.8-μF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PCB.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4271. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep their
leads and PC board trace length as short as
possible. Never use wire-wound type resistors in
a high frequency application. Since the output pin
and inverting input pin are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components,
such
as
noninverting
input-termination resistors, should also be placed
close to the package. Where double-side
component mounting is allowed, place the
feedback resistor directly under the package on
the other side of the board between the output
and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create
significant time constants that can degrade
28
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performance.
Good
axial
metal-film
or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2 kΩ, this parasitic capacitance can add a pole
and/or a zero below 400-MHz that can effect
circuit operation. Keep resistor values as low as
possible,
consistent
with
load
driving
considerations. A good starting point for design is
to set the Rf to 249-Ω for low-gain, noninverting
applications. Doing this automatically keeps the
resistor noise terms low, and minimizes the effect
of their parasitic capacitance.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set RISO from the
plot of recommended RISO vs capacitive load.
Low parasitic capacitive loads (
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