THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
500-mA DUAL DIFFERENTIAL LINE DRIVER
Check for Samples: THS6012
FEATURES
1
•
•
2
•
•
•
•
•
•
•
ADSL Differential Line Driver
400 mA Minimum Output Current Into 25-Ω
Load
High Speed
– 140 MHz Bandwidth (-3dB) With 25-Ω Load
– 315 MHz Bandwidth (-3dB) With 100-Ω Load
– 1300 V/μs Slew Rate, G = 5
Low Distortion
– -72 dB 3rd Order Harmonic Distortion at
f = 1 MHz, 25-Ω Load, and 20 VPP
Independent Power Supplies for Low
Crosstalk
Wide Supply Range ±4.5 V to ±16 V
Thermal Shutdown and Short Circuit
Protection
Improved Replacement for AD815
Evaluation Module Available
Thermally Enhanced SOIC (DWP) PowerPAD
Package
(TOP VIEW)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VCC −
1OUT
VCC+
1IN+
1IN−
NC
NC
NC
NC
NC
VCC −
2OUT
VCC+
2IN+
2IN−
NC
NC
NC
NC
NC
Cross Section View Showing PowerPAD
MicroStar Junior (GQE) Package
(TOP VIEW)
DESCRIPTION
The THS6012 contains two high-speed drivers
capable of providing 400 mA output current (min) into
a 25 Ω load. These drivers can be configured
differentially to drive a 50-VPP output signal over lowimpedance lines. The drivers are current feedback
amplifiers, designed for the high slew rates necessary
to support low total harmonic distortion (THD) in
xDSL applications. The THS6012 is ideally suited for
asymmetrical
digital
subscriber
line
(ADSL)
applications at the central office, where it supports
the high-peak voltage and current requirements of
this application.
Separate power supply connections for each driver
are provided to minimize crosstalk. The THS6012 is
available in the small surface-mount, thermally
enhanced 20-pin PowerPAD™ package.
(SIDE VIEW)
HIGH-SPEED xDSL LINE DRIVER/RECEIVER
FAMILY
DEVICE
DRIVER
RECEIVER
•
DESCRIPTION
Dual differential line drivers and
receivers
THS6002
•
THS6012
•
500-mA Dual differential line driver
THS6022
•
250-mA Dual differential line driver
THS6032
•
Low-power ADSL central office line
driver
THS6062
•
Low-noise ADSL receiver
THS7002
•
Low-noise programmable gain ADSL
receiver
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. AVAILABLE OPTIONS
PACKAGED DEVICE
(1)
TA
PowerPAD PLASTIC
SMALL OUTLINE (1)
(DWP)
MicroStar Junior
(GQE)
EVALUATION
MODULE
0°C to 70°C
THS6012CDWP
THS6012CGQE
THS6012EVM
-40°C to 85°C
THS6012IDWP
THS6012IGQE
—
The PWP packages are available taped and reeled. Add an R suffix to the device type (i.e.,
THS6012CPWPR)
FUNCTIONAL BLOCK DIAGRAM
Driver 1
3 V +
CC
1IN+
4
+
2
1IN–
5
1
Driver 2
2IN+
17
18
2IN–
VCC+
2OUT
_
20
2
VCC–
+
19
16
1OUT
_
VCC–
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
Terminal Functions
TERMINAL
DWP PACKAGE NO.
GQE PACKAGE NO.
1OUT
NAME
2
A3
1IN-
5
F1
1IN+
4
D1
2OUT
19
A7
2IN-
16
F9
2IN+
17
D9
VCC+
3, 18
B1, B9
VCC-
1, 20
A4, A6
NC
6, 7, 8 ,9, 10, 11, 12, 13,
14, 15
NA
PIN ASSIGNMENTS
A
VCC+
2
NC
NC
NC
B
C
1N+
1
NC
D
E
NC
F
3
4
5
6
2OUT
V CC–
V CC–
1OUT
MicroStar Junior (GQE) Package
(TOP VIEW)
7
NC
NC
NC
8
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC+
NC
2IN+
NC
1IN–
2IN–
G
NC
NC
NC
NC
NC
NC
NC
NC
NC
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
J
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTE: Shaded terminals are used for thermal connection to the ground plane.
Copyright © 1998–2012, Texas Instruments Incorporated
3
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC
Supply voltage, VCC+ to VCC-
33 V
VI
Input voltage (driver and receiver)
±VCC
IO
Output current (driver)
VID
Differential input voltage
(2)
800 mA
6V
Continuous total power dissipation at (or below) TA = 25°C
(2)
5.8 W
TA
Operating free air temperature
-40°C to 85°C
Tstg
Storage temperature
-65°C to 125°C
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS6012 incorporates a PowerPad on the underside of the chip. This acts as a heatsink and must be connected to a thermal
dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum junction temperature, which could
permanently damage the device. See the Thermal Information section of this document for more information about PowerPad
technology.
RECOMMENDED OPERATING CONDITIONS
Split supply
VCC
Supply voltage
TA
Operating free-air temperature
Single supply
C suffix
I suffix
MIN
TYP MAX
±4.5
±16
9
32
0
70
–40
85
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
VCC = ±15 V, RL = 25 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Small-signal bandwidth (-3 dB)
BW
Bandwidth for 0.1 dB flatness
Full power bandwidth
SR
Slew rate
ts
Settling time to 0.1%
VI = 200 mV,
G = 1,
RF = 680 Ω,
RL = 25 Ω
VCC = ±15 V
140
VI = 200 mV,
G = 1,
RF = 1 kΩ,
RL = 25 Ω
VCC = ±5 V
100
VI = 200 mV,
G = 2,
RF = 620 Ω,
RL = 25 Ω
VCC = ±15 V
120
VI = 200 mV,
G = 2,
RL = 25 Ω,
RF = 820 Ω,
VCC = ±5 V
100
VI = 200 mV,
G = 1,
RF = 820 Ω,
RL = 100 Ω
VCC = ±15 V
315
VI = 200 mV,
G = 2,
RF = 560 Ω,
RL = 100 Ω
VCC = ±15 V
265
VCC = ±5 V,
RF = 820 Ω
30
VCC = ±15 V,
RF = 680 Ω
40
VI = 200 mV,
G=1
MHz
MHz
VCC = ±15 V,
VO(PP) = 20 V
20
VCC = ±5 V,
VO(PP) = 4 V
35
VCC = ±15 V,
VO = 20 V(PP),
G=5
1300
VCC = ±5 V,
VO = 5 V(PP),
G=2
900
G=2
70
0 V to 10 V Step,
MHz
V/μs
ns
NOISE/DISTORTION PERFORMANCE
(1)
4
Full range is 0°C to 70°C for the THS6012C and -40°C to 85°C for the THS6012I.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
VCC = ±15 V, RL = 25 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
THD
Total harmonic distortion
Input voltage noise
In
Input noise
current
AD
Differential gain error
Positive (IN+)
Negative (IN-)
Differential phase error
Crosstalk
RF = 680 Ω,
f = 1 MHz
VCC = ±5 V,
G = 2,
RF = 680 Ω,
f = 1 MHz
-65
VO(PP) = 2 V
-79
VO(PP) = 2 V
-76
G = 2,
RL = 150 Ω,
Driver to driver VI = 200 mV,
MAX
nV/√Hz
11.5
pA/√Hz
16
NTSC, 40 IRE
Modulation
VCC = ±5 V
0.04%
VCC = ±15 V
0.05%
NTSC, 40 IRE
Modulation
VCC = ±5 V
0.07°
VCC = ±15 V
0.08°
f = 1 MHz
UNIT
dBc
1.7
VCC = ±5 V or ±15 V, f = 10 kHz, G = 2
G = 2,
RL = 150 Ω,
TYP
VO(PP) = 20 V
VCC = ±5 V or ±15 V, f = 10 kHz, G = 2, Singleended
Vn
φD
VCC = ±15 V,
G = 2,
MIN
-62
dB
DC PERFORMANCE
Open loop transresistance
VIO
VCC = ±5 V
1.5
VCC = ±15 V
Input offset voltage
VCC = ±5 V or ±15 V
Input offset voltage drift
VCC = ±5 V or ±15 V,
Differential input offset voltage
VCC = ±5 V or ±15 V
Input bias current
Positive
TA = 25°C
2
TA = full range
TA = full range
20
TA = 25°C
1.5
TA = full range
3
Differential input offset voltage drift VCC = ±5 V or ±15 V,
9
12
TA = 25°C
4
TA = full range
10
12
TA = 25°C
Differential
4
5
TA = full range
VCC = ±5 V or ±15 V
5
7
TA = 25°C
Negative
IIB
MΩ
5
1.5
8
TA = full range
11
TA = full range
10
mV
μV/°C
mV
μA
μA
μA
μV/°C
INPUT CHARACTERISTICS
VICR
Common-mode input voltage
range
Common-mode rejection ratio
CMRR Differential common-mode
rejection ratio
VCC = ±5 V
±3.6
±3.7
VCC = ±15 V
±13.4
±13.5
62
70
VCC = ±5 V or ±15 V,
TA = full range
100
V
dB
RI
Input resistance
300
kΩ
CI
Differential input capacitance
1.4
pF
OUTPUT CHARACTERISTICS
VCC = ±5 V
Single ended
VO
RL = 25 Ω
VCC = ±15 V
Output voltage
swing
VCC = ±5 V
Differential
RL = 50 Ω
VCC = ±15 V
IO
(2)
Output current (2)
RL = 5 Ω,
VCC = ±5 V
RL = 25 Ω,
VCC = ±15 V
3 to
-2.8
3.2 to
-3
11.8 to 11.5
12.5 to 12.2
6 to
-5.6
6.4 to
-6
23.6 to 23
25 to 24.4
500
400
500
V
V
mA
A heat sink is required to keep the junction temperature below absolute maximum when an output is heavily loaded or shorted. See
absolute maximum ratings and Thermal Information section.
Copyright © 1998–2012, Texas Instruments Incorporated
5
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VCC = ±15 V, RL = 25 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
IOS
Short-circuit output current
RO
Output resistance
MIN
TYP
(2)
MAX
UNIT
800
mA
13
Ω
Open loop
POWER SUPPLY
Split supply
VCC
Power supply operating range
ICC
Quiescent current (each driver)
±4.5
±16.5
9
33
Single supply
VCC = ±5 V,
VCC = ±15 V
VCC = ±5 V
PSRR Power supply rejection ratio
VCC = ±15 V
TA = full range
V
12
TA = 25°C
11.5
TA = full range
13
mA
15
TA = 25°C
-68
TA = full range
-65
TA = 25°C
-64
TA = full range
-62
-74
dB
-72
dB
PARAMETER MEASUREMENT INFORMATION
1 kΩ
1 kΩ
1 kΩ
–
Driver 1
–
VO
+
VI
VO
25 Ω
50 Ω
+
25 Ω
1 kΩ
Driver 2
VI
50 Ω
Figure 1. Input-to-Output Crosstalk Test Circuit
RG
RF
15 V
–
VO
+
VI
50 Ω
–15 V
RL
25 Ω
Figure 2. Test Circuit, Gain = 1 + (RF/RG)
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Supply voltage
3
vs Load resistance
4
Input offset voltage
vs Free-air temperature
5
IIB
Input bias current
vs Free-air temperature
6
CMRR
Common-mode rejection ratio
vs Free-air temperature
7
Input-to-output crosstalk
vs Frequency
8
VO(PP)
Peak-to-peak output voltage
VIO
6
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
FIGURE
PSRR
Power supply rejection ratio
vs Free-air temperature
9
Closed-loop output impedance
vs Frequency
10
vs Supply voltage
11
vs Free-air temperature
12
ICC
Supply current
SR
Slew rate
vs Output step
Vn
Input voltage noise
vs Frequency
In
Input current noise
vs Frequency
Normalized frequency response
vs Frequency
16, 17
Output amplitude
vs Frequency
18 - 21
Normalized output response
vs Frequency
22 - 25
13, 14
15
Small and large frequency response
26, 27
Single-ended harmonic distortion
Differential gain
Differential phase
vs Frequency
28, 29
vs Output voltage
30, 31
DC input offset voltage
32, 33
Number of 150-Ω loads
34, 35
DC input offset voltage
32, 33
Number of 150-Ω loads
34, 35
Output step response
36 - 38
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
LOAD RESISTANCE
15
VO(PP) − Peak-to-Peak Output Voltage − V
VO(PP) − Peak-to-Peak Output Voltage − V
15
10
5
0
−5
TA = 25°C
RF = 1 kΩ
RL = 25 Ω
Gain = 1
−10
−15
5
6
7
8
9
10
11
12
VCC − Supply Voltage − V
Figure 3.
Copyright © 1998–2012, Texas Instruments Incorporated
13
14
15
VCC = ±15 V
10
VCC = ±5 V
5
0
TA = 25°C
RF = 1 kΩ
Gain = 1
VCC = ±5 V
−5
−10
VCC = ±15 V
−15
10
100
1000
RL − Load Resistance − Ω
Figure 4.
7
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
5
2
4
IIB − Input Bias Current − µ A
VIO − Input Offset Voltage − mV
1
VCC = ±15 V
IIB+
G=1
RF = 1 kΩ
G=1
RF = 1 kΩ
VCC = ±5 V
0
−1
−2
VCC = ±15 V
−3
VCC = ±5 V
IIB+
3
2
VCC = ±5 V
IIB−
1
VCC = ±15 V
IIB−
−4
−5
−40
−20
0
20
40
60
80
0
−40
100
−20
60
80
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
INPUT-TO-OUTPUT CROSSTALK
vs
FREQUENCY
−20
−30
Input−To−Output Crosstalk − dB
CMRR − Common-Mode Rejection Ratio − dB
40
Figure 6.
75
VCC = ±15 V
70
VCC = ±5 V
1 kΩ
65
1 kΩ
−
+
VI
1 kΩ
−20
0
VO
100
−40
−50
VCC = ± 15 V
RF = 1 Ω
RL = 25 Ω
Gain = 2
VI = 200 mV
See Figure 2
Driver 1 = Input
Driver 2 = Output
−60
Driver 1 = Output
Driver 2 = Input
−70
−80
1 kΩ
20
40
60
TA − Free-Air Temperature − °C
Figure 7.
8
20
Figure 5.
80
60
−40
0
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
80
−90
100k
1M
10M
100M
500M
f − Frequency − Hz
Figure 8.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
POWER SUPPLY REJECTION RATIO
vs
FREE-AIR TEMPERATURE
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
100
G=1
RF = 1 kΩ
90
Closed-Loop Output Impedance − Ω
PSRR − Power Supply Rejection Ratio − dB
95
85
VCC = 15 V
80
VCC = 5 V
75
VCC = −5 V
VCC = −15 V
70
10
VCC = ±15 V
RF = 1 kΩ
Gain = 2
TA = 25°C
VI(PP) = 1 V
1
0.1
VO
1 kΩ
1 kΩ
1 kΩ
−
+
0.01
50 Ω
VI
THS6012
1000
VI
Zo =
−1
VO
(
65
−40
−20
0
20
40
60
80
100
0.001
100k
1M
TA − Free-Air Temperature − °C
10M
f − Frequency − Hz
Figure 9.
Figure 10.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
12
13
11
12
100M
)
500M
I CC − Supply Current − mA
I CC − Supply Current − mA
VCC = ±15 V
10
9
8
7
TA = 25°C
RF = 1 kΩ
Gain = +1
6
6
7
8
6
4
2
5
5
VCC = ±5 V
10
8
9
10
11
12
± VCC − Supply Voltage − V
Figure 11.
Copyright © 1998–2012, Texas Instruments Incorporated
13
14
15
0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Figure 12.
9
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
SLEW RATE
vs
OUTPUT STEP
SLEW RATE
vs
OUTPUT STEP
1500
1000
VCC = ± 15V
Gain = 5
RF = 1 kΩ
RL = 25 Ω
1300
+SR
800
−SR
+SR
Slew Rate − Vµ S
1100
Slew Rate − Vµ S
VCC = ± 5V
Gain = 2
RF = 1 kΩ
RL = 25 Ω
900
900
700
700
−SR
600
500
400
500
300
300
200
100
100
0
0
Figure 14.
INPUT VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
NORMALIZED FREQUENCY RESPONSE
vs
FREQUENCY
In+ Noise
10
Vn Noise
0
−1
1k
f − Frequency − Hz
Figure 15.
10
10k
1
100k
RF = 510 Ω
−2
RF = 750 Ω
−3
RF = 1 kΩ
−4
−5
−6
−7
100
RF = 300 Ω
1
Normalized Frequency Response − dB
10
5
2
100
I n − Current Noise − pA/ Hz
VCC = ±15 V
TA = 25°C
In− Noise
1
10
2
3
4
1
Output Step (Peak−To−Peak) − V
Figure 13.
100
Vn − Voltage Noise − nV/ Hz
20
10
15
5
Output Step (Peak−To−Peak) − V
−8
100
VCC = ±15 V
VI = 200 mV
RL = 25 Ω
Gain = 1
TA = 25°C
1M
10M
100M
500M
f − Frequency − Hz
Figure 16.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
NORMALIZED FREQUENCY RESPONSE
vs
FREQUENCY
2
OUTPUT AMPLITUDE
vs
FREQUENCY
3
RF = 360 Ω
2
RF = 620 Ω
0
Output Amplitude − dB
Normalized Frequency Response − dB
1
−1
−2
−3
RF = 470 Ω
−4
−5
RF = 620 Ω
−6
−7
−8
−9
VCC = ±15 V
Vin = 200 mV
RL = 25 Ω
Gain = 2
TA = 25°C
−10
100K
1M
1
0
−1
−5
RF = 1 kΩ
100M
RF = 1.5 kΩ
−3
−4
10M
RF = 1 kΩ
−2
VCC = ± 5 V
Gain = 1
RL = 25 Ω
VI = 200 mV
−6
100k
500M
1M
Figure 17.
Figure 18.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
9
60
500M
100M
500M
Gain = 1000
50
6
Output Level − dB
Output Amplitude − dB
RF = 510 Ω
7
5
RF = 820 Ω
4
RF = 1.2 kΩ
3
1
100M
70
8
2
10M
f − Frequency − Hz
f − Frequency − Hz
1M
20
0
10M
f − Frequency − Hz
Figure 19.
Copyright © 1998–2012, Texas Instruments Incorporated
100M
500M
Gain = 100
30
10
VCC = ± 5 V
Gain = 2
RL = 25 Ω
VI = 200 mV
0
100k
40
VCC = ± 5 V
RG =10 Ω
RL = 25 Ω
VO = 2 V
−10
100k
1M
10M
f − Frequency − Hz
Figure 20.
11
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
OUTPUT AMPLITUDE
vs
FREQUENCY
NORMALIZED OUTPUT RESPONSE
vs
FREQUENCY
1
70
Output Level − dB
50
40
Gain = 100
30
20
10
0
VCC = ± 5 V
RG =10 Ω
RL = 25 Ω
VO = 2 V
−10
100k
1M
RL = 200 Ω
0
Normalized Output Response − dB
60
Gain = 1000
−1
−2
100M
RL = 50 Ω
−4
RL = 25 Ω
−5
−6
−7
−8
10M
RL = 100 Ω
−3
VCC = ±15 V
RF = 1 kΩ
Gain = 1
VI = 200 mV
−9
100k
500M
1M
NORMALILZED OUTPUT RESPONSE
vs
FREQUENCY
NORMALIZFED OUTPUT RESPONSE
vs
FREQUENCY
3
0
2
−1
1
−2
−3
−4
RL = 25 Ω
−5
RL = 200 Ω
RL = 100 Ω
−6
−8
VCC = ±15 V
RF = 1 kΩ
Gain = 2
VI = 200 mV
−9
100k
1M
RL = 50 Ω
10M
f − Frequency − Hz
100M
500M
500M
RF = 620 Ω
RF = 820 Ω
0
−1
RF = 1 kΩ
−2
−3
−4
−5
−6
Figure 23.
12
100M
Figure 22.
1
−7
10M
f − Frequency − Hz
Figure 21.
Normalized Output Response − dB
Normalized Output Response − dB
f − Frequency − Hz
VCC = ±15 V
RL = 100 Ω
Gain = 1
VI = 200 mV
−7
100k
1M
10M
f − Frequency − Hz
100M
500M
Figure 24.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
NORMALIZED OUTPUT RESPONSE
vs
FREQUENCY
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
−3
3
RF = 430 Ω
−6
0
−1
−2
RF = 620 Ω
−3
RF = 1 kΩ
−4
−5
1M
10M
f − Frequency − Hz
100M
Gain = 1
VCC = ± 15 V
RF = 820 Ω
RL = 25 Ω
1M
10M
100M
Figure 25.
Figure 26.
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
SINGLE-ENDED HARMONIC DISTORTION
vs
FREQUENCY
500M
−40
Single−Ended Harmonic Distortion (dBc)
Output Level − dBV
−21
f − Frequency − Hz
VI = 500 mV
VI = 250 mV
VI = 125 mV
−15
VI = 62.5 mV
−21
VI = 125 mV
−30
100k
500M
−9
−18
−18
−27
−3
−12
VI = 250 mV
−15
−24
3
−6
−12
VI = 62.5 mV
VCC = ±15 V
RL = 100 Ω
Gain = 2
VI = 200 mV
−6
100k
0
VI = 500 mV
−9
1
Output Level − dBV
Normalized Output Response − dB
2
Gain = 2
VCC = ± 15 V
RF = 680 Ω
RL = 25 Ω
−24
100k
1M
10M
f − Frequency − Hz
Figure 27.
Copyright © 1998–2012, Texas Instruments Incorporated
100M
500M
−50
VCC = ± 15 V
Gain = 2
RF = 680 Ω
RL = 25 Ω
VO(PP) = 2V
−60
−70
2nd Harmonic
−80
3rd Harmonic
−90
−100
100k
1M
10M
f − Frequency − Hz
Figure 28.
13
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
SINGLE-ENDED HARMONIC DISTORTION
vs
FREQUENCY
SINGLE-ENDED HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−50
VCC = ± 5 V
Gain = 2
RF = 680 Ω
RL = 25 Ω
VO(PP) = 2V
−60
−70
3rd Harmonic
−80
2nd Harmonic
−90
VCC = ± 15 V
Gain = 2
RF = 680 Ω
RL = 25 Ω
f = 1 MHz
−60
2nd Harmonic
−70
−80
−90
3rd Harmonic
−100
−100
100k
10M
1M
5
0
Figure 29.
Figure 30.
SINGLE-ENDED HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
DIFFERENTIAL GAIN AND PHASE
vs
DC INPUT OFFSET VOLTAGE
0.05
VCC = ± 5 V
Gain = 2
RF = 680 Ω
RL = 25 Ω
f = 1 MHz
−60
0.04
Differential Gain − %
Single−Ended Harmonic Distortion − dBc
−50
15
10
−70
3rd Harmonic
−80
20
VO(PP) − Output Voltage − V
f − Frequency − Hz
2nd Harmonic
0.10
VCC = ±15 V
RL = 150 Ω
RF = 1 kΩ
f = 3.58 MHz
Gain = 2
40 IRE Modulation
Gain
0.08
Phase
0.03
0.06
0.02
0.04
0.01
0.02
Differential Phase − °
−50
Single−Ended Harmonic Distortion (dBc)
Single−Ended Harmonic Distortion (dBc)
−40
−90
0
−0.7
−100
0
1
2
3
4
−0.5
−0.3
−0.1
0.1
0.3
0.5
0
0.7
DC Input Offset Voltage − V
VO(PP) − Output Voltage − V
Figure 31.
14
Figure 32.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
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SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
Differential Gain − %
0.04
0.03
0.10
0.15
0.08
0.12
0.06
Gain
0.04
0.02
Phase
Differential Gain − %
VCC = ±5 V
RL = 150 Ω
RF = 1 kΩ
f = 3.58 MHz
Gain = 2
40 IRE Modulation
Differential Phase − °
0.05
DIFFERENTIAL GAIN AND PHASE
vs
NUMBER OF 150-Ω LOADS
0.02
0.01
0
−0.7
−0.5
−0.3
−0.1
0.1
0.3
0.5
0.15
Phase
0.10
0.06
Gain
0.05
0.03
0
0.7
0
0
1
2
7
8
400
0.15
0.06
0.10
Gain
0.05
0.03
VO − Output Voltage − mV
0.20
Differential Phase − °
Differential Gain − %
6
300
0.09
200
100
0
−100
VCC = ±15 V
Gain = 2
RL = 25 Ω
RF = 1 kΩ
tr/tf= 300 ps
See Figure 3
−200
Phase
−300
0
0
3
5
400-mV STEP RESPONSE
0.25
VCC = ±5 V
RF = 1 kΩ
Gain = 2
f = 3.58 MHz
40 IRE Modulation
100 IRE Ramp
2
4
Figure 34.
DIFFERENTIAL GAIN AND PHASE
vs
NUMBER OF 150-Ω LOADS
1
3
Number of 150-Ω Loads
Figure 33.
0.12
0.20
0.09
DC Input Offset Voltage − V
0.15
0.25
VCC = ±15 V
RF = 1 kΩ
Gain = 2
f = 3.58 MHz
40 IRE Modulation
100 IRE Ramp
Differential Phase − °
DIFFERENTIAL GAIN AND PHASE
vs
DC INPUT OFFSET VOLTAGE
4
5
6
Number of 150-Ω Loads
7
8
−400
0
50
100 150 200 250 300 350 400 450 500
t − Time − ns
Figure 35.
Copyright © 1998–2012, Texas Instruments Incorporated
Figure 36.
15
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
6
12
4
8
2
0
−2
VCC = ±15 V
Gain = 2
RL = 25 Ω
RF = 1 kΩ
tr/tf= 5 ns
See Figure 3
−4
−6
−8
VCC = ±15 V
Gain = 5
RL = 25 Ω
RF = 2 kΩ
tr/tf= 5 ns
See Figure 3
4
0
−4
−8
−12
−16
0
16
20-V STEP RESPONSE
16
VO − Output Voltage − V
VO − Output Voltage − V
10-V STEP RESPONSE
8
50
100 150 200 250 300 350 400 450 500
0
50
100 150 200 250 300 350 400 450 500
t − Time − ns
t − Time − ns
Figure 37.
Figure 38.
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
APPLICATION INFORMATION
The THS6012 contains two independent operational amplifiers. These amplifiers are current feedback topology
amplifiers made for high-speed operation. They have been specifically designed to deliver the full power
requirements of ADSL and therefore can deliver output currents of at least 400 mA at full output voltage.
The THS6012 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This
process provides excellent isolation and high slew rates that result in the device's excellent crosstalk and
extremely low distortion.
INDEPENDENT POWER SUPPLIES
Each amplifier of the THS6012 has its own power supply pins. This was specifically done to solve a problem that
often occurs when multiple devices in the same package share common power pins. This problem is crosstalk
between the individual devices caused by currents flowing in common connections. Whenever the current
required by one device flows through a common connection shared with another device, this current, in
conjunction with the impedance in the shared line, produces an unwanted voltage on the power supply. Proper
power supply decoupling and good device power supply rejection helps to reduce this unwanted signal. What is
left is crosstalk.
However, with independent power supply pins for each device, the effects of crosstalk through common
impedance in the power supplies is more easily managed. This is because it is much easier to achieve low
common impedance on the PCB with copper etch than it is to achieve low impedance within the package with
either bond wires or metal traces on silicon.
POWER SUPPLY RESTRICTIONS
Although the THS6012 is specified for operation from power supplies of ±5 V to ±15 V (or singled-ended power
supply operation from 10 V to 30 V), and each amplifier has its own power supply pins, several precautions must
be taken to assure proper operation.
1. The power supplies for each amplifier must be the same value. For example, if the driver 1 uses ±±15 volts,
then the driver 2 must also use ±15 volts. Using ±15 volts for one amplifier and ±5 volts for another amplifier
is not allowed.
2. To save power by powering down one of the amplifiers in the package, the following rules must be followed.
– The amplifier designated driver 1 must always receive power. This is because the internal startup circuitry
uses the power from the driver 1 device.
– The -VCC pins from both drivers must always be at the same potential.
– Driver 2 is powered down by simply opening the +VCC connection.
The THS6012 incorporates a standard Class A-B output stage. This means that some of the quiescent current is
directed to the load as the load current increases. So under heavy load conditions, accurate power dissipation
calculations are best achieved through actual measurements. For small loads, however, internal power
dissipation for each amplifier in the THS6012 can be approximated by the following formula:
P
D
ǒ
≅ 2V
Ǔ ǒ
I
) V
_V
CC CC
CC
O
Ǔ
ǒ Ǔ
V
O
R
L
Where:
PD
VCC
ICC
VO
RL
= Power dissipation for one amplifier
= Split supply voltage
= Supply current for that particular amplifier
= Output voltage of amplifier
= Load resistance
To find the total THS6012 power dissipation, we simply sum up both amplifier power dissipation results.
Generally, the worst case power dissipation occurs when the output voltage is one-half the VCC voltage. One last
note, which is often overlooked: the feedback resistor (RF) is also a load to the output of the amplifier and should
be taken into account for low value feedback resistors.
Copyright © 1998–2012, Texas Instruments Incorporated
17
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
DEVICE PROTECTION FEATURES
The THS6012 has two built-in protection features that protect the device against improper operation. The first
protection mechanism is output current limiting. Should the output become shorted to ground the output current
is automatically limited to the value given in the data sheet. While this protects the output against excessive
current, the device internal power dissipation increases due to the high current and large voltage drop across the
output transistors. Continuous output shorts are not recommended and could damage the device. Additionally,
connection of the amplifier output to one of the supply rails (±VCC) can cause failure of the device and is not
recommended.
The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above
approximately 180°C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown
circuit automatically turns the device back on.
THERMAL INFORMATION
The THS6012 is packaged in a thermally-enhanced DWP package, which is a member of the PowerPAD family
of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure
39(a) and Figure 39(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the
underside of the package [see Figure 39(c)]. Because this thermal pad has direct thermal contact with the die,
excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. This is
discussed in more detail in the PCB design considerations section of this document.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A.
The thermal pad is electrically isolated from all terminals in the package.
Figure 39. Views of Thermally Enhanced DWP Package
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current feedback amplifiers, the bandwidth of the THS6012 is an inversely proportional function of the
value of the feedback resistor. This can be seen from Figure 17 through Figure 20. The recommended resistors
with a ±15 V power supply for the optimum frequency response with a 25-Ω load system are 680-Ω for a gain = 1
and 620-Ω for a gain = 2 or -1. Additionally, using a ±5 V power supply, it is recommended that a 1-kΩ feedback
resistor be used for a gain of 1 and a 820-Ω feedback resistor be used for a gain of 2 or -1. These should be
used as a starting point and once optimum values are found, 1% tolerance resistors should be used to maintain
frequency response characteristics. Because there is a finite amount of output resistance of the operational
amplifier, load resistance can play a major part in frequency response. This is especially true with these drivers,
which tend to drive low-impedance loads. This can be seen in Figure 11, Figure 23, and Figure 24. As the load
18
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
resistance increases, the output resistance of the amplifier becomes less dominant at high frequencies. To
compensate for this, the feedback resistor should change. For 100-Ω loads, it is recommended that the feedback
resistor be changed to 820 Ω for a gain of 1 and 560 Ω for a gain of 2 or -1. Although, for most applications, a
feedback resistor value of 1 kΩ is recommended, which is a good compromise between bandwidth and phase
margin that yields a very stable amplifier.
Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the
bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback
amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value of
the gain resistor to increase or decrease the overall amplifier gain.
Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and increases the distortion. It is also important to know that decreasing load impedance
increases total harmonic distortion (THD). Typically, the third order harmonic distortion increases more than the
second order harmonic distortion.
OFFSET VOLTAGE
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 40. Output Offset Voltage Model
Copyright © 1998–2012, Texas Instruments Incorporated
19
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
NOISE CALCULATIONS AND NOISE FIGURE
Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise
model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input while VFB amplifiers usually only specify one noise current parameter. The noise model is shown in
Figure 41. This model includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN- = Inverting current noise (pA/√Hz)
• eRX = Thermal voltage noise associated with each resistor (eRX = 4 kTRx)
eRs
RS
en
Noiseless
+
_
eni
IN+
IN–
eno
eRf
RF
eRg
RG
Figure 41. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
Where:
ni
+
Ǹ
ǒenǓ ) ǒIN )
2
R
Ǔ
S
2
ǒ
) IN–
ǒR F ø R G ǓǓ
2
ǒ
) 4 kTRs ) 4 kT R ø R
F
G
Ǔ
k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
R
e no + e A + e ni 1 ) F (Noninverting Case)
ni V
RG
ǒ
Ǔ
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
20
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
NF +
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
ȱ e 2ȳ
10logȧ ni ȧ
ȧ 2ȧ
ȲǒeRsǓ ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
2
2
) IN ) R
e
S
n
NF +
ȱ ȡǒ
ȧ
ȧ
Ȣ
ȧ
10logȧ1 )
ȧ
ȧ
Ȳ
Ǔ ǒ
4 kTR
S
ȳ
Ǔȣ
ȧȧ
Ȥȧ
ȧ
ȧ
ȧ
ȴ
Figure 42 shows the noise figure graph for the THS6012.
NOISE FIGURE
vs
SOURCE RESISTANCE
20
18
TA = 25°C
Noise Figure – dB
16
14
12
10
8
6
4
2
0
10
100
1k
10k
Rs – Source Resistance – Ω
Figure 42. Noise Figure vs Source Resistance
Copyright © 1998–2012, Texas Instruments Incorporated
21
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6012 has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 43. A minimum value of 10 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kΩ
1 kΩ
Input
_
10 Ω
Output
THS6012
+
CLOAD
Figure 43. Driving a Capacitive Load
PCB DESIGN CONSIDERATIONS
Proper PCB design techniques in two areas are important to assure proper operation of the THS6012. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6012 is a highspeed part, the following guidelines are recommended.
• Ground plane - It is essential that a ground plane be used on the board to provide all components with a low
inductive ground connection. Although a ground connection directly to a terminal of the THS6012 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and it
provides the path for heat removal.
• Input stray capacitance - To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This is
especially true in the noninverting configuration. An example of this can be seen in Figure 44, which shows
what happens when 1.8 pF is added to the inverting input terminal in the noninverting configuration. The
bandwidth increases dramatically at the expense of peaking. This is because some of the error current is
flowing through the stray capacitor instead of the inverting node of the amplifier. Although, in the inverting
mode, stray capacitance at the inverting input has little effect. This is because the inverting node is at a virtual
ground and the voltage does not fluctuate nearly as much as in the noninverting configuration.
22
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
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SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
NORMALIZED FREQUENCY RESPONSE
vs
FREQUENCY
3
Normalized Frequency Response – dB
2
1
VCC = ±15 V
VI = 200 mV
RL = 25 Ω
RF = 1 kΩ
Gain = 1
0
CI = 0 pF
(Stray C Only)
–1
–2
CI = 1.8 pF
1 kΩ
–3
–4
Cin
Vin
–5
–6
–7
100
Vout
–
+
50 Ω
1M
RL =
25 Ω
10M
100M
500M
f – Frequency – Hz
Figure 44. Driver Normalized Frequency Response vs Frequency
•
Proper power supply decoupling - Use a minimum of a 6.8-μF tantalum capacitor in parallel with a 0.1-μF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of
every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal.
As this distance increases, the inductance in the connecting etch makes the capacitor less effective. The
designer should strive for distances of less than 0.1 inches between the device power terminal and the
ceramic capacitors.
Because of its power dissipation, proper thermal management of the THS6012 is required. Although there are
many ways to properly heatsink this device, the following steps illustrate one recommended approach for a
multilayer PCB with an internal ground plane.
1. Prepare the PCB with a top side etch pattern as shown in Figure 45. There should be etch for the leads as
well as etch for the thermal pad.
2. Place 18 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept
small so that solder wicking through the holes is not a problem during reflow.
3. It is recommended, but not required, to place six more holes under the package, but outside the thermal pad
area. These holes are 25 mils in diameter. They may be larger because they are not in the area to be
soldered so that wicking is not a problem.
4. Connect all 24 holes, the 18 within the thermal pad area and the 6 outside the pad area, to the internal
ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS6012 package should make their connection to the internal ground plane with a
complete connection around the entire circumference of the plated through hole.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with
its five holes. The four larger holes outside the thermal pad area, but still under the package, should be
covered with solder mask.
7. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.
8. With these preparatory steps in place, the THS6012 is simply placed in position and run through the solder
Copyright © 1998–2012, Texas Instruments Incorporated
23
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
0.080
0.026
0.024
0.1025
0.476
0.120
0.085
0.178
0.450
0.0165
0.021
PowerPAD and via placement
pad area (0.085 x 0.120) with 15
vias (Via diameter = 0.013)
.039
0.026
Vias should go through the board connecting the top layer
PowerPad to any and all ground planes. (The larger the ground
plane, the larger the area to distribute the heat.) Solder resist should
be used on the bottom side ground plane in order to prevent wicking
of the solder through the vias during the reflow process.
All Units in Inches
Figure 45. PowerPAD PCB Etch and Via Pattern
The actual thermal performance achieved with the THS6012 in its PowerPAD package depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, ΘJA, is about 21.5°C/W. For a givenΘ JA, the maximum power dissipation
is shown in Figure 46 and is calculated by the following formula:
ǒ
T
P
D
+
–T
MAX A
q
JA
Ǔ
Where:
PD
TMAX
TA
θJA
= Maximum power dissipation of THS6012 (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
= θJC + θCA
θJC = Thermal coefficient from junction to case (0.37°C/W)
θCA = Thermal coefficient from case to ambient
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found
at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered
through your local TI sales office. Refer to literature number SLMA002 when ordering.
24
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
9
TJ = 150°C
PCB Size = 3” x 3”
No Air Flow
Maximum Power Dissipation – W
8
7
θJA = 21.5°C/W
2 oz Trace and
Copper Pad
with Solder
6
5
4
3
2
θJA = 43.9°C/W
2 oz Trace and Copper Pad
without Solder
1
0
–40
–20
0
20
40
60
80
100
TA – Free-Air Temperature – °C
Figure 46. Maximum Power Dissipation vs Free-Air Temperature
ADSL
The THS6012 was primarily designed as a line driver and line receiver for ADSL (asymmetrical digital subscriber
line). The driver output stage has been sized to provide full ADSL power levels of 20 dBm onto the telephone
lines. Although actual driver output peak voltages and currents vary with each particular ADSL application, the
THS6012 is specified for a minimum full output current of 400 mA at its full output voltage of approximately 12 V.
This performance meets the demanding needs of ADSL at the central office end of the telephone line. A typical
ADSL schematic is shown in Figure 47.
Copyright © 1998–2012, Texas Instruments Incorporated
25
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
15 V
0.1 µF
THS6012
Driver 1
VI+
+
6.8 µF
12.5 Ω
+
_
1:2
1 kΩ
100 Ω
Telephone Line
1 kΩ
0.1 µF
6.8 µF
+
–15 V
1 kΩ
15 V
THS6012
Driver 2
VI–
15 V
0.1 µF
+
2 kΩ
6.8 µF
0.1 µF
12.5 Ω
+
_
1 kΩ
–
+
1 kΩ
VO+
THS6062
–15 V
1 kΩ
0.1 µF
1 kΩ
6.8 µF
+
15 V
–15 V
2 kΩ
0.1 µF
1 kΩ
–
+
VO–
THS6062
0.01 µF
–15 V
Figure 47. THS6012 ADSL Application
The ADSL transmit band consists of 255 separate carrier frequencies each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as low
a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies.
The THS6012 has been specifically designed for ultra low distortion by careful circuit implementation and by
taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figure 28 through Figure 31. It is commonly known that in the differential
driver configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion
(THD) will be primarily due to the third order harmonics. For these tests the load was 25 Ω. Additionally,
distortion should be reduced as the feedback resistance drops. This is because the bandwidth of the amplifier
increases, which allows the amplifier to react faster to any nonlinearities in the closed-loop system.
Another significant point is the fact that distortion decreases as the impedance load increases. This is because
the output resistance of the amplifier becomes less significant as compared to the output load resistance.
26
Copyright © 1998–2012, Texas Instruments Incorporated
THS6012
www.ti.com
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
GENERAL CONFIGURATIONS
A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6012,
like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors
directly from the output to the inverting input is not recommended. This is because, at high frequencies, a
capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when
using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily
implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an
RC-filter at the noninverting terminal of the operational-amplifier (see Figure 48).
RG
RF
R1
O +
V
I
VO
+
VI
ǒ
V
–
R
1)
C1
f
–3dB
+
R
F
G
Ǔǒ
Ǔ
1
1 ) sR1C1
1
2pR1C1
Figure 48. Single-Pole Low-Pass Filter
If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of
their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 49.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
–3dB
RG =
RF
+
(
1
2pRC
RF
1
2–
Q
)
Figure 49. 2-Pole Low-Pass Sallen-Key Filter
There are two simple ways to create an integrator with a CFB amplifier. The first one shown in Figure 50 adds a
resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and
the feedback impedance never drops below the resistor value. The second one shown in Figure 51 uses positive
feedback to create the integration. Caution is advised because oscillations can occur because of the positive
feedback.
C1
RF
RG
–
VI
+
VO
THS6012
V
O +
VI
ȡS ) RF1C1ȣ
ǒRGǓȧ S ȧ
Ȣ
Ȥ
R
F
Figure 50. Inverting CFB Integrator
Copyright © 1998–2012, Texas Instruments Incorporated
27
THS6012
SLOS226F – SEPTEMBER 1998 – REVISED JUNE 2012
www.ti.com
RG
RF
For Stable Operation:
R2
R1 || RA
–
THS6012
VO
+
VO ≅ VI
R1
R2
(
≥
RF
RG
RF
RG
sR1C1
1+
)
VI
C1
RA
Figure 51. Non-Inverting CFB Integrator
Another good use for the THS6012 amplifiers is as very good video distribution amplifiers. One characteristic of
distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised
as the number of lines increases and the closed-loop gain increases. Be sure to use termination resistors
throughout the distribution system to minimize reflections and capacitive loading.
620 Ω
620 Ω
–
75 Ω
75 Ω Transmission Line
VO1
+
VI
75 Ω
75 Ω
THS6012
N Lines
75 Ω
VON
75 Ω
Figure 52. Video Distribution Amplifier Application
EVALUATION BOARD
An evaluation board is available for the THS6012 (literature number SLOP132). This board has been configured
for proper thermal management of the THS6012. The circuitry has been designed for a typical ADSL application
as shown previously in this document. For more detailed information, refer to the THS6012EVM User's Manual
(literature number SLOU034). To order the evaluation board contact your local TI sales office or distributor.
28
Copyright © 1998–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS6012CDWP
ACTIVE SO PowerPAD
DWP
20
25
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS6012C
THS6012CDWPR
ACTIVE SO PowerPAD
DWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS6012C
THS6012IDWP
ACTIVE SO PowerPAD
DWP
20
25
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS6012I
THS6012IDWPR
ACTIVE SO PowerPAD
DWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS6012I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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