THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
2
3-Channel RGBHV Video Buffer with I C™ Control, 2:1 Input Mux,
Monitor Pass-Through, and Selectable Input Bias Modes
Check for Samples: THS7347
FEATURES
APPLICATIONS
• 3-Video Amplifiers for CVBS, S-Video, EDTV,
HDTV Y'P'BP'R, G'B'R', and R'G'B' Video
• H/V Sync Paths with Adjustable Schmitt
Trigger
• 2:1 Input Mux
• I2C Control of All Functions on Each Channel
• Unity-Gain Buffer Path for ADC Buffering:
– 500-MHz Bandwidth, 1200-V/μs Slew Rate
• Monitor Pass-Through Function:
– 500-MHz Bandwidth, 1300-V/μs Slew Rate
– 6-dB Gain with SAG Correction Capable
– High Output Impedance in Disable State
• Selectable Input Bias Modes:
– AC-Coupled with Sync-Tip Clamp
– AC-Coupled with Bias
– DC-Coupled with Offset Shift
– DC-Coupled
• +2.7-V to +5-V Single-Supply Operation
• Total Power Consumption: 265 mW at 3.3 V
• Disable Function Reduces Current to 0.1 μA
• Rail-to-Rail Output:
– Output Swings Within 0.1 V of the Rails,
Allowing AC- or DC-Output Coupling
• Lead-free, RoHS TQFP Package
•
•
•
1
2345
Input 1
DESCRIPTION
Fabricated using the revolutionary complimentary
silicon-germanium (SiGe) BiCom3 process, the
THS7347 is a low-power, single-supply 2.7-V to 5-V
3-channel integrated video buffer with horizontal (H)
and vertical (V) sync signal paths. It incorporates a
500-MHz bandwidth, 1200-V/μs unity-gain buffer ideal
for driving analog-to-digital converters (ADCs) and
video decoders. In parallel with the unity-gain buffer,
a monitor pass-through path allows for passing the
input signal on to other systems. This path has a
6-dB gain, 500-MHz bandwidth, 1300-V/μs slew rate,
SAG correction capability, and high output impedance
while disabled.
Each channel of the THS7347 is individually
I2C-configurable for all functions, including controlling
the 2:1 input mux. Its rail-to-rail output stage allows
for both ac- and dc-coupling applications.
3.3 V
0.1 mF
In A
In B
2:1
0.1 mF
DC
+Offset
DC
ACBIAS
75 W
0.1 mF
+
X1
75 W
Input 2
Projectors
Professional Video Systems
LCD/ DLP®/LOCS Input Buffering
ADC
-
AC
Sync
TIP
Clamp
+
Disable
= OPEN
-
Out
75 W
675 W
SAG
1 kW
SDA
SCL
878 W
47 mF
150 W
33 mF
Monitor
Output
75 W
3.3 V
3.3 V Single-Supply Projector Input System with Monitor Pass-Through
(One of Three R'G'B' Channels Shown)
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
DESCRIPTION, CONTINUED
As part of the THS7347 flexibility, the device input can be selected for ac- or dc-coupled inputs. The ac-coupled
modes include a sync-tip clamp option for CVBS/Y'/G'B'R' with sync or a fixed bias for the C'/P'B/P'R/R'G'B'
channels without sync. The dc input options include a dc input or a dc+Offset shift to allow for a full sync
dynamic range at the output with 0-V input.
The THS7347 is available in a lead-free, RoHS-compliant TQFP package.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
PACKAGED DEVICES
PACKAGE TYPE
THS7347IPHP
Tray, 250
HTQFP-48 PowerPAD™
THS7347IPHPR
(1)
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 1000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
THS7347
UNIT
5.5
V
–0.4 to VA or VDD
V
Continuous output current
±80
mA
Continuous power dissipation
See Dissipation Rating Table
VSS
Supply voltage, GND to VA or GND to VDD
VI
Input voltage
IO
TJ
Maximum junction temperature, any condition (2)
(3)
+125
°C
°C
300
°C
HBM
1500
V
CDM
1500
V
MM
100
V
Maximum junction temperature, continuous operation, long term reliability
Tstg
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
°C
–65 to +150
TJ
ESD ratings
+150
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS
(1)
(2)
2
POWER RATING (1)
(TJ = +125°C)
(2)
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA = +25°C
TA = +85°C
HTQFP-48 with PowerPAD (PHP)
1.2
35
2.85 W
1.14 W
This data was taken with a PowerPAD standard 3-inch by 3-inch, 4-layer printed circuit board (PCB) with internal ground plane
connections to the PowerPAD.
Power rating is determined with a junction temperature of +125°C. This temperature is the point where distortion starts to substantially
increase and long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction
temperature at or below +125°C for best performance and reliability.
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Digital supply voltage
VA
TA
NOM
MAX
UNIT
2.7
5
Analog supply voltage. Must be equal to or greater than VDD
VDD
5
V
V
Ambient temperature
–40
+85
°C
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V
RL = 150 Ω ∥ 5 pF to GND for Monitor Output, 19 kΩ || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor
Output Pin, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
–40°C to
+85°C
UNIT
MIN/MAX/
TYP
500
MHz
Typ
450
MHz
Typ
425
MHz
Typ
375
MHz
Typ
+25°C
+25°C
0°C to
+70°C
AC PERFORMANCE
Small-signal
bandwidth (–3 dB)
–1 dB flatness
Large-signal
bandwidth (–3 dB)
Slew rate
Group delay at
100 kHz
Differential gain
Differential phase
Total harmonic
distortion f = 1 MHz
Signal-to-noise ratio
Channel-to-channel
crosstalk
MUX isolation
Gain
Settling time
Output impedance
Buffer output
Monitor output
Buffer output
Monitor output
VO = 0.2 VPP
VO = 0.2 VPP
Buffer output
VO = 1 VPP
475
MHz
Typ
Monitor output
VO = 2 VPP
240
MHz
Typ
Buffer output
VO = 1 VPP
1050
V/μs
Typ
Monitor output
VO = 2 VPP
1050
V/μs
Typ
Buffer output
1.2
ns
Typ
Monitor output
1.2
ns
Typ
0.05/0.05
%
Typ
0.1/0.1
%
Typ
0.1/0.15
degrees
Typ
0.15/0.2
degrees
Typ
Buffer output
Monitor output
Buffer output
Monitor output
NTSC/PAL
NTSC/PAL
Buffer output
VO = 1 VPP
–58
dB
Typ
Monitor output
VO = 2 VPP
–57
dB
Typ
63
dB
Typ
65
dB
Typ
–40
dB
Typ
–36
dB
Typ
64
dB
Typ
66
dB
Typ
dB
Typ
dB
Min/Max
6
ns
Typ
6
ns
Typ
0.3
Ω
Typ
0.4
Ω
Typ
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
No weighting, up to 100 MHz
f = 100 MHz
f = 100 MHz
Buffer output
f = 100 kHz; VO = 1 VPP
0
Monitor output
f = 100 kHz; VO = 2 VPP
6
Buffer output
Monitor output
Buffer output
Monitor output
VIN = 1 VPP; 0.5% settling
f = 10 MHz
5.8/6.25
5.75/6.3
5.75/6.35
DC PERFORMANCE
Output offset voltage
Average offset
voltage drift
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Bias output voltage
Monitor output
Sync tip clamp
voltage
Buffer output
Monitor output
Bias = dc
15
±80
±85
±85
mV
Max
20
±120
±125
±125
mV
Max
20
μV/°C
Typ
20
μV/°C
Typ
160/370
mV
Min/Max
Bias = dc
Bias = dc + shift, VIN = 0 V
255
175/355
Bias = ac
1.0
0.85/1.15
0.8/1.2
0.8/1.2
V
Min/Max
Bias = dc + shift, VIN = 0 V
235
145/350
135/360
130/365
mV
Min/Max
Bias = ac
Bias = ac STC, clamp voltage
Copyright © 2007–2011, Texas Instruments Incorporated
165/365
1.7
1.55/1.85
1.5/1.9
1.5/1.9
V
Min/Max
290
200/405
195/410
190/415
mV
Min/Max
300
200/400
195/405
190/410
mV
Min/Max
3
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V (continued)
RL = 150 Ω ∥ 5 pF to GND for Monitor Output, 19 kΩ || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor
Output Pin, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
–1.3
–3.0
–3.5
–40°C to
+85°C
UNIT
MIN/MAX/
TYP
–3.5
μA
Max
10
nA/°C
Typ
0.7/3.9
μA
Min/Max
DC PERFORMANCE, continued
Input bias current
Bias = dc; (–) implies IB out of the pin
Average bias current drift
Bias = dc
Sync tip clamp bias current
Bias = ac STC, low bias
2.3
0.9/3.6
0.8/3.8
Bias = ac STC, mid bias
5.8
3.8/8.0
3.7/8.2
3.6/8.3
μA
Min/Max
Bias = ac STC, high bias
8.1
5.7/10.8
5.6/11.0
5.5/11.1
μA
Min/Max
INPUT CHARACTERISTICS
Input voltage range
Bias = dc
Input resistance
0 to 2
V
Typ
Bias = ac bias mode
25
kΩ
Typ
Bias = dc, dc + shift, ac STC
3
MΩ
Typ
1.5
pF
Typ
Input capacitance
OUTPUT CHARACTERISTICS: MONITOR OUTPUT
High output voltage swing
Low output voltage swing
Output current
Sourcing
Sinking
RL = 150 Ω to 1.65 V
3.15
2.9
2.8
2.8
V
Min
RL = 150 Ω to GND
3.05
2.85
2.75
2.75
V
Min
RL = 75 Ω to 1.65 V
3.05
V
Typ
RL = 75 Ω to GND
2.9
V
Typ
RL = 150 Ω to 1.65 V
0.15
0.25
0.28
0.29
V
Max
RL = 150 Ω to GND
0.1
0.18
0.21
0.22
V
Max
RL = 75 Ω to 1.65 V
0.25
V
Typ
RL = 75 Ω to GND
0.08
V
Typ
RL = 10 Ω to 1.65 V
80
50
47
45
mA
Min
75
50
47
45
mA
Min
2
1.8
1.75
1.75
V
Min
0.05
0.12
0.13
0.14
V
Max
OUTPUT CHARACTERISTICS: BUFFER OUTPUT
High output voltage swing
(Limited by input range and G = 0 dB)
Low Output voltage swing
(Limited by input range and G = 0 dB)
Load = 19 kΩ ∥ 8 pF to 1.65 V
Sourcing
RL = 10 Ω to GND
80
50
47
45
mA
Min
Sinking
RL = 10 Ω to 1.65 V
75
50
47
45
mA
Min
Maximum operating voltage
VA
3.3
5.5
5.5
5.5
V
Max
Minimum operating voltage
VA
3.3
2.7
2.7
2.7
V
Min
Maximum quiescent current
VA, dc + shift mode, VIN = 100 mV
80
100
103
105
mA
Max
Minimum quiescent current
VA, dc + shift mode, VIN = 100 mV
80
60
57
55
mA
Min
Power supply rejection (+PSRR)
Buffer output
50
dB
Typ
Maximum operating voltage
VDD
3.3
5.5
5.5
5.5
V
Max
Minimum operating voltage
VDD
3.3
2.7
2.7
2.7
V
Min
Maximum quiescent current
VDD, VIN = 0 V
0.65
1.2
1.3
1.4
mA
Max
Minimum quiescent current
VDD, VIN = 0 V
0.65
0.35
0.3
0.25
mA
Min
0.1
μA
Typ
5
μs
Typ
2
μs
Typ
Output Current
POWER SUPPLY: ANALOG
POWER SUPPLY: DIGITAL
DISABLE CHARACTERISTICS: ALL CHANNELS DISABLED
Quiescent current
All channels disabled
Turn-on time delay (tON)
Time for lS to reach 50% of final value
after I2C control is initiated
Turn-on time delay (tOFF)
4
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V (continued)
RL = 150 Ω ∥ 5 pF to GND for Monitor Output, 19 kΩ || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor
Output Pin, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
+25°C
OVER TEMPERATURE
+25°C
0°C to
+70°C
–40°C to
+85°C
UNIT
MIN/MAX/
TYP
DIGITAL CHARACTERISTICS (1)
High level input voltage
VIH
2.3
V
Typ
Low level input voltage
VIL
1.0
V
Typ
H/V SYNC CHARACTERISTICS: RLoad = 1 kΩ To GND (2)
Schmitt trigger adjust pin voltage
Reference for Schmitt trigger
Schmitt trigger threshold range
Allowable range for Schmitt trigger adjust
V
Min/Max
0.9 to 2
V
Typ
Schmitt trigger VT+
Positive-going input voltage threshold
relative to Schmitt trigger threshold
0.25
V
Typ
Schmitt trigger VT–
Negative-going input voltage threshold
relative to Schmitt trigger threshold
–0.3
V
Typ
Schmitt trigger threshold pin input
resistance
Input resistance into Control pin
10
kΩ
Typ
MΩ
Typ
H/V Sync input impedance
1.47
1.35/1.6
1.3/1.65
1.27/1.68
10
H/V Sync high output voltage
1 kΩ to GND
3.15
3.05
3.0
3.0
V
Min
H/V Sync low output voltage
1 kΩ to GND
0.01
0.05
0.1
0.1
V
Max
H/V Sync source current
10 Ω to GND
50
35
30
30
mA
Min
H/V Sync sink current
10 Ω to 3.3 V
35
25
23
21
mA
Min
H/V Delay
Delay from Input to output
6.5
ns
Typ
5
ns
Typ
H/V to buffer output skew
(1)
(2)
Standard CMOS logic.
Schmitt trigger threshold is defined by (VT+ – VT–)/2.
Copyright © 2007–2011, Texas Instruments Incorporated
5
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V
RL = 150Ω || 5pF to GND for Monitor Output, 19kΩ || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output
Pin, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
–40°C to
+85°C
UNIT
MIN/MAX/
TYP
550
MHz
Typ
500
MHz
Typ
450
MHz
Typ
400
MHz
Typ
+25°C
+25°C
0°C to
+70°C
AC PERFORMANCE
Small-signal
bandwidth (–3 dB)
–1 dB flatness
Large-signal
bandwidth (–3 dB)
Slew rate
Group delay at
100 kHz
Differential gain
Differential phase
Total harmonic
distortion f = 1 MHz
Signal-to-noise ratio
Channel-to-channel
crosstalk
MUX Isolation
Gain
Settling time
Output impedance
Buffer output
Monitor output
Buffer output
Monitor output
VO = 0.2 VPP
VO = 0.2 VPP
Buffer output
VO = 1 VPP
525
MHz
Typ
Monitor output
VO = 2 VPP
325
MHz
Typ
Buffer output
VO = 1 VPP
1200
V/μs
Typ
Monitor output
VO = 2 VPP
1350
V/μs
Typ
Buffer output
1.15
ns
Typ
Monitor output
1.15
ns
Typ
0.05/0.05
%
Typ
0.1/0.1
%
Typ
0.05/0.05
degrees
Typ
Buffer output
Monitor output
Buffer output
Monitor output
NTSC/PAL
NTSC/PAL
0.05/0.05
degrees
Typ
Buffer output
VO = 1 VPP
–71
dB
Typ
Monitor output
VO = 2 VPP
–67
dB
Typ
63
dB
Typ
65
dB
Typ
–40
dB
Typ
–36
dB
Typ
64
dB
Typ
66
dB
Typ
dB
Typ
dB
Min/Max
6
ns
Typ
6
ns
Typ
0.3
Ω
Typ
0.4
Ω
Typ
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
No weighting, up to 100 MHz
f = 100 MHz
f = 100 MHz
Buffer output
f = 100 kHz; VO = 1 VPP
0
Monitor output
f = 100 kHz; VO = 2 VPP
6
Buffer output
Monitor output
Buffer output
Monitor output
VIN = 1 VPP; 0.5% settling
f = 10 MHz
5.8/6.25
5.75/6.3
5.75/6.35
DC PERFORMANCE
Output offset voltage
Average offset
voltage drift
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Bias output voltage
Monitor output
Sync tip clamp
voltage
Buffer output
Monitor output
Bias = dc
±85
±85
mV
Max
±120
±125
±125
mV
Max
20
μV/°C
Typ
20
μV/°C
Typ
Bias = dc + shift, VIN = 0 V
265
185/370
175/380
170/385
mV
Min/Max
Bias = ac
1.5
1.3/1.65
1.25/1.7
1.25/1.7
V
Min/Max
Bias = dc + shift, VIN = 0 V
235
145/345
135/355
130/360
mV
Min/Max
Bias = ac
2.65
2.5/2.8
2.45/2.85
2.45/2.85
V
Min/Max
295
205/410
200/415
195/420
mV
Min/Max
300
200/400
195/405
190/410
mV
Min/Max
–1.4
–3.0
–3.5
–3.5
μA
Max
10
nA/°C
Typ
0.7/4.1
μA
Min/Max
Bias = ac STC, clamp voltage
Bias = dc; (–) implies IB out of the pin
Average bias current drift
Bias = dc
6
±80
20
Bias = dc
Input bias current
Sync tip clamp bias current
15
Bias = ac STC, low bias
2.4
0.9/3.9
0.8/4.0
Bias = ac STC, mid bias
6.2
3.9/8.4
3.8/8.6
3.7/8.7
μA
Min/Max
Bias = ac STC, high bias
8.6
6/11.2
5.8/11.4
5.7/11.5
μA
Min/Max
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V (continued)
RL = 150Ω || 5pF to GND for Monitor Output, 19kΩ || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output
Pin, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
+25°C
OVER TEMPERATURE
+25°C
0°C to
+70°C
–40°C to
+85°C
UNIT
MIN/MAX/
TYP
INPUT CHARACTERISTICS
Input voltage range
Bias = dc
Input resistance
0 to 3.4
V
Typ
Bias = ac bias mode
25
kΩ
Typ
Bias = dc, dc + shift, ac STC
3
MΩ
Typ
1.5
pF
Typ
Min
Input capacitance
OUTPUT CHARACTERISTICS: MONITOR OUTPUT
High output voltage swing
Low output voltage swing
Output current
Sourcing
Sinking
RL = 150 Ω to 2.5 V
4.8
4.65
4.6
4.6
V
RL = 150 Ω to GND
4.7
4.55
4.5
4.5
V
Min
RL = 75 Ω to 2.5 V
4.7
V
Typ
RL = 75 Ω to GND
4.6
V
Typ
RL = 150 Ω to 2.5 V
0.2
0.25
0.28
0.30
V
Max
RL = 150 Ω to GND
0.1
0.19
0.23
0.24
V
Max
RL = 75 Ω to 2.5 V
0.24
V
Typ
RL = 75 Ω to GND
0.085
V
Typ
RL = 10 Ω to 2.5 V
110
85
80
75
mA
Min
110
85
80
75
mA
Min
3.4
3.1
3.0
3.0
V
Min
0.05
0.12
0.13
0.14
V
Max
OUTPUT CHARACTERISTICS: BUFFER OUTPUT
High output voltage swing
(Limited by input range and G = 0 dB)
Low output voltage swing
(Limited by input range and G = 0 dB)
Load = 19 kΩ ∥ 8 pF to 2.5 V
Sourcing
RL = 10 Ω to GND
110
85
80
75
mA
Min
Sinking
RL = 10 Ω to 2.5 V
110
85
80
75
mA
Min
Maximum operating voltage
VA
5.0
5.5
5.5
5.5
V
Max
Minimum operating voltage
VA
5.0
2.7
2.7
2.7
V
Min
Maximum quiescent current
VA, dc + shift mode, VIN = 100 mV
90
112
115
117
mA
Max
Minimum quiescent current
VA, dc + shift mode, VIN = 100 mV
90
68
65
63
mA
Min
Power supply rejection (+PSRR)
Buffer Output
46
dB
Typ
Maximum operating voltage
VDD
5.0
5.5
5.5
5.5
V
Max
Minimum operating voltage
VDD
5.0
2.7
2.7
2.7
V
Min
Maximum quiescent current
VDD, VIN = 0 V
1
2
3
3
mA
Max
Minimum quiescent current
VDD, VIN = 0 V
1
0.5
0.4
0.4
mA
Min
Output current
POWER SUPPLY: ANALOG
POWER SUPPLY: DIGITAL
DIGITAL CHARACTERISTICS (1)
High level input voltage
VIH
3.5
V
Typ
Low level input voltage
VIL
1.5
V
Typ
DISABLE CHARACTERISTICS: ALL CHANNELS DISABLED
Quiescent current
All channels disabled
1
μA
Typ
Turn-on time delay (tON)
Time for lS to reach 50% of final value
after I2C control is initiated
5
μs
Typ
2
μs
Typ
Turn-on time delay (tOFF)
(1)
Standard CMOS logic.
Copyright © 2007–2011, Texas Instruments Incorporated
7
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V (continued)
RL = 150Ω || 5pF to GND for Monitor Output, 19kΩ || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output
Pin, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
1.54
1.43/1.65
1.38/1.7
–40°C to
+85°C
UNIT
MIN/MAX/
TYP
1.35/1.73
H/V SYNC CHARACTERISTICS: RLoad = 1 kΩ To GND (2)
Schmitt trigger adjust pin voltage
Reference for Schmitt trigger
Schmitt trigger threshold range
Allowable range for Schmitt trigger adjust
V
Min/Max
0.9 to 2
V
Typ
Schmitt trigger VT+
Positive-going input voltage threshold
relative to Schmitt trigger threshold
0.25
V
Typ
Schmitt trigger VT–
Negative-going input voltage threshold
relative to Schmitt trigger threshold
–0.3
V
Typ
Schmitt trigger threshold pin input
resistance
Input resistance into Control pin
10
kΩ
Typ
MΩ
Typ
H/V Sync high output voltage
1 kΩ to GND
4.8
4.7
4.6
4.6
V
Min
H/V Sync low output voltage
1 kΩ to GND
0.01
0.05
0.1
0.1
V
Max
H/V Sync source current
10 Ω to GND
90
60
55
55
mA
Min
H/V Sync sink current
10 Ω to 5 V
50
30
27
25
mA
Min
H/V Delay
Delay from input to output
6.5
ns
Typ
5
ns
Typ
H/V Sync input impedance
10
H/V to buffer output skew
(2)
8
Schmitt trigger threshold is defined by (VT+ – VT–)/2.
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
TIMING REQUIREMENTS FOR I2C INTERFACE (1) (2)
At VDD = 2.7 V to 5 V.
STANDARD MODE
PARAMETER
FAST MODE
MIN
MAX
MIN
MAX
UNIT
fSCL
Clock frequency, SCL
0
100
0
400
kHz
tw(H)
Pulse duration, SCL high
4
0.6
μs
tw(L)
Pulse duration, SCL low
4.7
1.3
μs
tr
Rise time, SCL and SDA
1000
300
ns
tf
Fall time, SCL and SDA
300
300
ns
tsu(1)
Setup time, SDA to SCL
th(1)
Hold time, SCL to SDA
0
0
ns
t(buf)
Bus free time between stop and start conditions
4.7
1.3
μs
tsu(2)
Setup time, SCL to start condition
4.7
0.6
μs
th(2)
Hold time, start condition to SCL
4
0.6
μs
tsu(3)
Setup time, SCL to stop condition
4
0.6
Cb
Capacitive load for each bus line
(1)
(2)
250
100
400
ns
μs
400
pF
The THS7347 I2C address = 01011(A1)(A0)(R/W). See the Applications Information section for more information.
The THS7347 was designed to comply with version 2.1 of the I2C specification.
t w(H)
t w(L)
tr
tf
SCL
t su(1)
t h(1)
SDA
Figure 1. SCL and SDA Timing
SCL
t su(2)
t h(2)
t su(3)
t (buf)
SDA
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions
Copyright © 2007–2011, Texas Instruments Incorporated
9
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Channel 1
Input A
2:1
X1
Channel 2
Input A
DC
+Offset
Channel 3
Input A
DC
ACBIAS
H-Sync
Input A
+
Channel 1 Buffer
Output (To ADC)
-
AC
Sync
TIP
Clamp
+
Disable
= OPEN
-
Channel 1 Monitor
Output
675 W
V-Sync
Input A
Channel 1 SAG
1 kW
2:1
X1
DC
+Offset
DC
ACBIAS
150 W
878 W
+
Channel 2 Buffer
Output (To ADC)
-
AC
Sync
TIP
Clamp
+
Disable
= OPEN
-
675 W
Channel 2 Monitor
Output
Channel 2 SAG
1 kW
X1
2:1
150 W
878 W
+
Channel 3 Buffer
DC
+Offset
DC
ACBIAS
-
AC
Sync
TIP
Clamp
Output (To ADC)
+
Disable
= OPEN
-
675 W
Channel 3 Monitor
Output
Channel 3 SAG
1 kW
Channel 1
Input B
2:1
150 W
878 W
+
Channel 2
Input B
Horizontal Sync
Buffer OUTPUT
-
Channel 3
Input B
Horizontal Sync
Monitor OUTPUT
H-Sync
Input B
2:1
V-Sync
Input B
+
Vertical Sync
Buffer OUTPUT
10 kW
Vertical Sync
Monitor OUTPUT
+1.4 V
MUX
MODE
MUX
SELECT
SCHMITT
TRIGGER
ADJUST
SDA SCL
I2C,
A1
I2C,
A0
PUC
+VDD
DGND
+VA
AGND
NOTE: The I2C address of the THS7347 is 01011(A1)(A0)(R/W).
10
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
PIN CONFIGURATION
+VA
AGND
CH. 1, MONITOR OUTPUT
CH. 1, SAG
CH. 2, MONITOR OUTPUT
CH. 2, SAG
CH. 3, MONITOR OUTPUT
CH. 3, SAG
H-SYNC MON. OUTPUT
V-SYNC MON. OUTPUT
+VA
AGND
48
47
46
45
44
43
42
41
40
39
38
37
THS7347IPHP
HTQFP-48 (PHP)
(Top View)
CH. 1, INPUT A
1
36
CH. 1, BUFFER OUTPUT
CH. 2, INPUT A
2
35
CH. 1, BUFFER OUTPUT
CH. 3, INPUT A
3
34
AGND
H-SYNC, INPUT A
4
33
+VA
V-SYNC, INPUT A
5
32
CH. 2, BUFFER OUTPUT
AGND
6
31
CH. 2, BUFFER OUTPUT
CH. 1, INPUT B
7
30
AGND
CH. 2, INPUT B
8
29
+VA
CH. 3, INPUT B
9
28
CH. 3, BUFFER OUTPUT
H-SYNC, INPUT B
10
27
CH. 3, BUFFER OUTPUT
V-SYNC, INPUT B
11
26
AGND
AGND
12
25
H-SYNC BUFFER OUTPUT
13
14
15
16
17
18
19
20
21
22
23
24
AGND
SCHMITT-TRIGGER ADJ.
MUX MODE
MUX SELECT
I2C, A1
I2C, A0
SDA
SCL
PUC
VDD
DGND
V-SYNC BUFFER OUTPUT
THS7347
PowerPAD
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CH. 1, INPUT A
1
I
Video Input Channel 1, Input A
CH. 2, INPUT A
2
I
Video Input Channel 2, Input A
CH. 3, INPUT A
3
I
Video Input Channel 3, Input A
H-SYNC, INPUT A
4
I
Horizontal Sync, Input A
V-SYNC, INPUT A
5
I
Vertical Sync, Input A
CH. 1, INPUT B
7
I
Video Input Channel 1, Input B
CH. 2, INPUT B
8
I
Video Input Channel 2, Input B
CH. 3, INPUT B
9
I
Video Input Channel 3, Input B
Copyright © 2007–2011, Texas Instruments Incorporated
11
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
H-SYNC, INPUT B
10
I
Horizontal Sync, Input B
V-SYNC, INPUT B
11
I
Vertical Sync, Input B
I2C, A1
17
I
I2C Slave Address Control Bit A1. Connect to VDD for a logic 1 preset value or GND for a logic 0 preset
value.
I2C, A0
18
I
I2C Slave Address Control Bit A0. Connect to VDD for a logic 1 preset value or GND for a logic 0 preset
value.
SDA
19
I/O
SCL
20
I
I2C bus clock line. Pull-up resistor should have a minimum value = 2 kΩ and a maximum value = 19 -kΩ.
Pull up to VDD.
PUC
21
I
Power-Up Condition. Connect to GND for all channels disabled upon power-up. Connect to VDD (logic
high) to set buffer outputs to OFF and monitor outputs ON with ac-bias configuration on Channels 1 to 3
and both H-Sync/V-Sync enabled.
MUX MODE
15
I
Sets the MUX configuration control. Connect to logic low for MUX Select (pin 16) control of the MUX.
Connect to logic high for I2C control of the MUX.
MUX SELECT
16
I
Controls the MUX selection when MUX MODE (pin 15) is set to logic low. Connect to logic low for MUX
selector set to Input A. Connect to logic high for MUX selector set to Input B.
CH. 1, BUFFER OUTPUT
35, 36
O
Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B. Connect to ADC/Scalar/Decoder. Both
pins should be connected together on the PCB.
CH. 2, BUFFER OUTPUT
31, 32
O
Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B. Connect to ADC/Scalar/Decoder. Both
pins should be connected together on the PCB.
CH. 3, BUFFER OUTPUT
27, 28
O
Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B. Connect to ADC/Scalar/Decoder. Both
pins should be connected together on the PCB.
H-SYNC BUFFER
OUTPUT
25
O
Horizontal Sync Buffer Output. Connect to ADC/Scalar H-sync input.
V-SYNC BUFFER
OUTPUT
24
O
Vertical Sync Buffer Output. Connect to ADC/Scalar V-sync input.
CH. 1, SAG
45
O
Video Monitor Pass-Through Output Channel 1 SAG Correction pin. If SAG is not used, connect Directly to
CH. 1, OUTPUT pin 46.
CH. 1, MONITOR
OUTPUT
46
O
Video Monitor Pass-Through Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B.
CH. 2, SAG
43
O
Video Monitor Pass-Through Output Channel 2 SAG Correction pin. If SAG is not used, connect Directly to
CH. 2, OUTPUT pin 44.
CH. 2, MONITOR
OUTPUT
44
O
Video Monitor Pass-Through Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B.
CH. 3, SAG
41
O
Video Monitor Pass-Through Output Channel 3 SAG Correction pin. If SAG is not used, connect Directly to
CH. 3, OUTPUT pin 42.
CH. 3, MONITOR
OUTPUT
42
O
Video Monitor Pass-Through Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B.
H-SYNC MONITOR
OUTPUT
40
O
Horizontal Sync Monitor Pass-Through Output.
V-SYNC MONITOR
OUTPUT
39
O
Vertical Sync Monitor Pass-Through Output.
AGND
6, 12, 13, 26,
30, 34, 37, 47
I
Ground Reference pin for analog signals. Internally, these pins connect to DGND, although it is
recommended to have the AGND and DGND connected to the proper signals for best results.
+VA
29, 33, 38, 48
I
Analog Positive Power Supply Input pins. Connect to 2.7 V to 5 V. Must be equal to or greater than VDD.
VDD
22
I
Digital Positive Supply pin for I2C circuitry and H-Sync/V-Sync outputs. Connect to 2.7 V to 5 V.
DGND
23
I
Digital GND pin for HV circuitry and I2C circuitry.
Schmitt Trigger Adjust
14
I
Defaults to 1.45 V (TTL compatible). Connect to external voltage reference to adjust H-Sync/V-Sync input
thresholds from 0.9 V to 2 V range.
12
Serial data line of the I2C bus. Pull-up resistor should have a minimum value = 2 kΩ and a maximum value
= 19 kΩ. Pull up to VDD.
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
APPLICATIONS INFORMATION
The THS7347 is targeted for RGB+HV video buffer applications. Although it can be used for numerous other
applications, the needs and requirements of the video signal were the most important design parameters of the
THS7347. Built on the revolutionary complementary silicon-germanium (SiGe) BiCom3 process, the THS7347
incorporates many features not typically found in integrated video parts while consuming very low power. Each
channel configuration is completely independent of the other channels. This architecture allows for any
configuration for each channel to be dictated by the end user, rather than the part dictating what the configuration
must be—resulting in a highly flexible system.
The THS7347 has the following features:
• I2C interface for easy interfacing to the system.
• Single-supply 2.7-V to 5-V operation with low quiescent current of 80 mA at 3.3 V.
• 2:1 input mux.
• Input configuration accepts dc, dc + shift, ac bias, or ac sync-tip clamp selection.
• 500-MHz unity-gain buffer amplifier to drive ADC/Scalar/Decoder.
• Monitor Pass-Through path has an internal fixed gain of 2 V/V (+6 dB) amplifier that can drive two video lines
per channel with dc coupling, traditional ac coupling, or SAG-corrected ac coupling.
• While disabled, the Monitor Pass-Through path has a very high output impedance (> 500 kΩ || 8 pF)
• Power-Up Control (PUC) allows the THS7347 to be fully disabled or have the Monitor Pass-Through function
(with ac-bias mode on all channels) enabled upon initial device power-up.
• Mux is controlled by either I2C or a general-purpose input/output (GPIO) pin, based on the MUX Mode pin
logic.
• H-Sync and V-Sync paths have an externally-adjustable Schmitt trigger threshold
• Disable mode reduces quiescent current to as low as 0.1-μA.
OPERATING VOLTAGE
The THS7347 is designed to operate from 2.7 V to 5 V over a -40°C to +85°C temperature range. The impact on
performance over the entire temperature range is negligible because of the implementation of thin film resistors
and high-quality, low temperature coefficient capacitors.
A 0.1-μF to 0.01-μF capacitor should be placed as close as possible to the power-supply pins. Failure to do so
may result in the THS7347 outputs ringing or oscillating. Additionally, a large capacitor, such as 100 μF, should
be placed on the power-supply line to minimize issues with 50-Hz/60-Hz line frequencies.
INPUT VOLTAGE
The THS7347 input range allows for an input signal range from ground to approximately (VS+ – 1.6 V). However,
because of the internal fixed gain of 2 V/V (+6 dB), the output is generally the limiting factor for the allowable
linear input range. For example, with a 5-V supply, the linear input range is from GND to 3.4 V. As a result of the
gain, the linear output range limits the allowable linear input range from GND to 2.5 V at most.
Copyright © 2007–2011, Texas Instruments Incorporated
13
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
INPUT OVERVOLTAGE PROTECTION
The THS7347 is built using a very high-speed complementary bipolar and CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 3.
VS+
External
Input/
Output
Pin
Internal
Circuitry
Figure 3. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies. The
protection diodes can typically support 30 mA of continuous current when overdriven.
TYPICAL CONFIGURATION
A typical application circuit usng the THS7347 as an ac-coupled input video buffer is shown in Figure 4. It shows
the THS7347 driving a video ADC (such as the TVP7000) with 0-dB gain and also driving an output line with
6-dB gain. The Horizontal and Vertical Sync signals are also driven to the ADC and the Monitor Output
separately. Although the computer resolution R’G’B’HV signals are shown, these channels can easily be the
high-definition video (HD), enhanced-definition (ED), or standard-definition (SD) Y’P’BP’R (sometimes labeled
Y’U’V’ or incorrectly labeled Y’C’BC’R) channels. These channels could also be S-Video Y’/C’ channels and the
composite video baseband signal (CVBS). Note that the R’G’B’ channels could be professional/broadcast G’B’R’
signals or other R’G’B’ variations based on the placement of the sync signals that are commonly called R’G’sB’
(sync on Green) or R’sG’sB’s (sync on all signals).
The second set of inputs (B-Channels) shown are connected to another set of inputs. Again, these inputs can be
either HD, ED, SD, or R'G'B'/G'B'R' video signals. The THS7347 flexibility allows for virtually any input signal to
be driven into the THS7347 regardless of the other set of inputs. Simple control of the I2C configures the
THS7347 for any conceivable combination. For example, the THS7347 can be configured to have Channel 1
Input connected to input A while Channel 2 and Channel 3 are connected to input B. See the multiple application
notes sections explaining the I2C interface later in this document for details on configuring these options.
Note that the Y' term is used for the luma channels throughout this document, rather than the more common
luminance (Y) term. The reason for this usage is to account for the true definition of luminance as stipulated by
the CIE (International Commission on Illumination). Video departs from true luminance because a nonlinear term,
gamma, is added to the true RGB signals to form R'G'B' signals. These R'G'B' signals are then utilized to
mathematically create luma (Y'). Therefore, true luminance (Y) is not maintained, and thus the difference in
terminology arises.
This rationale is also utilized for the chroma (C') term. Chroma is derived from the nonlinear R'G'B' terms and
therefore it is also nonlinear. True chominance (C) is derived from linear RGB, and thus the difference between
chroma (C') and chrominance (C) exists. The color difference signals (P'B/ P'R/U'/V') are also referenced this way
to denote the nonlinear (gamma-corrected) signals.
R'G'B' (commonly labeled RGB) is also called G'B'R' (again commonly labeled as GBR) in professional video
systems. The SMPTE component standard stipulates that the luma information is placed on the first channel, the
blue color difference is placed on the second channel, and the red color difference signal is placed on the third
channel. This approach is consistent with the Y'P'BP'R nomenclature. Because the luma channel (Y') carries the
sync information and the green channel (G') also carries the sync information, it makes logical sense that G' be
14
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
placed first in the system. Since the blue color difference channel (P'B) is next and the red color difference
channel (P'R) is last, then it also makes logical sense to place the B' signal on the second channel and the R'
signal on the third channel, respectively. Thus, hardware compatibility is better achieved when using G'B'R'
rather than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels; this configuration
may not always be the case for all systems.
Monitor Output
2.2 mF
Red
75 W
75 W
75 W
75 W
75 W
75 W
Green
75 W
Y’
2.2 mF
75 W
75 W
P’B
2.2 mF
INPUT1
Blue
75 W
H-Sync
75 W
VA
806 W
P’R
VA
1.4 kW
V-Sync
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
806 W
1.4 kW
0.1 mF
INPUT2
Component
480i
576i
480p
576p
720p
1080i
1080p
G’B’R’
Y’
75 W
P’B
2.2 mF
30
29
28
27
VA
0.1 mF
VA
ADC
Scalar/
Decoder
0.1 mF
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
75 W
P’R
THS7347
7
8
9
10
11
+3.3 V +1.8 V
0.1 mF
2.2 mF
75 W
H-Sync and
V-Sync
0.1 mF
Not Used
3.3 V
3.3 V
22 pF
22 pF
100
100
VA = 3.3 V to 5 V
2
IC
(1)
Inputs and/or outputs can be ac- or dc-coupled if desired.
(2)
H-Sync and V-Sync input resistance as shown above = 2.2 kΩ, but may be changed to any desired resistance.
(3)
If the Monitor or Buffer PCB trace is > 25 mm, it is recommended to place at least a 10-Ω resistor in series with each
signal to reduce PCB parasitic issues
Figure 4. Typical R'G'B'HV and Y'P' BP' R AC-Coupled Inputs and DC-Coupled Output Configuration
Copyright © 2007–2011, Texas Instruments Incorporated
15
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
I2C INTERFACE NOTES
The I2C interface is used to access the internal registers of the THS7347. I2C is a two-wire serial interface
developed by Philips Semiconductor (see the I2C Bus Specification, Version 2.1, January 2000). The THS7347
was designed in compliance with version 2.1 specifications. The bus consists of a data line (SDA) and a clock
line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the
I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating
the SCL signal and device addresses. The master also generates specific conditions that indicate the START
and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master
device. The THS7347 works as a slave and supports the standard mode transfer (100 kbps) and fast mode
transfer (400 kbps) as defined in the I2C Bus Specification. The THS7347 has been tested to be fully functional
with the high-speed mode (3.4 Mbps) but it is not specified at this time.
Figure 5 shows the basic I2C start and stop access cycles.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SCL
S
P
Start
Condition
Stop
Condition
Figure 5. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
•
The master initiates data transfer by generating a start condition. The start condition exists when a
high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 5. All I2C-compatible
devices should recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 6). All devices
recognize the address sent by the master and compare it to the respective internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 7) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 6. I2C Bit Transfer
16
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
8
2
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 7. I2C Acknowledge
•
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 8).
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Stop
MSB
Acknowledge
Slave Address
Acknowledge
Data
2
Figure 8. I C Address and Data Cycles
•
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 5). This transaction releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition.
Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start
condition followed by a matching address.
Copyright © 2007–2011, Texas Instruments Incorporated
17
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
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During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. Figure 9 and Figure 10 show an example of a write cycle. Note that the
THS7347 does not allow multiple write transfers to occur. See the example, Writing to the THS7347, in WRITE
AND READ EXAMPLES for more information.
From Receiver
S
Slave Address
W
A
DATA
A
DATA
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
A
From Transmitter
Figure 9. I2C Write Cycle
Acknowledge
(From Receiver)
Start
Condition
A6
A5
A1
A0
R/W ACK
D7
Acknowledge
(Transmitter)
Acknowledge
(Receiver)
D6
D0
D1
ACK
D7
D6
D1
D0
ACK
SDA
2
First Data
Byte
I C Device Address and
Read/Write Bit
Other
Data Bytes
Stop
Condition
Last Data Byte
Figure 10. Multiple Byte Write Transfer
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle, as shown in Figure 11 and Figure 12.
Note that the THS7347 does not allow multiple read transfers to occur. See the example, Reading from the
THS7347, in WRITE AND READ EXAMPLES for more information.
S
Slave Address
R
A
DATA
A
DATA
A
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
Transmitter
Receiver
Figure 11. I2C Read Cycle
Start
Condition
SDA
Acknowledge
(From
Receiver)
A6
A0
R/W
ACK
I 2 C Device Address and
Read/Write Bit
D7
Not
Acknowledge
(Transmitter)
Acknowledge
(From
Transmitter)
D0
First Data
Byte
ACK
D7
Other
Data Bytes
D6
D1
D0
Last Data Byte
ACK
Stop
Condition
Figure 12. Multiple Byte Read Transfer
18
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THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
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Slave Address
Both the SDA and the SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors
should range from 2 kΩ to 19 kΩ in order to comply with the I2C specification. When the bus is free, both lines
are high. The address byte is the first byte received following the START condition from the master device. The
first five bits (MSBs) of the address are factory-preset to 01011. The next two bits of the THS7347 address are
controlled by the logic levels appearing on the I2C, A1 and I2C, A0 pins. The I2C, A1 and I2C, A0 address inputs
can be connected to VDD for logic 1, GND for logic 0, or actively driven by TTL/CMOS logic levels. The device
address is set by the state of these pins and is not latched. Thus, a dynamic address control system could be
used to incorporate several devices on the same system. Up to four THS7347 devices can be connected to the
same I2C bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7347.
Table 1. THS7347 Slave Addresses
SELECTABLE WITH
ADDRESS PINS
FIXED ADDRESS
READ/WRITE
BIT
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 (A1)
Bit 1 (A0)
Bit 0 (R/W)
0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
0
1
0
1
1
1
1
1
Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin
The THS7347 operates using only a single-byte transfer protocol similar to that illustrated in Figure 9 and
Figure 11. The internal subaddress registers and the functionality of each are given in Table 2. When writing to
the device, it is required to send one byte of data to the corresponding internal subaddress. If control of all three
channels is desired, then the master must cycle through all the subaddresses (channels) one at a time; see the
example, Writing to the THS7347 (in WRITE AND READ EXAMPLES) for the proper procedure of writing to the
THS7347.
During a read cycle, the THS7347 sends the data in its selected subaddress (or channel) in a single transfer to
the master device requesting the information. See the Reading from the THS7347 example (in WRITE AND
READ EXAMPLES) for the proper procedure on reading from the THS7347.
On power-up, the THS7347 registers are dictated by the Power-Up Control (PUC) pin. If the PUC pin is tied to
GND, the THS7347 powers up in a fully disabled state. If the PUC pin is tied to VDD, upon power-up the
THS7347 is configured in the following state: ADC buffers disabled, monitor pass-through enabled, and ac-bias
on, for all three input channels. It remains in the state dictated by the PUC unti a valid write sequence is
completed.
Table 2. THS7347 Channel Selection Register Bit Assignments
REGISTER NAME
BIT ADDRESS
(b7b6b5....b0)
Channel 1
0000 0001
Channel 2
0000 0010
Channel 3
0000 0011
Channel H Sync, Channel V Sync, and
Disable Controls
0000 0100
Copyright © 2007–2011, Texas Instruments Incorporated
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THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
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Channel Register Bit Descriptions
Each bit of the subaddress (channel selection) control register as described in the previous section allows the
user to individually control the THS7347 functionality. This process allows the user to control the functionality of
each channel independently with regard to the other channels. The bit description for Channel 1 through Channel
3 is shown in Table 3, while the H/V sync channels and the analog channel states are described in Table 4.
Table 3. THS7347 Channel Register (Channel 1 through Channel 3) Bit Decoder Table.
Use with Register Bit Codes (0000 0001), (0000 0010), and (0000 0011)
BIT
(MSB)
7
6, 5, 4, 3
2, 1, 0
(LSB)
FUNCTION
Sync-Tip Clamp Filter
MUX Selection
Input Mode
+
Operation
BIT VALUE(S)
RESULT
0
500-kHz filter on the STC circuit
1
5-MHz filter on the STC circuit
0000
MUX Input A
0001
MUX Input A
0010
MUX Input A
0011
MUX Input A
0100
MUX Input A
0101
MUX Input B
0110
MUX Input B
0111
MUX Input B
1000
MUX Input B
1001
MUX Input B
1010
Reserved; do not care
1011
Reserved; do not care
1100
Reserved; do not care
1101
Reserved; do not care
1110
Reserved; do not care
1111
Reserved; do not care
000
Disables both monitor and buffer paths of the respective
channel/register
001
Channel Mute
010
Input Mode = dc
011
Input Mode = dc + Shift
100
Input Mode = ac-bias
101
Input Mode = ac-STC with low bias
110
Input Mode = ac-STC with mid bias
111
Input Mode = ac-STC with high bias
Bit 7 (MSB): Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected.
Bits 6, 5, 4, 3: Selects the Input MUX channel.
Bits 2, 1, and 0 (LSB): Configures the channel mode and operation. See Table 4, Bits 6 and 5, for more
information with respect to the enable/disable state.
20
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
Table 4. THS7347 Channel Register (H/V Sync Channel + Analog Channels State) Bit Decoder Table.
Use in Conjunction With Register Bit Code (0000 0100)
BIT
FUNCTION
BIT
VALUE(S)
(MSB)
7
Reserved; Do not care
X
Reserved; do not care
Monitor Pass-Through Path Disable
Mode
(Use in Conjunction with Table 3)
0
6
Disables all monitor channels regardless of bits 2:0 of Register 1
through Register 3
1
Enables monitor channels functions dictated by each programmed
register code
0
5
Buffer Path Disable Mode
(Use in Conjunction with Table 3)
Disables all buffer channels regardless of bits 2:0 of Register 1
through Register 3
1
Enables buffer channel functions dictated by each programmed
register code
4, 3
2, 1
0
(LSB)
Vertical Sync Channel MUX Selection
Horizontal Sync Channel MUX Selection
H/V Sync Paths Disable Mode
RESULT
00
MUX Input A
01
MUX Input B
10
Reserved; do not care
11
Reserved; do not care
00
MUX Input A
01
MUX Input B
10
Reserved; do not care
11
Reserved; do not care
0
Disable H-Sync and V-Sync Channels
1
Enable H-Sync and V-Sync Channels
Bit (MSB) 7: Reserved; do not care.
Bit 6: Master Monitor Path Disable. Disables all monitor channels regardless of what is programmed into
each register channel (1 to 3).
Bit 5: Master Buffer Path Disable. Disables all buffer channels regardless of what is programmed into each
register channel (1 to 3).
Bits 4, 3: Selects the Input MUX channel for the Vertical Sync.
Bits 2, 1: Selects the Input MUX channel for the Horizontal Sync.
Bit 0 (LSB): Enables or disables the H-Sync and V-Sync Channels.
Copyright © 2007–2011, Texas Instruments Incorporated
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THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
WRITE AND READ EXAMPLES
These examples illustrate the proper way to write to and read from the THS7347.
WRITING TO THE THS7347
An I2C master initiates a write operation to the THS7347 by generating a start condition (S) followed by the
THS7347 I2C address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an
acknowledge from the THS7347, the master presents the subaddress (channel) it wants to write, consisting of
one byte of data, MSB first. The THS7347 acknowledges the byte after completion of the transfer. Finally, the
master presents the data it wants to write to the register (channel) and the THS7347 acknowledges the byte. The
I2C master then terminates the write operation by generating a stop condition (P). Note that the THS7347 does
not support multi-byte transfers. To write to all three channels (or registers), this procedure must be repeated for
each register, one series at a time (that is, repeat steps 1 through 8 for each channel).
Step 1
0
I2C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
1
X
X
0
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.
Step 3
2
I C Acknowledge (Slave)
9
A
Step 4
7
6
5
4
3
2
1
0
I2C Write Channel Address (Master)
0
0
0
0
0
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
2
I C Write Data (Master)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the values shown in Table 3.
Step 7
2
9
I C Acknowledge (Slave)
A
Step 8
0
I2C Stop (Master)
P
22
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
READING FROM THE THS7347
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the THS7347 by generating a start condition (S) followed by the THS7347 I2C
address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an acknowledge from the
THS7347, the master presents the subaddress (channel) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7347 by
generating a start condition followed by the THS7347 I2C address, in MSB-first order, followed by a '1' to indicate
a read cycle. After an acknowledge from the THS7347, the I2C master receives one byte of data from the
THS7347. After the data byte has been transferred from the THS7347 to the master, the master generates a
not-acknowledge (A) followed by a stop. As with the Write function, to read all channels, steps 1 through 11 must
be repeated for each channel desired.
THS7347 Read Phase 1:
Step 1
0
I2C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
1
X
X
0
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.
Step 3
2
I C Acknowledge (Slave)
9
A
Step 4
7
6
5
4
3
2
1
0
I2C Read Channel Address (Master)
0
0
0
0
0
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
0
2
I C Start (Master)
P
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23
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
THS7347 Read Phase 2:
Step 7
0
I2C Start (Master)
S
Step 8
2
I C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
1
Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.
Step 9
9
I2C Acknowledge (Slave)
A
Step 10
I2C Read Data (Slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the logic values contained in the Channel Register.
Step 11
9
I2C Not-Acknowledge (Master)
A
Step 12
0
I2C Stop (Master)
P
24
Copyright © 2007–2011, Texas Instruments Incorporated
THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2008) to Revision B
Page
•
Changed first DC Performance, Bias output voltage, Buffer output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 3.3-V Electrical Characteristics table .......................................................................................... 3
•
Changed first DC Performance, Bias output voltage, Monitor output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 3.3-V Electrical Characteristics table .......................................................................................... 3
•
Changed DC Performance, Sync tip clamp voltage, Buffer output parameter +25°C, 0°C to +70°C, and –40°C to
+85°C specifications in 3.3-V Electrical Characteristics table .............................................................................................. 3
•
Changed first DC Performance, Bias output voltage, Buffer output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 5-V Electrical Characteristics table ............................................................................................. 6
•
Changed first DC Performance, Bias output voltage, Monitor output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 5-V Electrical Characteristics table ............................................................................................. 6
•
Changed DC Performance, Sync tip clamp voltage, Buffer output parameter +25°C, 0°C to +70°C, and –40°C to
+85°C specifications in 5-V Electrical Characteristics table ................................................................................................. 6
Changes from Original (May 2007) to Revision A
Page
•
Added Digital Characteristics section to 3.3-V Electrical Characteristics table .................................................................... 3
•
Added Digital Characteristics section to 5-V Electrical Characteristics table ....................................................................... 6
Copyright © 2007–2011, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS7347IPHP
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
THS7347
THS7347IPHPG4
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
THS7347
THS7347IPHPR
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
THS7347
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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