THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
features
applications
D
D
D
D
D
D
D
D
D
D
48 PHP PACKAGE
(TOP VIEW)
AVSS
AVDD
AVSS
AVDD
AVSS
AVSS
DRVSS
DRVSS
DRVDD
DRVDD
D
D
D
D
D
Wireless Local Loop
Wireless Internet Access
Cable Modem Receivers
Medical Ultrasound
Magnetic Resonant Imaging
VCM
AVDD
D
D
50 MSPS Maximum Sample Rate
10-Bit Resolution
No Missing Codes
On-Chip Sample and Hold
73 dB Spurious Free Dynamic Range at
fin = 15.5 MHz
5 V Analog and Digital Supply
3 V and 5 V CMOS Compatible Digital
Output
9.7 Bit ENOB at fIN = 31 MHz
60 dB SNR at fIN = 31 MHz
82 MHz Bandwidth
Internal or External Reference
Buffered 900-Ω Differential Analog Input
48 47 46 45 44 43 42 41 40 39 38 37
AVSS
AVDD
VIN+
VIN–
AVDD
1
36
2
35
3
34
4
33
5
32
VREFOUT–
VREFIN–
VREFIN+
VREFOUT+
VBG
AVSS
AVDD
6
description
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DVSS
CLK+
CLK–
DVDD
DVSS
DVSS
DVDD
DVSS
DVDD
DRVSS
DRVDD
AV SS
31
The THS1050 is a high-speed low-noise 10-bit
30
7
CMOS pipelined analog-to-digital converter. A
29
8
differential sample and hold minimizes even order
28
9
harmonics and allows for a high degree of
27
10
common-mode rejection at the analog input. A
26
11
buffered analog input enables operation with a
25
12
constant analog input impedance, and prevents
transient voltage spikes from feeding backward to
13 14 15 16 17 18 19 20 21 22 23 24
the analog input source. Full temperature DNL
performance allows for industrial application with
the assurance of no missing codes. The typical
integral nonlinearity (INL) for the THS1050 is less
than one LSB. The superior INL curve of the THS1050 results in SFDR performance that is exceptional for a
10-bit analog-to-digital converter. The THS1050 can operate with either internal or external references. Internal
reference usage selection is accomplished simply by externally connecting reference output terminals to
reference input terminals.
AVAILABLE OPTIONS
PACKAGE
TA
48-TQFP
(PHP)
– 40°C to 85°C
THS1050I
0°C to 70°C
THS1050C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
functional block diagram
AVDD DVDD DRVDD
VIN+
S/H
900 Ω
A/D
Σ
D/A
A/D
D/A
A/D
1
1
1
3.0 V
Reference
AVDD/2
2.0 V
VREFOUT–
VREFIN–
Stage 10
Σ
VIN–
VREFIN+
VREFOUT+
Stages 2 – 9
Stage 1
Buffer
Digital Error Correction
VCM
CLK+
Timing
CLK–
AVSS
DVSS DRVSS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVDD
2, 5, 12 43,
45, 47
I
Analog power supply
AVSS
1, 11, 13, 41,
42, 44, 46
I
Analog ground return for internal analog circuitry
CLK+
15
I
Clock input
CLK–
16
I
Complementary clock input
D9–D0
25–34
O
Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRVDD
DRVSS
24, 37, 38
I
Digital output driver supply
23, 39, 40
I
Digital output driver ground return
DVDD
17, 20, 22
I
Positive digital supply
DVSS
18, 19, 21
I
Digital ground return
VBG
VCM
10
O
Band gap reference. Bypass to ground with a 1-µF and a 0.01-µF chip capacitor.
48
O
Common mode voltage output. Bypass to ground with a 0.1-µF and a 0.01-µF chip device capacitor.
VIN+
VIN–
3
I
Analog signal input
4
I
Complementary analog signal input
VREFIN –
VREFIN+
7
I
External reference input low
8
I
External reference input high
VREFOUT+
VREFOUT –
9
O
Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
6
O
Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
detailed description
The THS1050 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 900-Ω resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational
amplifier based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional
block diagram. The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic
block which then outputs the final 10 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range: AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DRVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage between AVSS and DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 0.5 V
Voltage between DRVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Voltage between AVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Digital data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V
CLK peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA
Operating free-air temperature range, TA: THS1050C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
THS1050I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
PARAMETER
MIN
Sample rate
NOM
MAX
UNIT
50
MSPS
1
Analog supply voltage, AVDD
4.75
5
5.25
V
Digital supply voltage, DVDD
4.75
5
5.25
V
Digital output driver supply voltage, DRVDD
3
3.3
5.25
V
CLK + high level input voltage, VIH
4
5
5.5
V
0
1
V
5
5.5
V
0
1
V
CLK + low-level input voltage, VIL
CLK – high-level input voltage, VIH
4
CLK – low-level input voltage, VIL
CLK pulse-width high, tp(H)
9
10
ns
CLK pulse-width low, tp(L)
9
10
ns
Operating free-air temperature range, TA
THS1050C
Operating free-air temperature range, TA
THS1050I
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0
70
°C
– 40
85
°C
3
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
electrical characteristics over recommended operating free-air temperature range,
AVDD = DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 50 MHz (unless otherwise noted)†
dc accuracy
PARAMETER
DNL
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
± 0.3
±0.6
LSB
± 2.5
LSB
Differential nonlinearity
No missing codes
INL
Assured
± 0.9
Integral nonlinearity
EO
Offset error
EG
Gain error
† All typical values are at TA = 25°C.
14
29
–7
– 10
%FSR
mV
TYP
MAX
UNIT
100
145
mA
2
5
mA
2
6
mA
power supply
PARAMETER
I(AVDD)
I(DVDD)
TEST CONDITIONS
Analog supply current
MIN
V(VIN) = V(VCM)
V(VIN) = V(VCM)
Digital supply current
I(DRVDD) Output driver supply current
PD
Power dissipation
† All typical values are at TA = 25°C.
V(VIN) = V(VCM)
V(VIN) = V(VCM)
0.5
W
reference
MIN
TYP
VREFOUT –
VREFOUT+
Negative reference output voltage
PARAMETER
TEST CONDITIONS
1.9
2
2.1
V
Positive reference output voltage
2.9
3
3.1
V
VREFIN –
VREFIN+
External reference supplied
V(VCM)
Common mode output voltage
External reference supplied
I(VCM)
Common mode output current
† All typical values are at TA = 25°C.
MAX
UNIT
2
V
3
V
AVDD/2
V
10
µA
analog input
PARAMETER
RI
Differential input resistance
CI
Differential input capacitance
VI
VID
Analog input common mode range
TEST CONDITIONS
MIN
TYP
MAX
Ω
4
pF
VCM ± 0.05
2
Differential input voltage range
BW Analog input bandwidth (large signal)
† All typical values are at TA = 25°C.
–3 dB
UNIT
900
V
V p-p
82
MHz
digital outputs
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = – 50 µA
IOL = 50 µA
High-level output voltage
Low-level output voltage
CL
Output load capacitance
† All typical values are at TA = 25°C.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
0.2DRVDD
VDD
15
pF
0.8DRVDD
V
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
ac specifications over recommended operating free-air temperature range, AVDD = DVDD = 5 V,
DRVDD = 3.3 V, internal references, CLK = 50 MHz, analog input at –2 dBFS (unless otherwise
noted)†
PARAMETER
SNR
Signal-to-noise ratio
TEST CONDITIONS
fIN = 2.2 MHz
fIN =15.5 MHz
MIN
Signal-to-noise and distortion
fIN =15.5 MHz
fIN =31 MHz
fIN =15.5 MHz
58
60.5
56
dBFS
60.8
60.2
Effective number of bits
Total harmonic distortion
SFDR
Spurious-free dynamic range
fIN =15.5 MHz
fIN =15.5 MHz
Distortion
fIN = 2.2 MHz
fIN =15.5 MHz
–83
d Harmonic
2nd
fIN = 31 MHz
fIN = 2.2 MHz
–77
fIN =15.5 MHz
fIN = 31 MHz
–73
9.3
9.8
–72
65
bits
–63
73
–89
dBc
–65
dBc
–65
dBc
–68
–80
F1 = 14.9 MHz,
F2 = 15.6 MHz,
Analog inputs at – 8 dBFS each
Two tone SFDR
dBFS
61
THD
Distortion
UNIT
60.5
ENOB
d Harmonic
3rd
MAX
61
fIN =31 MHz
fIN = 2.2 MHz
SINAD
TYP
72
dBc
† All typical values are at TA = 25°C.
operating characteristics over recommended operating conditions, AVDD = DVDD = 5 V,
DRVDD = 3.3 V†
switching specifications
PARAMETER
TEST CONDITIONS
Aperture delay, td(A)
TYP
MAX
120
Aperture jitter
Output delay td(O)
MIN
ps
1
After falling edge of CLK+
Pipeline delay td(PIPE)
ps RMS
13
6.5
UNIT
ns
CLK
Cycle
† All typical values are at TA = 25°C.
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• DALLAS, TEXAS 75265
5
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
definitions of specifications
analog bandwidth
The analog input frequency at which the spectral power of the fundamental frequency of a large input signal
is reduced by 3 dB.
aperture delay
The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is
sampled.
aperture uncertainity (jitter)
The sample-to-sample variation in aperture delay
differential nonlinearity
The average deviation of any output code from the ideal width of 1 LSB.
clock pulse width/duty cycle
Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve
rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock
rate, these specs define acceptable clock duty cycles.
offset error
The difference between the analog input voltage at which the analog-to-digital converter output changes from
negative full scale, to one LSB above negative full scale, and the ideal voltage at which this transition should
occur.
gain error
The maximum error in LSBs between a digitized ideal full scale low frequency offset corrected triangle wave
analog input, from the ideal digitized full scale triangle wave, divided by the full scale range, in this case 1024.
harmonic distortion
The ratio of the power of the fundamental to a given harmonic component reported in dBc.
integral nonlinearity
The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB.
Also the integral of the DNL curve.
output delay
The delay between the 50% point of the falling edge of the clock and signal and the time when all output data
bits are within valid logic levels (not including pipeline delay).
signal-to-noise-and distortion (SINAD)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral
components, excluding dc, referenced to full scale.
signal-to-noise ratio (SNR)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral
components, excluding dc and the first 9 harmonics, referenced to full scale.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the effective number of bits, using the following formula,
ENOB
+ (SINAD6.02* 1.76)
spurious-free dynamic range (SFDR)
The ratio of the signal power to the power of the worst spur, excluding dc. The worst spurious component may
or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered).
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
Sample N
V(VIN)
td(A)
td(Pipe)
tp(H)
tP(L)
CLK+
tc
Digital Output
(D0 – D9)
td(O)
Data N–7
Data N–6
Data N–5
Data N–4
Data N–3
Data N–2
Data N–1
Data N
Data N+1
Data N+2
Figure 1. Timing Diagram
equivalent circuits
φ2
R2
BAND
GAP
R1
VCM
VREFOUT+
VREFOUT–
R1
R2
VIN+
φ1′
φ1
900 Ω
AVDD
VIN–
φ1
φ1′
600 Ω
VCM
VCM
590 Ω
φ2
AVSS
Figure 3. Analog Input Stage
Figure 2. References
DVDD
VDD
CLK+
10 Ω
DVSS
DVDD
D0–D11
Timing
CLK–
VSS
Figure 5. Digital Outputs
DVSS
Figure 4. Clock Inputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS†
Power – dBFS
OUTPUT POWER SPECTRUM
vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
Fs = 50 MSPS
fIN = 2.2 MHz, VIN @ –2 dBFS
8K Point Discrete Fourier
Transform
0
5
10
15
20
25
f – Frequency – MHz
Figure 6
Power – dBFS
OUTPUT POWER SPECTRUM
vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
Fs = 50 MSPS
fIN = 15.5 MHz, VIN @ –2 dBFS
8K Point Discrete Fourier
Transform
0
5
10
15
f – Frequency – MHz
Figure 7
† AVDD = 5 V, DVDD = 5 V, DRVDD = 3.3 V, TA = 25°C (unless otherwise noted)
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
25
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
OUTPUT POWER SPECTRUM
vs
FREQUENCY
0.00
–10.00
–20.00
–30.00
–40.00
–50.00
–60.00
–70.00
–80.00
–90.00
–100.00
–110.00
Power – dBFS
Fs = 50 MSPS
fIN = 31 MHz, VIN @ –2 dBFS
8K Point Discrete Fourier
Transform
0
5
10
15
20
25
20
25
f – Frequency – MHz
Figure 8
Power – dBFS
OUTPUT POWER SPECTRUM
vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
Fs = 50 MSPS
fIN = 69 MHz, VIN @ –2 dBFS
8K Point Discrete Fourier
Transform
0
5
10
15
f – Frequency – MHz
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
NOISE AND DISTORTION
vs
ANALOG INPUT FREQUENCY
90.00
Fs = 50 MSPS
VIN @ –2 dBFS
Power – dB
80.00
70.00
60.00
2nd
Harmonic
(dBc)
50.00
3rd
Harmonic
(dBc)
SFDR (dBc)
SINAD
(dBFS)
SNR (dBFS)
40.00
0
10
20
30
40
50
60
70
80
90
f – Analog Input Frequency – MHz
Figure 10
Power – dBFS
TWO-TONE OUTPUT POWER SPECTRUM
vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
Fs = 50 MSPS, F1 = 14.9 MHz,
F2 = 15.6 MHz each @ –8 dBFS
8K Point Discrete Fourier
Transform
0
5
10
15
f – Frequency – MHz
Figure 11
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
25
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
Power – dB
NOISE AND DISTORTION
vs
ANALOG INPUT POWER LEVEL
100
90
Fs = 50 MSPS
fIN = 15.5 MHz
80
70
60
50
40
30
20
10
0
–50
–45
–40
SFDR(dBc)
SNR(dBFS)
–35
–30
SINAD(dBFS)
–25
–20
–15
–10
–5
0
Analog Input Power – dBFS
Figure 12
Power – dB
NOISE AND DISTORTION
vs
CLOCK FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
SNR(dBFS)
SFDR(dBc)
SINAD(dBFS)
fIN = 15.5 MHz, VIN @ –2 dBFS
5
10
15
20
25
30
35
40
45
50
55
60
65
70
Clock Frequency – MHz
Figure 13
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• DALLAS, TEXAS 75265
11
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
Power – dB
NOISE AND DISTORTION
vs
DUTY CYCLE
100
90
80
70
60
50
40
30
20
10
0
SNR (dBFS)
SFDR (dBc)
SINAD (dBFS)
Fs = 50 MSPS
fIN = 15.5 MHz, VIN @ –2 dBFS
40
45
50
55
60
Duty Cycle – %
Figure 14
DIFFERENTIAL NONLINEARITY (DNL)
vs
OUTPUT CODE
1
DNL – (LSBs)
Fs = 50 MSPS
fIN = 15.5 MHz
0
–1
0
256
512
768
Output Code
Figure 15
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1024
1023
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY (INL)
vs
OUTPUT CODE
1.00
INL – LSBs
Fs = 50 MSPS
fIN = 15.5 MHz
0.00
–1.00
0
256
512
Output Code – LSBs
768
1023
Figure 16
LARGE SIGNAL ANALOG INPUT BANDWIDTH
Power – dBFS
0
–10
–20
Fs = 50 MSPS
–3 dB Point @ 82 MHz
–30
0
20
40
60
80
100
f – Analog Input Frequency – MHz
Figure 17
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• DALLAS, TEXAS 75265
13
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
APPLICATION INFORMATION
using the THS1050 references
The option of internal or external reference is provided by allowing for an external connection of the internal
reference to the reference inputs. This type of reference selection offers the lowest noise possible by not relying
on any active switch to make the selection. Compensating each reference output with a 1-µF and 0.01-µF chip
capacitor is required as shown in Figure 18. The differential analog input range is equal to
2 (VREFOUT+ – VREFOUT–). When using external references, it is best to decouple the reference inputs with a
0.1-µF and 0.01-µF chip capacitor as shown in Figure 19.
VREFIN+
VREFOUT+
0.01 µF
VREFIN+
External Reference +
0.01 µF
1 µF
0.1 µF
VREFIN–
VREFOUT–
0.01 µF
0.01 µF
1 µF
Figure 18. Internal Reference Usage
VREFIN–
External Reference –
0.1 µF
Figure 19. External Reference Usage
using the THS1050 clock input
The THS1050 is a high performance A/D converter. In order to obtain the best possible performance, care
should be taken to ensure that the device is clocked appropriately. The optimal clock to the device is a low jitter
square wave with sharp rise times (< 2ns) at 50% duty cycle. The two clock inputs (CLK+ and CLK–), should
be driven with complementary signals that have minimal skew, and nominally swing between 0 V and 5 V. The
device still operates with a peak-to-peak swing of 3 V on each clock channel (around the 2.5-V midpoint).
Use of a transformer coupled clock input ensures minimal skew between the CLK+ and CLK– signals. If the
available clock signal swing is not adequate, a step-up transformer can be used in order to deliver the required
levels to the converter’s inputs, see Figure 20. For example if a 3.3-V standard CMOS logic is used for clock
generation, a minicircuits T4 –1H transformer can be used for 2x voltage step-up. This provides greater than
6-V differential swing at the secondary of the transformer, which provides greater than 3-V swings to both CLK+
and CLK– terminals of THS1050. The center tap of the transformer secondary is connected to the VCM terminal
of the THS1050 for proper dc biasing.
Both the transformer and the clock source should be placed close to THS1050 to avoid transmission line effects.
3.3-V TTL logic is not recommended with T4 –1H transformer due to TTLs tendency to have lower output swings.
If the input to the transformer is a square wave (such as one generated by a digital driver), care must be taken
to ensure that the transformer’s bandwidth does not limit the signal’s rise time and effectively alter its shape and
duty cycle characteristics. For a 50 MSPS rate, the transformer’s bandwidth should be at least 300 MHz. A low
phase noise sinewave can also be used to effectively drive the THS1050. In this case, the bandwidth of the
transformer becomes less critical, as long as it can accommodate the frequency of interest (for example,
50 MHz). The turns ratio should be chosen to ensure appropriate levels at the device’s input. If the clock signal
is fed through a transmission line of characteristic impedance Zo, then the secondary of the transformer should
be terminated with a resistor of nZo, where n is the transformer’s impedance ratio (1:n) as shown in Figure 20.
Alternatively a series termination resistor having impedance equal to the characteristic impedance of the
transmission line can be used at the clock source.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
APPLICATION INFORMATION
3 V p-p
to
5 V p-p
0.1 µF
Impedance Ratio = 1:4
Zo
CLK+
R = Zo
T4-1H
R = 4 Zo
ac Signal Source
THS1050
CLK–
VCM
0.01 µF
0.1 µF
Figure 20. Driving the Clock From an Impedance Matched Source
The clock signals, CLK+ and CLK–, should be well matched and must both be driven.
A transformer ensures minimal skew between the two complementary channels. However, skew levels of up
to 500 ps between CLK+ and CLK– can be tolerated with some performance degradation.
The clock input can also be driven differentially with a 5-V TTL signal by using an RF transformer to convert the
TTL signal to a differential signal. The TTL signal is ac-coupled to the positive primary terminal with a high pass
circuit. The negative terminal of the transformer is connected to ground (see Figure 21). The transformer
secondary is connected to the CLK inputs.
Impedance Ratio = 1:4
0.1 µF
5 V TTL CLK
CLK+
THS1050
T4 - 1H
CLK–
VCM
0.01 µF
0.1 µF
Figure 21. TTL Clock Input
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
APPLICATION INFORMATION
using the analog input
The THS1050 obtains optimum performance when the analog signal inputs are driven differentially. The circuit
below shows the optimum configuration, see Figure 22. The signal is fed to the primary of an RF transformer.
Since the input signal must be biased around the common mode voltage of the internal circuitry, the common
mode (VCM) reference from the THS1050 is connected to the center-tap of the secondary. To ensure a steady
low noise VCM reference, the best performance is obtained when the VCM output is connected to ground with
a 0.1-µF and 0.01-µF low inductance capacitor.
Z0 = 50 Ω
R0
1:1
VIN+
50 Ω
R
50 Ω
ac Signal Source
THS1050
VIN–
T1-1T
VCM
0.01 µF
0.1 µF
Figure 22. Driving the THS1050 Analog Input With Impedance Matched Transmission Line
When it is necessary to buffer or apply a gain to the incoming analog signal, it is also possible to combine a
single-ended amplifier with an RF transformer as shown in Figure 23. For this application, a wide-band current
mode feedback amplifier such as the THS3001 is best. The noninverting input to the op-amps is terminated with
a resistor having an impedance equal to the characteristic impedance of the wave-guide or trace that sources
the IF input signal. The single ended output allows the use of standard passive filters between the amplifier
output and the primary. In this case, the SFDR of the op amp is not as critical as that of the A/D converter. While
harmonics generated from within the A/D converter fold back into the first Nyquist zone, harmonics generated
externally in the op amps can be filtered out with passive filters.
1 kΩ
1 kΩ
Impedance Ratio = 1:n
10 Ω
_
RT
VIN+
BPF
+
IF Input
THS3001
THS1050
VIN–
VCM
0.1 µF
Figure 23. IF Input Buffered With THS3001 Op-Amp
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.01 µF
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
APPLICATION INFORMATION
digital outputs
The digital outputs are in 2s complement format and can drive either TTL, 3-V CMOS, or 5-V CMOS logic. The
digital output high voltage level is equal to DRVDD. Table 1 shows the value of the digital output bits for full scale
analog input voltage, midrange analog input voltage, and negative full scale input voltage. To reduce capacitive
loading, each digital output of the THS1050 should drive only one digital input. The CMOS output drivers are
capable of handling up to a 15-pF load. For better SNR performance, use 3.3 V for DRVDD. Resistors of 200 Ω
in series with the digital output can be used for optimizing SNR performance.
Table 1. Digital Outputs
ANALOG INPUT (VIN+) OR – (VIN–)
D9
D8
D7
D6
D5
D4
D
D2
D1
D0
Vref+
0
1
1
1
1
1
1
1
1
1
VCM
Vref–
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
power supplies
Best performance is obtained when AVDD is kept separate from DVDD. Regulated or linear supplies, as opposed
to switched power supplies, must be used to minimize supply noise. It is also recommended to partition the
analog and digital components on the board in such a way that the analog supply plane does not overlap with
the digital supply plane in order to limit dielectric coupling between the different supplies.
package
The THS1050 is packaged in a small 48-pin quad flat-pack PowerPAD package. The die of the THS1050 is
bonded directly to copper alloy plate which is exposed on the bottom of the package. Although, the PowerPAD
provides superior heat dissipation when soldered to ground land, it is not necessary to solder the bottom of the
PowerPAD to anything in order to achieve minimum performance levels indicated in this specification over the
full recommended operating temperature range.
If the device is to be used at ambient temperatures above the recommended operating temperatures, use of
the PowerPAD is suggested.
The copper alloy plate or PowerPAD is exposed on the bottom of the device package for a direct solder
attachment to a PCB land or conductive pad. The land dimensions should have minimum dimensions equal to
the package dimensions minus 2 mm, see Figure 24.
For a multilayer circuit board, a second land having dimensions equal to or greater than the land to which the
device is soldered should be placed on the back of the circuit board (see Figure 25). A total of 9 thermal vias
or plated through-holes should be used to connect the two lands to a ground plane (buried or otherwise) having
a minimum total area of 3 inches square in 1 oz. copper. For the THS1050 package, the thermal via centers
should be spaced at a minimum of 1 mm. The ground plane need not be directly under or centered around the
device footprint if a wide ground plane thermal run having a width on the order of the device is used to channel
the heat from the vias to the larger portion of the ground plane. The THS1050 package has a standoff of 0.19
mm or 7.5 mils. In order to apply the proper amount of solder paste to the land, a solder paste stencil with a 6
mils thickness is recommended for this device. Too thin a stencil may lead to an inadequate connection to the
land. Too thick a stencil may lead to beading of solder in the vicinity of the pins which may lead to shorts. For
more information, refer to Texas Instruments literature number SLMA002 PowerPAD Thermally Enhanced
Package.
PowerPAD is a trademark of Texas Instruments.
POST OFFICE BOX 655303
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17
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
APPLICATION INFORMATION
package (continued)
1.25 mm
2 x 1.25 mm
1.25 mm
5 mm
2 x 1.25 mm
0.33 mm Diameter
Plated Through Hole
5 mm
Figure 24. Thermal Land (top view)
PHP (S-PQFP-G48)
Thermal
Land
ÏÏÏÏÌÌÎÎ
ÎÎÎÎÎ
ÌÌÎÎ
ÌÌÌÌÌ
ÎÎÎÎÎÎ
ÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÌÌÎÎ
ÌÌÎÎ
ÌÌÌÌÌ
Plated Through Hole
PWB
Figure 25. Top and Bottom Thermal Lands With Plated Through Holes (side view)
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278A – APRIL 2000 – REVISED MARCH 2001
MECHANICAL DATA
PHP (S-PQFP-G48)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
Thermal Pad
(see Note D)
48
13
0,13 NOM
1
12
5,50 TYP
Gage Plane
7,20
SQ
6,80
9,20
SQ
8,80
0,25
0,15
0,05
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146927/A 01/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS1050CPHP
OBSOLETE
HTQFP
PHP
48
TBD
Call TI
Call TI
THS1050IPHP
OBSOLETE
HTQFP
PHP
48
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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