THS7530PWPG4

THS7530 THS7530 SLOS405E – DECEMBER 2002 – REVISED AUGUST 2020 SLOS405E – DECEMBER 2002 – REVISED AUGUST 2020 www.ti.com THS7530 High-Speed, Fully Differential, Continuously Variable Gain Amplifier 1 Features 3 Description • The THS7530 device is fabricated using Texas Instruments' state-of-the-art BiCom III SiGe complementary bipolar process. The THS7530 device is a DC-coupled, wide bandwidth amplifier with voltage-controlled gain. The amplifier has highimpedance differential inputs and low-impedance differential outputs with high-bandwidth gain control, output common-mode control, and output voltage clamping. • • • • • • • Low Noise: Vn = 1.1 nV/√ Hz, Noise Figure = 9 dB Low Distortion: – HD2 = –65 dBc, HD3 = –61 dBc at 32 MHz – IMD3 = –62 dBc, OIP3 = 21 dBm at 70 MHz 300-MHz Bandwidth Continuously Variable Gain Range: 11.6 dB to 46.5 dB Gain Slope: 38.8 dB/V Fully Differential Input and Output Output Common-Mode Voltage Control Output Voltage Limiting Signal-channel performance is exceptional with 300-MHz bandwidth, and third harmonic distortion of – 61 dBc at 32 MHz with 1-VPP output into 400 Ω. Gain control is linear in dB with 0 V to 0.9 V varying the gain from 11.6 dB to 46.5 dB with 38.8-dB/V gain slope. 2 Applications • • • • Time Gain Amplifiers in Ultra Sound, Sonar, and Radar Automatic Gain Control in Communication and Video System Gain Calibration in Communications Variable Gain in Instrumentation Output voltage limiting is provided to limit the output voltage swing and to prevent saturating following stages. The device is characterized for operation over the industrial temperature range, –40°C to +85°C. Device Information (1) PART NUMBER THS7530 (1) 1 kW PACKAGE HTSSOP (14) BODY SIZE (NOM) 5.00 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. VS+ = 5 V 1 kW 0.1 mF 0.1 mF 24.9 W 6.8 mF 33 pF 24.9 W VCL+ VCL- 0.1 mF 24.9 W 0.1 mF VIN+ VOUT0.1 mF VOCM PD THS7530 0.1 mF VOUT+ VIN24.9 W VG- 0.1 mF 33 pF VS- VG+ AGC Detect VREF Typical Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: THS7530 1 THS7530 www.ti.com SLOS405E – DECEMBER 2002 – REVISED AUGUST 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics: Main Amplifier....................5 6.6 Package Thermal Data............................................... 7 6.7 Typical Characteristics................................................ 7 7 Parameter Measurement Information.......................... 11 7.1 Test Circuits...............................................................11 8 Detailed Description......................................................12 8.1 Overview................................................................... 12 8.2 Functional Block Diagram......................................... 12 8.3 Feature Description...................................................12 8.4 Device Functional Modes..........................................13 9 Application and Implementation.................................. 14 9.1 Application Information............................................. 14 9.2 Typical Application.................................................... 16 10 Power Supply Recommendations..............................18 11 Layout........................................................................... 19 11.1 Layout Guidelines................................................... 19 11.2 Layout Examples.....................................................21 12 Device and Documentation Support..........................23 12.1 Device Support....................................................... 23 12.2 Documentation Support.......................................... 23 12.3 Support Resources................................................. 23 12.4 Trademarks............................................................. 23 12.5 Electrostatic Discharge Caution..............................23 12.6 Glossary..................................................................23 13 Mechanical, Packaging, and Orderable Information.................................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (July 2015) to Revision E (August 2020) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 Changes from Revision C (February 2010) to Revision D (July 2015) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 Changes from Revision B (February 2006) to Revision C (February 2010) Page • Corrected polarity indication on input and output in front-page figure................................................................ 1 • Deleted lead temperature specification from Absolute Maximum Ratings table.................................................4 • Corrected Figure 7-2 ........................................................................................................................................11 • Changed Figure 9-2 and Figure 9-3 to correct problem with output polarity indication.................................... 14 • Changed Figure 9-4 and Figure 9-5 to correct problem with output polarity indication.................................... 14 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: THS7530 THS7530 www.ti.com SLOS405E – DECEMBER 2002 – REVISED AUGUST 2020 5 Pin Configuration and Functions VCL+ NC 1 14 NC 2 13 VCL- VIN+ 3 12 VIN- 4 11 VOUT- VG+ 5 10 VOUT+ VG- 6 9 VS+ PD 7 8 VS- VOCM Figure 5-1. PWP Package 14-Pin HTSSOP With PowerPAD™ Top View Pin Functions PIN NAME NC NO. 1 2 I/O DESCRIPTION — No internal connection — Power down, PD = logic low puts the device into low power mode; PD = logic high or open for normal operation PD 7 VCL– 13 I Output negative clamp voltage input VCL+ 14 I Output positive clamp voltage input VG- 6 I Gain setting negative input VG+ 5 I Gain setting positive input VIN– 4 I Inverting amplifier input VIN+ 3 I Noninverting amplifier input VOCM 12 I Output common-mode voltage input VOUT– 11 O Inverted amplifier output VOUT+ 10 O Noninverted amplifier output VS– 8 I Negative amplifier power-supply input VS+ 9 I Positive amplifier power-supply input Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: THS7530 3 THS7530 www.ti.com SLOS405E – DECEMBER 2002 – REVISED AUGUST 2020 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted.(1) MIN MAX UNIT VS+ – VS– Supply voltage 5.5 V VI Input voltage ±VS V IO Output current 65 mA VID Differential input voltage ±4 V Continuous power dissipation TJ (2) 150 Maximum junction temperature for long term Tstg (1) See Section 6.4 Maximum junction temperature stability(2) Storage temperature –65 °C 125 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 Machine model (MM) ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN [VS– to VS+] Supply voltage TA NOM 4.5 Input common mode voltage [VS– to VS+] = 5 V Output common mode voltage [VS– to VS+] = 5 V Operating free-air temperature 5 MAX UNIT 5.5 2.5 V 2.5 –40 V V 85 °C 6.4 Thermal Information THS7530 THERMAL METRIC(1) PWP (HTSSOP) UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 50.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.9 °C/W RθJB Junction-to-board thermal resistance 29 °C/W ψJT Junction-to-top characterization parameter 1.6 °C/W ψJB Junction-to-board characterization parameter 28.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: THS7530 THS7530 www.ti.com SLOS405E – DECEMBER 2002 – REVISED AUGUST 2020 6.5 Electrical Characteristics: Main Amplifier VS+ = 5 V, VS– = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG- = 0 V, VG+ = 1 V (maximum gain), TA = 25°C, AC performance measured using the AC test circuit shown in Figure 7-1 (unless otherwise noted). DC performance is measured using the DC test circuit shown in Figure 7-2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE Small-signal bandwidth All gains, PIN = –45 dBm Slew rate(1) 1-VPP Step, 25% to 75%, minimum gain 300 MHz 1250 Settling time to 1%(1) 1-VPP Step, minimum gain V/µs Harmonic distortion, 2nd harmonic f = 32 MHz, VO(PP) = 1 V, RL(diff)= 400 Ω –65 dBc Harmonic distortion, 3rd harmonic f = 32 MHz, VO(PP) = 1 V, RL(diff)= 400 Ω –61 dBc Third-order intermodulation distortion PO = –10 dBm each tone, fC= 70 MHz, 200-kHz tone spacing –62 dBc 21 dBm 9 dB 11 Third-order output intercept point fC= 70 MHz, 200-kHz tone spacing Noise figure (with input termination) Source impedance: 50 Ω Total input voltage noise f > 100 kHz 1.1 TA = 25°C 20 ns nV/√ Hz DC PERFORMANCE—INPUTS Input bias current TA = –40°C to +85°C 40 Input bias current offset Minimum input voltage Maximum input voltage Common-mode rejection ratio 39