THS788PFD

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 THS788 Quad-Channel Time Measurement Unit (TMU) 1 Features 3 Description • • • • • • The THS788 device is a four-channel timing measurement unit (TMU) that incorporates a time-todigital converter (TDC) architecture for fast and accurate measurements. The TMU can provide 8 ps of single-shot accuracy. The TDC has a 13-ps resolution (LSB), which is derived from an external master clock of 200 MHz. The TDC uses fast LVDScompatible interfaces for all of its event inputs and serial result outputs, which allows for fast and reliable data transfer. Each channel can process timestamps at a maximum speed of 200 MSPS. 1 • • • • • • Four Event Channels + Sync Channel Single-Shot Accuracy: 8 ps, One Sigma Precision: 13 ps Result Interface Range: 0 s to 7 s Event Input Rate: 200 MHz Programmable Serial-Result Interface Speed: 75 MHz to 300 MHz High-Speed Serial Host-Processor Bus Interface: 50 MHz High-Speed LVDS-Compatible Serial-Result Bus per Channel Programmable Serial-Result Bus Length Temperature Sensor Single 3.3-V Supply Power: 675 mW per Channel, 18 Bits, 300 MHz, Four Channels The THS788 device has a wide range of programmability that makes it flexible in different applications. The serial-result interface has programmable data length, frequency, and data-rate mode (DDR and normal). The event channels can be programmed to take timestamps on rising edges or falling edges. The TMU has a mode for event management, in which the user can program wait times before measurements. This programming is achieved through a 50-MHz LVCMOS interface. 2 Applications • • • • • • • • The THS788 device is available in an HTQFP-100 package with a heat slug on top for easy heat-sink access. The device is built using TI's RF SiGe process technology, which allows for maximum timing accuracy with low power. Automatic Test Equipment Benchtop Time-Measurement Equipment Radar and Sonar Medical Imaging Mass Spectroscopy Nuclear and Particle Physics Laser Distance Measurement Ultrasonic Flow Measurement Device Information(1) PART NUMBER THS788 PACKAGE HTQFP (100) BODY SIZE (NOM) 14.00 mm × 14.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic SYNC EVENT T1 T2 T3 T1 - 0000 1100 T2 - 0011 1010 T3 - 1110 0010 T0429-01 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 5 5 5 5 6 7 7 7 8 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Host Serial Interface DC Characteristics .................. Host Serial Interface AC Characteristics................... Power Consumption.................................................. Typical Characteristics ............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ......................................... 9 Feature Description................................................. 10 Device Functional Modes ....................................... 11 Programming .......................................................... 17 Register Maps ........................................................ 22 Application and Implementation ........................ 29 9.1 Application Information............................................ 29 9.2 Typical Application ................................................. 30 10 Power Supply Recommendations ..................... 37 11 Layout................................................................... 38 11.1 Layout Guidelines ................................................. 38 11.2 Layout Example .................................................... 38 11.3 Thermal Considerations ........................................ 39 12 Device and Documentation Support ................. 40 12.1 Trademarks ........................................................... 40 12.2 Electrostatic Discharge Caution ............................ 40 12.3 Glossary ................................................................ 40 13 Mechanical, Packaging, and Orderable Information ........................................................... 40 5 Revision History Changes from Revision C (January 2015) to Revision D Page • Updated Features to remove "800 ps" from single-shot accuracy ......................................................................................... 1 • Updated measurement accuracy after calibration, mean values to –8 and 8 ps and updated single-event accuracy, one sigma parameter to 8 ps in Electrical Characteristics .................................................................................................... 6 Changes from Revision B (June 2011) to Revision C • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 6 Pin Configuration and Functions GND RstrobeA RstrobeA RdataA RdataA VCC NC 82 81 80 79 78 77 76 GND VCC 85 84 GND 86 83 GND VCC 87 GND VCC 90 89 Reserved 91 88 GND Reserved 92 GND RstrobeC 95 VCC RstrobeC 96 93 RdataC 97 94 VCC RdataC 98 NC 99 100 PFD Package 100-Pin HTQFP (Top View) GND 1 75 GND GND 2 74 GND NC 3 73 NC NC 4 72 NC NC 5 71 NC NC 6 70 NC VCC 7 69 VCC EventC 8 68 EventA NC 9 67 NC EventC 10 66 EventA GND 11 65 GND GND 12 64 GND 63 EventB THS788 EventD 13 NC 14 62 NC EventD 15 61 EventB VCC 16 60 VCC NC 17 59 NC NC 18 58 VCC 47 49 50 RdataB NC 46 RstrobeB 48 45 RCLK RdataB 44 RCLK RstrobeB 42 43 Hstrobe VCC 41 VCC GND 39 40 GND 37 38 VCC 36 VCC GND 34 35 GND Reset HCLK TEMP 51 33 52 25 Hdata 24 GND 32 Reserved GND OT ALARM 31 53 VCC 23 29 NC Reserved 30 GND 54 RstrobeD 55 22 RstrobeD 21 VCC 28 GND RdataD SYNC 27 SYNC 56 RdataD 57 20 26 19 NC MCLK MCLK P0011-03 NOTE: Pin 1 indicator is symbolized with a white dot, and is located near pin 1 corner. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 3 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Pin Functions PIN NAME TYPE NO. DESCRIPTION EventA 68 LVDS-compatible input Positive event input for channel A EventA 66 LVDS-compatible input Negative event input for channel A EventB 61 LVDS-compatible input Positive event input for channel B EventB 63 LVDS-compatible input Negative event input for channel B EventC 8 LVDS-compatible input Positive event input for channel C EventC 10 LVDS-compatible input Negative event input for channel C EventD 15 LVDS-compatible input Positive event input for channel D EventD 13 LVDS-compatible input Negative event input for channel D 1, 2, 11, 12, 21, 25, 32, 35, 37, 39, 42, 55, 64, 65, 74, 75, 82, 84, 85, Ground 87, 89, 92, 94 GND Chip ground HCLK 34 LVCMOS input Host serial-interface clock Hdata 33 LVCMOS I/O Host serial-interface data I/O Hstrobe 41 LVCMOS input Host serial-interface chip select MCLK 19 LVDS-compatible input Positive master-clock input MCLK 20 LVDS-compatible input Negative master-clock input No connect Physically not connected to silicon 3–6, 9, 14, 17, 18, 26, 50, 54, 59, 62, 67, 70–73, 76, 100 NC OT_ALARM 53 Open-drain output Overtemperature alarm RCLK 45 LVDS-compatible output Positive result-interface clock RCLK 44 LVDS-compatible output Negative result-interface clock RdataA 78 LVDS-compatible output Positive result-data output for channel A RdataA 79 LVDS-compatible output Negative result-data output for channel A RdataB 49 LVDS-compatible output Positive result-data output for channel B RdataB 48 LVDS-compatible output Negative result-data output for channel B RdataC 98 LVDS-compatible output Positive result-data output for channel C RdataC 97 LVDS-compatible output Negative result-data output for channel C RdataD 27 LVDS-compatible output Positive result-data output for channel D RdataD 28 LVDS-compatible output Negative result-data output for channel D 23, 24, 90, 91 Engineering or test pins Connect to VCC Reserved Reset 51 LVCMOS input Chip reset, active-low RstrobeA 80 LVDS-compatible output Positive strobe signal for channel A RstrobeA 81 LVDS-compatible output Negative strobe signal for channel A RstrobeB 47 LVDS-compatible output Positive strobe signal for channel B RstrobeB 46 LVDS-compatible output Negative strobe signal for channel B RstrobeC 96 LVDS-compatible output Positive strobe signal for channel C RstrobeC 95 LVDS-compatible output Negative strobe signal for channel C RstrobeD 29 LVDS-compatible output Positive strobe signal for channel D RstrobeD 30 LVDS-compatible output Negative strobe signal for channel D SYNC 57 LVDS-compatible input Positive input for sync channel SYNC 56 LVDS-compatible input Negative input for sync channel TEMP 52 Analog output Die temperature 7, 16, 22, 31, 36, 38, 40, 43, 58, 60, 69, 77, 83, 86, 88, 93, 99 Power supply Positive supply, nominal 3.3 V VCC 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted) MIN MAX UNIT 4 V –0.3 VCC + 0.3 V –0.3 VCC + 0.3 V VCC Analog I/O to GND (1) Digital I/O to GND TJ Maximum junction temperature (2) 150 °C Tstg Storage temperature 150 °C (1) (2) LVDS outputs are not short-circuit-proof to GND. The THS788 device has an automatic power shutdown at 140°C, typical. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN VCC Supply voltage TJ Junction temperature NOM 3.135 0 MAX UNIT 3.465 V 105 MCLOCK frequency °C 200 MHz 7.4 Thermal Information THS788 THERMAL METRIC (1) PFD (HTQFP) UNIT 100 PINS 27.2 (60.2 without heat sink) RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 0.6 RθJB Junction-to-board thermal resistance 6.8 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 6.8 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 5 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 7.5 Electrical Characteristics Typical conditions are at TJ = 55°C and VCC = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TDC CHARACTERISTICS Time-measurement precision (LSB) 13.02 Measurement accuracy after calibration, mean –8 Single-event accuracy, one sigma ps 8 8 Time-measurement temperature coefficient 0.1 Time-measurement voltage coefficient ±30 Event input rate ps ps/°C ps/V 200 Minimum event pulse duration ps MHz With preconditioning 2.5 ns Without preconditioning 250 ps 250 ps Minimum event pulse duration Turnon time (ready to take timestamp) 250 μs MASTER CLOCK CHARACTERISTICS Frequency 200 Duty cycle 0.4 MHz 0.6 Jitter 3 ps rms HIGH-SPEED LVDS INPUTS: MCLK, EVENT, SYNC Differential input voltage 100-Ω termination, line-to-line 200 Common-mode voltage 350 500 1.25 Peak voltage, either input 0.6 Input capacitance mV V 1.7 1 V pF HIGH-SPEED LVDS OUTPUTS: Rdata, Rstrobe, RCLK Differential output voltage 100-Ω termination, line-to-line Common-mode voltage Rise time/fall time 250 325 400 1.125 1.28 1.375 20%/80% Output resistance mV V 250 ps 40 Ω 1.69 V TEMPERATURE SENSOR DC CHARACTERISTICS Output voltage TJ = 65°C Output voltage temperature slope 5 Max capacitive load mV/°C 30 pF Max resistive load 10 kΩ OVERTEMPERATURE ALARM DC CHARACTERISTICS Trip point Active-low pulldown Leakage current Temperature < trip point Output voltage, low Isink = 1 ma 141 °C 1 μA 0.2 V OUTPUT INTERFACE TIMING RCLK duty cycle Rdata/Rstrobe to RCLK setup time Rdata/Rstrobe to RCLK hold time 45% 300 MHz 1.4 150 MHz 3.1 75 MHz 6.4 300 MHz 1.5 150 MHz 3.2 75 MHz 6.5 50% 55% ns ns OPERATING PARAMETERS Coarse counter range 18 Coarse counter max time range 14.31 Result-interface clock 6 34 75 Submit Documentation Feedback 300 bit s MHz Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Electrical Characteristics (continued) Typical conditions are at TJ = 55°C and VCC = 3.3 V. PARAMETER TEST CONDITIONS MIN Result-interface transfer format Result-interface time range TYP MAX UNIT 16 40 bit –7.158 7.158 s 7.6 Host Serial Interface DC Characteristics over operating junction temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 0.7 × VCC VCC + 0.5 V VIL Low-level input voltage GND – 0.3 0.3 × VCC V VOH High-level output voltage VCC – 0.5 VCC + 0.3 V VOL Low-level output voltage 0 0.4 V Ilkg Leakage current 1 µA 7.7 Host Serial Interface AC Characteristics over operating junction temperature range (unless otherwise noted) MAX UNIT HCLK frequency PARAMETER TEST CONDITIONS 50 MHz Rise and fall times 3.5 ns HCLK duty cycle MIN 40% Hstrobe high period between two consecutive transactions TYP 50% 60% 40 ns Hstrobe low to HCLK high setup 5 ns HCLK high to Hstrobe high hold time 5 ns Hdata in to HCLK high setup 5 ns Hdata in to HCLK high hold time 5 ns HCLK falling edge to Hdata out (L or H) CL = 20 pF 3.25 ns HCLK falling edge to Hdata out (H or L) CL = 20 pF 3.25 ns 7.8 Power Consumption Typical conditions are at 55°C junction temperature, VCC = 3.3 V CONDITION One channel plus sync, counter length = 18 bits, output interface speed = 75 MHz As above with an additional channel Output interface speed Counter length TYP mA mA 300 MHz add 25 27 bits add 60 34 bits add 105 34 bits UNIT 420 add 10 27 bits MAX add 125 150 MHz 18 bits Four-channel current CURRENT mA mA 75 MHz 795 1075 150 MHz 805 1090 300 MHz 820 1101 75 MHz 855 1150 150 MHz 865 1165 300 MHz 880 1176 75 MHz 900 1210 150 MHz 910 1225 300 MHz 925 1236 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 mA 7 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 7.9 Typical Characteristics 9 920 Supply Current (mA) Sigma (ps) 900 7 6 5 4 3 880 27-bit Counter 860 840 820 18-bit Counter 800 780 0 1 2 3 4 Sync to Event Delay (ns) 5 6 760 8 Figure 1. Typical Per Channel Sigmas vs 5-ns (200-MHz) Window 8 34-bit Counter 75 MHz 150 MHz 300 MHz 8 16 24 32 40 8 16 24 32 40 Rdata Size 8 16 24 32 40 D001 Figure 2. Four-Channel Supply Current vs Rdata, Counter, and Rclock Functional Modes Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 8 Detailed Description 8.1 Overview The THS788 TMU includes four measurement channels plus a synchronization channel optimized to make highaccuracy time-interval measurements. The following is a brief description of the various circuit blocks and how they interact to make and process the time measurements. 8.2 Functional Block Diagram PLL RdataA RdataB DLL MCLK (Fixed) RdataC Sync Input RdataD RCLK Serial Result Data RstrobeA EventA Time Stamp Logic Event Logic EventB RstrobeB EventC RstrobeC EventD RstrobeD Reset Control Registers Hdata Host Interface Output (Voltage) TEMP OT_ALARM HCLK Serial Host Processor Interface Hstrobe Temp Sensor B0347-01 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 9 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 8.3 Feature Description 8.3.1 Counter, Latches, Clock Multiplier The center of the TMU is a master synchronous counter which counts continuously at a rate of 1.2 GHz. This is the master timing generator for the whole TMU and defines the basic timing interval of 833 ps, which is further subdivided with Interpolator circuitry. The output bits of the counter are connected to five sets of latches, which can latch and hold the counter state on command from each of the channels. In this way, when an event occurs, the counter time is recorded in the particular channel’s latches. The latch output is converted to CMOS levels and passed to the respective channel’s FIFO buffer, which is 15 samples deep. The counter 1.2-GHz clock is derived from the MCLK input to the TMU at 200 MHz. This MCLK input is critical to the accuracy of the TMU, and any error in frequency is reflected as errors in time measurement. Likewise, jitter propagates to the counter and other circuits and adds noise to the measurement accuracy. The 200-MHz clock is the input to a clock multiplier. The clock multiplier uses delay-lock loop (DLL) techniques and combinatorial logic to construct a six-times clock from the reference input. This 1.2-GHz clock is passed to a high-power clock buffer, which drives all the circuitry in the master counter and many other circuits in the TMU. 8.3.2 Channels, Interpolator There are four event channels and one sync channel. The event channels are identical, and the sync channel contains most of the event channel circuitry, but without a FIFO. An input pulse to the sync channel serves as the reference time zero for the TMU. An event input to a channel is compared to the sync time reference, and the time delay is calculated as the time difference modified by a calibration value. An event input follows the following signal path: the event input edge sets a fast latch (hit latch). The output of the latch is current-buffered and applied to the interpolator. The interpolator uses DLL techniques to subdivide the counter interval of 833 ps into 64 time intervals of 13 ps each. A large array of fast latches triggered by the hit latch captures the state of the 64 time intervals and logically determines 6 bits of timing data based on where the event occurred in the 833ps clock interval. These 6 bits are latched and eventually passed to the FIFO, where they become the LSBs of the time-to-data conversion. A synchronizer circuit is also connected to the 64-latch array and removes the possible timing ambiguity between the 64 latches and the master counter. This takes a few 1.2-GHz clock pulses. When this process is complete, a pulse occurs which captures the master counter bits into the channel latches. A subsequent pulse loads all the bits from the interpolator and the counter into the channel FIFO. While this is happening, the hit latch is being reset, and the channel is prepared to accept another event edge. This process is fast enough to accept and measure event edges as close together as 5 ns. 8.3.3 FIFO Each event channel contains a 15-deep, 40-bit-wide FIFO, which allows for rapid accepting and measurement of event inputs and a user-defined data-output rate of those measurements. 8.3.4 Calibration, ALU, Tag, Shifter The output of the FIFO is controlled by the shifter, which is a free-running parallel-to-serial register. The shifter generates a load pulse, which transfers the data in the FIFO output into an arithmetic logic unit, which does the sync time and calibration time subtractions and then parallel-loads the result into the output serial register. An LVDS output buffer outputs the clock, data, and strobe signals to transfer the time-measurement data to the user. A TAG bit is appended to the leading edge of the data word. Currently the TAG feature is not implemented. The bit will always be 0 representing data. 8.3.5 Serial Interface, Temperature, Overhead The TMU functions and options are controlled and read out by a serial interface built in CMOS logic that can operate up to 50 MB/s. There is one central controller which then drives registers, counters, etc., in each channel. A temperature sensor is located central to the chip and outputs a voltage proportional to the chip temperature. If the chip temperature rises above 141°C, the TMU powers down and outputs an overtemperature alarm signal. The TMU does not restart without a command through the serial interface. A bias circuit provides a regulated current bias and voltage reference for the TMU. The serial controller sequences some of the bias circuits to account for some acquisition times, and thereby, turns on the TMU. 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 8.4 Device Functional Modes 8.4.1 Serial-Results Interface The TMU captures time-stamp results and sends them to external logic using an LVDS serial-results port. The serial-results port consists of a clock signal (RCLK), four strobe signals (Rstrobex) and four data signals (Rdatax). The Rstrobex signal indicates that a time-stamp data transfer is about to begin for the corresponding channel. The serial-result interface can be programmed to have a variable data-length format. Three register bits (Rlength0, Rlength1, and Rlength2), are used to program the required data transfer formats. The default length of the data field is 40 bits, and it is in 2s-complement format. Table 1 defines the various data formats. Table 1. Result Transfer Format and Time Range RESULT TRANSFER FORMAT TIME RANGE Rlength2 Rlength1 Rlength0 8 bits –1.653 ns to 1.667 ns 0 0 0 16 bits –426.626 ns to 426.639 ns 0 0 1 24 bits –109.22 µs to 109.22 μs 0 1 0 32 bits –27.96 ms to 27.96 ms 0 1 1 40 bits –7.158 s to 7.158 s 1 0 0 Table 1 refers to the 2s-complement format. Therefore, the 8-bit result represents a number between –127 and 128. 8.4.2 Result-Interface Clock The result-interface clock (RCLK) is generated internally and runs at a maximum frequency of 300 MHz. RCLK is programmable and may be programmed using two register bits (RCLK_sel0 and RCLK_sel1) according to the following table. 8.4.3 DDR Mode The result interface may be operated using one-half the clock frequency while keeping the data bit rate unchanged. In this mode, data is clocked out of the device using both edges of RCLK. A register bit (DDR_EN) is used to enable DDR mode. Table 2. Result-Interface Clock RCLK FREQUENCY (MHz) NORMAL MODE RCLK FREQUENCY (MHz) DDR MODE RCLK_sel1 RCLK_sel0 75 (default) 37.5 0 0 150 75 0 1 300 150 1 0 8.4.4 Output Interface Throughput Multiple data-word lengths and bit speeds, combined with a 15-sample-deep FIFO, give exceptional flexibility to output data throughput. The actual throughput is easily calculated, keeping in mind the following: The selected word length includes N – 1 data bits and 1 sign bit, which are sent out last as the MSB. Two bit times do not have meaningful data during the Rstrobe high time. The TAG bit is appended to the data bits and is sent first. Example: for a bit rate of 300 MB/s and 16-bit length, the bit time is 3.33 ns, and the total word length is 16 + 1 + 2 = 19 bit times. Therefore, the throughput is 15.8 M samples/s. This is a constant output sample rate. The TMU can take time measurements at up to 200 MS/s. The 15-deep FIFO buffers these two rates until it is filled, in which case samples are lost. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 11 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 8.4.5 Counter Range The coarse counter has three supported ranges: 18, 27, and 34 bits. The coarse counter applies to the 1.2-GHz clock. Table 3. Counter Range COUNTER RANGE MAX TIME RANGE CNT_RNG1 CNT_RNG0 Reserved X 0 0 18 bit 218.45 µs 0 1 27 bit 111.84 ms 1 0 34 bit 14.31 s 1 1 8.4.5.1 Preconditioning Holdoff Delay Time The preconditioning circuitry controls the ON/OFF state of the event latches. Following a Sync input signal, the TMU checks for a number of conditions before it proceeds with the time-measurement operation. Event input signals are ignored until all arming conditions are met. These conditions are as follows: The hold-off delay is a programmable delay used to inhibit the creation of the next timestamp until the hold-off delay has expired. A 16-bit register is used for the hold-off delay count register. One holdoff delay register exists for each of the four event input channels. The generation of a timestamp reloads the value from the holdoff delay register into a down counting counter. Timestamp generation pauses until hold-off delay counter reaches zero. There are seven ranges for the holdoff delay maximum duration. Three register bits are used to specify the required range. Table 4 defines these ranges. Table 4. Preconditioning Holdoff Delay Time RANGE HOffRng2_x HOffRng1_x HOffRng0_x FULL RANGE (ms) LSB (ns) 1 0 0 0 0.655 10 2 0 0 1 2.621 40 3 0 1 0 10.486 160 4 0 1 1 41.943 640 5 1 0 0 167.772 2560 6 1 0 1 671.089 10,240 7 1 1 X 2,684 40,960 In range 1 each count in the holdoff register delays the next possible timestamps by 10 ns (100-MHz clock period). The maximum delay range for this feature is 2.684 s for each channel. To disable this feature, a register bit (HOffTm_EN_x) is set to 0. 12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 8.4.5.2 Arming Conditions An additional arming condition for each event channel is based on other channels meeting some preprogrammed conditions before it can become fully armed. These conditions are in addition to the individual channel arming conditions. • A given channel does not become fully armed until one, two, or all three of the other channels are armed. A logical AND of one or more channels. • A given channel does not become fully armed until the holdoff delay expires, the arming counter reaches zero, and the logical OR of one or more channels has been active. The following tables define this conditional operation. Table 5. Channel-A Conditional Arming Definition Arm_sel3A Arm_sel2A Arm_sel1A Arm_sel0A OUTCOME 0 0 0 0 ChA is armed if ChB is fully armed. 0 0 0 1 ChA is armed if ChC is fully armed. 0 0 1 0 ChA is armed if ChD is fully armed. 0 0 1 1 ChA is armed if ChB AND ChC are fully armed. 0 1 0 0 ChA is armed if ChB AND ChD are fully armed. 0 1 0 1 ChA is armed if ChC AND ChD are fully armed. 0 1 1 0 ChA is armed if ChB AND ChC AND ChD are fully armed. 0 1 1 1 ChA will be armed if ChB OR ChC is fully armed. 1 0 0 0 ChA will be armed if ChB OR ChD is fully armed. 1 0 0 1 ChA will be armed if ChC OR ChD is fully armed. 1 0 1 0 ChA will be armed if ChB OR ChC OR ChD is fully armed. 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Table 6. Channel-B Conditional Arming Definition Arm_sel3A Arm_sel2A Arm_sel1A Arm_sel0A 0 0 0 0 ChB is armed if ChA is fully armed. OUTCOME 0 0 0 1 ChB is armed if ChC is fully armed. 0 0 1 0 ChB is armed if ChD is fully armed. 0 0 1 1 ChB is armed if ChA AND ChC are fully armed. 0 1 0 0 ChB is armed if ChA AND ChD are fully armed. 0 1 0 1 ChB is armed if ChC AND ChD are fully armed. 0 1 1 0 ChB is armed if ChA AND ChC AND ChD are fully armed. 0 1 1 1 ChB will be armed if ChA OR ChC is fully armed. 1 0 0 0 ChB will be armed if ChA OR ChD is fully armed. 1 0 0 1 ChB will be armed if ChC OR ChD is fully armed. 1 0 1 0 ChB will be armed if ChA OR ChC OR ChD is fully armed. 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 13 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Table 7. Channel-C Conditional Arming Definition Arm_sel3A Arm_sel2A Arm_sel1A Arm_sel0A 0 0 0 0 ChC is armed if ChA is fully armed. OUTCOME 0 0 0 1 ChC is armed if ChB is fully armed. 0 0 1 0 ChC is armed if ChD is fully armed. 0 0 1 1 ChC is armed if ChA AND ChB are fully armed. 0 1 0 0 ChC is armed if ChB AND ChD are fully armed. 0 1 0 1 ChC is armed if ChA AND ChD are fully armed. 0 1 1 0 ChC is armed if ChA AND ChB AND ChD are fully armed. 0 1 1 1 ChC will be armed if ChA OR ChB is fully armed. 1 0 0 0 ChC will be armed if ChB OR ChD is fully armed. 1 0 0 1 ChC will be armed if ChB OR ChD is fully armed. 1 0 1 0 ChC will be armed if ChA OR ChB OR ChD is fully armed. 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Table 8. Channel-D Conditional Arming Definition Arm_sel3A Arm_sel2A Arm_sel1A Arm_sel0A 0 0 0 0 ChD is armed if ChA is fully armed. OUTCOME 0 0 0 1 ChD is armed if ChB is fully armed. 0 0 1 0 ChD is armed if ChC is fully armed. 0 0 1 1 ChD is armed if ChA AND ChB are fully armed. 0 1 0 0 ChD is armed if ChA AND ChC are fully armed. 0 1 0 1 ChD is armed if ChB AND ChC are fully armed. 0 1 1 0 ChD is armed if ChA AND ChB AND ChC are fully armed. 0 1 1 1 ChD will be armed if ChA OR ChB is fully armed. 1 0 0 0 ChD will be armed if ChB OR ChC is fully armed. 1 0 0 1 ChD will be armed if ChB OR ChC is fully armed. 1 0 1 0 ChD will be armed if ChA OR ChB OR ChC is fully armed. 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved NOTE When programming individual-channel arming conditions, it is important to avoid conditions where dependency would cause a lockup situation. 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 8.4.6 Resister Map Descriptions for All Channels and Central Register Table 9. Control and Status Register Descriptions For All Channels (X) Register Bit 0 1 00h 20h 40h 60h 2 7 Name Function LogicState Description Enable or disable channel X by powering down the channel. Time to enable a channel is 200 μs. 0 Channel is disabled 1 Channel is enabled ChX_IP_EN Enables or disables the input of channel X. Events are prevented from entering a channel. 0 Input is disabled 1 Input is enabled Pol_X Defines the polarity of the event inputX for the upcoming timestamp generation. 0 Positive edge 1 Negative edge 0 Holdoff range value 1 Holdoff range value 0 Holdoff range value 1 Holdoff range value 0 Holdoff range value 1 Hold-off range value En_ChX HOffRng0_X Defines holdoff range for event input X. 8 HOffRng1_X Defines holdoff range for event input X. 9 HOffRng2_X Defines holdoff range for event input X. Table 10. Control and Status Register Descriptions for All Channels (X) Register Bit 0 1 01h 21h 41h 61h 2 Reserved Arm_sel0X Arm_sel1X Function Reserved Define arming conditions for channel X. Define arming conditions for channel X. Arm_sel2X Define arming conditions for channel X. 4 Arm_sel3X Define arming conditions for channel X. Armg_Con_En_X Logic State Description x 3 5 04h 24h 44h 64h Name Enables or disables the arming conditions for channel X. 0 Arming value 1 Arming value 0 Arming value 1 Arming value 0 Arming value 1 Arming value 0 Arming value 1 Arming value 0 Arming cond. disabled 1 Arming cond. enabled 0 DLL locked 1 DLL not locked 0 DLL_Lock_X Indicates the DLL lock status for channel X. 2 Reserved Reserved x 3 FIFO_Full_X Indicates that the FIFO is full. Timestamps arriving while FIFO is full are lost. 0 FIFO not full 1 FIFO full 0 FIFO not empty 1 FIFO empty 4 FIFO_Empty_X Indicates that the FIFO is empty. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 15 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Table 11. Central Control and Status Registers Description Register Bit 0 1 2 RESET DDR_En Reset the device. Device is fully operational after 250 μs. It enables DDR mode allowing the result interface to output data on both edges. It connects channels A and B inputs together. 4 Connect_CD It connects channels C and D inputs together. 7 Normal mode 1 DDR Mode 0 Inputs not connected 1 Inputs connected 0 Inputs not connected 1 Inputs connected Length value Length value Rlength1 Length value 1 Length value Define the result data length being used for the timestamps. 0 Length value 1 Length value 0 Frequency value 1 Frequency value 0 Frequency value 1 Frequency value 0 Disabled 1 Enabled Rlength2 OT_En RST_OT_ALM SYNC_TS_Pol Enables or disables the overtemperature alarm circuits. 1 Reset alarm state 0 Positive edge 1 Negative edge 0 Sync disabled 1 Sync enabled 0 Powered up 1 Powered down 0 Range value 1 Range value 0 Range value 1 Range value It disables the RCLK digital clks internal during timestamp process. Allows for only 16 timestamps. 0 Normal mode 1 Quiet mode Device is not ready Defines the polarity of the Sync input for the upcoming timestamp generation. 13 SYNC_IP_ENI Enables or disables the sync channel 14 PWR_DN Powers down the device CNT_Rng0 CNT_Rng1 Quiet_Mod 0 Resets the temperature alarm. Defines the coarse counter range Defines the coarse counter range 0 TMU_Ready Indicates that the internal clks, coarse counter and Sync channel are operational. 0 1 Device is ready 1 OT_ALM Over temperature alarm. Indicates that the junction temperature is 140°C. 0 No alarm 1 Alarm is enabled 0 DLL is locked 1 DLL is not locked 0 DLL is locked 1 DLL is not locked 82h 2 3 16 Reset 0 0 Define RCLK frequency. 3 1 1 RCLK_sel1 2 Enabled 0 Define the result data length being used for the timestamps. 9 1 1 Define the result data length being used for the timestamps. Define RCLK frequency. 12 Disabled Rlength0 RCLK_sel0 11 Description 0 0 8 10 Logic State Enables or disables factory test routines. Connect_AB 6 81h TEST_En Function 3 5 80h Name DLL_Lock_Sync DLL_Lock_1G2 Indicates the Sync channel DLL lock status. Indicates the lock status of the 1.2-GHz internal clock. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 8.5 Programming 8.5.1 Host Processor Bus Interface The THS788 device includes a high-speed serial interface to a host processor. The host interface is used for writing or reading registers that reside in the TMU chip. These registers allow configuration of the device functions. All registers are capable of both read and write operations unless otherwise stated. 8.5.1.1 Serial Interface The TMU serial interface operates at speeds of up to 50 MHz. Register addresses are 8 bits long. Data words are 16 bits wide, enabling more-efficient interface transactions. The serial bus implementation uses three LVCMOS signals: HCLK, Hstrobe, and Hdata. The HCLK and Hstrobe signals are inputs only, and the Hdata signal is bidirectional. The HCLK signal is not required to run continuously. Thus, the host processor may disable the clock by setting it to a low state after the completion of any required register accesses. When data is transferred into the device, Hdata is configured as an input bus, and data is latched on a rising edge of HCLK. When data is transferred out of the part, Hdata is configured as an output bus, and data is updated on the falling edge of HCLK. Hstrobe is the control signal that identifies the beginning of a host bus transaction. Hstrobe must remain low for the duration of the transaction, and must go high for at least two clock cycles before another transaction can begin. 8.5.1.2 Read vs Write Cycle The first Hdata bit latched by HCLK in a transaction identifies the transaction type. First Hdata bit = 1 for read; data flows out of the chip. First Hdata bit = 0 for write; data flows into the chip. 8.5.1.3 Parallel (Broadcast) Write Parallel write is a means of allowing identical data to be transferred to more than one channel in one transaction. The second Hdata bit of a transaction indicates whether a parallel write occurs. Second Hdata bit = 0; data goes to the selected channel. Second Hdata bit = 1; data goes to all four channels. 8.5.1.4 Address After the R/W bit and the parallel write bit, the following 8 bits on the Hdata line contain the source address of the data word for a read cycle or the destination address of the data word for a write cycle. Address bits are shifted in MSB first, LSB last. Third HCLK – Address Bit 7 (MSB) Tenth HCLK – Address Bit 0 (LSB) 8.5.1.5 Data The data stream is 16 bits long, and it is loaded or read back MSB first, LSB last. The timing for read and write cycles is different, as the drivers on Hdata alternate between going into high-impedance and driving the line. 8.5.1.6 Reset Reset is an external hardware signal that places all internal registers and control lines into their default states. The THS788 device resets after a power-up sequence (POR). Hardware reset is an LVCMOS active-low signal and is required to stay low for approximately 100 ns. Reset places the TMU in a predetermined idle state at power on, and anytime the system software initializes the system hardware. In the idle state, the TMU ignores state changes on the Event inputs and never creates timestamps. The TMU is capable of switching within 250 μs from the idle state to a state that creates accurate timestamps. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 17 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Programming (continued) 8.5.1.7 Chip ID Address (83h) is a read-only register that identifies the product and the die revision. The 16-bit register is divided into two 8-bit sections. The LSB represents the revision history and the MSB represents the last two digits of THS788 device (i.e., 80). The first revision (1.0) is as follows: 1000 0000 0001.0000 8.5.1.8 Read Operations Reading the THS788 device registers via the host interface requires the following sequence: The host controller initiates a read cycle by setting the host strobe signal, Hstrobe, to a low state. The serial Hdata sequence starts with a high R/W bit, followed by (either 1 or 0) for parallel-write bit and 8 bits of address, with most-significant bit (A7) first. The host controller should put the Hdata signal in the high-impedance state beginning at the falling edge of HCLK pulse 10. The THS788 device allows one clock cycle, (r0) for the host to reverse the data-channel direction and begins driving the Hdata line on the falling edge of HCLK pulse 11. The data is read beginning with the most-significant bit (D15) and ending with the least-significant bit (D0). The host must drive Hstrobe to a high state for a minimum of two HCLK periods beginning at the falling edge of HCLK pulse 27 to indicate the completion of the read cycle. Figure 3 shows the timing diagram of the read operation. Hstrobe 1 2 R/W 1 X 3 4 5 6 7 8 9 10 11 A7 A6 A5 A4 A3 A2 A1 A0 r0 12 13 14 15 D15 D14 D13 D12 16 17 D11 D10 18 27 28 29 X X HCLK Hdata Register Address (A7:A0) D0 D9 R/W Data Out Hdata becomes output Driving the line Data transfer protocol for Read operations T0427-01 Figure 3. Read Operation 8.5.1.9 Write Operations Writing into the THS788 device registers via the host interface requires the following sequence: After the Hstrobe line is pulled low (start condition), the R/W bit is set low, followed by a 0 for the parallel-write bit (single-register write), then the memory address (A7–A0) followed by the data (D15:D0) to be programmed. The next clock cycle (w) is required to allow data to be latched and stored at the destination address (or addresses in the case of a parallel write), followed by at least two dummy clock cycles during which the Hstrobe is high, indicating the completion of the write cycle. Figure 4 and Figure 4 show timing diagrams of write operations. Hstrobe st 1 2 3 4 A7 A6 5 6 7 8 9 10 11 12 13 14 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 24 25 26 27 28 29 1 clock for next transaction = 30 HCLK Hdata R/W 1 0 Register Address (A7:A0) D2 D1 D0 w0 X X R/W Data In Data transfer protocol for single write operation T0425-01 Figure 4. Write Operation 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Programming (continued) 8.5.1.10 Write Operations to Multiple Destinations This is similar to the single-write operation except the parallel-load bit is set to 1. Hstrobe st 1 2 3 4 A7 A6 5 6 7 8 9 10 11 12 13 14 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 24 25 26 27 28 29 1 clock for next transaction = 30 HCLK Hdata R/W 1 1 Register Address (A7:A0) D2 D1 D0 w0 X X R/W Data In Data transfer protocol for parallel write operation T0426-01 Figure 5. Write Operations to Multiple Destinations 8.5.2 Serial-Results Interface and ALU 8.5.2.1 Event Latches Each event channel and the sync channel include two event latches whose inputs are both connected to the LVDS input-buffer output. One latch is the time-measurement signal path and connects to the interpolator and synchronizer. The other latch connects to the preconditioning circuitry. A selectable rising or falling edge of an event pulse sets the latch. the latch remains set until the interpolator has finished processing the event, at which time the interpolator resets the latch. The latch, however, does not accept another event pulse until the event input returns to its initial state and remains for the initial event-pulse duration. Any event transitions which occur before the interpolator has completed processing the previous event are ignored. For example, assume that rising edge is selected. Two rising edges can occur as quickly as 5 ns apart. The falling edge can occur anywhere from 250 ps after the rising edge to 250 ps before the next rising edge. Any other edges or glitches are ignored. In addition to the rising/falling-edge selection, the event latch includes the gating function whereby the preconditioning logic controls whether the TMU accepts and processes an event input. The second event latch operates similarly to the main signal-path latch with the following exceptions: The latch is followed by and ECLto-CMOS converter , because all the preconditioning logic is CMOS instead of the fast ECL circuitry in the measurement chain. The preconditioning logic rather than the interpolator resets this latch, and the timing of the reset pulse is slightly faster than the interpolator. 8.5.2.2 FIFO Timestamps are written to a FIFO at high speed and read for further processing at a lower speed before being sent to the result interface. This FIFO is 15 bits deep and 40 bits wide. There are four FIFOs in THS788 device, one for each channel. There are two status registers (FIFO_Full_x and FIFO_Empty_x), which are set when a FIFO reaches its full capacity and when it is empty, respectively. Timestamps are taken and loaded into the FIFO as events occur. Timestamps are mathematically processed by an arithmetic logic unit (ALU) which calculates the difference between the event and the sync timestamps and factors in the appropriate calibration value from the calibration register. The ALU operates on the data as it is read out of the FIFO and sent out through the serial-results interface. The serial-results interface controls the output of the FIFO. 8.5.2.3 Result-Interface Operation The TMU initiates a read cycle by setting the strobe signal, Rstrobe, to a low state, indicating that the data transfer is about to begin. The serial Rdata sequence starts with a TAG bit, followed by the 40-bit data (R0 to R39). R39 (MSB) is the sign bit. Following the last data bit (R39), the strobe signal (Rstrobe) goes high for two clock cycles, indicating the end of the transaction. The data is clocked out of the TMU on the rising edge of RCLK. The receiving device clocks the data in on the rising edge of RCLK. Figure 6 and Figure 7 show a 40-bit result on the result interface. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 19 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Programming (continued) Rstrobe RCLK Rdata 0 0 0 R0 R1 R2 R3 R4 R5 R34 R35 R36 R37 R38 R39 Result Data Sign bit when programmed TAG TAG = 0, Valid Data 0 0 0 R0 R1 R2 R3 R4 R5 R6 R7 New Cycle Cycle End T0428-01 Figure 6. Result-Interface Operation A Rstrobe RCLK Rdata 0 0 0 R0 R1 R2 R3 R4 R5 R10 R11 R12 R13 R14 R15 Result Data Sign bit when programmed TAG 0 0 0 R0 R1 R2 R3 R4 R5 R6 R7 New Cycle Cycle End T0455-01 Figure 7. Result-Interface Operation B NOTE In the preceding diagrams, only RCLK_P is drawn to indicate the correct edge with respect to data. 8.5.2.4 Serial Results Latency The event stored in the FIFO will be transferred to ALU and subsequently to the free running results data shift register when the shift register enters a load pulse. The load pulse is generated once per ALU/shift register processing cycle. The load pulse will trigger the ALU and transfer result to the parallel to serial shift register for output. The cycle time of the load pulse is dependent upon the depth of the result transfer register and data rate. Because the results parallel to serial register are free running, the load pulse will be asynchronous to the actual event. So, the latency will depend upon where in the current cycle the load pulse occurred relative to the event being captured into the FIFO. The worst case for data to be output from serial bus: Tevent + 5(Rclkcycles) + (Rdatalength + 3) x Rclkcycles + (Rdatalength + 3) × Rclkcycles (1) The best case for data to be output from serial bus: Tevent + 5(Rclkcycles) + (Rdatalength + 3) × Rclkcycles where • • • • Tevent = 5 ns (minimum repeat capture time) 5(Rclkcycles) = number cycles for FIFO to ALU to Shift register Rclkcycles is period of RCLK data = 300 MHz, SDR = 3.33 ns Rdatalength = number of results bits = 40 for THS788 device (2) In the case where RCLK = 300 MHz, with 40-bit serial result: Min Latency = 5 ns + 17 ns + (40 + 3) × 3.33 ns = 165 ns 20 Submit Documentation Feedback (3) Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Programming (continued) Max Latency = 5 ns + 17 ns + (40 + 3) × 3.33 ns + (40 + 3) × 3.33 ns = 308 ns (4) NOTE The THS788 device was intended for sync-event, event, event, sync-event ... processing. However, some applications desire the use of a sync pulse that is a fixed period. During a sync period, there could be multiple events, or no events. The TMU can be used effectively for this scenario as well. For applications using the THS788 device in this fashion, it is important to consider the uncertainty that is introduced by the load pulse timing. Because the load pulse is free running and asynchronous to any events, the latency will vary based on this timing. Additionally, the load pulse is the mechanism that will cause the ALU to grab the current sync value for the result calculation. If an event is in the FIFO, waiting for the load pulse and a new sync occurs, the ALU will use the new sync value for calculating the result. In this case, the event would precede the sync resulting in a negative result. The system could then offset the result by one sync cycle as the result is negative, indicating that is was captured during a prior sync cycle. 8.5.2.5 TMU Calibration The TMU calibration process is identical to a normal TMU time-stamp measurement. The process involves measuring a known interval and calculating the difference between the measured value and the actual value. The result is then stored into calibration registers inside the TMU. The TMU takes the stored calibration values and corrects the subsequent time-stamp measurements. There are four calibration registers for each channel. These are identified as follows: • A calibration register for positive sync edge and positive event edge • A calibration register for positive sync edge and negative event edge • A calibration register for negative sync edge and positive event edge • A calibration register for negative sync edge and negative event edge Calibration due to temperature changes following the initial system calibration may be required if temperature variations are significant. 8.5.2.6 Temperature Sensor A temperature sensor has been located centrally in the THS788 device for monitoring the die temperature. There are two monitor outputs for this feature. An analog voltage proportional to the die temperature is presented at the TEMP pin. Also, an overtemperature alarm output is available at the OT_ALARM pin. The overtemperature alarm (OT_ALARM) is an open-drain output that is activated when the die temperature reaches 141°C. The overtemperature alarm sets a register bit (OT_ALM) in the central register and may be accessed through the serial interface. The overtemperature alarm initiates an automatic power down to prevent overheating of the device. The digital blocks remain functional when in automatic power down. Following a power down, the user is required to reset OT_ALM using the serial interface. A register bit (RST_OT_ALM) is used for this purpose. The temperature-monitoring function and its associated overtemperarture alarm circuit may be disabled by the user, using a register bit (OT_EN). The default for the temperature-monitoring function is enabled. OT_EN = 1: Temperature-monitoring function is enabled. OT_EN = 0: Temperature-monitoring function is disabled. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 21 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 8.6 Register Maps 8.6.1 Register Address Space Table 12. Channel-A Registers Address (Hex) Register 00h–01h Control register 02h–03h Not used NA 04h Status registers RO 05h Not used NA 06h Holdoff delay time register R/W 07h Not used R/W 08h Not used R/W 09h Not used R/W 0Ah Not used R/W 0Bh Not used R/W 0Ch Positive edge sync and positive edge hit calibration register, 16 bits R/W 0Dh Positive edge sync and negative edge hit calibration register, 16 bits R/W 0Eh Negative edge sync and positive edge hit calibration register, 16 bits R/W 0Fh Negative edge sync and negative edge hit calibration register, 16 bits R/W 10h–12h Timestamp register, 40 bits 13h–1Fh Not used R/W R NA Table 13. Channel-B Registers Address (Hex) Register 20h–21h Control register 22h–23h Not used NA 24h Status registers RO 25h Not used NA 26h Hold_off delay time register R/W 27h Not used R/W 28h Not used R/W 29h Not used R/W 2Ah Not used R/W 2Bh Not used R/W 2Ch Positive edge sync and positive edge hit calibration register, 16 bits R/W 2Dh Positive edge sync and negative edge hit calibration register, 16 bits R/W 2Eh Negative edge sync and positive edge hit calibration register, 16 bits R/W 2Fh Negative edge sync and negative edge hit calibration register, 16 bits R/W 30h–32h Timestamp register, 40 bits 33h–3Fh Not used 22 R/W R NA Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Table 14. Channel-C Registers Address (Hex) Register 40h–41h Control register 42h–43h Not used NA 44h Status registers RO 45h Not used NA 46h Not used R/W 47h Not used R/W 48h Not used R/W 49h Not used R/W 4Ah Not used R/W 4Bh Not used R/W 4Ch Positive edge sync and positive edge hit calibration register, 16 bits R/W 4Dh Positive edge sync and negative edge hit Calibration register, 16 bits R/W 4Eh Negative edge sync and positive edge hit Calibration register, 16 bits R/W 4Fh Negative edge sync and negative edge hit Calibration register, 16 bits R/W 50h–52h Timestamp register, 40 bits 53h–5Fh Not used R/W R NA Table 15. Channel-D Registers Address (hex) Register 60h-61h Control register 62h-63h Not used NA 64h Status registers RO 65h Not used NA 66h Not used R/W 67h Not used R/W 68h Not used R/W 69h Not used R/W 6Ah Not used R/W 6Bh Not used R/W 6Ch Positive sync edge and positive hit edge, calibration register, 16 bits R/W 6Dh Positive sync edge and negative hit edge, calibration register, 16 bits R/W 6Eh Negative sync edge and positive hit edge, calibration register, 16 bits R/W 6Fh Negative sync edge and negative hit edge, calibration register, 16 bits R/W 71h-73h Timestamp register, 40 bits 74h-7Fh Not used R/W R NA Table 16. Central Registers Address (hex) Register 80h Control register R/W 81h Control register R/W 82h Status register RO 83h Chip ID RO 84h Test key register R/W 85h Test1 R/W 86h Test2 R/W 87h Reserved R/W 88h Reserved R/W Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 23 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 8.6.2 Register Map Detail Table 17. Channel A Submit Documentation Feedback En_ChA D0 DLL_Lock_A D0 D0 0000h 0000h D0 D1 D1 D1 D1 D33 D17 0000h 0000h D0 0000h 0000h D32 D16 ChA_IP_En Arm_sel0_A X D1 X Pol_A Arm_sel1_A X D2 D4 D4 D4 D4 D4 D36 D20 D5 D5 D5 D5 D37 D21 0 D6 0 D6 0 D6 0 D6 0 D7 0 D7 0 D7 0 X D2 X D2 X D2 X D2 X D34 D18 X Arm_sel2_A X FIFO_Full_A X 0000h D3 X X D3 X Default Value X D3 X 0 0000h D3 FIFO_Empty_A X 1 0 D3 X 2 0000h D35 D19 X Arm_sel3_A ArmgCon_En_A X D5 X D6 HOffRng0_A X D7 X D38 D22 12h X D8 Timestamp X D8 10h X D8 Calibration:Neg Sync EdgeNeg Event Edge X D8 0Fh X D8 Calibration:Neg Sync EdgePos Event Edge X D9 0Eh X D9 Calibration:Pos Sync EdgeNeg Event Edge X D9 0Dh X D9 Calibration:Pos Sync EdgePos Event Edge X D9 Reserved 0 D7 X 06h 0Ch 0 D39 D23 X 0 HOffRng1_A Status 3 X D24 04h 4 X D25 X D26 D10 D10 D10 D10 D10 X 5 0 D27 D11 D11 D11 D11 D11 Control 6 0 D28 D12 D12 D12 D12 D12 01h 7 0 D29 D13 D13 D13 D13 D13 X D30 D14 D14 D14 D14 D14 X 8 D31 D15 D15 D15 D15 D15 Control 9 HOffRng2_A 15 14 13 12 11 10 00h 11h 24 Word/Bit HOffTm_En_A Register Name PreCon_En_A Register Address 0000h 0000h Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Table 18. Channel B Word/Bit D0 0000h D0 0000h D0 0000h D0 En_ChB DLL_Lock_B DLL_Lock_B 0000h 0000h D0 ChB_IP_En Pol_B Arm_sel0_B D1 0000h 0000h D32 D16 D8 D8 D8 D8 D9 D9 D9 D9 D1 0 D1 0 D1 0 X D1 0 X D33 D17 0 D5 0 D8 0 D9 0 D5 Timestamp D5 30h D5 Calibration:Neg Sync EdgeNeg Event Edge D37 D21 2Fh D6 Calibration:Neg Sync EdgePos Event Edge D6 2Eh D6 Calibration:Pos Sync EdgeNeg Event Edge D6 2Dh D38 D22 Calibration:Pos Sync EdgePos Event Edge Arm_sel1_B X D2 X D2 X D2 X D2 X D2 X D34 D18 X Arm_sel2_B X FIFO_Full_B X X FIFO_Full_B X Default Value X D3 X D3 X D3 X 0 0000h D3 X 1 0 D3 X 2 0000h D35 D19 X Arm_sel3_B X D4 FIFO_Empty_B FIFO_Empty_B X D4 X D4 ArmgCon_En_B X D4 X D4 X D36 D20 X D5 X D6 HOffRng0_B X D7 2Ch 32h X D7 X 31h X D7 Reserved 0 D7 26h 0 D7 X 0 D39 D23 Status 3 HOffRng1_B 24h 4 X D24 X D25 X 5 0 D26 D10 D10 D10 D10 D10 Control 6 0 D27 D11 D11 D11 D11 D11 21h 7 0 D28 D12 D12 D12 D12 D12 X D29 D13 D13 D13 D13 D13 X D30 D14 D14 D14 D14 D14 Control 8 D31 D15 D15 D15 D15 D15 20h 9 HOffRng2_B 15 14 13 12 11 10 HOffTm_En_B Register Name PreCon_En_B Register Address 0000h 0000h Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 25 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Table 19. Channel C Word/Bit En_ChC DLL_Lock_C D0 0000h 0000h D0 X 0000h D0 X 0000h D0 X 0000h D0 ChC_IP_En X 0000h D32 D16 D4 D4 D4 D4 D8 D8 D8 D8 D9 D9 D9 D9 Submit Documentation Feedback D4 0 D36 D20 0 D5 0 D5 0 D5 0 D5 0 D8 0 D9 0 D37 D21 Timestamp D6 50h D6 Calibration:Neg Sync EdgeNeg Event Edge D6 4Fh D6 Calibration:Neg Sync EdgePos Event Edge D38 D22 4Eh Arm_sel0_C X D1 X D1 X D1 X D1 X D1 X D33 D17 X Pol_C X Arm_sel1_C X 0000h D2 X X D2 FIFO_Empty_C X X D2 X D2 X D2 X D34 D18 X Arm_sel2_C X Default Value FIFO_Full_C X D3 X D3 X D3 X 0 0000h D3 ArmgCon_En_C X 1 0 D3 X 2 0000h D35 D19 X Arm_sel3_C X D5 X D6 HOffRng0_C Calibration:Pos Sync EdgeNeg Event Edge 26 X D7 4Dh 52h X D7 X Calibration:Pos Sync EdgePos Event Edge 51h X D7 Reserved 4Ch 0 D7 46h 0 D7 X 0 D39 D23 Status 3 HOffRng1_C 44h 4 X D24 X D25 X 5 0 D26 D10 D10 D10 D10 D10 Control 6 0 D27 D11 D11 D11 D11 D11 41h 7 0 D28 D12 D12 D12 D12 D12 X D29 D13 D13 D13 D13 D13 X D30 D14 D14 D14 D14 D14 Control 8 D31 D15 D15 D15 D15 D15 40h 9 HOffRng2_C 15 14 13 12 11 10 HOffTm_En_C Register Name PreCon_En_C Register Address 0000h 0000h Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Table 20. Channel D Word/Bit En_ChD DLL_Lock_D D0 0000h 0000h D0 X 0000h D0 X 0000h D0 X 0000h D0 ChD_IP_En X 0000h D32 D16 D4 D4 D4 D8 D8 D8 D8 D9 D9 D9 D9 D4 0 D4 0 D36 D20 0 D5 0 D5 0 D5 0 D8 0 D9 0 D5 Timestamp D37 D21 70h D6 Calibration:Neg Sync EdgeNeg Event Edge D6 6Fh D6 Calibration:Neg Sync EdgePos Event Edge D6 6Eh D38 D22 Calibration:Pos Sync EdgeNeg Event Edge Arm_sel0_D X D1 X D1 X D1 X D1 X D1 X D33 D17 X Pol_D X Arm_sel1_D X 0000h D2 X X D2 FIFO_Empty_D X X D2 X D2 X D2 X D34 D18 X Arm_sel2_D X Default Value FIFO_Full_D X D3 X D3 X D3 X 0 0000h D3 ArmgCon_En_D X 1 0 D3 X 2 0000h D35 D19 X Arm_sel3_D X D5 X D6 HOffRng0_D X D7 6Dh 72h X D7 X Calibration:Pos Sync EdgePos Event Edge 71h X D7 Reserved 6Ch 0 D7 66h 0 D7 X 0 D39 D23 Status 3 HOffRng1_D 64h 4 X D24 X D25 X 5 0 D26 D10 D10 D10 D10 D10 Control 6 0 D27 D11 D11 D11 D11 D11 61h 7 0 D28 D12 D12 D12 D12 D12 X D29 D13 D13 D13 D13 D13 X D30 D14 D14 D14 D14 D14 Control 8 D31 D15 D15 D15 D15 D15 60h 9 HOffRng2_D 15 14 13 12 11 10 HOffTm_En_D Register Name PreCon_En_D Register Address 0000h 0000h Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 27 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Table 21. Central Registers Word/Bit X 82h Status X X X X X X X X X X X X 83h Chip ID ID ID ID ID ID ID ID ID 28 Submit Documentation Feedback Test_En X X 0000h TMU_Ready X 0000h 0000h Rev X Default Value RESET X 0 OT_ALM CNT_Rng0 X 1 8010h Rev X DDR_En X 2 Rev DLL_Lock_Sync CNT_Rng1 X Connect_AB X Quiet_Mod Connect_CD X 3 DLL_Lock_1G2 Rlength0 X Rev Rlength1 Control Rev Rlength2 81h Rev Control Rev 80h RCLK_sel0 4 RCLK_sel1 5 OT_En 6 RST_OT_ALM 7 Sync_TS_Pol 8 Sync_IP_En 9 PWR_DN 15 14 13 12 11 10 RCLK_En Register Name Rev Register Address Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The THS788 device is a high-speed, high-resolution time-measurement unit that measures the difference in time between a signal applied to an event channel and the signal applied to the sync channel. This difference is then transmitted to a result interface in the form of a digital word. Figure 8 shows an example of three time measurements (T1, T2, and T3). SYNC EVENT T1 T2 T3 T1 - 0000 1100 T2 - 0011 1010 T3 - 1110 0010 T0429-01 Figure 8. Time-Measurement Example With 8-Bit Words Triggered by Rising Edges The previous time difference is calculated by an internal ALU that subtracts the timestamps created by the Event signal and the SYNC signal stored in a FIFO. These timestamps are performed by the TDC that is composed by the following: an interpolator, a synchronizer, a programmable (18-, 27-, 34-bit) counter, a 34-bit counter, and a 1.2-GHz clock. It is important to note that the event and sync channels share the same TDC. When a valid edge is applied to the event channel, the TDC uses the value in the counter and stores it in the FIFO. Then the ALU uses the value of the event and the value of the sync, stored in the FIFO already, and subtracts them. After the operation is done, the final value is shifted out to the result interface for retrieval. All the programming to the THS788 device is achieved through an LVCMOS host-serial interface. With this interface, the user has the ability to set up the THS788 device for time measurements. It also provides the user with different modes to retrieve the results. Results are available through an LVDS-compatible high-speed serial interface. Data-word length and speed are programmable to cover a wide range of data rates. Each channel has it own output to maximize data throughput. All of the data ports (RdataA, -B, -C, and -D) are synchronized to a global clock. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 29 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 9.2 Typical Application Time Stamp Processor Sequencer Formatter Timing Logic Error Logic PLL RdataA RdataB DLL MCLK (Fixed) RdataC Sync Input RdataD Serial Result Data RCLK RstrobeA EventA Time Stamp Logic Hold-Off Logic EventB DCL/PPMU RstrobeB EventC RstrobeC EventD DUT RstrobeD Reset Control Registers Output (Voltage) TEMP OT_ALARM Hdata Host Interface HCLK Hstrobe Serial Host Processor Interface Temp Sensor B0387-01 Figure 9. Example of Application Diagram in ATE Environment 30 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 Typical Application (continued) 9.2.1 Design Requirements For this design example, use the parameters listed in Table 22 as the input parameters. Table 22. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Results interface size 40 bit Results time range –7.158 to 7.158 s Rclock 300 MHz DDR mode Off Temperature monitor On Connect CD/Connect AB Off Counter size 34 bit REGISTER WRITE (80h) 0xA680 REGISTER WRITE (81h) 0x0003 9.2.2 Detailed Design Procedures 9.2.2.1 Time Measurement Time measurements in the THS788 device follow the timing of Figure 10. This diagram illustrates that time measurements are valid as long as events do not happen at speeds higher than 200 MHz. If an event happens at less than 5 ns from the previous one, then this event is ignored. The same applies to the SYNC signal. Even though the minimum period is 5 ns, the pulse duration of both Event and SYNC signals can be as low as 200 ps. SYNC 200 ps Min PW Max Freq. 200 MHz EVENT T1 T2 T3 T0430-01 Figure 10. Time-Measurement Example at Maximum Retrigger Rate and Minimum Pulse Duration The TH788 is capable of making time measurements using any combination of rising-falling edge between Event and SYNC. The example in Figure 10 uses rising edges only to trigger the time measurement. Table 23 describes what registers bits must be programmed to achieve the desired combination. Registers to be programmed are 00h, 20h, 40h, and 60h for event channels and 80h for the sync channel. The examples in Figure 11 illustrate the other three combinations. All of the channels can be programmed individually with respect to the sync channel. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 31 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com Table 23. Trigger Polarity Programmability REGISTER BITS TRIGGER POLARITY FROM SYNC TO EVENT SYNC_TS_Pol Pol_X 0 0 Pos to Pos 0 1 Pos to Neg 1 0 Neg to Pos 1 1 Neg to Neg SYNC SYNC SYNC_TS_Pol = 1 Pol_X = 0 SYNC_TS_Pol = 0 Pol_X = 1 EVENT EVENT T1 T3 T2 T1 SYNC SYNC_TS_Pol = 1 Pol_X = 1 EVENT T1 T2 T0431-01 Figure 11. Time-Measurement Examples With Different Edge Polarities 9.2.2.2 Output Clock to Data/Strobe Phasing The output of each channel is an Rdata and Rstrobe signal. The RCLK for all the channels is a common output. Operating at 300 MHz, these signals must be handled carefully. Particularly important are the termination and phase alignment of the signals at the receiving circuitry. Termination has been discussed previously. Phase alignment is now discussed: The two outputs from each channel are clocked out through identical flip-flops with the same internal clock. Data and strobe output edges from a particular channel match well (< 50 pS). The match channel-to-channel is not as good due to the greater wiring distances internal to the TMU. However, the total time difference is below 125 pS. Because the RClock is a common output, the wiring lengths from the four channels must be matched and controlled to achieve good setup and hold times at the input to the receiving circuit. The RClock rising edge is adjusted internal to the TMU to be close to the center of the eye diagram of the data/strobe signals. (The internal clock has a good 50/50 duty cycle. The rising edge clocks out the data/strobe. The falling edge is inverted and used as the RClock after appropriate adjustments for the internal propagation delay times.) The receiving circuitry requirements for setup and hold timing must be carefully examined for the proper timing. Delays may be added to the PCB microstrips to adjust timing. A good rule is 125 ps of delay per inch of microstrip length. 32 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 THS788 www.ti.com SLOS616D – MARCH 2010 – REVISED MARCH 2015 9.2.2.3 Master Clock Input and Clock Multiplier All of the internal timing of the TMU is derived from the 200-MHz master clock. Therefore, its quality is critical to the accurate operation of the TMU. Absolute accuracy of the master clock linearly affects the accuracy of the measurements. This imposes little burden upon the master clock, as accurate oscillators are easy to procure or distribute. However, the jitter of the master clock is also highly critical to the single-event precision of the TMU and should be absolutely minimized (.6 ns). Discussion of the clock multiplier follows: The TMU operates from a master-clock frequency of 1200 MHz, which implies a measurement period of 0.833 ns. The master counter runs from this frequency, and all the other clocks are divided down from this main clock. An interpolator allows finer precision in time measurement, as discussed elsewhere. The clock multiplier is the circuit that takes the 200-MHz master-clock reference and generates from that the high quality 1200-MHz clock. The clock multiplier consists of five major sections: First is the delay-lock loop (DLL), which is a series connection of 12 identical and closely matched variable time-delay circuits. A single control voltage connects to each of the delay elements. The master 200-MHz clock connects to the input of the DLL. Because the period of 200 MHz is 5 ns, if the control voltage is adjusted to make the time delay of the DLL equal to 5 ns, the input and the output of the delay line is exactly phase matched. A phase detector connected to the input and the output of the delay line can sense this condition accurately, and a feedback loop with a lowoffset-error amplifier is included in the clock multiplier to achieve this result. These are the second and third circuit blocks. With 12 equally spaced 200-MHz clock phases, select out six equally spaced 833-ps-wide pulses with AND gates and combine these pulses into a single 1200-MHz clock waveform with a six-input OR gate. The last circuit element is a powerful differential signal buffer to distribute the 1200-MHz clock to the various circuit elements in the TMU. The DLL feedback loop is fairly narrowband, so some time is required to allow the DLL to initialize at start-up (about 100 μs, typical). The DLL is insensitive to the duty cycle of the input 200-MHz clock. Duty cycles of 40/60 to 60/40 are acceptable. What matters most is as little jitter as possible. 9.2.2.4 Temperature Measurement and Alarm Circuit Chip temperature of the TMU is monitored by a temperature sensor located near the center of the chip. A small buffer outputs a voltage proportional to the absolute temperature of the TMU. The buffer drives a load of up to 100 pF typical (50 pF minimum) and open circuit to 10 kΩ to ground resistive. The output voltage slope is 5 mV, typical. Therefore, the output voltage equation is as follows: Output Voltage = (Temperature in °C × 5 mV) + 1.365 V (5) Also included in the TMU is an overtemperature comparator. At approximately 140°C, the alarm goes active, and at approximately 7°C below this temperature, the alarm becomes inactive (hysteresis of 7°C prevents tripping on noise and comparator oscillations). If the alarm goes active, the chip powers down and sets a bit in the serial register. An alarm output pin is provided that is an open-drain output. Connect this output through a pullup resistor to the 3.3-V power supply. The resistor must be at least 3.3 kΩ. This creates a slow-speed, low-voltage CMOS digital output with a logical 1 being the normal operating state and a logical 0 being the overtemperature state. 9.2.2.5 LVDS-Compatible I/Os The Event, SYNC, and master-clock inputs are LVDS-compatible input receivers optimized for high-speed and low-time-distortion operation. The Rdata, Rstrobe, and RCLK outputs are similarly LVDS-compatible output drivers optimized for high-speed/low-distortion operation, driving 50-Ω transmission lines. Typically, LVDS data transmission is thought of in terms of 100-Ω twisted-wire-pair (TWP) transmission lines. TWP is not applicable to printed wiring boards and high-speed operation. Therefore, the THS788 device interfaces were designed to operate most effectively with 50-Ω, single-ended transmission lines. Instead of a current-mode output with its correspondingly high output impedance, a more-nearly impedance-matched voltage-mode output driver is used. This minimizes reflections from mismatched transmission line terminations and the resulting waveform distortion. The input receivers do not include the 100-Ω terminating resistor, which must be connected externally to the THS788 device. This was done to accommodate daisy-chaining the THS788 inputs. Input offset voltage was minimized, and the fail-safe feature in the LVDS standard was eliminated in order to minimize distortion. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: THS788 33 THS788 SLOS616D – MARCH 2010 – REVISED MARCH 2015 www.ti.com 9.2.2.6 LVDS-Compatible Inputs The four event inputs, the sync input and the master-clock input all use the same input interface circuitry. Figure 12 is a simplified schematic diagram of the LVDS-compatible receiver input stage. The input signal is impedance-transformed and level-shifted with a PNP emitter-follower and translated into ECL-like differential signals with a common-emitter amplifier. There is no internal termination resistor and no internal pullup/pulldown resistors. Unused inputs may be tied off by connecting both input terminals to ground. If the input terminals are left floating, they are protected by ESD clamps from damage; however, noise may be injected into the THS788 device and may degrade accuracy. The peak input voltage limits are 0.6 V to 1.7 V. Outside of these limiting voltages, parts of the input circuit may saturate and distort the timing. VCC R R 2.5 nH Bond Wire IN 0.5 pf Package 0.1 pf Bond Pad 0.4 pf VCC 2.5 nH Bond Wire IN 0.5 pf Package 0.1 pf Bond Pad 0.4 pf S0389-01 Figure 12. Simplified Schematic of the LVDS Input Figure 13 shows the typical input connections. The transmission line lengths must be matched from the driver to the THS788 input [