TL331QDBVRQ1

TL331-Q1 www.ti.com SLVS969C – OCTOBER 2009 – REVISED AUGUST 2013 SINGLE DIFFERENTIAL COMPARATOR Check for Samples: TL331-Q1 FEATURES 1 • • • • • • • • • • DBV PACKAGE (TOP VIEW) Qualified for Automotive Applications Single Supply or Dual Supplies Wide Range of Supply Voltage: 2 V to 36 V Low Supply-Current Drain Independent of Supply Voltage: 0.4 mA Typ. Low Input Bias Current: 25 nA Typ. Low Input Offset Voltage: 2 mV Typ. Common-Mode Input Voltage Range Includes Ground Differential Input Voltage Range Equal to Maximum-Rated Supply Voltage: ±36 V Low Output Saturation Voltage Output Compatible With TTL, MOS, and CMOS IN− VCC−/GND IN+ 1 5 VCC 4 OUT 2 3 DESCRIPTION AND ORDERING INFORMATION This device consists of a single voltage comparator designed to operate from a single power supply over a wide range of voltages. Operation from dual supplies also is possible if the difference between the two supplies is 2 V to 36 V and VCC is at least 1.5 V more positive than the input common-mode voltage. Current drain is independent of the supply voltage. To achieve wired-AND relationships, one can connect the output to other open-collector outputs. ORDERING INFORMATION (1) PACKAGE (2) TA (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C SOT-23 – DBV Reel of 3000 TL331IDBVRQ1 TQ1U –40°C to 125°C SOT-23 – DBV Reel of 3000 TL331QDBVRQ1 T1RU For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated TL331-Q1 SLVS969C – OCTOBER 2009 – REVISED AUGUST 2013 www.ti.com LOGIC DIAGRAM IN+ OUT IN− SCHEMATIC VCC 80-µA Current Regulator 10 µA 60 µA 10 µA 80 µA IN+ COMPONENT COUNT OUT Epi-FET Diodes Resistors Transistors 1 2 1 20 IN− GND Note: Current values shown are nominal. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage (2) 36 V VID Differential input voltage (3) ±36 V VI Input voltage range (either input) VO Output voltage 36 V IO Output current 20 mA –0.3 V to 36 V Duration of output short-circuit to ground (4) TJ Operating virtual junction temperature Tstg Storage temperature range (1) (2) (3) (4) 2 Unlimited 150°C –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to the network ground. Differential voltages are at IN+ with respect to IN–. Short circuits from outputs to VCC can cause excessive heating and eventual destruction. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TL331-Q1 TL331-Q1 www.ti.com SLVS969C – OCTOBER 2009 – REVISED AUGUST 2013 THERMAL INFORMATION TL331-Q1 THERMAL METRIC (1) DBV UNIT 5 PINS Junction-to-ambient thermal resistance (2) θJA (3) 218.3 °C/W θJCtop Junction-to-case (top) thermal resistance 87.3 °C/W θJB Junction-to-board thermal resistance (4) 44.9 °C/W ψJT Junction-to-top characterization parameter (5) 4.3 °C/W ψJB Junction-to-board characterization parameter (6) 44.1 °C/W θJCbot Junction-to-case (bottom) thermal resistance (7) N/A °C/W (1) (2) (3) (4) (5) (6) (7) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer ELECTRICAL CHARACTERISTICS at specified free-air temperature, VCC = 5 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VIO Input offset voltage VCC = 5 V to 30 V, VO = 1.4 V, VIC = VIC(min) IIO Input offset current VO = 1.4 V IIB Input bias current VO = 1.4 V VICR Common-mode input voltage range (2) AVD Large-signal differential-voltage amplification IOH High-level output current TA TYP MAX 2 5 –40°C to 125°C 9 25°C 5 –40°C to 125°C 25°C 25°C –25 25°C VOH = 5 V, VID = 1 V 25°C VOH = 30 V, VID = 1 V –40°C to 125°C 0 to VCC – 1.5 50 IOL = 4 mA, VID = –1 V IOL Low-level output current VOL = 1.5 V, VID = –1 V 25°C ICC Supply current RL = ∞, VCC = 5 V 25°C UNIT mV nA nA V 0 to VCC – 2 25°C Low-level output voltage –250 –400 –40°C to 125°C VCC = 15 V, VO = 1.4 V to 11.4 V, RL ≥ 15 kΩ to VCC 50 250 –40°C to 125°C VOL (1) (2) MIN 25°C 200 V/mV 0.1 50 nA 1 μA 150 400 –40°C to 125°C 700 6 mV mA 0.4 0.7 mA All characteristics are measured with zero common-mode input voltage, unless otherwise specified. The voltage at either input or common-mode should not be allowed to go negative by more than 0.3 V. The upper end of the commonmode voltage range is VCC+ – 1.5 V at 25ºC, but either or both inputs can go to 30 V without damage. SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C PARAMETER Response time (1) (2) TEST CONDITIONS RL connected to 5 V through 5.1 kΩ, CL = 15 pF (1) (2) TYP 100-mV input step with 5-mV overdrive 1.3 TTL-level input step 0.3 UNIT μs CL includes probe and jig capacitance. The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TL331-Q1 3 TL331-Q1 SLVS969C – OCTOBER 2009 – REVISED AUGUST 2013 www.ti.com VERTICAL SPACE VERTICAL SPACE REVISION HISTORY Changes from Revision B (September 2012) to Revision C Page • Added a Thermal Information table ...................................................................................................................................... 3 • Changed VICR in the Electrical Characteristics ..................................................................................................................... 3 • Changed test conditions of IOL in the Electrical Characteristics ........................................................................................... 3 Changes from Revision A (July 2010) to Revision B • 4 Page Changed VICR in the Electrical Characteristics ..................................................................................................................... 3 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TL331-Q1 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TL331IDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TQ1U TL331QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T1RU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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OTHER QUALIFIED VERSIONS OF TL331-Q1 : Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 • Catalog: TL331 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TL331IDBVRQ1 SOT-23 DBV 5 3000 179.0 8.4 TL331QDBVRQ1 SOT-23 DBV 5 3000 179.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 3.2 3.2 1.4 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL331IDBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0 TL331QDBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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