Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
TLA2518 Small, 8-Channel, 12-Bit ADC with SPI Interface and GPIOs
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
Small package size:
– WQFN 3 mm × 3 mm
8 channels configurable as any combination of:
– Up to 8 analog inputs, digital inputs, or digital
outputs
GPIOs for I/O expansion:
– Open-drain, push-pull digital outputs
Wide operating ranges:
– AVDD: 2.35 V to 5.5 V
– DVDD: 1.65 V to 5.5 V
– –40°C to +85°C temperature range
Enhanced-SPI digital interface:
– High-speed, 60-MHz interface
– Achieve full throughput with >13.5-MHz SPI
Programmable averaging filters:
– Programmable sample size for averaging
– Averaging with internal conversions
– 16-bit resolution
Macro remote radio units (RRU)
Battery management systems (BMS)
String inverters
Central inverters
3 Description
The TLA2518 is an easy-to-use, 8-channel,
multiplexed,
12-bit,
1-MSPS,
successive
approximation register analog-to-digital converter
(SAR ADC). The eight channels can be
independently configured as either analog inputs,
digital inputs, or digital outputs. The device has an
internal oscillator for the ADC conversion process.
The TLA2518 communicates via an SPI compatible
interface and supports averaging multiple data
samples with a single start of conversion. The built-in
programmable averaging filters help reduce noise
from the analog inputs and reduce the number of
data samples required to be read by the host.
Device Information(1)
PART NUMBER
TLA2518
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
TLA2518 Block Diagram and Applications
Device Block Diagram
Example Applications
DVDD
AIN0 / GPIO0
AIN1 / GPIO1
ADC
AIN2 / GPIO2
Programmable
Averaging Filters
CS
SPI Interface
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
SCLK
SDO
AIN3 / GPIO3
SDI
MUX
Sequencer
Pin CFG
GND
GPO Write
GPI Read
TLA2518
AVDD (VREF)
AIN / GPIO
AIN / GPIO
DECAP
AVDD
AIN / GPIO
AIN / GPIO
AIN / GPIO
AIN / GPIO
SPI
TLA2518
Controller
AIN / GPIO
AIN / GPIO
VSIGNAL + noise
R1
R2
TLA2518
+
Averaging
Filters
Reduced
noise
Controller
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 19
7.5 TLA2518 Registers ................................................. 22
8
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Applications ................................................ 29
9
Power Supply Recommendations...................... 32
9.1 AVDD and DVDD Supply Recommendations......... 32
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2019) to Revision B
Page
•
Changed description of DECAP pin in Pin Functions table.................................................................................................... 3
•
Added last sentence to AVDD and DVDD Supply Recommendations section .................................................................... 32
•
Changed last sentence of Layout Guidelines section ......................................................................................................... 33
Changes from Original (June 2019) to Revision A
•
2
Page
Changed device status from advance information to production data ................................................................................... 1
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
5 Pin Configuration and Functions
AIN2/GPIO2
1
AIN3/GPIO3
2
AIN1/GPIO1
AIN0/GPIO0
SDI
SCLK
16
15
14
13
RTE Package
16-Pin WQFN
Top View
12
SDO
11
CS
10
DVDD
Thermal
7
8
AVDD
DECAP
9
6
4
AIN7/GPIO7
AIN5/GPIO5
Pad
5
3
AIN6/GPIO6
AIN4/GPIO4
GND
Not to scale
Pin Functions
PIN
NAME
NO.
FUNCTION (1)
DESCRIPTION
AIN0/GPIO0
15
AI, DI, DO
Channel 0; can be configured as either an analog input (default), digital input, or digital output.
AIN1/GPIO1
16
AI, DI, DO
Channel 1; can be configured as either an analog input (default), digital input, or digital output.
AIN2/GPIO2
1
AI, DI, DO
Channel 2; can be configured as either an analog input (default), digital input, or digital output.
AIN3/GPIO3
2
AI, DI, DO
Channel 3; can be configured as either an analog input (default), digital input, or digital output.
AIN4/GPIO4
3
AI, DI, DO
Channel 4; can be configured as either an analog input (default), digital input, or digital output.
AIN5/GPIO5
4
AI, DI, DO
Channel 5; can be configured as either an analog input (default), digital input, or digital output.
AIN6/GPIO6
5
AI, DI, DO
Channel 6; can be configured as either an analog input (default), digital input, or digital output.
AIN7/GPIO7
6
AI, DI, DO
Channel 7; can be configured as either an analog input (default), digital input, or digital output.
AVDD
7
Supply
CS
11
DI
DECAP
8
Supply
Connect a 1-µF decoupling capacitor to GND for the internal power supply.
DVDD
10
Supply
Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND.
GND
9
Supply
Ground for the power supply; all analog and digital signals are referred to this pin voltage.
SCLK
13
DI
Serial clock for the SPI interface.
SDI
14
DI
Serial data in for the device.
SDO
12
DO
Serial data out for the device.
Thermal pad
—
Supply
(1)
Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF
decoupling capacitor to GND.
Chip-select input pin; active low. The device takes control of the data bus when CS is low.
The device starts converting the active input channel on the rising edge of CS. SDO goes hi-Z
when CS is high.
Exposed thermal pad; connect to GND.
AI = analog input, DI = digital input, and DO = digital output.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
3
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted) (1).
DVDD to GND
AVDD to GND
MIN
MAX
–0.3
5.5
UNIT
V
–0.3
5.5
V
AINx / GPOx (2) to GND
GND – 0.3 AVDD + 0.3
V
Digital input to GND
GND – 0.3
5.5
V
Current through any pin except supply pins
(3)
–10
10
mA
Junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–60
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AINx / GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16.
Pin current must be limited to 10 mA or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
Analog supply voltage
2.35
3.3
5.5
V
DVDD
Digital supply voltage
1.65
3.3
5.5
V
ANALOG INPUTS
FSR
Full-scale input range
AINX - GND
0
AVDD
V
VIN
Absolute input voltage
AINX - GND
–0.1
AVDD + 0.1
V
85
℃
TEMPERATURE RANGE
TA
(1)
Ambient temperature
–40
25
AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
6.4 Thermal Information
TLA2518
THERMAL METRIC
(1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
49.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.4
°C/W
RθJB
Junction-to-board thermal resistance
24.7
°C/W
ΨJT
Junction-to-top characterization parameter
1.3
°C/W
ΨJB
Junction-to-board characterization parameter
24.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
6.5 Electrical Characteristics
At AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and
maximum values at TA = –40°C to +85°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
CSH
Sampling capacitance
12
pF
DC PERFORMANCE
Resolution
No missing codes
12
bits
±0.5
LSB
±0.5
LSB
DNL
Differential nonlinearity
INL
Integral nonlinearity
V(OS)
Input offset error
Post offset calibration
±0.5
Input offset thermal drift
Post offset calibration
±1
GE
Gain error
LSB
ppm/°C
±0.05
%FSR
±1
ppm/°C
Gain error thermal drift
AC PERFORMANCE
SINAD
Signal-to-noise + distortion ratio
SNR
Signal to noise ratio
AVDD = 5 V, fIN = 2 kHz
72.9
AVDD = 3 V, fIN = 2 kHz
72.7
AVDD = 5 V, fIN = 2 kHz
73.1
AVDD = 3 V, fIN = 2 kHz
72.8
dB
dB
DECAP Pin
Decoupling capacitor on DECAP
pin
0.22
1
4.7
µF
0.7 x DVDD
5.5
V
–0.3
0.3 x DVDD
V
Source current = 2 mA,
DVDD > 2 V
0.8 x DVDD
DVDD
Source current = 2 mA,
DVDD ≤ 2 V
0.7 x DVDD
DVDD
SPI INTERFACE (CS, SCLK, SDI, SDO)
VIH
Input high logic level
VIL
Input low logic level
VOH
VOL
Output high logic level
Output low logic level
V
Sink current = 2 mA, DVDD > 2 V
0
0.4
Sink current = 2 mA, DVDD ≤ 2 V
0
0.2 x DVDD
0.7 x AVDD
AVDD + 0.3
V
–0.3
0.3 x AVDD
V
0.8 x AVDD
AVDD
V
0
0.2 x AVDD
V
V
GPIOs
VIH
Input high logic level
VIL
Input low logic level
VOH
Output high logic level
GPO_DRIVE_CFG = push-pull,
ISOURCE = 2 mA
VOL
Output low logic level
ISINK = 2 mA
IOH
Output high source current
VOH > 0.7 x AVDD
5
mA
IOL
Output low sink current
VOL < 0.3 x AVDD
5
mA
POWER-SUPPLY CURRENTS
IAVDD
Analog supply current
Full throughput, AVDD = 5 V
495
540
Full throughput, AVDD = 3 V
455
500
No conversion, AVDD = 5 V
7
15
µA
6.6 Timing Requirements
At AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C.
MIN
MAX
UNIT
1000
kSPS
CONVERSION CYCLE
fCYCLE
Sampling frequency
tCYCLE
ADC cycle-time period
1 / fCYCLE
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
s
5
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Timing Requirements (continued)
At AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C.
MIN
tACQ
Acquisition time
tQT_ACQ
tD_CNVCAP
tWH_CSZ
tWL_CSZ
MAX
UNIT
400
ns
Quiet acquisition time
10
ns
Quiet conversion time
10
ns
Pulse duration: CS high
200
ns
Pulse duration: CS low
200
ns
SPI INTERFACE TIMINGS
fCLK
Maximum SCLK frequency
tCLK
Minimum SCLK time period
60
MHz
tPH_CK
SCLK high time
0.45
0.55
tCLK
tPL_CK
SCLK low time
0.45
0.55
tCLK
tSU_CSCK
Setup time: CS falling to the first SCLK capture edge
3.5
ns
tSU_CKDI
Setup time: SDI data valid to the SCLK capture edge
1.5
ns
tHT_CKDI
Hold time: SCLK capture edge to data valid on SDI
2
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
6
ns
16.67
ns
6.7 Switching Characteristics
At AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C.
PARAMETER
Test Conditions
MIN
MAX
UNIT
600
ns
5
ms
5
ms
CONVERSION CYCLE
tCONV
ADC conversion time
RESET
AVDD ≥ 2.35 V,
CDECAP = 1 µF
tPU
Power-up time for device
tRST
Delay time; RST bit = 1b to device reset
complete (1)
SPI INTERFACE TIMINGS
tDEN_CSDO
Delay time: CS falling to data enable
15
ns
tDZ_CSDO
Delay time: CS rising to SDO going Hi-Z
15
ns
tD_CKDO
Delay time: SCLK launch edge to (next)
data valid on SDO
16
ns
(1)
6
RST bit is automatically reset to 0b after tRST.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
tCYCLE
tCONV
CS
Acquiring
Sample N
tACQ
Converting Sample N
Acquiring Sample N+1
HI-Z
SDI
MSB
MSB-1
MSB-2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+1
LSB
HI-Z
SDO
tQUIET
SCLK
Figure 1. Conversion Cycle Timing
tCLK
tPH_CK
CS
tPL_CK
SCLK(1)
tSU_CKDI
tSU_CSCK
tD_CKCS
SCLK(1)
SDI
tDEN_CSDO
tDZ_CSDO
SDO
(1)
tHT_CKDI
tD_CKDO
SDO
The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 2. SPI-Compatible Serial Interface Timing
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
7
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
6.8 Typical Characteristics
At TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted).
0
45000
39581
30000
Amplitude (dB)
-30
Frequency
25955
15000
-60
-90
-120
-150
0
2048
0
2049
Output Code
C001
100
200
300
Frequency (kHz)
C008
Figure 4. Typical FFT
Figure 3. DC Input Histogram
0.8
Integral Nonlinearity (LSB)
0.8
0.4
0
-0.4
-0.8
0.4
0
-0.4
-0.8
0
1024
2048
Output Code
3072
4095
0
1024
C002
Typical DNL = ±0.5 LSB
2048
Output Code
3072
Figure 5. Typical DNL
C004
Figure 6. Typical INL
0.75
Maximum
Minimum
0.3
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Maximum
Minimum
0.1
-0.1
-0.3
-0.5
-40
4095
Typical INL = ±0.5 LSB
0.5
-15
10
35
Temperature (qC)
60
85
0.45
0.15
-0.15
-0.45
-0.75
-40
C003
Figure 7. DNL vs Temperature
8
500
fIN = 2 kHz, SNR = 73.2 dB, THD = –92.1 dB
Standard deviation = 0.49 LSB
Differential Nonlinearity (LSB)
400
-15
10
35
Temperature (qC)
60
85
C005
Figure 8. INL vs Temperature
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted).
0.5
0.75
Maximum
Minimum
0.3
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Maximum
Minimum
0.1
-0.1
-0.3
-0.5
2.5
3
3.5
4
AVDD (V)
4.5
5
0.45
0.15
-0.15
-0.45
-0.75
2.5
5.5
3
3.5
C018
0.05
1.2
0.03
0.4
-0.4
-1.2
-2
-40
5.5
C019
-0.01
-0.03
-15
10
35
Temperature (°C)
60
-0.05
-40
85
-15
C006
Figure 11. Offset Error vs Temperature
10
35
Temperature (°C)
60
85
C007
Figure 12. Gain Error vs Temperature
0.05
1.2
0.03
Gain Error (%FSR)
Offset Error (LSB)
5
0.01
2
0.4
-0.4
-1.2
-2
2.5
4.5
Figure 10. INL vs AVDD
2
Gain Error (%FSR)
Offset Error (LSB)
Figure 9. DNL vs AVDD
4
AVDD (V)
0.01
-0.01
-0.03
3
3.5
4
AVDD (V)
4.5
5
5.5
-0.05
2.5
C016
Figure 13. Offset Error vs AVDD
3
3.5
4
AVDD (V)
4.5
5
Product Folder Links: TLA2518
C017
Figure 14. Gain Error vs AVDD
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
5.5
9
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted).
11.8
73.5
73.1
11.775
73
11.75
72.9
11.725
-15
10
35
Temperature (°C)
11.7
85
60
73
11.85
72.5
11.7
72
11.55
71.5
2.5
3
4
AVDD (V)
C009
Figure 15. Noise Performance vs Temperature
-90.3
4.5
11.4
5.5
5
C010
Figure 16. Noise Performance vs AVDD
94.8
-82
THD
SFDR(dBFS)
96
-90.5
94.4
-90.7
94
-90.9
THD (dBFS)
THD
SFDR
SFDR (dBFS)
THD (dBFS)
3.5
-84
94
-86
92
-88
90
-90
88
SFDR (dBFS)
72.8
-40
12
SINAD
SNR
ENOB
ENOB (Bits)
SINAD, SNR (dBFS)
SINAD, SNR (dBFS)
SINAD
SNR
ENOB
ENOB (Bits)
73.2
93.6
-91.1
-40
-15
10
35
Temperature (°C)
93.2
85
60
-92
2.5
3
3.5
C011
Figure 17. Distortion Performance vs Temperature
4
AVDD (V)
4.5
86
5.5
5
C012
Figure 18. Distortion Performance vs AVDD
485
500
479
473
IAVDD (PA)
IAVDD (PA)
480
467
460
440
461
455
-40
-15
10
35
Temperature (°C)
60
85
3
C013
Figure 19. Analog Supply Current vs Temperature
10
420
2.5
3.5
4
AVDD (V)
4.5
5
5.5
C014
Figure 20. Analog Supply Current vs AVDD
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted).
500
IAVDD (PA)
400
300
200
100
0
0
200
400
600
Throughput (kSPS)
800
1000
C015
Figure 21. Analog Supply Current vs Throughput
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
11
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
7 Detailed Description
7.1 Overview
The TLA2518 is a small, eight-channel, multiplexed, 12-bit, 1-MSPS, analog-to-digital converter (ADC) with an
enhanced-SPI serial interface. The eight channels of the TLA2518 can be individually configured as either analog
inputs, digital inputs, or digital outputs. The device uses an internal oscillator for conversion. The analog input
channel selection can be auto-sequenced to simplify the digital interface with the host.
The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution.
7.2 Functional Block Diagram
DECAP
AVDD
DVDD
AIN0 / GPIO0
AIN1 / GPIO1
ADC
AIN2 / GPIO2
Averager
1 to 128
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
12
SCLK
SPI Interface
SDO
AIN3 / GPIO3
AIN4 / GPIO4
CS
SDI
MUX
Sequencer
Pin CFG
GPO Write
GND
GPI Read
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
7.3 Feature Description
7.3.1 Multiplexer and ADC
The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose
inputs/outputs (GPIOs). Figure 22 shows that each input pin has ESD protection diodes to AVDD and GND. On
power-up or after device reset, all eight multiplexer channels are configured as analog inputs.
Figure 22 shows an equivalent circuit for pins configured as analog inputs. The ADC sampling switch is
represented by ideal switch (SW) in series with the resistor RSW (typically 150 Ω) and the sampling capacitor,
CSH (typically 12 pF).
GPO_VALUE[0]
GPIO_CFG[0]
AVDD
GPI_VALUE[0]
PIN_CFG[0]
AIN0 / GPIO0
RSW
SW
MUX
Multiplexer
AVDD
CSH
ADC
AIN7 / GPIO7
PIN_CFG[7]
GPI_VALUE[7]
GPIO_CFG[7]
GPO_VALUE[7]
Figure 22. Analog Inputs, GPIOs, and ADC Connections
During acquisition, the SW switch is closed to allow the signal on the selected analog input channel to charge the
internal sampling capacitor. During conversion, the SW switch is opened to disconnect the analog input channel
from the sampling capacitor.
The multiplexer channels can be configured as GPIOs in the PIN_CFG register. The direction of a GPIO (either
as an input or an output) can be set in the GPIO_CFG register. The logic level on the channels configured as
digital inputs can be read from the GPI_VALUE register. The digital outputs can be accessed by writing to the
GPO_VALUE register. The digital outputs can be configured as either open-drain or push-pull in the
GPO_DRIVE_CFG register.
7.3.2 Reference
The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process.
TI recommends connecting a 1-µF, low-equivalent series resistance (ESR) ceramic decoupling capacitor
between the AVDD and GND pins.
7.3.3 ADC Transfer Function
The ADC output is in straight binary format. Equation 1 computes the ADC resolution:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD
N = 12
(1)
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
13
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Feature Description (continued)
Figure 23 and Table 1 detail the transfer characteristics for the device.
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
1 LSB
AVDD/2 (AVDD/2 + 1 LSB)
(AVDD ± 1 LSB)
Figure 23. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE FOR SINGLE-ENDED INPUT
CODE
DESCRIPTION
IDEAL OUTPUT
CODE
≤1 LSB
NFSC
Negative full-scale code
000
1 LSB to 2 LSBs
NFSC + 1
—
001
(AVDD / 2) to (AVDD / 2) + 1 LSB
MC
Mid code
800
(AVDD / 2) + 1 LSB to (AVDD / 2) + 2 LSB
MC + 1
—
801
≥ AVDD – 1 LSB
PFSC
Positive full-scale code
FFF
7.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the
CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit
to check the ADC offset calibration completion status.
14
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
7.3.5 Programmable Averaging Filter
The TLA2518 features a built-in oversampling (OSR) function that can be used to average several samples. The
averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging filter
configuration is common to all analog input channels. Figure 24 shows that the averaging filter module output is
16 bits long. In manual conversion mode and auto-sequence mode, only the first conversion for the selected
analog input channel must be initiated by the host; see the Manual Mode and Auto-Sequence Mode sections. As
shown in Figure 24, any remaining conversions for the selected averaging factor are generated internally. The
time required to complete the averaging operation is determined by the sampling speed and number of samples
to be averaged. As shown in Figure 24, the 16-bit result can be read out after the averaging operation completes.
Sample
AINx
(start of averaging)
Sample
AINx
Sample
AINx
CS
N ± 1 conversions triggered
internally
tAVG = N samples x tCYCLE
SCLK
SDO
[15:0] Data
16 clocks
Figure 24. Averaging Example
Equation 2 provides the LSB value of the 16-bit average result.
AVDD
1 LSB
216
(2)
7.3.6 General-Purpose I/Os
The eight channels of the TLA2518 can be independently configured as analog inputs, digital inputs, or digital
outputs. Table 2 describes how the PIN_CFG and GPIO_CFG registers can be used to configure the device
channels.
Table 2. Configuring Channels as Analog Inputs or GPIOs
PIN_CFG[7:0]
GPIO_CFG[7:0]
GPO_DRIVE_CFG[7:0]
CHANNEL CONFIGURATION
0
x
x
Analog input (default)
1
0
x
Digital input
1
1
0
Digital output; open-drain driver
1
1
1
Digital output; push-pull driver
Digital outputs can be configured to logic 1 or 0 by writing to the GPO_VALUE register. Reading the GPI_VALUE
register returns the logic level for all channels configured as digital inputs or digital outputs. The GPI_VALUE
register can be read to detect a failure in external components, such as a floating pullup resistor or a lowimpedance pulldown resistor, that prevents digital outputs being set to the desired logic level.
7.3.7 Oscillator and Timing Control
The device uses an internal oscillator for conversion. When using the averaging module, the host initiates the
first conversion and subsequent conversions are generated internally by the device. Also, in autonomous mode
of operation, the start of the conversion signal is generated by the device. Table 3 describes how the sampling
rate can be controlled by the OSC_SEL and CLK_DIV[3:0] register fields when the device generates the start of
the conversion.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
15
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Table 3. Configuring Sampling Rate for Internal Conversion Start Control
OSC_SEL = 0
CLK_DIV[3:0]
OSC_SEL = 1
SAMPLING FREQUENCY, fCYCLE
(kSPS)
CYCLE TIME,
tCYCLE (µs)
SAMPLING FREQUENCY,
fCYCLE (kSPS)
CYCLE TIME, tCYCLE
(µs)
0000b
1000
1
31.25
32
0001b
666.7
1.5
20.83
48
0010b
500
2
15.63
64
0011b
333.3
3
10.42
96
0100b
250
4
7.81
128
0101b
166.7
6
5.21
192
0110b
125
8
3.91
256
0111b
83
12
2.60
384
1000b
62.5
16
1.95
512
1001b
41.7
24
1.3
768
1010b
31.3
32
0.98
1024
1011b
20.8
48
0.65
1536
1100b
15.6
64
0.49
2048
1101b
10.4
96
0.33
3072
1110b
7.8
128
0.24
4096
1111b
5.2
192
0.16
6144
The conversion time of the device, given by tCONV in the Switching Characteristics table, is independent of the
OSC_SEL and CLK_DIV[3:0] configuration.
7.3.8 Output Data Format
Figure 25 depicts various SPI frames for reading data. The data output is MSB aligned. If averaging is enabled
the output data from the ADC are 16 bits long, otherwise the output data are 12 bits long. Optionally, a 4-bit
channel ID can be appended at the end of the output data by configuring the APPEND_STATUS[1:0] field.
CS
SCLK
1
12
2
13
14
15
16
17
18
19
20
Data output when averaging is disabled
OSR[2:0] = 00b
12 SCLKs minimum. Remaining clocks optional.
SDO
MSB
LSB
12 bit ADC data
Channel ID
4 bits optional
Data output when averaging is enabled
OSR[2:0] > 00b
16 SCLKs minimum. Remaining clocks optional.
SDO
LSB
MSB
16 bit averaged ADC data
Channel ID
4 bits optional
Figure 25. SPI Frames for Reading Data
16
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
7.3.9 Device Programming
7.3.9.1 Enhanced-SPI Interface
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds
and still achieve full throughput. As described in Table 4, the host controller can use any of the four SPIcompatible protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device.
Table 4. SPI Protocols for Configuring the Device
PROTOCOL
SCLK POLARITY
(At the CS Falling Edge)
SCLK PHASE
(Capture Edge)
CPOL_CPHA[1:0]
DIAGRAM
SPI-00
SPI-01
Low
Rising
00b
Figure 26
Low
Falling
01b
Figure 27
SPI-10
High
Falling
10b
Figure 26
SPI-11
High
Rising
11b
Figure 27
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data
read and data write operations. To select a different SPI-compatible protocol, program the CPOL_CPHA[1:0]
field. This first write operation must adhere to the SPI-00 protocol. Any subsequent data transfer frames must
adhere to the newly-selected protocol.
CS
CS
CPOL = 0
CPOL = 0
SCLK
SCLK
CPOL = 1
CPOL = 1
SDO
MSB
MSB-1
MSB-2
LSB+1
LSB
SDO
0
MSB
MSB-1
LSB+1
LSB
Figure 27. Standard SPI Timing Protocol
(CPHA = 1)
Figure 26. Standard SPI Timing Protocol
(CPHA = 0)
7.3.9.2 Register Read/Write Operation
The device supports the commands listed in Table 5 to access the internal configuration registers.
Table 5. Opcodes for Commands
OPCODE
COMMAND DESCRIPTION
0000 0000b
No operation
0001 0000b
Single register read
0000 1000b
Single register write
0001 1000b
Set bit
0010 0000b
Clear bit
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
17
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
7.3.9.2.1 Register Write
A 24-bit SPI frame is required for writing data to configuration registers. The 24-bit data on SDI, as shown in
Figure 28, consists of an 8-bit write command (0000 1000b), an 8-bit register address, and 8-bit data. The write
command is decoded on the CS rising edge and the specified register is updated with the 8-bit data specified
during the register write operation.
CS
SCLK
1
2
8
9
0000 1000b
(WR_REG)
SDI
10
16
18
17
8-bit Address
24
8-bit Data
Figure 28. Register Write Operation
7.3.9.2.2 Register Read
Register read operation consists of two SPI frames: the first SPI frame initiates a register read and the second
SPI frame reads data from the register address provided in the first frame. As shown in Figure 29, the 8-bit
register address and the 8-bit dummy data are sent over the SDI pin during the first 24-bit frame with the read
command (0001 0000b). On the rising edge of CS, the read command is decoded and the requested register
data are available for reading during the next frame. During the second frame, the first eight bits on SDO
correspond to the requested register read. During the second frame, SDI can be used to initiate another
operation or can be set to 0.
CS
SCLK
SDI
1
2
0001 0000b
(RD_REG)
8
9
10
8-bit Address
16
17
18
0000 0000b
24
1
2
8
9
Command
10
16
8-bit Address
17
18
24
8-bit Data
Optional; can set SDI = 0
SDO
8-bit Register Data
Figure 29. Register Read Operation
18
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
7.4 Device Functional Modes
Table 6 lists the functional modes supported by the TLA2518.
Table 6. Functional Modes
FUNCTIONAL
MODE
CONVERSION CONTROL
MUX CONTROL
SEQ_MODE[1:0]
Manual
CS rising edge
Register write to MANUAL_CHID
00b
On-the-fly
CS rising edge
First 5 bits after the CS falling edge
10b
Auto-sequence
CS rising edge
Channel sequencer
01b
The device powers up in manual mode and can be configured into either of these modes by writing the
configuration registers for the desired mode.
7.4.1 Device Power-Up and Reset
On power-up, the BOR bit is set indicating a power-cycle or reset event. The device can be reset by setting the
RST bit or by recycling the power on the AVDD pin.
7.4.2 Manual Mode
Manual mode allows the external host processor to directly select the analog input channel. Figure 30 shows the
steps for operating the device in manual mode.
Idle
SEQ_MODE = 0
Configure channels as AIN/GPIO using PIN_CFG
Select Manual mode
(SEQ_MODE = 00b)
Configure desired Channel ID in MANUAL_CHID field
Host starts conversion and reads conversion result
No
Same
Channel ID?
Yes
Figure 30. Device Operation in Manual Mode
In manual mode, the command to switch to a new channel (indicated by cycle N in Figure 31) is decoded by the
device on the CS rising edge. The CS rising edge is also the start of the conversion signal, and therefore the
device samples the previously selected MUX channel in cycle N+1. The newly selected analog input channel
data are available in cycle N+2. For switching the analog input channel, a register write to the MANUAL_CHID
field requires 24 clocks; see the Register Write section for more details. After a channel is selected, the number
of clocks required for reading the output data depends on the device output data frame size; see the Output Data
Format section for more details.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
19
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Sample
AINx
Sample
AINx
Sample
AINy
tCONV
Sample
AINz
tCYCLE
CS
SCLK
SDI
SDO
100-ns
Switch to AINy
Switch to AINz
Switch to AINx
Data AINx
Data AINx
Data AINy
24 clocks
MUX OUT = AINx
MUX
Cycle N
MUX OUT = AINy
MUX OUT = AINz
Cycle (N + 1)
Cycle (N + 2)
Figure 31. Starting Conversions and Reading Data in Manual Mode
7.4.3 On-the-Fly Mode
In the on-the-fly mode of operation, the analog input channel is selected, as shown in Figure 32, using the first
five bits on SDI without waiting for the CS rising edge. Thus, the ADC samples the newly selected channel on
the CS edge and there is no latency between the channel selection and the ADC output data.
Sample
AINx
Sample
AINx
Sample
AINy
tCONV
Sample
AINz
tCYCLE
CS
SCLK
1
24
1
2
3
4
5
12
1
2
3
4
5
12
5 clocks
SEQ_MODE =
10b
SDI
SDO
1
4-bit AINy ID
Data AINx
1
4-bit AINz ID
12 clocks
12 clocks
Data AINx
Data AINy
24 clocks
MUX
MUX OUT = AINx
100-ns
MUX OUT = AINy
MUX OUT = AINx
MUX OUT = AINz
No Cycle Latency
Figure 32. Starting Conversions and Reading Data in On-the-Fly Mode
20
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
The number of clocks required for reading the output data depends on the device output data frame size; see the
Output Data Format section for more details.
7.4.4 Auto-Sequence Mode
In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input
channel after every conversion. The desired analog input channels can be configured for sequencing in the
AUTO_SEQ_CHSEL register. To enable the channel sequencer, set SEQ_START = 1b. After every conversion,
the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel
sequencer from selecting channels, set SEQ_START = 0b.
In the example shown in Figure 33, AIN2 and AIN6 are enabled for sequencing in AUTO_SEQ_CHSEL. The
channel sequencer loops through AIN2 and AIN6 and repeats until SEQ_START is set to 0b. The number of
clocks required for reading the output data depends on the device output data frame size; see the Output Data
Format section for more details.
Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN2
Sample
AIN6
tCYCLE
CS
SCLK
SDI
SDO
MUX
SEQ_START
Data AINx
Data AINx
24 clocks
12 clocks
MUX OUT = AINx
MUX OUT = AIN2
Data AIN2
Data AIN6
Data AIN2
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AIN6
Scan channels AIN2 and AIN6 and repeat
Figure 33. Starting Conversions and Reading Data in Auto-Sequence Mode
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
21
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
7.5 TLA2518 Registers
Table 7 lists the TLA2518 registers. All register offset addresses not listed in Table 7 should be considered as
reserved locations and the register contents should not be modified.
Table 7. TLA2518 Registers
Address
Acronym
0x0
SYSTEM_STATUS
0x1
GENERAL_CFG
0x2
DATA_CFG
0x3
OSR_CFG
0x4
OPMODE_CFG
0x5
PIN_CFG
0x7
GPIO_CFG
0x9
GPO_DRIVE_CFG
Register
Name
Section
SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
DATA_CFG Register (Address = 0x2) [reset = 0x0]
OSR_CFG Register (Address = 0x3) [reset = 0x0]
OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
PIN_CFG Register (Address = 0x5) [reset = 0x0]
GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
0xB
GPO_VALUE
0xD
GPI_VALUE
GPO_VALUE Register (Address = 0xB) [reset = 0x0]
0x10
SEQUENCE_CFG
0x11
CHANNEL_SEL
0x12
AUTO_SEQ_CH_SEL
GPI_VALUE Register (Address = 0xD) [reset = 0x0]
SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for
access types in this section.
Table 8. TLA2518 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
7.5.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
SYSTEM_STATUS is shown in Figure 34 and described in Table 9.
Return to the Summary Table.
22
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
Figure 34. SYSTEM_STATUS Register
7
RSVD
6
SEQ_STATUS
R-1b
R-0b
5
RESERVED
4
3
OSR_DONE
R-0b
R/W-0b
2
CRCERR_FUS
E
R-0b
1
RESERVED
0
BOR
R-0b
R/W-1b
Table 9. SYSTEM_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
1b
Reads return 1b.
6
SEQ_STATUS
R
0b
Status of the channel sequencer.
0b = Sequence stopped
1b = Sequence in progress
5-4
RESERVED
R
0b
Reserved. Reads return 0b.
3
OSR_DONE
R/W
0b
Averaging status. Clear this bit by writing 1b to this bit.
0b = Averaging in progress or not started; average result is not
ready.
1b = Averaging complete; average result is ready.
2
CRCERR_FUSE
R
0b
Device power-up configuration CRC check status. To re-evaluate
this bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration.
1b = Device configuration not loaded correctly.
1
RESERVED
R
0b
Reserved. Reads return 0b.
0
BOR
R/W
1b
Brown out reset indicator. This bit is set if brown out condition occurs
or device is power cycled. Write 1b to this bit to clear the flag.
0b = No brown out from the last time this bit was cleared.
1b = Brown out condition detected or device power cycled.
7.5.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
GENERAL_CFG is shown in Figure 35 and described in Table 10.
Return to the Summary Table.
Figure 35. GENERAL_CFG Register
7
6
5
RESERVED
R-0b
4
3
2
CH_RST
R/W-0b
1
CAL
R/W-0b
0
RST
W-0b
Table 10. GENERAL_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0b
Reserved. Reads return 0b.
CH_RST
R/W
0b
Force all channels to be analog inputs.
2
0b = Normal operation.
1b = All channels are set as analog inputs irrespective of
configuration in other registers.
1
CAL
R/W
0b
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is
set to 0b.
0
RST
W
0b
Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and
BOR bit is set to 1b.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
23
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
7.5.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]
DATA_CFG is shown in Figure 36 and described in Table 11.
Return to the Summary Table.
Figure 36. DATA_CFG Register
7
FIX_PAT
R/W-0b
6
RESERVED
R-0b
5
4
APPEND_STATUS[1:0]
R/W-0b
3
2
RESERVED
R-0b
1
0
CPOL_CPHA[1:0]
R/W-0b
Table 11. DATA_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
FIX_PAT
R/W
0b
Device outputs fixed data bits which can be helpful for debugging
communication with the device.
0b = Normal operation.
1b = Device outputs fixed code 0xA5A repeatitively when reading
ADC data.
6
5-4
RESERVED
R
0b
Reserved. Reads return 0b.
APPEND_STATUS[1:0]
R/W
0b
Append 4-bit channel ID or status flags to output data.
0b = Channel ID is not appended to ADC data.
1b = 4-bit channel ID is appended to ADC data.
10b = Reserved.
11b = Reserved.
3-2
RESERVED
R
0b
Reserved. Reads return 0b.
1-0
CPOL_CPHA[1:0]
R/W
0b
This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0.
1b = CPOL = 0, CPHA = 1.
10b = CPOL = 1, CPHA = 0.
11b = CPOL = 1, CPHA = 1.
7.5.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 37 and described in Table 12.
Return to the Summary Table.
Figure 37. OSR_CFG Register
7
6
5
RESERVED
R-0b
4
3
2
1
OSR[2:0]
R/W-0b
0
Table 12. OSR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0b
Reserved. Reads return 0b.
2-0
OSR[2:0]
R/W
0b
Selects the oversampling ratio for ADC conversion result.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples
24
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
7.5.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
OPMODE_CFG is shown in Figure 38 and described in Table 13.
Return to the Summary Table.
Figure 38. OPMODE_CFG Register
7
6
RESERVED
R-0b
5
4
OSC_SEL
R/W-0b
3
2
1
0
CLK_DIV[3:0]
R/W-0b
Table 13. OPMODE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0b
Reserved. Reads return 0b.
OSC_SEL
R/W
0b
Selects the oscillator for internal timing generation.
4
0b = High-speed oscillator.
1b = Low-power oscillator.
3-0
CLK_DIV[3:0]
R/W
0b
Refer to section on oscillator and timing control for details.
7.5.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]
PIN_CFG is shown in Figure 39 and described in Table 14.
Return to the Summary Table.
Figure 39. PIN_CFG Register
7
6
5
4
3
2
1
0
PIN_CFG[7:0]
R/W-0b
Table 14. PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PIN_CFG[7:0]
R/W
0b
Configure device channels AIN / GPIO [7:0] as analog inputs or
GPIOs.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.
7.5.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPIO_CFG is shown in Figure 40 and described in Table 15.
Return to the Summary Table.
Figure 40. GPIO_CFG Register
7
6
5
4
3
2
1
0
GPIO_CFG[7:0]
R/W-0b
Table 15. GPIO_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPIO_CFG[7:0]
R/W
0b
Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input.
1b = GPIO is configured as digital output.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
25
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
7.5.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_DRIVE_CFG is shown in Figure 41 and described in Table 16.
Return to the Summary Table.
Figure 41. GPO_DRIVE_CFG Register
7
6
5
4
3
GPO_DRIVE_CFG[7:0]
R/W-0b
2
1
0
Table 16. GPO_DRIVE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_DRIVE_CFG[7:0]
R/W
0b
Configure digital outputs GPO[7:0] as open-drain or push-pull
outputs.
0b = Digital output is open-drain; connect external pullup resistor.
1b = Push-pull driver is used for digital output.
7.5.9 GPO_VALUE Register (Address = 0xB) [reset = 0x0]
GPO_VALUE is shown in Figure 42 and described in Table 17.
Return to the Summary Table.
Figure 42. GPO_VALUE Register
7
6
5
4
3
GPO_VALUE[7:0]
R/W-0b
2
1
0
Table 17. GPO_VALUE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_VALUE[7:0]
R/W
0b
Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.
7.5.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]
GPI_VALUE is shown in Figure 43 and described in Table 18.
Return to the Summary Table.
Figure 43. GPI_VALUE Register
7
6
5
4
3
GPI_VALUE[7:0]
R-0b
2
1
0
Table 18. GPI_VALUE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPI_VALUE[7:0]
R
0b
Readback the logic level on channels configured digital inputs.
0b = Digital input is at logic 0.
1b = Digital input is at logic 1.
7.5.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
SEQUENCE_CFG is shown in Figure 44 and described in Table 19.
Return to the Summary Table.
26
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
Figure 44. SEQUENCE_CFG Register
7
6
RESERVED
R-0b
5
4
SEQ_START
R/W-0b
3
2
1
0
SEQ_MODE[1:0]
R/W-0b
RESERVED
R-0b
Table 19. SEQUENCE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0b
Reserved. Reads return 0b.
4
SEQ_START
R/W
0b
Control for start of channel sequence when using auto sequence
mode (SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels
enabled in AUTO_SEQ_CH_SEL register.
3-2
RESERVED
R
0b
Reserved. Reads return 0b.
1-0
SEQ_MODE[1:0]
R/W
0b
Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID
field.
1b
=
Auto
sequence
AUTO_SEQ_CH_SEL.
mode;
channel
selected
by
10b = On-the-fly sequence mode.
11b = Reserved.
7.5.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
CHANNEL_SEL is shown in Figure 45 and described in Table 20.
Return to the Summary Table.
Figure 45. CHANNEL_SEL Register
7
6
5
4
3
RESERVED
R-0b
2
1
MANUAL_CHID[3:0]
R/W-0b
0
Table 20. CHANNEL_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0b
Reserved. Reads return 0b.
3-0
MANUAL_CHID[3:0]
R/W
0b
In manual mode (SEQ_MODE = 00b), this field contains the 4-bit
channel ID of the analog input channel for next ADC conversion. For
valid ADC data, the selected channel must not be configured as
GPIO in PIN_CFG register. 1xxx = Reserved.
0b = AIN0
1b = AIN1
10b = AIN2
11b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
7.5.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
AUTO_SEQ_CH_SEL is shown in Figure 46 and described in Table 21.
Return to the Summary Table.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
27
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Figure 46. AUTO_SEQ_CH_SEL Register
7
6
5
4
3
AUTO_SEQ_CH_SEL[7:0]
R/W-0b
2
1
0
Table 21. AUTO_SEQ_CH_SEL Register Field Descriptions
Bit
Field
Type
7-0
AUTO_SEQ_CH_SEL[7:0] R/W
Reset
Description
0b
Select analog input channels AIN[7:0] in for auto sequencing mode.
0b = Analog input channel is not enabled in scanning sequence.
1b = Analog input channel is enabled in scanning sequence.
28
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register analog-to-digital converter (SAR ADC) are the input driver and the reference driver circuits. This section
details some general principles for designing the input driver circuit, reference driver circuit, and provides some
application circuits designed for the TLA2518.
8.2 Typical Applications
8.2.1 Mixed-Channel Configuration
Digital Output (open-drain)
Digital Output (push-pull)
Analog Input
Analog Input
Analog Input
Analog Input
AVDD (VREF)
SPI
Device
Controller
Digital Input
Digital Input
Figure 47. DAQ Circuit: Single-Supply DAQ
8.2.1.1 Design Requirements
The goal of this application is to configure some channels of the TLA2518 as digital inputs, open-drain digital
outputs, and push-pull digital outputs.
8.2.1.2 Detailed Design Procedure
The TLA2518 can support GPIO functionality at each input pin. Any analog input pin can be independently
configured as a digital input, a digital open-drain output, or a digital push-pull output though the PIN_CFG and
GPIO_CFG registers; see Table 2.
8.2.1.2.1 Digital Input
The digital input functionality can be used to monitor a signal within the system. Figure 48 illustrates that the
state of the digital input can be read from the GPI_VALUE register.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
29
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
Typical Applications (continued)
ADC
From input device
AVDD
GPIx
SW
GPIx
Figure 48. Digital Input
8.2.1.2.2 Digital Open-Drain Output
The channels of the TLA2518 can be configured as digital open-drain outputs supporting an output voltage up to
5.5 V. An open-drain output, as shown in Figure 49, consists of an internal FET (Q) connected to ground. The
output is idle when not driven by the device, which means Q is off and the pullup resistor, RPULL_UP, connects the
GPOx node to the desired output voltage. The output voltage can range anywhere up to 5.5 V, depending on the
external voltage that the GPIOx is pulled up to. When the device is driving the output, Q turns on, thus
connecting the pullup resistor to ground and bringing the node voltage at GPOx low.
VPULL_UP
Receiving Device
ADC
RPULL_UP
GPOx
ILOAD
Q
Figure 49. Digital Open-Drain Output
The minimum value of the pullup resistor, as calculated in Equation 3, is given by the ratio of VPULL_UP and the
maximum current supported by the device digital output (5 mA).
RMIN = (VPULL_UP / 5 mA)
(3)
The maximum value of the pullup resistor, as calculated in Equation 4, depends on the minimum input current
requirement, ILOAD, of the receiving device driven by this GPIO.
RMAX = (VPULL_UP / ILOAD)
(4)
Select RPULL_UP such that RMIN < RPULL_UP < RMAX.
30
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
Typical Applications (continued)
8.2.1.3 Application Curve
45000
39581
30000
Frequency
25955
15000
0
2048
2049
Output Code
C001
Standard deviation = 0.49 LSB
Figure 50. DC Input Histogram
8.2.2 Digital Push-Pull Output Configuration
The channels of the TLA2518 can be configured as digital push-pull outputs supporting an output voltage up to
AVDD. As shown in Figure 51, a push-pull output consists of two mirrored opposite bipolar transistors, Q1 and
Q2. The device can both source and sink current because only one transistor is on at a time (either Q2 is on and
pulls the output low, or Q1 is on and sets the output high). A push-pull configuration always drives the line
opposed to an open-drain output where the line is left floating.
ADC
AVDD
Q1
GPOx
Digital
output
Q2
Figure 51. Digital Push-Pull Output
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
31
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
9 Power Supply Recommendations
9.1 AVDD and DVDD Supply Recommendations
The TLA2518 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. For supplies greater than 2.35 V, AVDD and DVDD can be shorted externally if
single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device.
Decouple the AVDD and DVDD pins individually, as illustrated in Figure 52, with 1-µF ceramic decoupling
capacitors. The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If
both supplies are powered from the same source, a minimum capacitor value of 220 nF is required for
decoupling.
Connect 1-µF ceramic decoupling capacitors between the DECAP and GND pins.
AVDD
AVDD
1 PF
DECAP
1 PF
GND
GND
1 PF
DVDD
DVDD
Figure 52. Power-Supply Decoupling
32
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
TLA2518
www.ti.com
SBAS980B – JUNE 2019 – REVISED JUNE 2020
10 Layout
10.1 Layout Guidelines
Figure 53 shows a board layout example for the TLA2518. Avoid crossing digital lines with the analog signal path
and keep the analog input signals and the AVDD supply away from noise sources.
Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply
pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to
the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference
voltage for the TLA2518. Place the decoupling capacitor for AVDD close to the device AVDD and GND pins and
connect the decoupling capacitor to the device pins with thick copper tracks.
GND
CS
DVDD
SDO
10.2 Layout Example
SCLK
DECAP
SDI
AVDD
AIN/GPIO
Figure 53. Example Layout
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
33
TLA2518
SBAS980B – JUNE 2019 – REVISED JUNE 2020
www.ti.com
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: TLA2518
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLA2518IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2518
TLA2518IRTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2518
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
