TLC5733AIPM

     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 D 3-Channel CMOS ADC D 5-V Single-Supply Operation or 5-V D D D D D D Analog/Digital Core Supply With I/O Digital Supply From 2.7 V to 5.25 V 8-Bit Resolution Differential Linearity Error . . . ± 0.5 LSB Max Linearity Error . . . ± 0.75 LSB Max Maximum Conversion Rate 20 Megasamples per Second (MSPS) Min Analog Input Voltage Range 2 VI(PP) Min 64-Pin Shrink QFP Package D Analog Input Bandwidth . . . >14 MHz D Suitable for YUV or RGB Applications D Digital Clamp Optimized for NTSC or PAL D D D D YUV Component High-Precision Clamp . . . ± 1 LSB Automatic Clamp Pulse Generator Output-Data Format Multiplexer Low Power Consumption description The TLC5733A is a 3-channel 8-bit semiflash analog-to-digital converter (ADC) that operates from a single 5-V power supply. It converts a wide-band analog signal (such as a video signal) to digital data at sampling rates up to 20 MSPS minimum. The TLC5733A contains a feed-back type high-precision clamp circuit for each ADC channel for video (YUV) applications and a clamp pulse generator that detects COMPOSITE SYNC† pulses automatically. A clamp pulse can also be supplied externally. The output-data format multiplexer selects a ratio of Y:U:V of 4:4:4, 4:1:1, or 4:2:2. For RGB applications, the 4:4:4 output format without clamp function can be used. The TLC5733A is characterized for operation from − 20°C to 75°C. AVAILABLE OPTIONS PACKAGE TA QUAD FLATPACK −20°C to 75°C TLC5733AIPM Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † COMPOSITE SYNC refers to the externally generated synchronizing signal that is a combination of vertical and horizontal sync information used in display and TV systems. Copyright  2001, Texas Instruments Incorporated 
 
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     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 GND A AIN A AV CC RT A CLPV A CLP OUT A INIT CLPEN CLK EXTCLP CLP OUT B CLPV B RT B B AV CC BIN GND B PM PACKAGE (TOP VIEW) 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 QB DGND DVDD CLP OUT C CLPV C RT C C AV CC CIN GND C RB A OE A NT/PAL TEST QA DGND AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 QA DVDD DGND QB DVDD 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RB B OE B MODE0 MODE1 QC DGND CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 QC DVDD OE C RB C 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 functional block diagram CLK A AIN RT A ADC (Sampling Comparators) 8 8 8 AD1 −8 Output Data Latch 8 RB A CLPV A Clamp Circuit CLP OUT A OE A CLK B 8 BIN RT B ADC (Sampling Comparators) 8 8 BD1 −8 Output Data Latch 8 RB B CLPV B Clamp Circuit Multiplexer For Output Format CLP OUT B OE B CLK C CIN RT C 8 ADC (Sampling Comparators) 8 8 CD1 −8 Output Data Latch 8 RB C CLPV C CLP OUT C Clamp Circuit OE C EXTCLP CLPEN NT/PAL Clock Generator Control For INT/EXT Clamp Circuit CLK POST OFFICE BOX 655303 Output Format Selector and Test MODE0 MODE1 TEST INIT • DALLAS, TEXAS 75265 3 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 Terminal Functions TERMINAL NAME A AVCC AD8 −AD1 AIN B AVCC BD8 −BD1 BIN C AVCC NO. I/O DESCRIPTION 62 I Analog supply voltage of ADC A 6 −13 O Data output of ADC A (LSB: AD1, MSB:AD8) 63 I Analog input of ADC A 51 I Analog supply voltage of ADC B 17 −24 O Data output of ADC B (LSB: BD1, MSB:BD8) 50 I Analog input of ADC B 30 I Analog supply voltage of ADC C 36 −43 O Data output of ADC C (LSB:CD1, MSB: CD8) When MODE0 = L, MODE1 = L, CD8 outputs MSB flag of BD8 −BD5 When MODE0 = L, MODE1 = L, CD7 outputs MSB flag of BD8 −BD5 When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8 −BD1 When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8 −BD1 CIN 31 I Analog input of ADC C CLK 56 I Clock input. The clock frequency is normally 4 × the frequency subcarrier (fsc) for most video systems (see Table 3). The nominal clock frequency is 14.31818 MHz for National Television System Committee (NTSC) and 17.745 MHz for phase alteration line (PAL). CLPEN 57 I Clamp enable. When using an internal clamp pulse, CLPEN should be high. When using an external clamp pulse, CLPEN should be low. CLP OUT A 59 O Clamping bias current of ADC A. A resistor-capacitor combination that sets the clamp timing. CLP OUT B 54 O Clamping bias current of ADC B. A resistor-capacitor combination that sets the clamp timing. CLP OUT C 27 O Clamping bias current of ADC C. A resistor-capacitor combination that sets the clamp timing. CLPV A 60 O Clamping level of ADC A. A capacitor is connected to CLPV A to set the clamp timing. The clamp level at CLPV A is connected to an output code of 16 (0010000). CLPV B 53 O Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at CLPV B is connected to an output code of 128 (1000000). CLPV C 28 O Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at CLPV C is connected to an output code of 128 (1000000). DGND 15 I Digital ground DVDD 26 I Digital supply voltage EXTCLP 55 I External clamp pulse input. When EXTCLP and CLPEN are low, the internal clamp circuit cannot be used. The external clamp pulse when used is active high. GND A 64 I Ground of ADC A GND B 49 I Ground of ADC B GND C 32 I Ground of ADC C INIT 58 I Output initialized. The output data is synchronous when INIT is taken high from low. INIT is a control terminal that allows the external system to initialize the TLC5733A data conversion cycle. INIT is usually used at power up or system reset. MODE0 46 I Output format mode selector 0. When MODE1 is low and MODE0 is low, output data format1 is selected. When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not used. MODE1 45 I Output format mode selector 1. When MODE1 is low and MODE0 is low, output data format1 is selected. When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not used. NT/ PAL 3 I NTSC/PAL control. NTSC/PAL should be low for NTSC and high for PAL. OE A 2 I Output enable A. OE A enables the output of ADC A. OE B 47 I Output enable B. OE B enables the output of ADC B. CD8 −CD1 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 Terminal Functions (Continued) TERMINAL NAME OE C NO. I/O DESCRIPTION 34 I Output enable C. OE C enables the output of ADC C. QA DGND 5 I Digital ground for output of ADC A QA DVDD 14 I Digital supply voltage for output of ADC A QB DGND 25 I Digital ground for output of ADC B QB DVDD 16 I Digital supply voltage for output of ADC B QC DGND 44 I Digital ground for output of ADC C QC DVDD 35 I Digital supply voltage for output of ADC C RB A 1 I Bottom reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is 2 V for video signals. RB B 48 I Bottom reference voltage of ADC B. The nominal externally applied dc voltage between RT B and RB B is 2 V for video signals. RB C 33 I Bottom reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C is 2 V for video signals. RT A 61 I Top reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is 2 V for video signals. RT B 52 I Top reference voltage of ADC B. The nominal externally applied dc voltage between RT B and RB B is 2 V for video signals. RT C 29 TEST 4 Top reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C is 2 V for video signals. I Test. TEST should be tied low when using this device. absolute maximum ratings† Supply voltage, VCC‡, VDD§ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference voltage input range,Vref(RT A), Vref(RT B), Vref(RT C), Vref(RB A), Vref(RB B), Vref(RB C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VCC Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VCC Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDD Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDD Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20°C to 75°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ VCC refers to all analog supplies: AAVCC, BAVCC, and CAVCC § VDD refers to all digital supplies: QADVDD, QBDVDD, QCDVDD, and DVDD. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 recommended operating conditions Supply voltage VCC −AGND DVDD −DGND QADVDD, QBDVDD, QCDVDD AGND −DGND MIN NOM MAX 4.75 5 5.25 4.75 5 5.25 2.7 3.3 5.25 −100 0 Vref(RB)+2 Reference input voltage, Vref(RT A), Vref(RT B), Vref(RT C) UNIT V 100 mV VCC V Reference input voltage, Vref(RB A), Vref(RB B), Vref(RB C) 0 Vref(RT)−2 V Analog input voltage, VI 0 Vref(RT) V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High-level pulse duration, tw(H) 25 ns Low-level pulse duration, tw(L) 25 ns Setup time for INIT input, tsu1 5 ns Operating free-air temperature range, TA −20 °C 75 electrical characteristics at QnDVDD = 2.7 V to 5.25 V, DVDD = 5 V, VCC = 5 V, Vref(RT) = 2.5 V, Vref(BB) = 0.5 V, f(CLK) = 20 MHz, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Rref Reference voltage resistor Measured between RT and RB Ci Analog input capacitance IIH High-level input current IIL Low-level input current VI = 1.5 V + 0.07 Vrms DVDD = MAX†, VCC = 5V DVDD = MAX†, VOH High-level output voltage VOL Low-level output voltage IOH(lkg) High-level output leakage current IOL(lkg) Low-level output leakage current ICC Supply current MAX 160 220 VIL = 0, 5 A µA QnDVDD −0.7 V V POST OFFICE BOX 655303 0.8 16 A µA VOL = 0, fc = 20 MSPS, NTSC ramp wave input • DALLAS, TEXAS 75265 Ω pF 5 All QnDVDD terminals = 2.7 V to 5.25 V, IOL = 2 mA QnDVDD = MAX†, VOH = VDD, VCC = 5V QnDVDD = MIN†, VCC = 5V 350 VIH = DVDD, VCC = 5V All QnDVDD terminals = 2.7 V to 5.25 V, IOH = −1 mA UNIT LSB 16 † Conditions marked MIN or MAX are as stated in recommended operating conditions. 6 TYP ±1 Clamp level accuracy 16 50 75 mA 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 operating characteristics at QnDVDD = 2.7 V to 5.25 V, DVDD = 5 V, VCC = 5 V, Vref(RT) = 2.5 V, Vref(RB) = 0.5 V, f(CLK) = 20 MHz, TA = 25°C (unless otherwise noted) PARAMETER EZS EFS TEST CONDITIONS Zero-scale error Vref = REFT − REFB = 2 V Vref = REFT − REFB = 2 V TYP MAX −18 −43 −68 mV mV 0 20 VI = 0.5 V to 2.5 V VI = 0.5 V to 2.5 V ± 0.4 ± 0.75 Linearity error f(CLK) = 20 MHz, f(CLK) = 20 MHz, TA = −20°C to 75°C ± 0.4 ±1 ± 0.5 Linearity error, differential VI = 0.5 V to 2.5 V VI = 0.5 V to 2.5 V ± 0.3 ED f(CLK) = 20 MHz, f(CLK) = 20 MHz, TA = −20°C to 75°C ± 0.3 ± 0.75 fc BW Maximum conversion rate VI = 0.5 V − 2.5 V, At − 1 dB fI = 1-kHz ramp waveform Analog input bandwidth tpd Digital output delay time CL = 10 pF Differential gain NTSC 40 IRE† modulation wave, NTSC 40 IRE† modulation wave, EL Full-scale error MIN Differential phase −20 20 LSB LSB MSPS 14 18 fc = 14.3 MSPS fc = 14.3 MSPS UNIT MHz 30 ns 1% Aperture jitter time Sampling delay time 0.7 deg 30 ps 4 ns † Institute of Radio Engineers detailed description clamp function The clamp function is optimized for a YUV video signal and has two clamp modes. The first mode uses the COMPOSITE SYNC signal as the input to the EXTCLP terminal to generate an internal clamp pulse and the second mode uses an externally generated clamp pulse as the input to the EXTCLP terminal. In the first mode, the device detects false pulses in the COMPOSITE SYNC signal by monitoring the rising and falling edges of the COMPOSITE SYNC signal pulses. This monitoring prevents faulty operation caused by disturbances and missing pulses of the COMPOSITE SYNC signal input on EXTCLP and external spike noise. When fault pulses are detected, the device internally generates a train of clamp pulses at the proper positions (1H) by an internal 910-counter for NTSC and a 1136-counter for PAL. The device checks clamp pulses for 1H time and generates clamp pulses at correct positions when COMPOSITE SYNC pulses are in error in time. The internal counter continually produces a horizontal sync period (1H) that is NTSC or PAL compatible as selected by the condition of the NT/PAL terminal. clamp voltages and selection Table 1 shows the clamping level during the clamp interval. Table 2 shows the selection of the internal or external clamp pulse. With either NTSC or PAL, the internal clamp pulse is always used. Table 1. Clamp Level (Internal Connection Level) CHANNEL OF ADC OUTPUT CODE ADC A • VI(A) 00010000 Y ADC B • VI(B) ADC C • VI(C) 10000000 (U, V) 10000000 (U, V) POST OFFICE BOX 655303 APPLICATION • DALLAS, TEXAS 75265 7 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 clamp voltages and selection (continued) Table 2. Clamp Level (Internal Connection Level) CONDITION CLPEN EXTCLP L H L COMPOSITE SYNC input FUNCTION (EACH ADC) NT/PAL INTERNAL CLAMP CLAMP PULSE Don’t Care Inactive External clamp pulse Don’t Care Inactive No clamping L Active Synchronous with NTSC H Active Synchronous with PAL The clamp circuit is shown in Figure 6. The clamp voltage is stored on capacitor C2 during the back porch of the horizontal blanking period. During the clamp pulse the input to channel A is clamped to: VC(A) = (16/256) × (voltage difference from terminal RT A to RB A) VC(B) = (128/256) × (voltage difference from terminal RT B to RB B) VC(C) = (128/256) × (voltage difference from terminal RT C to RB C) COMPOSITE SYNC time monitoring When CLPEN is high, COMPOSITE SYNC generates an internal clamp pulse on the horizontal blanking interval back porch. The TLC5733A has a timing window into which the horizontal sync tip must occur. There is a noise time window for the falling edge and one for the rising edge (see Figure 1, Figure 2, and Table 3). correct COMPOSITE SYNC timing The noise gate 1 signal provides the timing window for the COMPOSITE SYNC falling edge. After an interval A of 867 clocks for NTSC or 1075 for PAL from the last falling edge of COMPOSITE SYNC, noise gate 1 signal goes high for 43 clocks for NTSC or 61 clocks for PAL (interval B). The falling edge of the input signal to the EXTCLP terminal can occur at any time within this window to be a valid COMPOSITE SYNC falling edge. The noise gate 2 signal provides the timing window for the COMPOSITE SYNC rising edge. On the falling edge of the horizontal sync tip, the internal logic generates noise gate 2 as a low signal for 58 clocks (interval C) for both NTSC and PAL and then returns to a high active state. At this time if the input to EXTCLP is still low, it is considered a valid COMPOSITE SYNC signal. normal clamp pulse generation On the rising edge of COMPOSITE SYNC, the internal logic generates an internal delay (interval D) and then generates the internal positive clamp pulse 54 clocks wide (interval F). clamp operation with incorrect COMPOSITE SYNC timing noise suppression If the input to EXTCLP goes low prior to noise gate 1 going high (within 43 clocks for NTSC or 61 clocks for PAL of the normal 1H timing for the falling edge of COMPOSITE SYNC) then that input is not considered a valid COMPOSITE SYNC and is ignored. If the input to EXTCLP is high when noise gate 2 goes to the high state, the input signal is considered noise and is ignored. Therefore, the correct signal must be high for a maximum of 43 clocks for NTSC or 61 clocks for PAL, before the 1H timing, to be a valid sync signal. Also, the input to EXTCLP must be at least 58 clocks wide (interval C) to be valid. This function of monitoring the timing eliminates spurious noise spikes from falsely synchronizing the system. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 detailed description (continued) timing error of COMPOSITE SYNC The internal counter resets to zero on the first falling edge of COMPOSITE SYNC. After that time, if there is a missing COMPOSITE SYNC signal, then the internal logic waits an interval of 76 clocks (interval E) for NTSC or 93 for PAL from the counter zero count and then generates an internal clamp pulse 54 clocks wide (interval F). This function maintains the synchronization pattern when COMPOSITE SYNC is not present. summary of device operation with COMPOSITE SYNC This internal timing allows the TLC5733A to correctly position the clamp pulse when an external COMPOSITE SYNC input: • • • • Is delayed with respect to the horizontal sync period Is early with respect to the horizontal sync period Is nonexistent during the horizontal sync period Has falling edge noise spikes within the horizontal sync period The device operation is summarized as follows for these improper external clamp conditions: • • Under all four conditions on EXTCLP, the internal clamp generation circuit generates a clamp pulse at the proper time after the horizontal sync period as shown in Figure 1. The TLC5733A internal clamp circuit generates an internal clamp pulse each 1H time for the entire time interval that the COMPOSITE SYNC input is missing. 1H COMPOSITE SYNC B A Missing COMPOSITE SYNC, therefore, Noise Gate is Not Generated Noise Gate 1 C Noise Gate 2 F E F Internal Clamp Pulse D NTSC/PAL Counter Reset NTSC/PAL Counter at Max Count Figure 1. COMPOSITE SYNC and Internal Clamp Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 summary of device operation with COMPOSITE SYNC (continued) COMPOSITE SYNC B Noise Gate 1 Noise Gate 2 Figure 2. Proper COMPOSITE SYNC Timing Table 3. Sync and Clamp Timing for NTSC and PAL With CLK = 4 fsc TIME INTERVAL NTSC fsc = 3.58 MHz PAL fsc = 4.43 MHz NO. OF CLOCKS TIME (µs) NO. OF CLOCKS TIME (µs) A 867 60.6 1075 60.7 B 43 3 61 3.5 C 58 4.05 58 3.27 D 6 0.42 6 0.34 E 76 5.3 93 5.25 F 54 3.77 84 4.74 using an external clamp pulse When CLPEN is taken low, EXTCLP accepts an externally generated active-high clamp pulse. This pulse must occur within the horizontal-blanking interval back porch. CLPEN low inhibits the internal counters and no internal clamp pulse is generated. output digital code (for each channel of ADC) Table 4. Input Signal Versus Digital Output Code 10 DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP Vref(RT) 255 1 1 1 1 1 1 1 1 • • • • • • • • • • • • • • • • • • • • • 128 1 0 0 0 0 0 0 0 • 127 0 1 1 1 1 1 1 1 • • • • • • • • • • MSB LSB • • • • • • • • • • Vref(RB) 0 0 0 0 0 0 0 0 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 detailed description (continued) output data format The TLC5733A can select three output data formats to various TV/VCR (video) data processing by the combination of MODE0 and MODE1. The output is synchronous when INIT is taken high. Table 5. Output Data Format Selection CONDITION MODE0 OUTPUT DATA FORMAT RATIO OF Y:U:V L L Format 1 4:1:1 L H Format 2 4:4:4 H L Format 3 4:2:2 H H Not used N/A MODE1 tw(H) OUTPUT DATA tw(L) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 tsu1 INIT OE A OE B OE C Analog Input VI(ANLG) n+3 n n+4 n+5 n+2 n+1 n+6 n+7 6 fCLK tpd Output Data A A0 INVALID A1 A2 A3 A4 A5 A6 A7 B06 B05 C06 C05 B04 B03 C04 C03 B02 B01 C02 C01 B48 B47 C48 C47 B46 B45 C46 C45 B44 B43 C44 C43 B42 B41 C42 C41 tpd Output Data B BD8 −BD5 INVALID B08 B07 C08 C07 BD4 −BD1: Hi-Z tpd Output Data C CD8 CD7 CD6 −CD1: Hi-Z = Input signal sampling point Figure 3. Format 1, 4:1:1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 output data format (continued) Table 6. Format 1 OUTPUT DATA CHANNEL OF ADC CLK (see Note 1) BIT 6 7 8 9 10 11 12 13 A AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 A08 A07 A06 A05 A04 A03 A02 A01 A18 A17 A16 A15 A14 A13 A12 A11 A28 A27 A26 A25 A24 A23 A22 A21 A38 A37 A36 A35 A34 A33 A32 A31 A48 A47 A46 A45 A44 A43 A42 A41 A58 A57 A56 A55 A54 A53 A52 A51 A68 A67 A66 A65 A64 A63 A62 A61 A78 A77 A76 A75 A74 A73 A72 A71 B BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 B08 B07 C08 C07 Hi-Z Hi-Z Hi-Z Hi-Z B06 B05 C06 C05 Hi-Z Hi-Z Hi-Z Hi-Z B04 B03 C04 C03 Hi-Z Hi-Z Hi-Z Hi-Z B02 B01 C02 C01 Hi-Z Hi-Z Hi-Z Hi-Z B48 B47 C48 C47 Hi-Z Hi-Z Hi-Z Hi-Z B46 B45 C46 C45 Hi-Z Hi-Z Hi-Z Hi-Z B44 B43 C44 C43 Hi-Z Hi-Z Hi-Z Hi-Z B42 B41 C42 C41 Hi-Z Hi-Z Hi-Z Hi-Z C CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 H L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NOTES: 1. The value of the first sampling clock at A/D conversion is CLK 0. 2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and 6 is the bit number. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 output data format (continued) tw(H) tw(L) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 tsu1 INIT OE A OE B OE C Analog Input VI(ANLG) n+3 n n+4 n+5 n+2 n+1 n+6 n+7 6 fCLK tpd Output Data A AD8 −AD1 A0 INVALID A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 tpd Output Data B BD8 −BD1 B0 INVALID tpd Output Data C CD8 −CD1 C0 INVALID = Input signal sampling point Figure 4. Format 2, 4:4:4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 output data format (continued) Table 7. Format 2 OUTPUT DATA CHANNEL OF ADC CLK (see Note 1) BIT 6 7 8 9 10 11 12 13 A AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 A08 A07 A06 A05 A04 A03 A02 A01 A18 A17 A16 A15 A14 A13 A12 A11 A28 A27 A26 A25 A24 A23 A22 A21 A38 A37 A36 A35 A34 A33 A32 A31 A48 A47 A46 A45 A44 A43 A42 A41 A58 A57 A56 A55 A54 A53 A52 A51 A68 A67 A66 A65 A64 A63 A62 A61 A78 A77 A76 A75 A74 A73 A72 A71 B BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 B08 B07 B06 B05 B04 B03 B02 B01 B18 B17 B16 B15 B14 B13 B12 B11 B28 B27 B26 B25 B24 B23 B22 B21 B38 B37 B36 B35 B34 B33 B32 B31 B48 B47 B46 B45 B44 B43 B42 B41 B58 B57 B56 B55 B54 B53 B52 B51 B68 B67 B66 B65 B64 B63 B62 B61 B78 B77 B76 B75 B74 B73 B72 B71 C CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 C08 C07 C06 C05 C04 C03 C02 C01 C18 C17 C16 C15 C14 C13 C12 C11 C28 C27 C26 C25 C24 C23 C22 C21 C38 C37 C36 C35 C34 C33 C32 C31 C48 C47 C46 C45 C44 C43 C42 C41 C58 C57 C56 C55 C54 C53 C52 C51 C68 C67 C66 C65 C64 C63 C62 C61 C78 C77 C76 C75 C74 C73 C72 C71 NOTES: 1. The value of the first sampling clock at A/D conversion is CLK 0. 2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and 6 is the bit number. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 output data format (continued) tw(H) tw(L) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 tsu1 INIT OE A OE B OE C Analog Input VI(ANLG) n+3 n n+4 n+5 n+2 n+1 n+6 n+7 6 fCLK tpd Output Data A AD8 −AD1 A0 INVALID A1 A2 A3 A4 A5 A6 C0 B2 C2 B4 C4 B6 tpd Output Data B BD8 −BD1 INVALID B0 tpd Output Data C CD8 CD7 CD6 − CD1: Hi-Z = Input signal sampling point Figure 5. Format 3, 4:2:2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 output data format (continued) Table 8. Format 3 OUTPUT DATA CHANNEL OF ADC BIT CLK (see Note 1) 6 7 8 9 10 11 12 13 A AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 A08 A07 A06 A05 A04 A03 A02 A01 A18 A17 A16 A15 A14 A13 A12 A11 A28 A27 A26 A25 A24 A23 A22 A21 A38 A37 A36 A35 A34 A33 A32 A31 A48 A47 A46 A45 A44 A43 A42 A41 A58 A57 A56 A55 A54 A53 A52 A51 A68 A67 A66 A65 A64 A63 A62 A61 A78 A77 A76 A75 A74 A73 A72 A71 B BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 B08 B07 B06 B05 B04 B03 B02 B01 C08 C07 C06 C05 C04 C03 C02 C01 B28 B27 B26 B25 B24 B23 B22 B21 C28 C27 C26 C25 C24 C23 C22 C21 B48 B47 B46 B45 B44 B43 B42 B41 C48 C47 C46 C45 C44 C43 C42 C41 B68 B67 B66 B65 B64 B63 B62 B61 C68 C67 C66 C65 C64 C63 C62 C61 C CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 H L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L H Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NOTES: 1. The value of the first sampling clock at A/D conversion is CLK 0. 2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and 6 is the bit number. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 APPLICATION INFORMATION Feed Back Clamp Block of HSYNC CLK Vref (Top) C2 0.22 µF Video Signal Input (Composite or Component) A/D AIN Vref (Bottom) Digital Feedback _ + Clamp Gate R1 16 kΩ P Output Q C1 2200 pF Preset Data Magnitude Comparator FEEDBACK CLAMP AND CHARGE PUMP ACTIVITY INPUT DATA CONDITIONS OUTPUT CHARGE PUMP CONDITIONS PQ Active L Discharge Figure 6. Feedback Clamp Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 APPLICATION INFORMATION Channel−A TLC5733A 16 kΩ PNP: 2SA733 NPN: 2SC1815 2.2 kΩ 110 Ω 4.3 kΩ 1.8 kΩ C2 10 µF 10 µF Analog Signal Input 63 1 kΩ 1VI(PP) VIN(A) 2VI(PP) CW 75 Ω 470 Ω 5.6 kΩ Gain Adjust 5.6 kΩ 5.6 kΩ 1.8 kΩ Buffer Amplifier 60 C2 0.22 µF TLC5733A R1 15 kΩ ADC Channel−A to Channel−C Buffer Amp R1 59 CLPV(A) CLP OUT(A) C1 2 OE(A) C1 2200 pF Channel−B Channel−C 55 56 CLK IN 57 58 3 4 Figure 7. Interface Without Clamping 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EXTCLP CLK CLPEN INIT NT/PAL TEST 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 APPLICATION INFORMATION Channel−A TLC5733A 16 kΩ PNP: 2SA733 NPN: 2SC1815 2.2 kΩ 110 Ω 4.3 kΩ 1.8 kΩ C2 10 µF 10 µF Analog Signal Input 63 1 kΩ 1VI(PP) VIN(A) 2VI(PP) CW 75 Ω 470 Ω 5.6 kΩ Gain Adjust 5.6 kΩ 1.8 kΩ Buffer Amplifier 60 C2 0.22 µF TLC5733A R1 15 kΩ ADC Channel−A to Channel−C Buffer Amp R1 59 CLPV(A) CLP OUT A C1 2 OE(A) C1 2200 pF Channel−B Channel−C 10 µF Composite SYNC 0V 55 + EXTCLP 1 kΩ −5 V 0V 56 CLK IN 57 58 3 4 CLK CLPEN INIT NT/PAL TEST Figure 8. Interface Connection Using Composite Sync Signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 APPLICATION INFORMATION Channel−A TLC5733A 16 kΩ PNP: 2SA733 NPN: 2SC1815 2.2 kΩ 110 Ω 4.3 kΩ 1.8 kΩ C2 10 µF 10 µF Analog Signal Input 63 1 kΩ 1VI(PP) VIN(A) 2VI(PP) CW 75 Ω 5.6 kΩ 470 Ω Gain Adjust 5.6 kΩ 1.8 kΩ Buffer Amplifier 60 C2 0.22 µF TLC5733A R1 15 kΩ ADC Channel−A to Channel−C Buffer Amp R1 59 CLPV(A) CLP OUT A C1 2 OE(A) C1 2200 pF Channel−B Channel−C D Clamp Pulse IN Q 55 56 CLK IN 57 58 3 4 Figure 9. Interface Using External Clamp Pulse With Synchronization 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EXTCLP CLK CLPEN INIT NT/PAL TEST 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 APPLICATION INFORMATION AVDD ADC Block VRT(A) 61 ADC Block VRT(B) 52 ADC Block VRT(C) 29 + _ RREF VRB(A) 1 VRB(B) 48 VRB(C) 33 + _ Figure 10. Adjustment Circuit For Top and Bottom Reference Voltages POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 
     
 
 
 
     SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 MECHANICAL DATA PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 Gage Plane 0,25 0,05 MIN 0°−ā 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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