TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIER
FEATURES
1
• Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
• Extended Temperature Performance of
–55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree(1)
2
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
TLE2141
D PACKAGE
(TOP VIEW)
OFFSET N1
ININ+
VCC-
1
8
2
7
3
6
4
5
•
•
•
•
•
•
•
•
•
•
Low Noise
– 10 Hz...15 nV/√Hz
– 1 kHz...10.5 nV/√Hz
10 000-pF Load Capability
20-mA (Min) Short-Circuit Output Current
27-V/µs Slew Rate (Min)
High Gain-Bandwidth Product...5.9 MHz
Low VIO...900 µV (Max) at 25°C
Single or Split Supply...4 V to 44 V
Fast Settling Time
– 340 ns to 0.1%
– 400 ns to 0.01%
Saturation Recovery...150 ns
Large Output Swing...
VCC– + 0.1 V to VCC+ – 1 V
TLE2142
D PACKAGE
(TOP VIEW)
NC
VCC+
OUT
OFFSET N2
1OUT
1IN1IN+
VCC-
1
8
2
7
3
6
4
5
TLE2144
DW PACKAGE
(TOP VIEW)
VCC+
2OUT
2IN2IN+
1OUT
1IN1IN+
VCC+
2IN+
2IN2OUT
NC
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
4OUT
4IN4IN+
VCC3IN+
3IN3OUT
NC
NC – No internal connection
DESCRIPTION
The TLE214x devices are high-performance, internally compensated operational amplifiers built using the Texas
Instruments complementary bipolar Excalibur™ process. They are pin-compatible upgrades to standard industry
products.
The design incorporates an input stage that simultaneously achieves low audio-band noise of 10.5 nV/√Hz with a
10-Hz 1/f corner and symmetrical 40-V/µs slew rate typically with loads up to 800 pF. The resulting low distortion
and high power bandwidth are important in high-fidelity audio applications. A fast settling time of 340 ns to 0.1%
of a 10-V step with a 2-kΩ/100-pF load is useful in fast actuator/positioning drivers. Under similar test conditions,
settling time to 0.01% is 400 ns.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excalibur is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
The devices are stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz
at this high loading level. As such, the TLE214x are useful for low-droop sample-and-holds and direct buffering of
long cables, including 4-mA to 20-mA current loops.
The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as
is evidenced by a 900-µV maximum offset voltage and 1.7-µV/°C typical drift. Minimum common-mode rejection
ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.
Device performance is relatively independent of supply voltage over the ±2-V to ±22-V range. Inputs can operate
between VCC– – 0.3 V to VCC+ – 1.8 V without inducing phase reversal, although excessive input current may flow
out of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearly
rail-to-rail output swing of VCC– – 0.1 V to VCC+ – 1 V under light current-loading conditions. The device can
sustain shorts to either supply since output current is internally limited, but care must be taken to ensure that
maximum package power dissipation is not exceeded.
Both versions can also be used as comparators. Differential inputs of VCC± can be maintained without damage to
the device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good indication
as to output stage saturation recovery when the device is driven beyond the limits of recommended output swing.
The TLE214x devices are available in industry-standard 8-pin and 16-pin small-outline packages. The devices
are characterized for operation from –55°C to 125°C.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
Single
–55°C to 125°C
(1)
(2)
(3)
SOIC – D (8 pin)
ORDERABLE PART NUMBER
Reel of 2500
TLE2141MDREP
TOP-SIDE MARKING
2141EP
(3)
Dual
SOIC – D (8 pin)
Reel of 2500
TLE2142MDREP
Quad
SOIC – DW (16 pin)
Reel of 2000
TLE2144MDWREP (3)
TBD
TBD
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Product Preview. Contact your TI sales representative for availability.
SYMBOL
OFFSET N1
IN+
+
IN-
-
OUT
OFFSET N2
A.
2
OFFSET N1 and OFFSET N2 are available only on the TLE2141.
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Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
Q33
Q32
Q31
8
4
1
Diodes
Capacitors
Epi-FET
2
14
24
Resistors
16
86
65
43
46
Transistors
28
130
TLE2142
TLE2141
1
8
DEVICE COMPONENT COUNT
VCC -
COMPONENT
Q17
Q7
R5
C1
Q9
Q12
Q11
Q4
Q2
Q6
OFFSET N2
OFFSET N1
IN +
IN -
Q1
R2
D1
Q3
R1
A.
R10
Q16
Q15
Q14
R8
R3
Q5 Q8
R4
R6
Q10
D2
Q13
R7
R9
C2
R11
Q18
VCC +
Q19
R12
Q20
Q21
C3
C4
Q24
D5
TLE2144
Q29
D7
D6
Q28
Q25
R13
D3
D4
Q22
R14
R16
R17
Q23
R15
Q27
Q26
R18
D8
Q30
R20
R22
Q35
R23
Q36
Q37
R19
Q34
R21
R24
OUT
EQUIVALENT SCHEMATIC
OFFSET N1 and OFFSET N2 are available only on the TLE2141.
Copyright © 2008, Texas Instruments Incorporated
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3
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC+
Supply voltage (2)
22 V
VCC–
Supply voltage
–22 V
VID
Differential input voltage (3)
±44 V
VI
Input voltage range (any input)
II
Input current (each input)
±1 mA
IO
Output current
±80 mA
Total current into VCC+
80 mA
VCC+ V to (VCC– – 0.3) V
Total current out of VCC–
80 mA
Duration of short-circuit current at (or below) 25°C (4)
Unlimited
D package
97.1°C/W
θJA
Package thermal impedance (5) (6)
TA
Operating free-air temperature range
–55°C to 125 °C
Tstg
Storage temperature range (7)
–65°C to 150 °C
DW package
57.3°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
(4)
(5)
(6)
(7)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
Differential voltages are at IN+ with respect to IN–. Excessive current flows, if input, are brought below VCC– – 0.3 V.
The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Long-term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced product packaging.
RECOMMENDED OPERATING CONDITIONS
VCC±
Supply voltage
VIC
Common-mode input voltage
TA
Operating free-air temperature
4
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VCC = 5 V
VCC± = ±15 V
MIN
MAX
UNIT
±2
±22
V
0
2.7
–15
12.7
–55
125
V
°C
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
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TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
TLE2141 ELECTRICAL CHARACTERISTICS
VCC = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
αVIO
Temperature coefficient of
input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIO
Input offset current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIB
Input bias current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
VICR
Common-mode input
voltage range
TLE2141
TA (1)
MIN
25°C
25°C
8
Full range
25°C
–0.8
25°C
–0.3 to
3.2
0 to 2.7
–0.3 to
2.9
3.9
4.1
3.8
4
IOH = –15 mA
3.2
3.7
IOH = –100 µA
3.75
Full range
IOH = –10 mA
25°C
V
75
125
225
1.2
1.6
200
Full range
250
IOL = 10 mA
VIC = 2.5 V, RL = 2 kΩ,
VO = 1 V to –1.5 V
µA
V
150
IOL = 100 µA
IOL = 1 mA
–2
nA
3.25
IOL = 15 mA
Low-level output voltage
µV
3.65
IOL = 150 µA
IOL = 1.5 mA
100
–2.3
0 to 3
UNIT
µV/°C
250
Full range
Full range
IOH = –1 mA
VOL
1400
1.7
RS = 50 Ω
High-level output voltage
225
2100
Full range
IOH = –150 µA
VOH
MAX
Full range
25°C
IOH = –1.5 mA
TYP
1.25
25°C
50
Full range
5
220
mV
V
mV
V
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
70
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
f = 1 MHz
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
ICC
Supply current
VO = 2.5 V, No load, VIC = 2.5 V
(1)
25°C
25°C
85
Full range
80
25°C
90
Full range
85
25°C
118
dB
106
3.4
Full range
V/mV
dB
4.4
4.6
mA
Full range is –55°C to 125°C.
Copyright © 2008, Texas Instruments Incorporated
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TLE2141-EP
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TLE2144-EP
SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
TLE2141 OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
SR+
SR–
TLE2141
TEST CONDITIONS
MIN
AVD = –1, RL = 2 kΩ (1), CL = 500 pF
Positive slew rate
(1)
Negative slew rate
AVD = –1, RL = 2 kΩ , CL = 500 pF
TYP
V/µs
42
V/µs
0.16
To 0.01%
0.22
ts
Settling time
AVD = –1, 2.5-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
VN(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.92
f = 1 kHz
0.5
THD+N
Total harmonic distortion plus noise
B1
(1)
f = 10 Hz
15
f = 1 kHz
10.5
Unity-gain bandwidth
RL = 2 kΩ , CL = 100 pF
Gain-bandwidth product
RL = 2 kΩ (1), CL = 100 pF (1), f = 100 kHz
(1)
BOM
Maximum output-swing bandwidth
VO(PP) = 2 V, RL = 2 kΩ , AVD = 1
φm
Phase margin at unity gain
RL = 2 kΩ (1), CL = 100 pF (1)
(1)
6
0.0052
(1)
UNIT
45
To 0.1%
VO = 1 V to 3 V, RL = 2 kΩ (1), AVD = 2,
f = 10 kHz
MAX
µs
nV/√Hz
µV
pA/√Hz
%
5.9
MHz
5.8
MHz
660
kHz
57
°
RL and CL terminated to 2.5 V.
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TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
TLE2141 ELECTRICAL CHARACTERISTICS
VCC = ±15 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VIC = 0, RS = 50 Ω
αVIO
Temperature coefficient of
input offset voltage
VIC = 0, RS = 50 Ω
IIO
Input offset current
VIC = 0, RS = 50 Ω
IIB
Input bias current
VIC = 0, RS = 50 Ω
VICR
Common-mode input
voltage range
TLE2141
TA (1)
MIN
25°C
7
25°C
–0.7
–15 to –15.3 to
13
13.2
Full range
–15 to –15.3 to
12.7
12.9
13.8
14
IO = –15 mA
13.1
13.7
IO = –100 µA
13.7
Full range
µV
nA
µA
V
14.1
13.7
IO = –10 mA
–1.5
–1.8
25°C
25°C
100
250
Full range
UNIT
µV/°C
1.7
25°C
IO = –1 mA
V
13.6
13.1
IO = 150 µA
–14.7
–14.9
–14.5
–14.8
IO = 15 mA
–13.4
–13.8
IO = 100 µA
–14.6
IO = 1.5 mA
Maximum negative peak
output voltage swing
900
Full range
IO = –1.5 mA
VOM–
200
1700
Full range
RS = 50 Ω
Maximum positive peak
output voltage swing
MAX
Full range
IO = –150 µA
VOM+
TYP
25°C
IO = 1 mA
Full range
IO = 10 mA
V
–14.5
–13.4
25°C
100
Full range
20
450
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
65
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
VO = ±10 V, RL = 2 kΩ
f = 1 MHz
25°C
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
IOS
Short-circuit output current
VO = 0
ICC
Supply current
VO = 0, No load, VIC = 2.5 V
(1)
VID = 1 V
VID = –1 V
25°C
85
Full range
80
25°C
90
Full range
85
25°C
25°C
108
dB
106
–25
–50
20
31
3.5
Full range
V/mV
dB
mA
4.5
4.7
mA
Full range is –55°C to 125°C.
Copyright © 2008, Texas Instruments Incorporated
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SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
TLE2141 OPERATING CHARACTERISTICS
VCC = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TLE2141
TEST CONDITIONS
SR+
Positive slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
TYP
27
45
V/µs
42
V/µs
27
To 0.1%
0.34
To 0.01%
0.4
MAX
UNIT
MIN
µs
ts
Settling time
AVD = –1, 10-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
VN(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.89
f = 1 kHz
0.47
THD+N
Total harmonic distortion plus noise
VO(PP) = 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz
0.01
B1
Unity-gain bandwidth
RL = 2 kΩ, CL = 100 pF
6
MHz
Gain-bandwidth product
RL = 2 kΩ, CL = 100 pF, f = 100 kHz
5.9
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 20 V, AVD = 1, RL = 2 kΩ, CL = 100 pF
668
kHz
φm
Phase margin at unity gain
RL = 2 kΩ, CL = 100 pF
58
°
8
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f = 10 Hz
15
f = 1 kHz
10.5
nV/√Hz
µV
pA/√Hz
%
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
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TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
TLE2142 ELECTRICAL CHARACTERISTICS
VCC = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
αVIO
Temperature coefficient of
input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIO
Input offset current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIB
Input bias current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
VICR
Common-mode input
voltage range
TLE2142
TA (1)
MIN
25°C
25°C
8
Full range
25°C
–0.8
25°C
–0.3 to
3.2
0 to 2.7
–0.3 to
2.9
3.9
4.1
3.8
4
IOH = –15 mA
3.4
3.7
IOH = –100 µA
3.75
Full range
IOH = –10 mA
25°C
µA
V
V
75
125
150
225
1.2
1.4
IOL = 100 µA
IOL = 1 mA
–2
nA
3.45
IOL = 15 mA
Low-level output voltage
µV
3.65
IOL = 150 µA
IOL = 1.5 mA
100
–2.3
0 to 3
UNIT
µV/°C
200
Full range
Full range
IOH = –1 mA
VOL
1900
1.7
RS = 50 Ω
High-level output voltage
220
2600
Full range
IOH = –150 µA
VOH
MAX
Full range
25°C
IOH = –1.5 mA
TYP
200
Full range
250
IOL = 10 mA
1.25
25°C
50
Full range
5
220
mV
V
mV
V
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
70
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
VIC = 2.5 V, RL = 2 kΩ, VO = 1 V to 1.5 V
f = 1 MHz
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
ICC
Supply current
VO = 2.5 V, No load, VIC = 2.5 V
(1)
25°C
25°C
85
Full range
80
25°C
90
Full range
85
25°C
118
dB
106
6.6
Full range
V/mV
dB
8.8
9.2
mA
Full range is –55°C to 125°C.
Copyright © 2008, Texas Instruments Incorporated
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SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
TLE2142 OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
SR+
SR–
TLE2142
TEST CONDITIONS
MIN
AVD = –1, RL = 2 kΩ (1), CL = 500 pF
Positive slew rate
(1)
Negative slew rate
AVD = –1, RL = 2 kΩ , CL = 500 pF
TYP
V/µs
42
V/µs
0.16
To 0.01%
0.22
ts
Settling time
AVD = –1, 2.5-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
VN(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.92
f = 1 kHz
0.5
THD+N
Total harmonic distortion plus noise
B1
f = 10 Hz
15
f = 1 kHz
10.5
0.0052
(1)
nV/√Hz
µV
pA/√Hz
%
RL = 2 kΩ , CL = 100 pF
5.9
MHz
Gain-bandwidth product
RL = 2 kΩ (1), CL = 100 pF, f = 100 kHz
5.8
MHz
(1)
660
kHz
57
°
Maximum output-swing bandwidth
VO(PP) = 2 V, RL = 2 kΩ , AVD = 1, CL = 100 pF
φm
Phase margin at unity gain
RL = 2 kΩ (1), CL = 100 pF
10
µs
Unity-gain bandwidth
BOM
(1)
UNIT
45
To 0.1%
VO = 1 V to 3 V, RL = 2 kΩ (1), AVD = 2,
f = 10 kHz
MAX
RL terminated at 2.5 V.
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TLE2142-EP
TLE2144-EP
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TLE2142 ELECTRICAL CHARACTERISTICS
VCC = ±15 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VIC = 0, RS = 50 Ω
αVIO
Temperature coefficient of
input offset voltage
VIC = 0, RS = 50 Ω
IIO
Input offset current
VIC = 0, RS = 50 Ω
IIB
Input bias current
VIC = 0, RS = 50 Ω
VICR
Common-mode input
voltage range
TLE2142
TA (1)
MIN
25°C
7
25°C
–0.7
–15 to –15.3 to
13
13.2
Full range
–15 to –15.3 to
12.7
12.9
13.8
14
IO = –15 mA
13.3
13.7
IO = –100 µA
13.7
Full range
µV
nA
µA
V
14.1
13.7
IO = –10 mA
–1.5
–1.8
25°C
25°C
100
250
Full range
UNIT
µV/°C
1.7
25°C
IO = –1 mA
V
13.6
13.3
IO = 150 µA
–14.7
–14.9
–14.5
–14.8
IO = 15 mA
–13.4
–13.8
IO = 100 µA
–14.6
IO = 1.5 mA
Maximum negative peak
output voltage swing
1200
Full range
IO = –1.5 mA
VOM–
290
2000
Full range
RS = 50 Ω
Maximum positive peak
output voltage swing
MAX
Full range
IO = –150 µA
VOM+
TYP
25°C
IO = 1 mA
Full range
IO = 10 mA
V
–14.5
–13.4
25°C
100
Full range
20
450
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
65
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
VO = ±10 V, RL = 2 kΩ
f = 1 MHz
25°C
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
IOS
Short-circuit output current
VO = 0
ICC
Supply current
VO = 0, No load, VIC = 2.5 V
(1)
VID = 1 V
VID = –1 V
25°C
85
Full range
80
25°C
90
Full range
85
25°C
25°C
108
dB
106
–25
–50
20
31
6.9
Full range
V/mV
dB
mA
9
9.4
mA
Full range is –55°C to 125°C.
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TLE2142 OPERATING CHARACTERISTICS
VCC = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TLE2142
TEST CONDITIONS
SR+
Positive slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
TYP
27
45
V/µs
42
V/µs
27
To 0.1%
0.34
To 0.01%
0.4
MAX
UNIT
MIN
µs
ts
Settling time
AVD = –1, 10-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
Vn(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.89
f = 1 kHz
0.47
THD+N
Total harmonic distortion plus noise
VO(PP) = 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz
0.01
B1
Unity-gain bandwidth
RL = 2 kΩ, CL = 100 pF
6
MHz
Gain-bandwidth product
RL = 2 kΩ, CL = 100 pF, f = 100 kHz
5.9
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 20 V, AVD = 1, RL = 2 kΩ, AVD = 1,
CL = 100 pF
668
kHz
φm
Phase margin at unity gain
RL = 2 kΩ, CL = 100 pF
58
°
12
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f = 10 Hz
15
f = 1 kHz
10.5
nV/√Hz
µV
pA/√Hz
%
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TLE2144 ELECTRICAL CHARACTERISTICS
VCC = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
αVIO
Temperature coefficient of
input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIO
Input offset current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIB
Input bias current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
VICR
Common-mode input
voltage range
TLE2144
TA (1)
MIN
25°C
25°C
8
Full range
25°C
–0.8
25°C
–0.3 to
3.2
0 to 2.7
–0.3 to
2.9
3.9
4.1
3.8
4
IOH = –15 mA
3.4
3.7
IOH = –100 µA
3.75
Full range
IOH = –10 mA
25°C
V
75
125
225
1.2
1.6
200
Full range
250
IOL = 10 mA
VIC = 2.5 V, RL = 2 kΩ,
VO = 1 V to –1.5 V
µA
V
150
IOL = 100 µA
IOL = 1 mA
–2
nA
3.45
IOL = 15 mA
Low-level output voltage
mV
3.65
IOL = 150 µA
IOL = 1.5 mA
100
–2.3
0 to 3
UNIT
µV/°C
250
Full range
Full range
IOH = –1 mA
VOL
3.8
1.7
RS = 50 Ω
High-level output voltage
0.5
5.2
Full range
IOH = –150 µA
VOH
MAX
Full range
25°C
IOH = –1.5 mA
TYP
1.45
25°C
50
Full range
5
95
mV
V
mV
V
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
70
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
3.
Ω
f = 1 MHz
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
ICC
Supply current
VO = 2.5 V, No load, VIC = 2.5 V
(1)
25°C
25°C
85
Full range
80
25°C
90
Full range
85
25°C
118
dB
106
13.2
Full range
V/mV
dB
17.6
18.4
mA
Full range is –55°C to 125°C.
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TLE2144 OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
SR+
SR–
TLE2144
TEST CONDITIONS
MIN
AVD = –1, RL = 2 kΩ (1), CL = 500 pF
Positive slew rate
(1)
Negative slew rate
AVD = –1, RL = 2 kΩ , CL = 500 pF
TYP
V/µs
42
V/µs
0.16
To 0.01%
0.22
ts
Settling time
AVD = –1, 2.5-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
VN(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.92
f = 1 kHz
0.5
THD+N
Total harmonic distortion plus noise
B1
f = 10 Hz
15
f = 1 kHz
10.5
nV/√Hz
µV
pA/√Hz
%
RL = 2 kΩ , CL = 100 pF
5.9
MHz
Gain-bandwidth product
RL = 2 kΩ (1), CL = 100 pF, f = 100 kHz
5.8
MHz
(1)
660
kHz
57
°
Maximum output-swing bandwidth
VO(PP) = 2 V, RL = 2 kΩ , AVD = 1
φm
Phase margin at unity gain
RL = 2 kΩ (1), CL = 100 pF
14
µs
Unity-gain bandwidth
BOM
(1)
0.0052
(1)
UNIT
45
To 0.1%
VO = 1 V to 3 V, RL = 2 kΩ (1), AVD = 2,
f = 10 kHz
MAX
RL terminated at 2.5 V.
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TLE2144 ELECTRICAL CHARACTERISTICS
VCC = ±15 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VIC = 0, RS = 50 Ω
αVIO
Temperature coefficient of
input offset voltage
VIC = 0, RS = 50 Ω
IIO
Input offset current
VIC = 0, RS = 50 Ω
IIB
Input bias current
VIC = 0, RS = 50 Ω
VICR
Common-mode input
voltage range
TLE2144
TA (1)
MIN
25°C
4
1.7
25°C
7
25°C
–0.7
–15 to –15.3 to
13
13.2
Full range
–15 to –15.3 to
12.7
12.9
13.8
25°C
14
IO = –15 mA
13.1
13.7
IO = –100 µA
13.7
Full range
mV
–1.5
nA
µA
V
14.1
13.7
IO = –10 mA
100
–1.8
25°C
UNIT
µV/°C
250
Full range
IO = –1 mA
V
13.6
13.1
IO = 150 µA
–14.7
–14.9
–14.5
–14.8
IO = 15 mA
–13.4
–13.8
IO = 100 µA
–14.6
IO = 1.5 mA
Maximum negative peak
output voltage swing
2.4
Full range
IO = –1.5 mA
VOM–
0.6
25°C
RS = 50 Ω
Maximum positive peak
output voltage swing
MAX
Full range
IO = –150 µA
VOM+
TYP
25°C
IO = 1 mA
Full range
IO = 10 mA
V
–14.5
–13.4
25°C
100
Full range
20
170
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
65
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
VO = ±10 V, RL = 2 kΩ
f = 1 MHz
25°C
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
IOS
Short-circuit output current
VO = 0
ICC
Supply current
VO = 0, No load, VIC = 2.5 V
(1)
VID = 1 V
VID = –1 V
25°C
85
Full range
80
25°C
90
Full range
85
25°C
25°C
108
dB
106
–25
–50
20
31
13.8
Full range
V/mV
dB
mA
18
18.8
mA
Full range is –55°C to 125°C.
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TLE2144 OPERATING CHARACTERISTICS
VCC = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TLE2144
TEST CONDITIONS
SR+
Positive slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
TYP
27
45
V/µs
42
V/µs
27
To 0.1%
0.34
To 0.01%
0.4
MAX
UNIT
MIN
µs
ts
Settling time
AVD = –1, 10-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
Vn(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.89
f = 10 kHz
0.47
THD+N
Total harmonic distortion plus noise
VO(PP) = 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz
0.01
B1
Unity-gain bandwidth
RL = 2 kΩ, CL = 100 pF
6
MHz
Gain-bandwidth product
RL = 2 kΩ, CL = 100 pF, f = 100 kHz
5.9
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 20 V, AVD = 1, RL = 2 kΩ, CL = 100 pF
668
kHz
φm
Phase margin at unity gain
RL = 2 kΩ, CL = 100 pF
58
°
16
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f = 10 Hz
15
f = 1 kHz
10.5
nV/√Hz
µV
pA/√Hz
%
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www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
TYPICAL CHARACTERISTICS
Table of Graphs
VIO
Input offset voltage
Distribution
Figure 1,
Figure 2,
Figure 3
IIO
Input offset current
vs Free-air temperature
Figure 4
vs Common-mode input voltage
Figure 5
vs Free-air temperature
Figure 6
vs Supply voltage
Figure 7
vs Free-air temperature
Figure 8
vs Output current
Figure 9
vs Settling time
Figure 11
vs Supply voltage
Figure 7
IIB
VOM+
Input bias current
Maximum positive peak output voltage
vs Free-air temperature
Figure 8
vs Output current
Figure 10
VOM–
Maximum negative peak output voltage
vs Settling time
Figure 11
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
Figure 12
VOH
High-level output voltage
vs Output current
Figure 13
VOL
Low-level output voltage
vs Output current
Figure 14
Phase shift
vs Frequency
Figure 15
vs Frequency
Figure 15
AVD
Large-signal differential voltage amplification
vs Free-air temperature
Figure 16
zo
Closed-loop output impedance
vs Frequency
Figure 17
IOS
Short-circuit output current
vs Free-air temperature
Figure 18
vs Frequency
Figure 19
vs Free-air temperature
Figure 20
vs Frequency
Figure 21
vs Free-air temperature
Figure 22
vs Supply voltage
Figure 23
vs Free-air temperature
Figure 24
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
ICC
Supply current
Vn
Equivalent input noise voltage
vs Frequency
Figure 25
Vn
Input noise voltage
Over a 10-second period
Figure 26
In
Noise current
vs Frequency
Figure 27
THD+N
Total harmonic distortion plus noise
vs Frequency
Figure 28
vs Free-air temperature
Figure 29
SR
Slew rate
Pulse response
B1
φm
vs Load capacitance
Figure 30
Noninverting large signal
vs Time
Figure 31
Inverting large signal
vs Time
Figure 32
Small signal
vs Time
Figure 33
Unity-gain bandwidth
vs Load capacitance
Figure 34
Gain margin
vs Load capacitance
Figure 35
Phase margin
vs Load capacitance
Figure 36
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TLE2141
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
TLE2142
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
24
20
Percentage of Units − %
Percentage of Units − %
20
24
236 Units Tested From 1 Wafer Lot
VCC ± = ± 15 V
TA = 25°C
P Package
16
12
8
4
236 Units Tested From 1 Wafer Lot
VCC ± = ± 15 V
TA = 25°C
P Package
16
12
8
4
0
−800
0
−400
400
0
−800 −600
800
VIO − Input Offset Voltage − µV
200 400 600
−400 −200 0
VIO − Input Offset Voltage − µV
Figure 1.
Figure 2.
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
TLE2144
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
20
24
250 Units Tested From 1 Wafer Lot
VCC ± = ± 15 V
TA = 25°C
N Package
18
IIIO
IO − Input Offset Current − nA
Percentage of Units − %
20
800
16
12
8
4
VO = 0
VIC = 0
16
14
12
10
VCC ± = ± 2.5 V
8
6
VCC ± = ± 15 V
4
2
0
− 2 −1.6 −1.2 −0.8 −0.4
0
0.4 0.8 1.2 1.6
VIO − Input Offset Voltage − mV
2
0
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 3.
18
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Figure 4.
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INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
−1000
0
VCC ± = ± 2.5 V
VO = 0
VIC = 0
IIIB
IB − Input Bias Current − nA
uA
IIIB
IB − Input Bias Current − µA
−0.2
−0.4
−0.6
TA = 125°C
−0.8
TA = 25°C
−1
TA = − 55°C
−1.2
−1.4
−3
−2.5 −2
−1.5 −1 −0.5
0
0.5
VIC − Common-Mode Input Voltage − V
−900
VCC ± = ± 2.5 V
−800
−700
VCC ± = ± 15 V
−600
−500
−75 −50 −25
0
25
50 75 100 125 150
TA − Free-Air Temperature − °C
1
Figure 5.
Figure 6.
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
15
RL = 2 kΩ
TA = 25°C
18
VCC ± = ± 15 V
V OM − Maximum Peak Output Voltage − V
V OM − Maximum Peak Output Voltage − V
24
12
VOM +
6
0
−6
VOM −
−12
−18
− 24
0
3
6
9
12
15
18
VCC ± − Supply Voltage − V
Figure 7.
Copyright © 2008, Texas Instruments Incorporated
21
24
14.6
RL = ∞
14.2
VOM +
13.8
RL = 2 kΩ
−13.8
−14.2
−14.6
RL = 2 kΩ
VOM −
RL = ∞
−15
−75 −50 −25
0
25
50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 8.
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MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
14.6
VCC ± = ± 15 V
14.4
14.2
TA = 125°C
14
TA = 25°C
TA = − 55°C
13.8
13.6
−0.1
−0.4
−1
−4
−10
− 40
−100
V OM − − Maximum Negative Peak Output Voltage − V
V OM + − Maximum Positive Peak Output Voltage − V
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
−13.4
VCC ± = ± 15 V
−13.6
−13.8
TA = 125°C
−14
−14.2
TA = − 55°C
−14.4
−14.6
−14.8
− 15
0.1
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SETTLING TIME
0.1%
0.01%
5
2.5
Rising
0
Falling
−2.5
0.01%
−5
0.1%
−7.5
−10
−12.5
0
100
200
300
ts − Settling Time − ns
Figure 11.
20
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400
500
V O(PP) − Maximum Peak-to-Peak Output Voltage − V
VVOM
OM − Maximum Peak Output Voltage − V
7.5
1
4
10
40
100
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
AVD = −1
VCC ± = ± 15 V
TA = 25°C
10
0.4
IO − Output Current − mA
Figure 10.
IO − Output Current − mA
Figure 9.
12.5
TA = 25°C
30
VCC ± = ± 15 V
RL = 2 kΩ
25
TA = 25°C
20
TA = 125°C
15
10
TA = − 55°C
5
0
100 k
400 k
1M
4M
10 M
f − Frequency − Hz
Figure 12.
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HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4.6
1400
VCC = 5 V
VOL
V
OL − Low-Level Output Voltage − mV
V OH − High-Level Output Voltage − V
VCC = 5 V
4.4
TA = 125°C
4.2 TA = 25°C
4 TA = − 55°C
3.8
3.6
1200
TA = 125°C
1000
800
600
TA = 25°C
400
200
TA = − 55°C
3.4
−0.1
−1
−10
0
0.1
−100
IO − Output Current − mA
1
Figure 13.
20°
100
40°
90
60°
80 Phase Shift
80°
70
100°
120°
AVD
50
140°
40
160°
180°
30
VCC ± = ± 15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
10
0
200°
220°
240°
− 10
1
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
260°
10 M
140
VCC ± = ± 15 V
VO = ± 10 V
AAVD
VD − Large-Signal Differential
Voltage Amplification − dB
0°
110
Phase Shift
AAVD
VD − Large-Signal Differential
Voltage Amplification − dB
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
120
20
RL = 10 kΩ
120
RL = 2 kΩ
100
80
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 15.
Copyright © 2008, Texas Instruments Incorporated
100
Figure 14.
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
60
10
IO − Output Current − mA
Figure 16.
Submit Documentation Feedback
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
21
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
60
100
VCC ± = ± 15 V
VO = 0
IOS − Short-Circuit Output Current − mA
z o − Closed-Loop Output Impedance − Ω
30 Ω
10
1
AVD = 100
0.1
AVD = 10
AVD = 1
0.01
0.001
1k
10 k
100 k
1M
50
VID = 1
40
30
VID = − 1
20
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
10 M
f − Frequency − Hz
Figure 17.
Figure 18.
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
120
100
80
60
40
20
0
100
1k
10 k
f − Frequency − Hz
Figure 19.
22
120
VCC ± = ± 15 V
TA = 25°C
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
140
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
Submit Documentation Feedback
100 k
1M
VIC = VICRmin
VCC = 5 V
116
112
108
VCC ± = ± 15 V
104
100
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 20.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
110
kkSVR
SVR − Supply-Voltage Rejection Ratio − dB
kkSVR
SVR − Supply-Voltage Rejection Ratio − dB
160
140
kSVR +
120
kSVR −
100
80
60
40
20 VCC ± = ± 2.5 V to ± 15 V
TA = 25°C
0
10
100
1k
10 k
100 k
1M
VCC ± = ± 2.5 V to ± 15 V
108
106
104
102
100
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
10 M
f − Frequency − Hz
Figure 21.
Figure 22.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4
3.8
VO = 0
No Load
TA = 125°C
IIDD
CC − Supply Current − mA
IIDD
CC − Supply Current − mA
3.6
3.5
TA = 25°C
3
TA = − 55°C
2.5
VCC ± = ± 15 V
3.4
VCC ± = ± 2.5 V
3.2
3
VO = 0
No Load
2
0
4
8
12
16
20
|VCC ±| − Supply Voltage − V
24
2.8
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 23.
Copyright © 2008, Texas Instruments Incorporated
Figure 24.
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Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
23
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
INPUT NOISE VOLTAGE
OVER A 10-SECOND PERIOD
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
750
VCC ± = ± 15 V
RS = 20 Ω
VCC ± = ± 15 V
f = 0.1 to 10 Hz
TA = 25°C
500
200
Input Noise Voltage − nV
Vn − Equivalent Input Noise Voltage − nV/ Hz
250
TA = − 55°C
150
TA = 125°C
100
TA = 25°C
50
250
0
−250
−500
−750
0
1
100
10
1k
0
10 k
2
4
f − Frequency − Hz
Figure 25.
TA = − 55°C
4
TA = 25°C
2
TA = 125°C
0
100
1k
10 k
THD + N − Total Harmonic Distortion + Noise − %
In − Noise Current − pA/ Hz
6
f − Frequency − Hz
1%
VO(PP) = 20 V
VCC ± = ± 15 V
TA = 25°C
Submit Documentation Feedback
AV = 100
RL = 600 Ω
0.1%
AV = 10
RL = 600 Ω
AV = 100
RL = 2 kΩ
0.01%
AV = 10
RL = 2 kΩ
0.001%
10
100
Figure 27.
24
10
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
8
10
8
Figure 26.
NOISE CURRENT
vs
FREQUENCY
1
6
t − Time − s
1k
10 k
f − Frequency − Hz
100 k
Figure 28.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
SLEW RATE
vs
LOAD CAPACITANCE
SLEW RATE
vs
FREE-AIR TEMPERATURE
60
50
50
40
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µ s
SR +
40
SR −
30
20
VCC ± = ± 15 V
AVD = − 1
RL = 2 kΩ
CL = 500 pF
10
SR+
30
20
SR −
10 VCC ± = ± 15 V
AVD = − 1
TA = 25°C
0
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
0
0.01
0.1
1
CL − Load Capacitance − nF
Figure 29.
Figure 30.
INVERTING
LARGE-SIGNAL
PULSE RESPONSE
NONINVERTING
LARGE-SIGNAL
PULSE RESPONSE
15
15
TA = 125°C
TA = 25°C
10
10
TA = 25°C
5
V
VO
O − Output Voltage − V
V
VO
O − Output Voltage − V
10
TA = − 55°C
0
TA = − 55°C
−5
TA = 25°C
VCC ± = ± 15 V
AVD = 1
RL = 2 kΩ
CL = 300 pF
−10
TA = − 55°C
TA = 125°C
5
0
TA = 125°C
TA = 25°C
−5
VCC ± = ± 15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
−10
TA = 125°C
−15
TA = − 55°C
−15
0
1
2
3
4
5
0
1
2
t − Time − µs
t − Time − µs
Figure 31.
Figure 32.
Copyright © 2008, Texas Instruments Incorporated
3
4
Submit Documentation Feedback
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
5
25
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008........................................................................................................................................................................................................ www.ti.com
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
SMALL-SIGNAL
PULSE RESPONSE
100
7
VCC ± = ± 15 V
RL = 2 kΩ
B
B1
1 − Unity-Gain Bandwidth − MHz
V
VO
O − Output Voltage − mV
TA = − 55°C
50
0
VCC ± = ± 15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
TA = 25°C
−50
6
TA = 25°C
5
TA = 125°C
4
3
2
−100
0
400
800
1200
1
10
1600
t − Time − ns
100
1000
10000
CL − Load Capacitance − pF
Figure 33.
Figure 34.
PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN MARGIN
vs
LOAD CAPACITANCE
14
12
TA = − 55°C
8
6
TA = 125°C
TA = 25°C
50°
TA = 125°C
40°
30°
20°
4
2
10°
TA = 25°C
0
10
TA = − 55°C
60°
φ m − Phase Margin
Gain Margin − dB
10
70°
VCC ± = ± 15 V
AVD = 1
RL = 2 kΩ to ∞
VO = − 10 V to 10 V
100
1000
CL − Load Capacitance − pF
10000
VCC ± = ± 15 V
RL = 2 kΩ
0°
10
100
1000
CL − Load Capacitance − pF
Figure 35.
26
Submit Documentation Feedback
10000
Figure 36.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com........................................................................................................................................................................................................ SLOS577 – MAY 2008
APPLICATION INFORMATION
Input Offset Voltage Nulling
The TLE2141 offers external null pins that can be used to further reduce the input offset voltage. If this feature is
desired, connect the circuit of Figure 37 as shown. If external nulling is not needed, the null pins may be left
unconnected.
IN+
IN-
3
2
+
6
OUT
–
5 5 kW 1
OFFSET N2
OFFSET N1
1 kW
VCC– (split supply)
GND (single supply)
Figure 37. Input Offset Voltage Null Circuit
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
27
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLE2141MDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2144MDWREP
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
*All dimensions are nominal
Device
Package Type
TLE2141MDREP
SOIC
TLE2144MDWREP
SOIC
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
D
8
2500
340.5
336.1
25.0
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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