µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
D
D
D
TLV2471
D PACKAGE
(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
CMOS Rail-To-Rail Input/Output
Input Bias Current . . . 2.5 pA
Low Supply Current . . . 600 µA/Channel
Gain-Bandwidth Product . . . 2.8 MHz
High Output Drive Capability
− ±10 mA at 180 mV
− ±35 mA at 500 mV
Input Offset Voltage . . . 250 µV (typ)
Supply Voltage Range . . . 2.7 V to 6 V
NC
IN −
IN +
GND
1
8
2
7
3
6
4
5
NC
VDD
OUT
NC
description
The TLV247x is a family of CMOS rail-to-rail input/output operational amplifiers that establishes a new
performance point for supply current versus ac performance. These devices consume just 600 µA/channel
while offering 2.8 MHz of gain-bandwidth product. Along with increased ac performance, the amplifier provides
high output drive capability, solving a major shortcoming of older micropower operational amplifiers. The
TLV247x can swing to within 180 mV of each supply rail while driving a 10-mA load. For non-RRO applications,
the TLV247x can supply ±35 mA at 500 mV off the rail. Both the inputs and outputs swing rail-to-rail for increased
dynamic range in low-voltage applications. This performance makes the TLV247x family ideal for sensor
interface, portable medical equipment, and other data acquisition circuits.
The family is fully specified at 3 V and 5 V across the automotive temperature range (− 40°C to 125°C).
FAMILY TABLE
DEVICE
NUMBER OF
CHANNELS
UNIVERSAL EVM
BOARD
TLV2471
1
TLV2472
2
TLV2474
4
See the EVM
selection guide
(SLOU060)
A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS‡
DEVICE
VDD
(V)
VIO
(µV)
BW
(MHz)
SLEW RATE
(V/µs)
IDD (per channel)
(µA)
OUTPUT
DRIVE
RAIL-TO-RAIL
TLV247X
2.7 − 6
250
2.8
1.5
600
±35 mA
I/O
TLV245X
2.7 − 6
20
0.22
0.11
23
±10 mA
I/O
TLV246X
2.7 − 6
150
6.4
1.6
550
±90 mA
I/O
TLV277X
2.5 − 6
360
5.1
10.5
1000
±10 mA
O
‡ All specifications measured at 5 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2008 Texas Instruments Incorporated
! ! $%&'()*+$'% $, -.((/%+ *, '& 0.12$-*+$'% 3*+/
('3.-+, -'%&'() +' ,0/-$&$-*+$'%, 0/( +/ +/(), '& /*, %,+(.)/%+,
,+*%3*(3 4*((*%+5 ('3.-+$'% 0('-/,,$%6 3'/, %'+ %/-/,,*($25 $%-2.3/
+/,+$%6 '& *22 0*(*)/+/(,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
ORDERING INFORMATION†
ORDERABLE
PART NUMBER
PACKAGE}
TA
−40°C
−40
C to 125
125°C
C
−40°C
−40
C to 125
125°C
C
−40°C to 125°C
TOP-SIDE
MARKING
SOP − D
Tape and reel
TLV2471QDRQ1
2471Q1
SOP − D
Tape and reel
TLV2471AQDRQ1
2471AQ
SOT23 − DBV
Tape and reel
TLV2471QDBVRQ1
471Q
SOP − D
Tape and reel
TLV2472QDRQ1
2472Q1
SOP − D
Tape and reel
TLV2472AQDRQ1
2472AQ
MSOP − DGN
Tape and reel
TLV2472QDGNRQ1§
SOP − D
Tape and reel
TLV2474QDRQ1
2474Q1
SOP − D
Tape and reel
TLV2474AQDRQ1
2474AQ1
TSSOP − PWP
Tape and reel
TLV2474QPWPRQ1
2474Q1
TSSOP − PWP Tape and reel
TLV2474APWPRQ1
2474AQ1
† For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ Product Preview.
TLV247x PACKAGE PINOUTS
TLV2471
DBV PACKAGE
(TOP VIEW)
OUT
GND
IN+
1
5
VDD
2
3
4
TLV2474
D OR PWP PACKAGE
TLV2472
D OR DGN PACKAGE
(TOP VIEW)
IN−
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
(TOP VIEW)
VDD
2OUT
2IN −
2IN+
NC − No internal connection
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
D (8)
38.3
176
710 mW
D (14)
26.9
122.3
1022 mW
DBV (3)
55
324.1
385 mW
DGN (8)
4.7
52.7
2370 mW
PWP (14)
2.07
30.7
4070 mW
recommended operating conditions
Single supply
Supply voltage, VDD
Split supply
Common-mode input voltage range, VICR
Operating free-air temperature, TA
† Relative to GND
MIN
MAX
2.7
6
±1.35
±3
0
VDD
125
−40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
V
°C
3
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient of input
offset voltage
IIO
Input offset current
IIB
Input bias current
TEST CONDITIONS
TLV247x
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
High-level output voltage
MIN
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
Full range
1.5
2
Full range
VIC = VDD/2
VIC = VDD/2
Sinking
VO = 0.5 V from rail
AVD
Large-signal differential voltage
amplification
ri(d)
Differential input resistance
CIC
Common-mode input
capacitance
f = 10 kHz
zo
Closed-loop output impedance
f = 10 kHz,
Common-mode rejection ratio
VIC = 0 to 3 V,
RS = 50 Ω
CMRR
kSVR
IDD
Supply voltage rejection ratio
((∆V
VDD //∆V
VIO)
Supply current (per channel)
VO(PP) = 1 V,
25°C
2.85
Full range
2.8
25°C
2.6
Full range
2.5
RL = 10 kΩ
AV = 10
VIC = VDD /2,
VDD = 3 V to 5 V,
No load
VIC = VDD /2,
No load
† Full range is −40°C to 125°C. If not specified, full range is − 40°C to 125°C.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
50
50
pA
2.94
V
2.74
0.07
0.15
0.2
0.35
Full range
0.2
Full range
V
0.5
25°C
30
Full range
20
25°C
30
Full range
20
mA
±22
25°C
VDD = 2.7 V to 6 V,
No load
VO = 1.5 V,
µV/°C
V/°C
300
25°C
Short-circuit output current
µV
V
300
25°C
Sourcing
Output current
1600
UNIT
1800
Full range
IOL = 10 mA
IO
2200
250
25°C
IOL = 2.5 mA
IOS
250
2400
25°C
Low-level output voltage
MAX
0.4
IOH = − 10 mA
VOL
TYP
Full range
25°C
TLV247xA
IOH = − 2.5 mA
VOH
TA†
25°C
25°C
90
Full range
88
mA
116
dB
25°C
1012
Ω
25°C
19.3
pF
2
Ω
25°C
25°C
58
Full range
56
25°C
68
Full range
60
25°C
70
Full range
60
25°C
Full range
78
dB
90
dB
92
550
750
800
µA
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
In
Equivalent input noise current
TEST CONDITIONS
VO(PP) = 0.8 V,
RL = 10 kΩ
CL = 150 pF,
TA†
25°C
MIN
TYP
1.1
1.4
Full range
0.6
f = 100 Hz
25°C
28
25°C
15
25°C
0.405
Total harmonic distortion plus noise
VO(PP) = 2 V,
RL = 10 kΩ,
f = 1 kHz
AV = 1
AV = 10
Gain-bandwidth product
f = 10 kHz,
RL = 600 Ω
V(STEP)PP = 2 V,
AV = −1,
CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 2 V,
AV = −1,
CL = 56 pF,
RL = 10 kΩ
0.1%
RL = 10 kΩ,
CL = 1000 pF
25°C
61°
Gain margin
RL = 10 kΩ,
CL = 1000 pF
† Full range is −40°C to 125°C. If not specified, full range is − 40°C to 125°C.
‡ Depending on package dissipation rating
25°C
15
THD + N
ts
φm
Settling time
Phase margin
POST OFFICE BOX 655303
nV/√Hz
pA /√Hz
0.02%
25°C
25
C
AV = 100
0.1%
0.5%
25°C
2.8
MHz
1.5
0.01%
3.9
µss
25°C
1.6
0.01%
• DALLAS, TEXAS 75265
UNIT
V/ s
V/µs
f = 1 kHz
f = 1 kHz
MAX
4
dB
5
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient of input
offset voltage
IIO
Input offset current
IIB
Input bias current
TEST CONDITIONS
TLV247x
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
High-level output voltage
MIN
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
VIC = VDD/2,
VO = VDD/2,
RS = 50 Ω
Full range
1.7
2.5
Full range
VIC = VDD/2
VIC = VDD/2
Sinking
VO = 0.5 V from rail
AVD
Large-signal differential voltage
amplification
ri(d)
Differential input resistance
CIC
Common-mode input
capacitance
f = 10 kHz
zo
Closed-loop output impedance
f = 10 kHz,
Common-mode rejection ratio
VIC = 0 to 5 V,
RS = 50 Ω
CMRR
kSVR
IDD
Supply voltage rejection ratio
((∆V
VDD //∆V
VIO)
Supply current (per channel)
VO(PP) = 3 V,
25°C
4.85
Full range
4.8
25°C
4.72
Full range
4.65
RL = 10 kΩ
AV = 10
VIC = VDD /2,
VDD = 3 V to 5 V,
No load
VIC = VDD /2,
No load
† Full range is −40°C to 125°C. If not specified, full range is − 40°C to 125°C.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
50
50
pA
4.96
V
4.82
0.07
0.15
0.178
0.28
Full range
0.2
Full range
V
0.35
25°C
110
Full range
60
25°C
90
Full range
60
mA
±35
25°C
VDD = 2.7 V to 6 V,
No load
VO = 2.5 V,
µV/°C
V/°C
300
25°C
Short-circuit output current
µV
V
300
25°C
Sourcing
Output current
1600
UNIT
2000
Full range
IOL = 10 mA
IO
2200
250
25°C
IOL = 2.5 mA
IOS
250
2400
25°C
Low-level output voltage
MAX
0.4
IOH = − 10 mA
VOL
TYP
Full range
25°C
TLV247xA
IOH = − 2.5 mA
VOH
TA†
25°C
25°C
92
Full range
91
mA
120
dB
25°C
1012
Ω
25°C
18.9
pF
1.8
Ω
25°C
25°C
62
Full range
58
25°C
68
Full range
60
25°C
70
Full range
60
25°C
Full range
84
dB
90
dB
92
600
900
1000
µA
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
In
Equivalent input noise current
THD + N
ts
φm
TEST CONDITIONS
VO(PP) = 2 V,
RL = 10 kΩ
CL = 150 pF,
TYP
1.1
1.5
Full range
0.7
25°C
28
25°C
15
f = 1 kHz
25°C
VO(PP) = 4 V,
RL = 10 kΩ,
f = 1 kHz
Gain-bandwidth product
f = 10 kHz,
RL = 600 Ω
V(STEP)PP = 2 V,
AV = −1,
CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 2 V,
AV = −1,
CL = 56 pF,
RL = 10 kΩ
0.1%
RL = 10 kΩ,
CL = 1000 pF
POST OFFICE BOX 655303
25°C
25
C
0.39
nV/√Hz
pA /√Hz
0.05%
0.3%
25°C
2.8
MHz
1.8
0.01%
3.3
µss
25°C
1.7
0.01%
• DALLAS, TEXAS 75265
UNIT
0.01%
AV = 100
Gain margin
RL = 10 kΩ,
CL = 1000 pF
† Full range is −40°C to 125°C for Q suffix. If not specified, full range is − 40°C to 125°C.
MAX
V/ s
V/µs
f = 100 Hz
Total harmonic distortion plus noise
Phase margin
MIN
f = 1 kHz
AV = 1
AV = 10
Settling time
TA†
25°C
3
25°C
68°
25°C
23
dB
7
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
IIB
Input offset voltage
vs Common-mode input voltage
1, 2
IIO
VOH
Input offset current
vs Free-air temperature
3, 4
VOL
Zo
High-level output voltage
vs High-level output current
5, 7
Low-level output voltage
vs Low-level output current
6, 8
IDD
PSRR
Output impedance
vs Frequency
9
Supply current
vs Supply voltage
10
Power supply rejection ratio
vs Frequency
11
CMRR
Common-mode rejection ratio
vs Frequency
12
Vn
VO(PP)
Equivalent input noise voltage
vs Frequency
13
Maximum peak-to-peak output voltage
vs Frequency
14, 15
AVD
φm
Differential voltage gain and phase
vs Frequency
16, 17
Phase margin
vs Load capacitance
18, 19
Gain margin
vs Load capacitance
20, 21
Gain-bandwidth product
vs Supply voltage
22
vs Supply voltage
23
SR
Input bias current
Slew rate
vs Free-air temperature
24, 25
Crosstalk
vs Frequency
THD+N
Total harmonic distortion + noise
vs Frequency
27, 28
VO
Large and small signal follower
vs Time
29 − 32
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
26
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
600
TA=25° C
200
0
−200
−400
−600
−800
−0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VICR − Common-Mode Input Voltage − V
400
TA=25 °C
200
0
−200
−400
−600
−800
−0.5
0.5
1.5
2.5
3.5
4.5
5.5
VICR − Common-Mode Input Voltage − V
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
FREE-AIR TEMPERATURE
IIB
10
0
IIO
−10
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
VDD=3 V
3.0
2.5
2.0
TA=125°C
1.5
TA=85°C
1.0
TA=25°C
0.5
TA=−40°C
0
3.5
3.0
1.5
TA=25°C
0.5
TA=−40°C
0.0
TA=−40°C
1.0
0.5
10
20
30
40
50
IOL − Low-Level Output Current − mA
Figure 6
20 40 60 80 100 120 140 160
IOH − High-Level Output Current − mA
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
4.5
TA=125°C
4.0
TA=85°C
3.5
VDD=3 & 5 V
TA=25°C
TA=25°C
3.0
TA=−40°C
2.5
2.0
1.5
1.0
100
AV=100
10
AV=10
1
AV=1
0.1
0.5
VDD=5 V
0.0
Figure 7
TA=25°C
1.5
0
Z o − Output Impedance − Ω
4.0
1.0
TA=85°C
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
4.5
TA=85°C
TA=125°C
2.0
10
20
30
40
50
60
IOH − High-Level Output Current − mA
5.0
VDD=5 V
TA=125°C
VDD=3 V
2.5
Figure 5
5.5
2.0
IIO
0.0
0.0
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.5
0
3.0
Figure 4
5.0
10
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
20
V OH − High-Level Output Voltage − V
I IB − Input Bias Current − pA
I IO − Input Offset Current − pA
30
IIB
20
Figure 3
3.5
40
30
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
50
VDD=5 V
40
−10
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
Figure 2
Figure 1
0
VDD=3 V
I IB − Input Bias Current − pA
400
50
VDD=5 V
I IO − Input Offset Current − pA
VDD=3 V
VIO − Input Offset Voltage − µ V
VIO − Input Offset Voltage − µ V
600
V OH − High-Level Output Voltage − V
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
0
20
40
60
80 100 120 140
IOL − Low-Level Output Current − mA
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.01
100
1k
10k
100k
f − Frequency − Hz
1M
10M
Figure 9
9
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
TA=125°C
0.7
0.6
TA=25°C
0.5
TA=−40°C
0.4
0.3
0.2
AV= 1
SHDN= VDD
Per Channel
0.1
0.0
2.5
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
PSRR+
90
80
PSRR−
70
60
50
40
30
10
6.0
100
80
VDD=3 & 5 V
AV= 10
VIN= VDD/2
TA=25°C
50
40
30
20
10
0
10
100
1k
10k
f − Frequency − Hz
100k
V O(PP) − Maximum Peak-To-Peak Output Voltage − V
V n − Equivalent Input Noise Voltage − nV/
Hz
EQUIVALENT NOISE VOLTAGE
vs
FREQUENCY
60
1k
10k
100k
f − Frequency − Hz
5.0
4.5
VO(PP)=5 V
4.0
3.5
3.0
2.5
VO(PP)=3 V
2.0
1.5
1.0
0.5
0.0
10k
100k
f − Frequency − Hz
1M
VDD=5 V
90
VIC=2.5 V
80
70
60
50
100
VDD=3 V
VIC=1.5 V
1k
10k
100k
f − Frequency − Hz
0
−45
40
−90
20
−135
0
−180
−20
−225
1M
10k
100k
Frequency − Hz
10M
−270
100M
10M
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
5.5
THD+N ≤ 2.0%
RL=600 Ω
TA=25°C
5.0
4.5
4.0
VO(PP)=5 V
3.5
3.0
2.5
2.0
VO(PP)=3 V
1.5
1.0
0.5
0.0
10k
100k
f − Frequency − Hz
1M
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
45
VDD=±5
RL=600 Ω
CL=0
TA=25°C
80
60
0
−45
40
−90
20
−135
0
−180
−20
−225
−40
100
1k
10k
100k
1M
Frequency − Hz
Figure 17
POST OFFICE BOX 655303
1M
Figure 15
Figure 16
10
100
100
Phase − °
AVD − Differential Voltage Gain − dB
THD+N ≤ 2.0%
RL=10 kΩ
TA=25°C
45
VDD=±3
RL=600 Ω
CL=0
TA=25°C
1k
110
Figure 14
100
60
120
Figure 12
5.5
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
80
10M
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
Figure 13
−40
100
1M
130
Figure 11
Figure 10
70
VDD=3 & 5 V
RF=5 kΩ
RI=50 Ω
TA=25°C
V O(PP) − Maximum Peak-To-Peak Output Voltage − V
TA=85°C
0.8
100
AVD − Differential Voltage Gain − dB
I DD − Supply Current − mA
0.9
• DALLAS, TEXAS 75265
10M
−270
100M
Phase − °
1.0
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
PSRR − Power Supply Rejection Ratio − dB
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
LOAD CAPACITANCE
90
60
Rnull=100
80
50
Rnull=20
40
30
20
10
Rnull=0
Rnull=100
50
40
15
Rnull=20
25
1k
10k
CL − Load Capacitance − pF
Figure 18
Rnull=50
30
100
100k
1k
10k
CL − Load Capacitance − pF
Figure 19
GAIN MARGIN
vs
LOAD CAPACITANCE
4.0
5
3.5
SLEW RATE
vs
SUPPLY VOLTAGE
2.0
15
Rnull=20
20
Rnull=50
Rnull=100
VDD=5V
RL=10 kΩ
TA=25°C
30
3.0
RL=600 Ω
2.5
2.0
1.5
CL=11 pF
f=10 kHz
TA=25°C
1.0
1k
10k
CL − Load Capacitance − pF
100k
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
0.6
VO(PP)=1.5 V
AV=−1
RL=10 kΩ
CL=150 pF
2.5
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
6.0
Figure 23
SLEW RATE
vs
FREE-AIR TEMPERATURE
2.00
1.75
1.75
SR+
SR−
1.00
0.75
0.25
0.8
Figure 22
2.00
0.50
1.0
6.0
SLEW RATE
vs
FREE-AIR TEMPERATURE
1.25
1.2
0.0
2.5
Figure 21
1.50
SR+
1.4
0.2
0.5
0.0
35
100
SR−
1.6
0.4
SR − Slew Rate − V/µs
25
SR − Slew Rate − V/µs
Gain Margin − dB
10
RL=10 kΩ
SR − Slew Rate − V/µs
Gain-Bandwidth Product − MHz
1.8
Rnull=0
100k
Figure 20
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
0
Rnull=100
20
Rnull=0
0
100
100k
10
Rnull=20
20
10
1k
10k
CL − Load Capacitance − pF
5
60
30
VDD=3V
RL=10 kΩ
TA=25°C
Rnull=50
70
Rnull=0
0
100
0
VDD=5V
RL=10 kΩ
TA=25°C
See Figure 42
90
Gain Margin − dB
70
Rnull=50
φ m − Phase Margin − °
φ m − Phase Margin − °
100
VDD=3 V
RL=10 kΩ
TA=25°C
See Figure 42
80
GAIN MARGIN
vs
LOAD CAPACITANCE
VDD=3 V
RL=10 kΩ
CL=150 pF
AV=−1
SR+
1.25
1.00
0.75
0.50
0.25
0.00
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
SR−
1.50
VDD=5 V
RL=10 kΩ
CL=150 pF
AV=−1
0.00
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
Figure 24
Figure 25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
VDD = 3V & 5V
AV = 1
RL= 600Ω
VI(PP)=2V
All Channels
−20
Crosstalk − dB
−40
−60
−80
−100
−120
−140
−160
1k
100
10 k
f − Frequency − Hz
10
100 k
TOTAL HARMONIC
DISTORTION PLUS NOISE
vs
FREQUENCY
1
AV = 100
AV = 10
0.1
AV = 1
0.01
VDD = 3 V
RL = 10 kΩ
V0 = 2 VPP
TA = 25°C
0.001
10
100
1k
TOTAL HARMONIC
DISTORTION PLUS NOISE
vs
FREQUENCY
THD+N−Total Harmonic Distortion + Noise
0
THD+N−Total Harmonic Distortion + Noise
CROSSTALK
vs
FREQUENCY
AV = 100
AV = 10
0.1
AV = 1
0.01
VDD = 5 V
RL = 10 kΩ
V0 = 4 VPP
TA = 25°C
0.001
10
100k
10k
1
100
f − Frequency − Hz
Figure 26
Figure 27
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
VI (50 mV/DIV)
VDD = 3 V
RL = 10 kΩ
CL = 8 pF
f = 85 kHz
TA = 25°C
3
4 5 6
t − Time − µs
7
8
9
10
VO (1 V/DIV)
VDD = 5 V
RL = 10 kΩ
CL = 8 pF
f = 85 kHz
TA = 25°C
0
1
2
Figure 29
3
4 5
6
t − Time − µs
VO (50 mV/DIV)
7
8
9
10
Figure 30
VI (50 mV/DIV)
V O − Output Voltage
VDD = 5 V
RL = 10 kΩ
CL = 8 pF
f = 1 MHz
TA = 25°C
VO (50 mV/DIV)
100
200
300
t − Time − µs
400
500
Figure 32
12
POST OFFICE BOX 655303
0
100
200
300
t − Time − µs
Figure 31
SMALL SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
0
VDD = 3 V
RL = 10 kΩ
CL = 8 pF
f = 1 MHz
TA = 25°C
V O − Output Voltage
V O − Output Voltage
V O − Output Voltage
VO (1 V/DIV)
2
100k
SMALL SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
VI (2 V/DIV)
1
10k
Figure 28
VI (2 V/DIV)
0
1k
f − Frequency − Hz
• DALLAS, TEXAS 75265
400
500
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
Rnull
_
+
RL
CL
Figure 33
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 34. A minimum value of 20 Ω should work well for most applications.
RF
RG
RNULL
_
Input
Output
+
CLOAD
Figure 34. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage.
RF
IIB−
RG
+
−
VI
IIB+
V
OO
+V
IO
ǒ ǒ ǓǓ
1)
R
R
F
G
VO
+
RS
"I
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
R
F
Figure 35. Output Offset Voltage Model
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 36).
RG
RF
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
1)
R
R
F
G
–3dB
Ǔǒ
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 36. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
RG =
Figure 37. 2-Pole Low-Pass Sallen-Key Filter
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–3dB
+
(
1
2pRC
RF
1
2−
Q
)
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV247x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
D Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
D Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
general PowerPAD design considerations
The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 38(a) and Figure 38(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 38(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 38. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
Thermal Pad Area
Quad
Single or Dual
68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils
Figure 39. PowerPAD PCB Etch and Via Pattern
PowerPAD is a trademark of Texas Instruments Incorporated.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
78 mils x 94 mils) with 9 vias
(Via diameter = 13 mils)
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
1. Prepare the PCB with a top side etch pattern as shown in Figure 39. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils
in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 40 and is calculated by the following formula:
P
Where:
D
+
ǒ
T
Ǔ
–T
MAX A
q
JA
PD = Maximum power dissipation of TLV247x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
Maximum Power Dissipation − W
7
6
5
4
PWP Package
Low-K Test PCB
θJA = 29.7°C/W
TJ = 150°C
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
DGN Package
Low-K Test PCB
θJA = 52.3°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
3
2
1
0
−55 −40 −25 −10
5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 40.
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 41 to Figure 46 show this effect,
along with the quiescent heat, with an ambient air temperature of 70°C and 125°C. When using VDD = 3 V, there
is generally not a heat problem with an ambient air temperature of 70°C. But, when using VDD = 5 V, the
packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these
graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat
dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation
properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted
on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation
capability increases. The currents and voltages shown in these graphs are for the total package. For the dual
or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the
proper package.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
TLV2471†
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
Maximum Output
Current Limit Line
160
140
B
Packages With
θJA ≤ 110°C/W
at TA = 125°C
or
θJA ≤ 355°C/W
at TA = 70°C
120
100
A
80
60
| IO | − Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
180
Safe Operating Area
40
VDD = ± 3 V
TJ = 150°C
TA = 125°C
20
0
0
0.25
TLV2471†
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Maximum Output
Current Limit Line
160
140
B
120
100
A
80
Packages With
θJA ≤ 210°C/W
at TA = 70°C
60
40
VDD = ± 5 V
TJ = 150°C
TA = 125°C
20
0
0.5
0.75
1
1.5
1.25
0
0.5
| VO | − RMS Output Voltage − V
B
Packages With
θJA ≤ 55°C/W
at TA = 125°C
or
θJA ≤ 178°C/W
at TA = 70°C
80
60
40
VDD = ± 3 V
TJ = 150°C
TA = 125°C
20
0
0
0.25
Safe Operating Area
180
0.75
2.5
Maximum Output
Current Limit Line
160
140
120
100
C
80
B
60
1
1.25
1.5
Packages With
θJA ≤ 105°C/W
at TA = 70°C
40
20
0
0.5
2
TLV2472†
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
| IO | − Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
140
100
1.5
Figure 42
TLV2472†
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
Maximum Output
Current Limit Line
160
C
1
| VO | − RMS Output Voltage − V
Figure 41
120
Safe Operating Area
0
VDD = ± 5 V
TJ = 150°C
TA = 125°C
0.5
Safe Operating Area
1
1.5
2
2.5
| VO | − RMS Output Voltage − V
| VO | − RMS Output Voltage − V
Figure 44
Figure 43
† A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
TLV2474†
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
Maximum Output
Current Limit Line
160
140
| IO | − Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
180
D
120
100
Packages With
θJA ≤ 88°C/W
C
at TA = 70°C
80
60
40
VDD = ±3 V
TJ = 150°C
TA = 125°C
20
0
0
0.25
TLV2474†
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating Area
Maximum Output
Current Limit Line
160
140
D
120
100
80
VDD = ± 5 V
TJ = 150°C
TA = 125°C
60
40
0.75
1
1.25
1.5
Safe Operating Area
0
| VO | − RMS Output Voltage − V
0.5
1
Figure 45
Figure 46
POST OFFICE BOX 655303
1.5
2
| VO | − RMS Output Voltage − V
† A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14)
20
Packages With
θJA ≤ 52°C/W
at TA = 70°C
20
0
0.5
C
• DALLAS, TEXAS 75265
2.5
µ
!" "
"#
SGLS180B − AUGUST 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 47 are generated using
the TLV247x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 1: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
3
99
VDD
+
egnd
rd1
rd2
rss
ro2
css
fb
rp
−
c1
7
11
12
+
c2
vlim
1
+
r2
9
6
IN+
−
vc
D
D
8
+
−
vb
ga
2
G
G
−
IN−
ro1
gcm
ioff
53
S
S
OUT
dp
91
10
iss
GND
4
ve
+ 54
90
dln
+
hlim
−
+
dc
−
dlp
vlp
−
5
92
−
vln
+
de
* TLV247x operational amplifier ”macromodel” subcircuit
* created using Parts release 8.0 on 4/27/99 at 14:31
* Parts is a MicroSim product.
*
* connections: non−inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt TLV247x 1 2 3 4 5
*
c1
11
12
1.1094E−12
c2
6
7
5.5000E−12
css
10
99
556.53E−15
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
+ 39.614E6 −1E3 1E3 40E6 −40E6
ga
6
0
11
12 79.828E−6
gcm
0
6
10
99 32.483E−9
iss
hlim
ioff
j1
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
*$
10
90
0
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
4
dc
10.714E−6
0
vlim 1K
6
dc
75E−9
2
10 jx1
1
10 jx2
9
100.00E3
11
12.527E3
12
12.527E3
5
10
99
10
4
3.8023E3
99
18.667E6
0
dc 0
53
dc .842
4
dc .842
8
dc 0
0
dc 110
92
dc 110
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1)
NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1)
Figure 47. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2471AQDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2471AQ
TLV2471QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
471Q
TLV2472AQDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472AQ
TLV2472QDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472Q1
TLV2472QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472Q1
TLV2474APWPRQ1
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2474AQ1
TLV2474AQDRG4Q1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474AQ1
TLV2474QDRG4Q1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474Q1
TLV2474QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474Q1
TLV2474QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2474Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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