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TLV27L2-Q1
SLOS922A – SEPTEMBER 2015 – REVISED DECEMBER 2015
TLV27L2-Q1 Automotive Micropower Rail-to-Rail Output
Operational Amplifier
1 Features
3 Description
•
•
The TLV27L2-Q1 single-supply operational amplifiers
provide rail-to-rail output capability. The TLV27L2-Q1
device takes the minimum operating supply voltage
down to 2.7 V over the extended industrial
temperature range, while adding the rail-to-rail output
swing feature. The TLV27L2-Q1 device also provides
160-kHz bandwidth from only 7 µA. The maximum
recommended supply voltage is 16 V, which allows
the devices to be operated from (±8-V supplies down
to ±1.35 V) two rechargeable cells.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM Classification Level 2
– Device CDM Classification Level C6
BiMOS Rail-to-Rail Output
Input Bias Current: 1 pA
High Wide Bandwidth 160 kHz
High Slew Rate: 0.1 V/µs
Supply Current: 7 µA (per channel)
Input Noise Voltage: 89 nV/√Hz
Supply Voltage Range: 2.7 V to 16 V
2 Applications
•
•
•
•
The rail-to-rail outputs make the TLV27L2-Q1 device
good upgrades for the TLC27Lx family of devices
which offers more bandwidth at a lower quiescent
current. The TLV27L2-Q1 offset voltage is equal to
that of the TLC27LxA variant. Their cost effectiveness
makes them a good alternative to the TLC225x and
TLV225x families of devices, where offset and noise
are not of premium importance.
The TLV27L2-Q1 device is available in the
commercial temperature range to enable easy
migration from the equivalent TLC27Lx.
Portable Medical
Power Monitoring
Low Power Security Detection Systems
Smoke Detectors
The TLV27L2-Q1 device is available in an 8-pin SOIC
(D) package.
Device Information(1)
PART NUMBER
TLV27L2-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Low and Stable Quiescent Current
Application Schematic
8
VCC
7
VCC
Quiescent Currenr (µA)
R5
±
+
R6
ILOAD
R2
R1
+
VBUS
+
6
5
4
3
–40°C
2
0°C
25°C
VOUT
RSHUNT
±
±
R3
1
VCC
RL
70°C
125°C
0
0
R4
2
4
6
8
10
12
14
16
Supply Voltage (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV27L2-Q1
SLOS922A – SEPTEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Selection Guide......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................ 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes ....................................... 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
11.3 General Power Dissipation Considerations .......... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2015) to Revision A
•
2
Page
First public release of the data sheet. .................................................................................................................................... 1
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SLOS922A – SEPTEMBER 2015 – REVISED DECEMBER 2015
5 Selection Guide
All DC specifications are maximum values while AC specifications are typical values.
PART NUMBER
VS
(V)
IQ/ch
(µA)
VICR
(V)
VIO
(mV)
IIB
(pA)
GBW
(MHz)
SLEW RATE
(V/µs)
Vn, 1 kHz
(nV/√Hz)
TLV27L2-Q1
2.7 to 16
11
–0.2 to VS + 1.2
5
60
0.18
0.06
89
OPAx348-Q1
2.1 to 5.5
65
–0.2 to VS + 0.2
5
10
1
0.5
35
55
OPAx333-Q1
1.8 to 5.5
25
–0.1 to VS + 0.1
0.01
200
0.35
0.16
OPA2314-Q1
1.8 to 5.5
180
–0.2 to VS + 0.2
2.5
10
2.7
1.5
14
OPAx376-Q1
2.2 to 5.5
950
–0.1 to VS + 0.1
0.025
10
5.5
2
7.5
TLV226x-Q1
2.7 to 8
500
–0.3 to VS – 0.8
0.95
60
0.67
0.55
12
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
OUT A
1
8
V+
–IN A
2
7
OUT B
+IN A
3
6
–IN B
V–
4
5
+IN B
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
(1)
I = input, O = output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage
MAX
UNIT
16.5
V
VS
V
(2)
VI
Input voltage
VID
Differential input voltage
VS
V
IO
Output current
100
mA
See the Thermal
Information Table
Continuous total power dissipation
TJ
Maximum junction temperature
TA
Operating free-air temperature
–40
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Tstg
(1)
(2)
Storage temperature
–65
150
°C
125
°C
300
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Relative to the V–.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
VS
MIN
MAX
±1.35
±8
2.7
16
Input common-mode voltage
–0.2
VS – 1.2
V
Operating free-air temperature
–40
125
°C
Dual supply
Supply voltage
TA
Single supply
UNIT
V
7.4 Thermal Information
TLV27L2-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
122.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.5
°C/W
RθJB
Junction-to-board thermal resistance
62.5
°C/W
ψJT
Junction-to-top characterization parameter
22.3
°C/W
ψJB
Junction-to-board characterization parameter
62.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
at recommended operating conditions, VS = 2.7 V, 5 V, and 10 V (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
MIN
TYP
MAX
0.5
5
UNIT
DC PERFORMANCE
25°C
VIO
Input offset voltage
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
αVIO
Offset voltage drift
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
CMRR
Common-mode rejection ratio
VIC = 0 V to VS – 1.2 V, RS = 50 Ω
Full range
VS = 2.7 V, 5 V
Large-signal differential voltage
amplification
AVD
VO(PP) = VS / 2,
RL = 100 kΩ,
VS = ±5 V
mV
7
25°C
1.1
25°C
71
Full range
70
25°C
80
Full range
77
25°C
77
Full range
74
µV/°C
86
dB
100
dB
82
INPUT CHARACTERISTICS
≤ 25°C
IIO
Input offset current
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
1
100
≤ 125°C
1000
≤ 25°C
IIB
Input bias current
ri(d)
Differential input resistance
CIC
Common-mode input capacitance
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
f = 1 kHz
60
≤ 70°C
1
pA
60
≤ 70°C
200
≤ 125°C
1000
pA
≤ 25°C
1000
GΩ
≤ 25°C
8
pF
25°C
7
POWER SUPPLY
IQ
Quiescent current (per channel)
VO = VS/2
PSRR
Power supply rejection ratio
(ΔVS/ΔVIO)
No load, VS = 2.7 V to 16 V,
VIC = VS / 2 V
Full range
11
µA
16
25°C
74
Full range
70
82
dB
OUTPUT CHARACTERISTICS
VS = 2.7 V
VIC = VS / 2,
IOL = 100 µA
VO
Output voltage swing from rail
VS = 5 V
VS = ±5 V
VS = 5 V
VIC = VS / 2,
IOL = 500 µA
VS = ±5 V
IO
Output current
25°C
160
Full range
25°C
220
85
Full range
25°C
420
25°C
RL = 100 kΩ, CL = 10 pF, f = 1 kHz
mV
800
900
200
Full range
VO = 0.5 V from rail, VS = 2.7 V
120
150
Full range
25°C
120
200
50
Full range
25°C
200
400
500
400
µA
25°C
160
kHz
25°C
0.06
–40°C
0.05
125°C
0.8
25°C
62
DYNAMIC PERFORMANCE
GBP
SR
φM
ts
Gain bandwidth product
Slew rate at unity gain
Phase margin
Settling time (0.1%)
VO(pp) = 1 V, RL = 100 kΩ,
CL = 50 pF
RL = 100 kΩ, CL = 50 pF
V(STEP)pp = 1 V, AV = –1, rise
CL = 50 pF, RL = 100 kΩ, fall
25°C
V/µs
°
62
µs
44
NOISE AND DISTORTION PERFORMANCE
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
89
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.6
nV/√Hz
(1)
Full range is –40°C to 125°C for I suffix.
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7.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Figure 1,
Figure 2,
Figure 3
Input offset voltage (VIO)
vs Common-mode input voltage (VIC)
Input bias and offset current (IIB and IIO)
vs Free-air temperature (TA)
Figure 4
High-level output voltage (VOH)
vs High-level output current (IOH)
Figure 5,
Figure 7,
Figure 9
Low-level output voltage (VOL)
vs Low-level output current (IOL)
Figure 6,
Figure 8,
Figure 10
vs Supply voltage (VS)
Figure 11
vs Free-air temperature (TA)
Figure 12
Quiescent current (IQ)
Supply voltage and supply current ramp up
Figure 13
Differential voltage gain and phase shift (AVD)
vs Frequency (f)
Figure 14
Gain-bandwidth product (GBP)
vs Free-air temperature (TA)
Figure 15
Phase margin (φm)
vs Load capacitance (CL)
Figure 16
Common-mode rejection ratio (CMRR)
vs Frequency (f)
Figure 17
Power supply rejection ratio (PSRR)
vs Frequency (f)
Figure 18
Input referred noise voltage
vs Frequency (f)
Figure 19
Slew rate (SR)
vs Free-air temperature (TA)
Figure 20
Peak-to-peak output voltage (VO(PP))
vs Frequency (f)
Figure 21
Inverting small-signal response
Figure 22
Inverting large-signal response
Figure 23
vs Frequency (f)
Figure 24
2000
2000
1500
1500
1000
1000
Input Offset Voltage (µA)
Input Offset Voltage (µA)
Crosstalk
500
0
–500
–1000
–1500
500
0
–500
–1000
–1500
–2000
–2000
0
0.5
1
1.5
2
2.5
3
0 0.5
Common-Mode Input Voltage (V)
VS = 2.7 V
TA = 25°C
VS = 5 V
Figure 1. Input Offset Voltage vs Common-Mode Input
Voltage
6
1 1.5 2 2.5 3 3.5 4 4.5 5
Common-Mode Input Voltage (V)
TA = 25°C
Figure 2. Input Offset Voltage vs Common-Mode Input
Voltage
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2000
Input Bias and Input Offset Currents (pA)
100
Input Offset Voltage (µA)
1500
1000
500
0
–500
–1000
–1500
–2000
–5.2
IIB
90
IIO
80
70
60
50
40
30
20
10
0
–3.6
–2
– 0.4
1.2
2.8
25
4.4
Common-Mode Input Voltage (V)
VS = ±5 VDC
VS = 5 V
TA = 25°C
Figure 3. Input Offset Voltage vs Common-Mode Input
Voltage
VIC = 2.5 V
125
VO = 2.5 V
Figure 4. Input Bias And Input Offset Current vs Free-Air
Temperature
5
5
–40°C
–40°C
4
4
0°C
3
25°C
2
70°C
1
125°C
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
45
65
85
105
Free-Air Temperature (°C)
0
–1
–2
–3
0°C
3
25°C
2
70°C
1
125°C
0
–1
–2
–3
–4
–4
–5
–5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Low-Level Output Current (mA)
High-Level Output Current (mA)
VS = ±5 V
Figure 5. High-Level Output Voltage vs High-Level Output
Current
Figure 6. Low-Level Output Voltage vs Low-Level Output
Current
5
5
–40°C
–40°C
4.5
0°C
4
25°C
3.5
70°C
Low-Level Output Voltage (V)
Hgh-Level Output Voltage (V)
4.5
125°C
3
2.5
2
1.5
1
0.5
0°C
4
25°C
3.5
70°C
125°C
3
2.5
2
1.5
1
0.5
0
0
0.5
1 1.5
2
2.5
3
3.5
4
4.5
0
5
0 0 5 1 1 5 2 2.5 3 3.5 4 4.5 5 5.5 6
High-Level Output Current (mA)
Low-Level Output Current (mA)
VS = 5 V
VS = 5 V
Figure 7. High-Level Output Voltage vs High-Level Output
Current
Figure 8. Low-Level Output Voltage vs Low-Level Output
Current
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2.7
2.7
–40°C
2.4
0°C
2.1
25°C
Low-Level Output Voltage (V)
70°C
1.8
125°C
1.5
1.2
0.9
0.6
0.3
2.4
0°C
2.1
25°C
70°C
1.8
125°C
1.5
1.2
0.9
0.6
0.3
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
0.2
VS = 2.7 V
8
7
7
6
6
Quiescent Currenr (µA)
Quiescent Currenr (µA)
8
4
3
–40°C
2
0°C
1
1.4
3
5V
1
125°C
2
4
6
8
10
12
14
2.7 V
2
10 V
0
–40 –25 –10 5
16
Figure 11. Quiescent Current vs Supply Voltage
120
5
0
VO
IQ
15
10
5
15
20
25
Supply Current (µA)
VS
0
30
Differential Voltage Gain (dB)
10
10
100
0°
80
30°
60
60°
40
90°
20
120°
0
150°
–20
0.1
1
Time (ms)
RL = 100 Ω
20 35 50 65 80 95 110 125
Figure 12. Quiescent Current vs Free-Air Temperature
40
15
5
16 V
Free-Air Temperature (°C)
Supply Voltage (V)
Supply Voltage (V/dc)
1.2
4
70°C
0
10
100
1k
10 k 100 k
180°
1M
Frequency (Hz)
CL = 10 pF
Figure 13. Supply Voltage and Supply Current Ramp Up
8
1
5
25°C
VS = 0 to 15 V
TA = 25°C
0.8
Figure 10. Low-Level Output Voltage vs Low-Level Output
Current
5
0
0.6
VS = 2.7 V
Figure 9. High-Level Output Voltage vs High-Level Output
Current
0
0.4
Low-Level Output Current (mA)
High-Level Output Current (mA)
Phase Shift
High-Level Output Voltage (V)
–40°C
VS = 5 V
TA = 25°C
RL = 100 Ω
CL = 10 pF
Figure 14. Differential Voltage Gain and Phase Shift vs
Frequency
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170
80
160
70
Phase Margin (Degrees)
Gain-Bandwidth Product (kHz)
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150
140
130
120
110
2.7 V
100
–40 –25 –10 5
60
50
40
30
20
10
5V
0
10
20 35 50 65 80 95 110 125
100
Free-Air Temperature (°C)
VS = 5 V
100
110
90
100
90
80
70
60
50
40
30
20
10
RL = 100 kΩ
TA = 25°C
Figure 16. Phase Margin vs Load Capacitance
120
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
Figure 15. Gain-Bandwidth Product vs Free-Air Temperature
80
70
60
50
40
30
20
10
0
0
10
100
1k
10 k
100 k
10
1M
100
1k
VS = 5 V
10 k
100 k
1M
Frequency (Hz)
Frequency (Hz)
VS = ±2.5 V
TA = 25°C
Figure 17. Common-Mode Rejection Ratio vs Frequency
TA = 25°C
Figure 18. Power Supply Rejection Ratio vs Frequency
0.09
Hz)
250
0.08
200
0.07
Slew Rate (V/µs)
Input Referred Noise Voltage (nV/
1000
Load Capacitance (pF)
150
100
0.06
0.05
0.04
0.03
0.02
50
SR+
0.01
0
1
10
100
1k
10 k
100 k
0
–40 –25 –10 5
Frequency (Hz)
VS = 5 V
G=2
SR–
20 35 50 65 80 95 110 125
Free-Air Temperature (°C)
RF = 100 kΩ
Figure 19. Input Referred Noise Voltage vs Frequency
VS = 5 V
RL = 100 kΩ
G=1
CL = 50 pF
VO = 1 V
Figure 20. Slew Rate vs Free-Air Temperature
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2
16
14
1.5
VS = 5 V
VS = 15 V
12
1
Amplitude (VPP)
Output Voltage Peak-to-Peak (V)
VS = 2.7 V
10
8
6
0.5
VI = 3 VPP
0
VO = 3 VPP
–0.5
–1
4
–1.5
2
0
10
100
1000
1k
–2
–100
10 k
0
100 200 300 400 500 600 700
Time (µs)
Frequency (Hz)
RL = 100 kΩ
CL = 10 pF
THD+N ≤ 5%
VS = 5 V
RL = 100 kΩ
VO = 3 VPP
f = 1 kHz
Figure 22. Inverting Small-Signal Response
Figure 21. Peak-to-Peak Output Voltage vs Frequency
0.06
0
0.04
–20
–40
0.02
Crosstalk (dB)
Amplitude (VPP)
G = –1
CL = 10 pF
VI = 100 mVPP
0
VO = 100 mVPP
–0.02
–60
–80
–100
–0.04
–0.06
–100
–120
0
100 200 300 400 500 600 700
–140
10
100
Time (µs)
VS = 5 V
RL = 100 kΩ
G = –1
CL = 10 pF
VO = 100 mVPP
f = 1 kHz
VS = 5 V
RL = 2 kΩ
Figure 23. Inverting Large-Signal Response
10
1k
10 k
100 k
Frequency (Hz)
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G = –1
CL = 10 pF
TA = 25°C
Channel 1 to 2
Figure 24. Crosstalk vs Frequency
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8 Detailed Description
8.1 Overview
The TLV27L2-Q1 device is a micropower, rail-to-rail output, operational amplifier. This device operates from 2.7
V to 16 V, is unity-gain stable, and is suitable for a wide range of general-purpose applications. The class AB
output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+ and ground. The input
common-mode voltage range includes the negative rail and allows the TLV27L2-Q1 device to be used in virtually
any single-supply application from 2.7 V to 16 V. The typical supply current of 7 µA makes the TLV27L2-Q1
device an excellent choice for battery operated systems.
8.2 Functional Block Diagram
+IN
PMOS
Input
Stage
-IN
Output
Stage
OUT
NMOS
Input
Stage
8.3 Feature Description
8.3.1 Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. Use the schematic and formula in Figure 25 to calculate the output offset voltage.
RF
RG
IIB–
+
–
VI
+
RS
æ
æ
æ R öö
æ R öö
VOO = VIO ç 1 + ç F ÷ ÷ ± IIB + RS ç 1 + ç F ÷ ÷ ± IIB- RF
è RG ø ø
è RG ø ø
è
è
IIB+
Figure 25. Output Offset Voltage Model
8.4 Device Functional Modes
The TLV27L2-Q1 device is powered on when the supply is connected. The device can be operated as a singlesupply operational amplifier or a dual-supply amplifier, depending on the application. The TLV27L2-Q1 device
operates from power supplies as low as 2.7 V or as high as 16 V.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way limit the bandwidth is to place an RC filter at the noninverting terminal of the amplifier as
shown in Figure 26.
RG
RF
VO æ RF öæ
1
ö
= ç 1+ ÷ç
÷
VI
è RG øè 1+sR1C1 ø
VDD/2
VI
–
VO
+
R1
f-3dB =
C1
1
2pR1C1
Figure 26. Single-Pole Low-Pass Filter
If even more attenuation is required, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do select an amplifier with an appropriate bandwidth can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f-3dB =
C2
1
2pRC
R
RG
RF
VDD/2
RG =
RF
1ö
æ
ç2 - ÷
Q
è
ø
Figure 27. 2-Pole Low-Pass Sallen-Key Filter
9.2 Typical Application
This single-supply low-side, bi-directional current sensing solution can accurately detect load currents from –1 A
to +1 A. The linear range of the output is from 110 mV to 3.19 V. The design uses the TLV27L2-Q1 device
configured as a difference amplifier and reference voltage buffer.
Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore the current
sensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, a reference
voltage must be added to differentiate between positive and negative currents. Figure 28 shows a general circuit
topology for a low-side, bidirectional current-sensing solution. This topology is particularly useful when cost is a
priority at the expense of accuracy and printed circuit board (PCB) space. The shunt voltage (VSHUNT) is created
12
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Typical Application (continued)
by the load current (ILOAD) flowing through the shunt resistor (RSHUNT). The VSHUNT voltage is amplified by an op
amp (U1A) according to the gain set by the ratio of R4 to R3. To achieve the transfer function in Equation 1 and
to minimize errors, set R4 equal to R2 and R3 equal to R1. To provide the reference voltage in this design, divide
down the supply voltage (VCC) using R5 and R6. The reference voltage is then buffered using an additional op
amp (U1B).
VOUT = VSHUNT × GainDiff_Amp + Vref
(1)
VCC
VCC
Vref
R5
±
+
U1B
R6
ILOAD
R2
R1
+
+
VBUS
+
VSHUNT
VOUT
RSHUNT
±
±
±
R3
U1A
VCC
RL
R4
Figure 28. Application Schematic ±1-A Single-Supply Low-Side Current Sensing Solution
9.2.1 Design Requirements
The design requirements are as follows:
Supply voltage: 3.3 V
Input: –1 A to +1 A
Output: 110 mV to 3.19 V
Maximum shunt voltage: ±100 mV
9.2.2 Detailed Design Procedure
9.2.2.1 Shunt Resistor (RSHUNT)
As shown in Figure 28, the value of VSHUNT is the ground potential for the system load. If the value of VSHUNT is
too large, it can cause issues when interfacing with systems with a true ground potential of 0 V. If the value of
VSHUNT is too negative, it can violate the input common-mode voltage of the differential amplifier in addition to
potential interfacing issues. Therefore, limit the voltage across the shunt resistor. Use Equation 2 to calculate the
maximum value of RSHUNT given a maximum shunt voltage of 100 mV.
RSHUNT(MAX) =
VSHUNT(MAX)
ILOAD(MAX)
=
100 mV
= 100 mW
1A
(2)
Because cost is a priority in this design, a shunt resistor with a 0.5% tolerance was selected.
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Typical Application (continued)
9.2.2.2 Operational Amplifiers
The shunt voltage in this design can range from –100 mV to +100 mV. The shut voltage is divided down by the
resistors, R1 and R2. The op amp configured as a difference amplifier (U1A) must have an input common-mode
that includes this voltage range. Therefore an op amp with rail-to-rail input (RRI) that extends below V– is
recommended. The output swing of the amplifier should also be rail-to-rail output (RRO) to maximize the
dynamic range of the system. Use of a CMOS op amp is recommended because the supply voltage is 3.3 V. The
supply-splitter op amp (U1B) should have low offset voltage. Because this design includes two op amps, a dual
package minimizes the required area. This design uses the TLV27L2-Q1 device because it is a RRO CMOS
device. In addition, the cost versus performance of the device is excellent.
9.2.2.3 Reference Voltage Resistors (R5-R6)
Because the load current range is symmetric (–1 A to +1 A), the resistors that divide down the supply voltage
should be equal so that the reference voltage is the mid supply ([(V+) – (V–)] / 2 or, for this example, (3.3 V – 0
V) / 2 = 1.65 V). Because cost is a priority in this design, the tolerance should be consistent with the shunt
resistor tolerance (0.5%). Finally, select resistors that are large enough to meet the power consumption
requirement of the system. For this design, 10-kΩ resistors were selected.
9.2.2.4 Difference Amplifier Gain Setting Resistors (R1-R4)
Equation 3 and Equation 4 show the input common-mode (VCM) and output voltage range (VOUT) of the
TLV27L2-Q1 device given a 3.3-V supply.
–200 mV < VCM < 2.1 V
100 mV < VOUT < 3.2 V
(3)
(4)
Use Equation 5 to calculate the gain.
VOUT _ MAX - VOUT _ MIN
3.2 V - 100 mV
V
GainDiff _ Amp =
=
= 15.5
RSHUNT ´ (IMAX - IMIN ) 100 mW ´ (1 A - (1 A ))
V
(5)
The selected value for the R1 and R3 resistors was 1 kΩ. The selected value for the R2 and R4 resistors was
15.4 kΩ, which is the nearest 0.1% value to the ideal value of 15.5 kΩ. Therefore, the ideal gain of the difference
amplifier is 15.4 V/V.
9.2.3 Application Curve
Figure 29 shows the measured transfer function of the design.
Output Voltage (V)
3.3
y = 1.4471x + 1.6177
1.65
0
-1
-0.5
0
Load Current (A)
0.5
1
D001
Figure 29. Measured Output Voltage vs Load Current (Board 1)
14
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10 Power Supply Recommendations
The TLV27L2-Q1 device is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 16.5 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high performance of the TLV27L2-Q1 device, follow proper printed-circuit board design
techniques. The following list is a general set of guidelines:
• Ground planes—Using a ground plane on the board is highly recommended to provide all components with a
low inductive-ground connection. However, in the areas of the amplifier inputs and output, the ground plane
can be removed to minimize the stray capacitance.
• Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. Sharing the tantalum capacitor among several amplifiers is possible depending on
the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every
amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As
this distance increases, the inductance in the connecting trace makes the capacitor less effective. The
designer should strive for distances of less than 0.1 inches between the device power terminals and the
ceramic capacitors.
• Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board are
the best implementation.
• Short trace runs and compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To achieve this performance, the circuit layout should be as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. The length should be kept as short as possible which helps minimize stray capacitance
at the input of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, keep the lead lengths as short as possible.
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11.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 30. TLV27L2-Q1 Layout Example
11.3 General Power Dissipation Considerations
Use to calculate the maximum power dissipation for a given θJA.
æ T -T ö
PD = ç MAX A ÷
è qJA ø
where
•
•
•
•
16
PD = Maximum power dissipation of TLV27L2-Q1 IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
– θJC = Thermal coefficient from junction to case
– θCA = Thermal coefficient from case to ambient air (°C/W)
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General Power Dissipation Considerations (continued)
2
Maximum Power Dissipation (W)
1.75
1.5
1.25
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
0
–55 –40 –25 –10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C)
TJ = 150°C
Results are with no air flow and using JEDEC Standard
Low-K test PCB.
Figure 31. Maximum Power Dissipation vs Free-Air Temperature
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• OPAx348-Q1 1-MHz 45-μA CMOS Rail-to-Rail Operational Amplifier, SBOS465
• OPAx333-Q1 1.8-V microPower CMOS Operational Amplifier Zero-Drift Series, SBOS522
• OPA2314-Q1 3-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier, SLOS896
• OPAx376-Q1 Low-Noise, Low Quiescent Current, Precision Operational Amplifier e-trim™ Series, SBOS549
• TLV226x-Q1 Advanced LinCMOS™ CMOS Operational Amplifiers, SGLS193
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV27L2QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
27L2Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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