TLV320AIC1109PBSR

  SLAS358 − DECEMBER 2001   D D D D D D D Differential Earphone Output, and One Single-Ended Earphone Output Programmable Gain Amplifiers for Transmit, Receive, Sidetone, and Volume Control Earphone Mute and Microphone Mute On-Chip I2C-Bus, Which Provides a Simple, Standard, Two-Wire Serial Interface With Digital ICs Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-Law or A-Law) Mode 32-Terminal TQFP Package Designed for Analog and Digital Wireless Handsets and Telecommunications Applications Dual-Tone Multifrequency (DTMF) Pulse Density Modulated (PDM) Buzzer Output APPLICATIONS D Digital Handset D Digital Headset D Cordless Phones D Digital PABX D Digital Voice Recording The PCM codec is designed to perform the transmit encoding analog/digital (A/D) conversion and receive decoding digital/analog (D/A) conversion, together with transmit and receive filtering, for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I2C interface. From a 2.048-MHz master clock input, the PCM codec generates its own internal clocks. PBS PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 PLLVDD EARVSS EAR1ON EARVDD EAR1OP EARVSS EAR2O AVDD 16 25 PCMO PCMI DVSS DVDD 12 SCL 11 SDA 10 NC 9 NC 26 15 14 13 27 28 29 30 31 32 1 2 3 4 5 6 7 8 MBIAS MIC1P MIC1N MIC2P MIC2N REXT NC AVSS D DESCRIPTION PLLVSS VSS MCLK RESET PWRUPSEL BUZZCON PCMSYN PCMCLK FEATURES D 2.7-V Operation D Two Differential Microphone Inputs, One NC − No internal connection This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 
 
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'  $$ ()% $ !* $  #) #$ *  ## !% Copyright  2001, Texas Instruments Incorporated www.ti.com 1 2 MIC2N MIC2P MIC1N MIC1P PCMCLK PCMSYN PCMIN MIC Amplifier 1 g= 23.5 dB www.ti.com I 2C I/F Control Bus MIC Amplifier 2 g = 12 dB or 0 dB Analog Modulator DTMF Sidetone g = −24 db to −12 dB REF Generator TX Filter and PGA g = 10 dB to 0 dB PCM Interface PLL RX Vol Control g = 18 dB to 0 dB RX Filter and PGA g = −6 dB to +6 dB Power and RESET Buzzer Control Digital Modulator and Filter Ear Amp2 Ear Amp1 BUZZCON EAR2O EAR1ON EAR1OP PCMOUT
  SLAS358 − DECEMBER 2001 functional block diagram PWRUPSEL V SS AV DD DV DD AV SS DV SS PLLV DD EARV DD PLLV SS EARV SS RESET MCLK REXT MBIAS SDATA SCLK 
  SLAS358 − DECEMBER 2001 functional description power-on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low/RESET terminal to assure reset upon power on and to bring the device to an operational state. After the initial power-on sequence the TLV320AIC1109 can be functionally powered up and down by writing to the power control register through the I2C interface. The device has a pin selectable power-up in the default mode option. The hardwired pin-selectable PWRUPSEL function allows the PCM codec to power up in the default mode and to be used without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. control interface The I2C interface is a two-wire bidirectional serial interface. The I2C interface controls the PCM codec by writing data to six control registers: 1) power control, 2) mode control, 3) transmit PGA and sidetone control, 4) receive PGA gain and volume control, 5) DTMF routing, and 6) tone selection control. There are two power-up modes which may be selected at the PWRUPSEL terminal: 1) the PWRUPSEL state (VDD at terminal 20) causes the device to power-up in the default mode when power is applied. Without an I2C interface or controlling device, the programmable functions will be fixed at he default gain levels and functions, such as the sidetone and DTF, will not be accessible. 2) The PWRUPSEL state (ground at terminal 20) causes the device to go to a power-down state when power is applied. In this mode an I2C interface is required to power up the device. phase-locked loop The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the 2.048-MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK may be tied directly to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low noise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of 0 dB or 12 dB. analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either the 15-bit linear or 8-bit companded µ-law or A-law mode that is selectable through the I2C interface. The transmit PGA defaults to 0 dB. www.ti.com 3 
  SLAS358 − DECEMBER 2001 functional description (continued) sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to the mute condition. The default gain of -12 dB is set in the sidetone control register. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of −18 dB to 0 dB in 2 dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates in either the 15-bit linear or 8-bit µ-law or A-law companded mode, which is selectable through the I2C interface. The gain defaults to −1 dB representing a 3 dBm0 level for a 32 Ω to 110 Ω load impedance and the corresponding digital full scale PCMI code of −4 dB. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones which are output to one of the following: 1) the buzzer driver, as a pulse density modulation (PDM) signal, or 2) the receive path digital/analog converter (D/A), for outputting through the earphone or as PCMO data. The integer value is loaded into one of two 8-bit registers, the high tone register [04} or the low tone register {05}. The tone output is 2 dB higher when applied to the high tone register {04}. The high DTMF tones must be applied to the high tone register, and the low DTMF tones to the low tone register. 4 www.ti.com 
  SLAS358 − DECEMBER 2001 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TQFP AVDD AVSS 32 I Analog positive power supply 8 I Analog negative power supply BUZZCON 19 O Buzzer output, a pulse-density modulated signal to apply to external buzzer driver DVDD 13 I Digital positive power supply DVSS 14 I Digital negative power supply EAR1ON 27 O Earphone 1 amplifier output (−) EAR1OP 29 O Earphone 1 amplifier output (+) EAR2O 31 O Earphone 2 amplifier output EARVDD EARVSS 28 I Analog positive power supply for the earphone amplifiers 30, 26 I Analog negative power supply for the earphone amplifiers MBIAS 1 O Microphone bias supply output, no decoupling capacitors MCLK 22 I Master system clock input (2.048 MHz) (digital) MIC1P 2 I MIC1 input (+) MIC1N 3 I MIC1 input (−) MIC2P 4 I MIC2 input (+) MIC2N 5 I MIC2 input (−) PCMI 15 I Receive PCM input PCMO 16 O Transmit PCM output PCMSYN 18 I PCM frame sync PCMCLK 17 I PCM data clock PLLVSS PLLVDD 24 I PLL negative power supply 25 I PLL digital power supply PWRUPSEL 20 I Selects the power-up default mode REXT 6 I/O RESET 21 I SCL 12 I SDA 11 I/O VSS 23 I Internal reference current setting terminal. This terminal uses a precision 100-kΩ resistor and no filtering capacitors. Active low reset I2C-bus serial clock. This input is used to synchronize the data transfer from and to the PCM codec. I2C-bus serial address/data input/output. This is a bidirectional terminal used to transfer register control addresses and data into and out of the codec. It is an open-drain terminal and therefore requires a pullup resistor to VDD (typical 10 kΩ for 100 kHz). Ground return for bandgap internal reference absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature range (industrial temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. www.ti.com 5 
  SLAS358 − DECEMBER 2001 DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING PBS 702 mW 7.2 mW/°C 270 mW recommended operating conditions (see Notes 1 and 2) MIN Supply voltage, AVDD, DVDD, PLLVDD, EARVDD NOM 2.7 MAX UNIT 3.3 V 0.7 × VDD High-level input voltage (VIHMIN) V 0.3 × VDD Low-level input voltage (VILMAX) Load impedance between EAR1OP and EAR1ON-RL Load impedance for EAR2OP-RL Ω 32 Operating free-air temperature, TA V Ω 32 to 110 −40 °C 85 NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, the power-on initialization paragraph should be followed, described in the Principles of Operations. 2. Voltages are with respect to AVSS, DVSS, PLLVSS and EARVSS. electrical characteristics over recommended ranges of supply voltage and free air temperature (unless otherwise noted) supply current PARAMETER TYP MAX Operating, EAR1 selected, MicBias disabled 6 8 mA Operating, EAR2 selected, MicBias disabled 5.4 7 mA Power down, Reg 2 bit 7 = 1, MCLK not present (see Note 3) 0.5 35 µA Power down, Reg 2 bit 7 = 0, MCLK not present (see Note 3) 25 75 µA ton(i) Power-up time from power down 5 10 NOTE 3: Measured while MIC1P and MIC1N are connected together. Less than 5 mV offset results in 0 value code on PCMOUT. ms IDD Supply current from VDD TEST CONDITIONS MIN UNIT digital interface PARAMETER TEST CONDITIONS MAX IIH IIL High-level input current, any digital input CI Input capacitance Co Output capacitance 20 pF RL Load impedance (BUZZCON) 5 kΩ 6 Low-level input current, any digital input www.ti.com DVDD = −0.25 UNIT High-level output voltage PCMO (BUZZCON) VI = VDD VI = VSS VDD = 3 V VDD = 3 V TYP VOH VOL Low-level output voltage PCMO IOH = − 3.2 mA, IOL = 3.2 mA, MIN V 0.25 V 10 µA 10 µA 10 pF 
  SLAS358 − DECEMBER 2001 electrical characteristics over recommended ranges of supply voltage and free air temperature (unless otherwise noted) (continued) microphone interface PARAMETER TEST CONDITIONS VIO IIB Input offset voltage at MIC1N, MIC2N Ci Input capacitance at MIC1N, MIC2N Vn Microphone input referred noise, psophometric weighted, (C-message weighted is similar) IOmax V(mbias) See Note 3 Input bias current at MIC1N, MIC2N MIN TYP MAX −5 5 mV −250 250 nA 5 Micamp 1 gain = 23.5 dB Micamp 2 gain = 0 dB Output source current − MBIAS 2.4 MICMUTE pF 3 7.7 µVrms 1.2 mA 2.5 2.55 V 60 100 kΩ 1 Microphone bias supply voltage (see Note 4) −80 Input impedance Fully differential UNIT 35 dB NOTES: 3. Measured while MIC1P and MIC1N are connected together. Less than 5-mV offset results in 0 value code on PCMOUT. 4. Not a JEDEC symbol speaker interface PARAMETER TEST CONDITIONS Earphone AMP1 output power (See Note 5) VOO IOmax TYP MAX UNIT Fully differential, 110-Ω load, 3-dBm0 output, RGXPA = − 4 dB 23.4 31.2 mW VDD = 2.7 V, fully differential, 32-Ω load, 3-dBm0 output, RGXPA = −4 dB 80.5 107.3 mW 10 12.5 mW mV Earphone AMP2 output power (See Note 5) VDD = 2.7 V, single ended, 32-Ω load, 3-dBm0 output Output offset voltage at EAR1 Fully differential Maximum output current for EAR1(rms) Maximum output current for EAR2 (rms) MIN ±5 ±30 3-dBm0 input, 110-Ω load 14.6 19.4 3-dBm0 input, 32-Ω load 50.2 66.9 17.7 22.1 3-dBm0 input EARMUTE −80 mA dB NOTE 5: Maximum power is with a load impedance of −25%. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (see Notes 6 and 7) PARAMETER Transmit reference-signal level (0dB) Overload-signal level (3 dBm0) Absolute gain error MAX UNIT Differential TEST CONDITIONS 175 mVpp Differential, normal mode 248 0 dBm0 input signal, VDD ±10% TYP 63 mVpp −1 1 dB −0.5 0.5 Differential, extended mode MIC1N, MIC1P to PCMO at 3 dBm0 to −30 dBm0 Gain error with input level relative to gain at −10 dBm0 MIC1N, MIC1P to PCMO MIN MIC1N, MIC1P to PCMO at −31 dBm0 to −45 dBm0 −1 1 MIC1N, MIC1P to PCMO at −46 dBm0 to −55 dBm0 −1.2 1.2 dB NOTES: 6. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 7. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. www.ti.com 7 
  SLAS358 − DECEMBER 2001 electrical characteristics over recommended ranges of supply voltage and free air temperature (unless otherwise noted) (continued) transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter enabled (see Notes 6 and 7) PARAMETER Transmit reference-signal level (0dB) Overload-signal level (3 dBm0) MAX UNIT Differential TEST CONDITIONS 175 mVpp Differential, normal mode 248 MIC1N, MIC1P to PCMO at 3 dBm0 to −30 dBm0 Gain error with input level relative to gain at −10 dBm0 MIC1N, MIC1P to PCMO TYP 63 mVpp −1 1 dB −0.5 0.5 Differential, extended mode 0 dBm0 input signal, VDD ±10 % Absolute gain error MIN MIC1N, MIC1P to PCMO at −31 dBm0 to −45 dBm0 −1 1 MIC1N, MIC1P to PCMO at −46 dBm0 to −55 dBm0 −1.2 1.2 dB NOTES: 6. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 7. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed, external high-pass filter bypassed (MCLK = 2.048 MHz) PARAMETER Gain relative to input signal gain at 1020 Hz, internal high-pass filter disabled. Gain relative to input signal gain at 1020 Hz, internal high-pass filter enabled. 8 TEST CONDITIONS MIN TYP MAX fMIC1 or fMIC2