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TLV341, TLV341A, TLV342, TLV342S
SLVS568D – JANUARY 2005 – REVISED APRIL 2016
TLV34xx Low-Voltage Rail-to-Rail Output CMOS Operational Amplifiers
With Shutdown
1 Features
3 Description
•
•
The TLV34xx devices are single and dual CMOS
operational amplifiers, respectively, with low-voltage,
low-power, and rail-to-rail output swing capabilities.
The PMOS input stage offers an ultra-low input bias
current of 1 pA (typical) and an offset voltage of
0.3 mV (typical). For applications requiring excellent
dc precision, the A grade (TLV34xA) has a low offset
voltage of 1.25 mV (maximum) at 25°C.
1
•
•
•
•
•
•
•
•
•
•
•
1.8-V and 5-V Performance
Low Offset (A Grade)
– 1.25 mV Maximum (25°C)
– 1.7 mV Maximum (–40°C to 125°C)
Rail-to-Rail Output Swing
Wide Common-Mode Input Voltage Range: –0.2 V
to (V+ – 0.5 V)
Input Bias Current: 1 pA (Typical)
Input Offset Voltage: 0.3 mV (Typical)
Low Supply Current: 70 μA/Channel
Low Shutdown Current:
10 pA (Typical) Per Channel
Gain Bandwidth: 2.3 MHz (Typical)
Slew Rate: 0.9 V/μs (Typical)
Turnon Time From Shutdown: 5 μs (Typical)
Input Referred Voltage Noise (at 10 kHz):
20 nV/√Hz
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (HBM)
– 750-V Charged-device model (CDM)
These single-supply amplifiers are designed
specifically for ultra-low-voltage (1.5 V to 5 V)
operation, with a common-mode input voltage range
that typically extends from –0.2 V to 0.5 V from the
positive supply rail.
The TLV341 (single) and TLV342 (dual) in the RUG
package also offer a shutdown (SHDN) pin that can
be used to disable the device. In shutdown mode, the
supply current is reduced to 45 pA (typical). Offered
in both the SOT-23 and smaller SC70 packages, the
TLV341 is suitable for the most space-constrained
applications. The dual TLV342 is offered in the
standard SOIC, VSSOP, and X2QFN packages.
An extended industrial temperature range from –40°C
to 125°C makes the TLV34xx suitable in a wide
variety of commercial and industrial applications.
2 Applications
•
•
•
•
•
•
•
•
Device Information(1)
Cellular Phones
Consumer Electronics (Laptops)
Audio Preamplifier for Voice
Portable and Battery-Powered Electronic
Equipment
Supply Current Monitoring
Battery Monitoring
Buffers
Filters
PART NUMBER
TLV341
TLV342
TLV342S
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (6)
2.00 mm × 1.25 mm
SOT (6)
1.60 mm × 1.20 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
X2QFN (10)
1.50 mm × 2.00 mm
X2QFN (10)
1.50 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Sample and Hold Circuit Using Two TLV341
V+
V+
−
VO
−
+
VI
+
C = 200 pF
Sample
Clock
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV341, TLV341A, TLV342, TLV342S
SLVS568D – JANUARY 2005 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
5
5
5
5
6
7
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: TLV341 ...................................
Thermal Information: TLV342 ...................................
Thermal Information: TLV342S .................................
Electrical Characteristics: V+ = 1.8 V ........................
Electrical Characteristics: V+ = 5 V ...........................
Shutdown Characteristics: V+ = 1.8 V.......................
Shutdown Characteristics: V+ = 5 V........................
Typical Characteristics ............................................
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2007) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Removed DPK package and TLV344 part from the Pin Configuration and Functions table ................................................ 3
2
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SLVS568D – JANUARY 2005 – REVISED APRIL 2016
5 Pin Configuration and Functions
TLV341 DBV or DCK Package
6-Pin SOT-23 or SC70
Top View
IN+
GND
IN−
1
6
2
5
3
4
TLV341 DRL Package
6-Pin SOT
Top View
V+
SHDN
OUT
GND
IN+
IN−
1
6
2
5
3
4
V+
SHDN
OUT
Pin Functions: TLV341
PIN
NAME
I/O
DESCRIPTION
SOT-23, SC70
SOT
1IN+
1
2
I
Noninverting input on channel 1
1IN–
3
3
I
Inverting input on channel 1
1OUT
4
4
O
Output on channel 1
GND
2
1
—
Ground
SHDN
5
5
I
Shutdown active low
V+
6
6
—
Positive power supply
TLV342 D or DGK Package
10-Pin SOIC or VSSOP
Top View
1OUT
1IN−
1IN+
GND
1
8
2
7
3
6
4
5
TLV342 RUG Package
10-Pin X2QFN
Top View
1IN−
V+
2OUT
2IN−
2IN+
10
1IN+
1
GND
2
8 NC
NC
3
7 V+
2IN+
4
5
9 1OUT
6 2OUT
2IN−
Pin Functions: TLV342
PIN
NAME
SOIC, VSSOP
X2QFN
I/O
DESCRIPTION
1IN+
3
1
I
Noninverting input on channel 1
1IN–
2
10
I
Inverting input on channel 1
1OUT
1
9
O
Output on channel 1
2IN+
5
4
I
Noninverting input on channel 2
2IN–
6
5
I
Inverting input on channel 2
2OUT
7
6
O
Output on channel 2
GND
4
2
—
Ground
NC (1)
—
3, 8
—
Not connected
V+
8
7
—
Positive power supply
(1)
NC – No internal connection
Copyright © 2005–2016, Texas Instruments Incorporated
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TLV341, TLV341A, TLV342, TLV342S
SLVS568D – JANUARY 2005 – REVISED APRIL 2016
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TLV342S RUG Package
10-Pin X2QFN
Top View
1IN−
10
1IN+
1
GND
2
8 NC
SHDN
3
7 V+
2IN+
4
5
9 1OUT
6 2OUT
2IN−
Pin Functions: TLV342S
PIN
NAME
I/O
NO.
DESCRIPTION
1IN+
1
I
Noninverting input on channel 1
1IN–
10
I
Inverting input on channel 1
1OUT
9
O
Output on channel 1
2IN+
4
I
Noninverting input on channel 2
2IN–
5
I
Inverting input on channel 2
2OUT
6
O
Output on channel 2
GND
2
—
Ground
NC (1)
8
—
Not connected
SHDN
3
I
Shutdown active low
V+
7
—
Positive power supply
(1)
NC – No internal connection
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
(2)
V+
Supply voltage
VID
Differential input voltage (3)
VI
Input voltage (either input or shutdown)
VO
Output voltage
TJ
Operating virtual-junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
MAX
UNIT
–0.3
5.5
V
±5.5
V
–0.3
5.5
V
–0.3
VCC + 0.3
V
150
°C
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values (except differential voltages) are with respect to the network GND.
Differential voltages are at IN+ with respect to IN−.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLVS568D – JANUARY 2005 – REVISED APRIL 2016
6.3 Recommended Operating Conditions
MIN
MAX
V+
Supply voltage (single-supply operation)
1.5
5.5
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information: TLV341
TLV341
THERMAL METRIC (1)
DBV
(SOT-23)
DCK
(SC70)
DRL
(SOT)
UNIT
6 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
193.4
196.8
221.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
145.6
82.4
109.1
°C/W
RθJB
Junction-to-board thermal resistance
44.1
95.2
111.4
°C/W
ψJT
Junction-to-top characterization parameter
34.1
1.8
6.2
°C/W
ψJB
Junction-to-board characterization parameter
43.4
93.2
109.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: TLV342
TLV342
THERMAL METRIC
(1)
D
(SOIC)
DGK
(MSOP)
RUG
(X2QFN)
10 PINS
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
123.6
192.3
167
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.8
78.2
56.5
°C/W
RθJB
Junction-to-board thermal resistance
63.9
112.6
94.3
°C/W
ψJT
Junction-to-top characterization parameter
24.4
15.2
4.1
°C/W
ψJB
Junction-to-board characterization parameter
63.4
111.2
94
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information: TLV342S
TLV342S
THERMAL METRIC
RUG
(X2QFN)
(1)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
158.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.6
°C/W
RθJB
Junction-to-board thermal resistance
87.9
°C/W
ψJT
Junction-to-top characterization parameter
1
°C/W
ψJB
Junction-to-board characterization parameter
87
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2005–2016, Texas Instruments Incorporated
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SLVS568D – JANUARY 2005 – REVISED APRIL 2016
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6.7 Electrical Characteristics: V+ = 1.8 V
V+ = 1.8 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted). See Shutdown Characteristics: V+ = 1.8 V.
PARAMETER
TEST CONDITIONS
A grade
αVIO
IIB
Input bias current
Input offset current
CMRR
Common-mode rejection ratio
0 ≤ VICR ≤ 1.2 V
kSVR
Supply-voltage rejection ratio
1.8 V ≤ V+ ≤ 5 V
VICR
Common-mode input voltage
range
CMRR ≥ 60 dB
Large-signal voltage gain (2)
AV
RL = 2 kΩ to 1.35 V
Low level
RL = 2 kΩ to 1.35 V
High level
Output swing
(delta from supply rails)
VO
Low level
RL = 10 kΩ to 1.35 V
High level
UNIT
4
4.5
25°C
0.3
1.25
0°C to 125°C
0.3
1.5
–40°C to 125°C
0.3
1.7
Full range
1.9
1
100
375
–40°C to 125°C
3000
6.6
25°C
60
Full range
50
25°C
75
Full range
65
25°C
0
25°C
70
Full range
60
25°C
65
Full range
55
25°C
mV
μV/°C
–40°C to 85°C
25°C
RL = 10 kΩ to 1.35 V
MAX
0.3
25°C
IIO
TYP (1)
Full range
Input offset voltage
Average temperature coefficient
of input offset voltage
MIN
25°C
Standard grade
VIO
TA
pA
fA
85
dB
95
dB
1.2
V
110
dB
100
22
Full range
50
75
25°C
25
Full range
50
75
25°C
14
Full range
20
mV
25
25°C
7
20
70
150
Full range
25
25°C
μA
ICC
Supply current (per channel)
IOS
Output short-circuit current
SR
Slew rate
RL = 10 kΩ (3)
25°C
0.9
V/μs
GBW
Unity-gain bandwidth
RL = 10 kΩ, CL = 200 pF
25°C
2.2
MHz
φm
Phase margin
RL = 100 kΩ, CL = 200 pF
25°C
55
°
Gm
Gain margin
RL = 100 kΩ, CL = 200 pF
25°C
15
dB
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
33
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.001
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = 1, RL = 600 Ω,
VI = 1 VPP
25°C
0.015%
THD
(1)
(2)
(3)
6
Full range
Sourcing
Sinking
25°C
200
6
12
10
20
mA
Typical values represent the most likely parametric norm.
GND + 0.2 V ≤ VO ≤ V+ – 0.2 V
Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.
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SLVS568D – JANUARY 2005 – REVISED APRIL 2016
6.8 Electrical Characteristics: V+ = 5 V
V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted). See Shutdown Characteristics: V+ = 5 V.
PARAMETER
TEST CONDITIONS
A grade
αVIO
IIB
Input bias current
Input offset current
CMRR
Common-mode rejection ratio
0 ≤ VICR ≤ 4.4 V
kSVR
Supply-voltage rejection ratio
1.8 V ≤ V+ ≤ 5 V
VICR
Common-mode input voltage
range
CMRR ≥ 70 dB
Large-signal voltage gain (2)
AV
RL = 2 kΩ to 2.5 V
Low level
RL = 2 kΩ to 2.5 V
High level
Output swing
(delta from supply rails)
VO
Low level
RL = 10 kΩ to 2.5 V
High level
UNIT
4
4.5
25°C
0.3
1.25
0°C to 125°C
0.3
1.5
–40°C to 125°C
0.3
1.7
Full range
1.9
1
mV
μV/°C
200
–40°C to 85°C
375
–40°C to 125°C
3000
25°C
RL = 10 kΩ to 2.5 V
MAX
0.3
25°C
IIO
TYP (1)
Full range
Input offset voltage
Average temperature coefficient
of input offset voltage
MIN
25°C
Standard grade
VIO
TA
pA
6.6
25°C
75
Full range
70
25°C
75
Full range
65
25°C
0
25°C
80
Full range
70
25°C
75
Full range
60
25°C
fA
90
dB
95
dB
4.4
V
110
dB
105
40
Full range
60
85
25°C
25
Full range
60
85
25°C
18
Full range
mV
30
40
25°C
7
15
75
150
Full range
20
25°C
μA
ICC
Supply current (per channel)
IOS
Output short-circuit current
SR
Slew rate
RL = 10 kΩ (3)
25°C
1
V/μs
GBW
Unity-gain bandwidth
RL = 10 kΩ, CL = 200 pF
25°C
2.3
MHz
φm
Phase margin
RL = 100 kΩ, CL = 200 pF
25°C
55
°
Gm
Gain margin
RL = 100 kΩ, CL = 200 pF
25°C
15
dB
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
33
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.001
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = 1, RL = 600 Ω,
VI = 1 VPP
25°C
0.012%
THD
(1)
(2)
(3)
Full range
Sourcing
Sinking
200
25°C
60
113
80
115
mA
Typical values represent the most likely parametric norm.
GND + 0.2 V ≤ VO ≤ V+ – 0.2 V
Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.
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6.9 Shutdown Characteristics: V+ = 1.8 V
V+ = 1.8 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
ICC(SHDN)
Supply current in shutdown mode
t(on)
Amplifier turnon time
VSD
TEST CONDITIONS
VSD = 0 V
TA
MIN
25°C
0.01
Full range
Recommended shutdown pin voltage range
Shutdown mode
25°C
MAX
1
1.5
25°C
On mode
TYP
UNIT
μA
μs
5
1.5
1.8
0
0.5
V
6.10 Shutdown Characteristics: V+ = 5 V
V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
ICC(SHDN)
Supply current in shutdown mode
t(on)
Amplifier turnon time
VSD
8
TEST CONDITIONS
VSD = 0 V
TA
MIN
25°C
Recommended shutdown pin voltage range
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Shutdown mode
MAX
0.01
1
Full range
1.5
25°C
On mode
TYP
25°C
UNIT
μA
μs
5
4.5
5
0
0.8
V
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SLVS568D – JANUARY 2005 – REVISED APRIL 2016
6.11 Typical Characteristics
130
1,000
V+ = 5 V
120
IIB − Input Bias Current − pA
ICC − Supply Current − µA
110
125°C
100
90
85°C
80
25°C
70
60
−40°C
50
100
10
1
40
30
1.5
2
2.5
3
3.5
4
4.5
0.1
−40 −20
5
VCC − Supply Voltage − V
7
35
RL = 2 kΩ
VO − Output Swing From Supply Voltage − mV
VO − Output Swing From Supply Voltage − mV
140
Figure 2. Input Bias Current vs
Temperature
Figure 1. Supply Current vs
Supply Voltage
30
Negative Swing
25
20
Positive Swing
15
10
1.5
2
2.5
3
3.5
4
4.5
RL = 10 kΩ
6.5
6
5
4.5
4
Positive Swing
3.5
3
5
Negative Swing
5.5
1.5
2
2.5
3
3.5
4
4.5
5
VCC − Supply Voltage − V
VCC − Supply Voltage − V
Figure 3. Output Voltage Swing vs
Supply Voltage
Figure 4. Output Voltage Swing vs
Supply Voltage
1000
1000
V+ = 5 V
V+ = 2.7 V
IS − Source Current − mA
−40°C
25°C
10
85°C
1
125°C
10
25°C
85°C
1
125°C
0.1
0.1
0.01
0.001
−40°C
100
100
IS − Source Current − mA
0
20
40
60
80 100 120
TA − Free-Air Temperature − °C
0.01
0.1
1
10
0.01
0.001
0.01
0.1
1
VO − Output Voltage Referenced to V+ (V)
VO − Output Voltage Referenced to V+ (V)
Figure 5. Source Current vs
Output Voltage
Figure 6. Source Current vs
Output Voltage
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Typical Characteristics (continued)
1000
V+ = 2.7 V
V+ = 5 V
100
100
−40°C
−40°C
IS − Sink Current − mA
IS − Sink Current − mA
1000
10
25°C
85°C
1
125°C
0.1
10
25°C
85°C
1
125°C
0.1
0.01
0.001
0.01
0.1
1
0.01
0.001
10
0.1
Figure 8. Sink Current vs
Output Voltage
1
0.5
0
0
VIO − Offset Voltage − mV
0.5
−0.5
−1
125°C
−1.5
85°C
−2
25°C
V+ = 5 V
−0.5
−1
125°C
85°C
−1.5
25°C
−2
−40°C
−40°C
−2.5
−2.5
−3
−0.2
0.8
1.8
−3
−0.2
2.8
VIC − Common-Mode Voltage − V
0.8
1.8
2.8
3.8
4.8
VIC − Common-Mode Voltage − V
Figure 9. Offset Voltage vs
Common-Mode Voltage
Figure 10. Offset Voltage vs
Common-Mode Voltage
300
V+ /GND = ±1.35 V
VI − Input Voltage − mV
200
RL = 2 kΩ
100
0
RL = 10 kΩ
200
−200
−200
−1
0
1
2
3
VO − Output Voltage − V
Figure 11. Input Voltage vs Output Voltage
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RL = 10 kΩ
0
−100
−2
RL = 2 kΩ
100
−100
−300
−3
5.8
300
V+ /GND = ±2.5 V
VI − Input Voltage − µV
10
Figure 7. Sink Current vs
Output Voltage
V+ = 2.7 V
10
1
VO − Output Voltage Referenced to V− (V)
1
VIO − Offset Voltage − mV
0.01
VO − Output Voltage Referenced to V− (V)
−300
−1.5
−1
−0.5
0
0.5
1
1.5
VO − Output Voltage − V
Figure 12. Input Voltage vs
Output Voltage
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Typical Characteristics (continued)
2.5
1.9
RL = 10 kΩ
AV = 1
VI = 2 VPP
V+ = 2.7 V
2.3
Falling Edge
1.7
SR − Slew Rate − V/µs
SR − Slew Rate − V/ms
2.1
1.5
1.3
Rising Edge
1.1
0.9
0.5
1.5
2
Falling Edge
1.7
1.5
1.3
Rising Edge
1.1
0.9
RL = 10 kΩ
AV = 1
VI = 0.8 VPP for V+ < 2.7 V
VI = 2 VPP for V+ > 2.7 V
0.7
1.9
0.7
2.5
3
3.5
4
VCC − Supply Voltage − V
4.5
0.5
−40 −20
5
Figure 13. Slew Rate vs
Supply Voltage
Figure 14. Slew Rate vs
Temperature
2.5
100
RL = 10 kΩ
AV = 1
VI = 2 VPP
V+ = 5 V
2.3
90
1.9
70
Falling Edge
1.7
1.5
1.3
Rising Edge
60
50
2.7 V
40
1.1
30
0.9
20
0.7
10
0.5
−40 −20
5V
80
Gain − dB
SR − Slew Rate − V/µs
2.1
VI = V+ /2
RL = 5 kΩ
0
100
1K
0
20 40
60
80 100 120 140
TA – Free-Air Temperature – °C
Figure 15. Slew Rate vs
Temperature
100
1M
220
200
VI − Input Voltage Noise − nV/ Hz
−PSRR (2.7 V)
80
70
Gain − dB
10K
100K
f − Frequency − Hz
Figure 16. CMRR vs Frequency
+PSRR (2.7 V)
90
60
0
20
40
60
80 100 120 140
TA – Free-Air Temperature – °C
−PSRR (5 V)
50
+PSRR (5 V)
40
30
20
10
0
100
160
140
120
100
80
5V
2.7 V
60
40
20
RL = 5 kΩ
1K
180
0
10K
100K
f − Frequency − Hz
1M
Figure 17. PSRR vs Frequency
Copyright © 2005–2016, Texas Instruments Incorporated
10M
10
100
1K
10K
f − Frequency − Hz
Figure 18. Input Voltage Noise vs
Frequency
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10
RL = 600 Ω
VO = 1 VPP for V+ = 2.7 V
VO = 2.5 VPP for V+ = 5 V
1
5V
AV = 10
2.7 V
AV = 10
2.7 V
AV = 1
0.01
5V
AV = 1
0.001
0.0001
10
100
1K
10K
f − Frequency − Hz
100K
Figure 19. Total Harmonic Distortion +Noise
vs Frequency
100
Gain − dB
140
140
120
120
100
100
80
−40°C
Gain
60
80
−40°C
25°C
60
40
125°C
20
125°C
10
1K
5V
AV = 1
0.01
0.001
0.01
0.1
1
VO − Output Voltage − VPP
100
60
RL = 100 kΩ
RL = 100 kΩ
40
RL = 2 kΩ
20
RL = 600 Ω
10
100
1K
f − Frequency − kHz
140
160
V+ = 5 V
Closed-Loop
Gain = 60 dB
Phase
RL = 600 Ω
Gain
RL = 2 kΩ
RL = 100 kΩ
80
60
40
RL = 100 kΩ
40
RL = 2 kΩ
RL = 600 Ω
CL = 0 pF
100
60
40
CL = 500 pF
Gain
CL = 1000 pF
60
20
0
40
CL = 0 pF
20
−20
0
−40
100
f − Frequency − kHz
1K
Figure 23. Frequency Response vs RL
12
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10K
−20
−40
0
20
CL = 500 pF
CL = 1000 pF
10
80
CL = 100 pF
80
Gain − dB
100
80
100
Phase
V+ = 5 V
RL = 600 Ω
Closed-Loop Gain = 60 dB
120
140
120
1
0
10K
−20
Phase Margin − Deg
Gain − dB
60
40
Figure 22. Frequency Response vs RL
100
−20
80
RL = 2 ΩW
Gain
0
10K
140
0
140
120
f − Frequency − kHz
20
160
Phase
Figure 21. Frequency Response vs
Temperature
60
10
V+ = 2.7 V
Closed-Loop
Gain = 60 dB
1
120
2.7 V
AV = 1
RL = 600 Ω
20
100
0.1
20
0
1
2.7 V
AV = 10
80
40
25°C
0
−20
160
Phase Margin − Deg
Gain − dB
V+ = 5 V
RL = 2 kΩ
120
1
Figure 20. Total Harmonic Distortion +Noise
vs Output Voltage
140
Phase
5V
AV = 10
Phase Margin − Deg
0.1
f = 10 kHz
RL = 600 Ω
Phase Margin − Deg
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Typical Characteristics (continued)
1
10
100
f − Frequency − kHz
−60
CL = 100 pF
1K
10K
−80
Figure 24. Frequency Response vs CL
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Typical Characteristics (continued)
0.1
0.25
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
VI − Input Voltage − V
−0.2
−0.05
5
1
4
0
−1
3
2
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
1
−3
0
−4
−5
−1
Output
Output
−0.25
−0.1
−6
−2
4 µs/div
4 µs/div
Figure 25. Small-Signal Noninverting Response
Figure 26. Large-Signal Noninverting Response
0.1
0.25
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
VO − Output Voltage − V
VO − Output Voltage − V
0
0.15
VI − Input Voltage − V
0.05
−0.2
−0.05
5
1
4
0
3
2
−1
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
1
−3
0
−4
−1
−5
Output
Output
−2
−0.25
−6
4 µs/div
4 µs/div
Figure 27. Small-Signal Noninverting Response
Figure 28. Large-Signal Noninverting Response
0.1
0.25
2
6
Input
Input
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
5
1
0
4
0
−0.05
−0.1
0.05
−0.15
0
−0.05
VO − Output Voltage − V
0.15
0.05
VI − Input Voltage − V
VO − Output Voltage − V
0.2
0.1
−2
−1
3
2
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
−2
1
−3
0
−4
−0.2
−5
−1
Output
−0.1
VI − Input Voltage − V
Input
−0.1
2
6
Input
0.2
0.1
−2
VI − Input Voltage − V
VO − Output Voltage − V
0
0.15
VO − Output Voltage − V
0.05
VI − Input Voltage − V
Input
0.2
0.1
2
6
Input
Output
−0.25
4 µs/div
Figure 29. Small-Signal Noninverting Response
Copyright © 2005–2016, Texas Instruments Incorporated
−2
4 µs/div
−6
Figure 30. Large-Signal Noninverting Response
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Typical Characteristics (continued)
6
0.1
0.25
−0.15
0
−0.2
−0.05
1
4
0
3
2
−1
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
1
−3
0
−4
−1
−5
Output
Output
−2
−0.25
4 µs/div
4 µs/div
Figure 32. Large-Signal Inverting Response
Figure 31. Small-Signal Noninverting Response
0.1
0.25
2
6
Input
Input
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
5
1
0
4
0
−0.05
−0.1
0.05
−0.15
0
−0.2
−0.05
VO − Output Voltage − V
0.15
0.05
VI − Input Voltage − V
VO − Output Voltage − V
0.2
0.1
−1
3
2
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
−3
0
−4
−5
−1
Output
−0.25
−0.1
Figure 33. Small-Signal Inverting Response
2
6
Input
Input
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
−0.2
−0.05
VO − Output Voltage − V
0
0.15
VI − Input Voltage − V
0.05
0.2
VO − Output Voltage − V
4 µs/div
Figure 34. Large-Signal Inverting Response
0.1
0.25
−6
−2
4 µs/div
5
1
4
0
−1
3
2
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
−2
1
−3
0
−4
−5
−1
Output
Output
−0.25
−0.1
−6
−2
4 µs/div
4 µs/div
Figure 35. Small-Signal Inverting Response
14
−2
1
Output
0.1
−6
VI − Input Voltage − V
−0.1
−2
VI − Input Voltage − V
−0.1
5
VI − Input Voltage − V
0.05
−0.05
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
VO − Output Voltage − V
VO − Output Voltage − V
0
0.15
VI − Input Voltage − V
0.05
0.2
0.1
2
Input
Input
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Figure 36. Large-Signal Inverting Response
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7 Detailed Description
7.1 Overview
The TLV34xx devices are precision operational amplifiers with CMOS inputs for very low input bias current.
Grade A devices offer lower VIO for high accuracy in direct-coupled applications. Output is rail to rail and input
common mode includes ground. TLV341 and TLV342S have shutdown mode for very low supply current.
7.2 Functional Block Diagram
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 PMOS Input Stage
PMOS Input Stage supports a lower input range that includes ground. Upper range limit is VCC – 0.6 V.
7.3.2 CMOS Output Stage
The CMOS drain output topology allows rail-to-rail output swing.
7.3.3 Shutdown
TLV341 and TLV342S include a shutdown pin. During shutdown, ICC is nearly zero and the output becomes high
impedance. The typical turnon time coming out of shutdown is 5 µs.
7.4 Device Functional Modes
The TLV34xx devices have two operation modes:
• Normal operation when SHDN pin is at V+ level or the SHDN pin is not present
• Shutdown mode when SHDN is at GND level; ICC is very low and output is high impedance.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV34xx devices have rail-to-rail output and input range from ground to VCC – 0.6 V. CMOS inputs provide
very low input current. Shutdown capability is an option in dual amplifier version. Operation from 1.5 V to 5.5 V is
possible.
8.2 Typical Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
RF
RI
Vsup+
VOUT
VIN
+
VsupCopyright © 2016, Texas Instruments Incorporated
Figure 37. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output voltage range.
For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ± 2 V is sufficient to
accommodate this application. The supplies can power up in any order; however, neither supply can be of
opposite polarity relative to ground at any time; otherwise, a large current can flow though the input ESD diodes.
TI highliy recommends adding a series resistor to the grounded input to limit current in such an occurrence.
Vsup+ must be more positive than Vsup– at all times; otherwise, a large reverse supply current may flow.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable
because the amplifier circuit uses currents in the mA range. This ensures the part does not draw too much
current. For this example, choose 10 kΩ for RI, which means 36 kΩ is used for RF. This was determined by
Equation 3.
(3)
16
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Typical Application (continued)
8.2.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 38. Input and Output Voltages of the Inverting Amplifier
9 Power Supply Recommendations
CAUTION
Supply voltages larger than 5.5 V for a single supply can permanently damage the
device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds while paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Guidelines.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
RIN
VIN
RG
+
VOUT
RF
Figure 39. Layout Schematic
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
NC
NC
IN1í
VCC+
IN1+
OUT
VCCí
NC
VS+
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 40. Operational Amplifier Schematic for Noninverting Configuration
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV341
Click here
Click here
Click here
Click here
Click here
TLV341A
Click here
Click here
Click here
Click here
Click here
TLV342
Click here
Click here
Click here
Click here
Click here
TLV342S
Click here
Click here
Click here
Click here
Click here
11.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2005–2016, Texas Instruments Incorporated
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19
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV341AIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
YCGE
Samples
TLV341AIDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
YCGE
Samples
TLV341AIDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y5E
Samples
TLV341AIDCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y5E
Samples
TLV341AIDCKTG4
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y5E
Samples
TLV341IDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
YC9E
Samples
TLV341IDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y4E
Samples
TLV341IDCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y4E
Samples
TLV341IDRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(Y4A, Y4W)
Samples
TLV342AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY342A
Samples
TLV342AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY342A
Samples
TLV342ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY342
Samples
TLV342IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y6A
Samples
TLV342IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY342
Samples
TLV342IRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y6E
Samples
TLV342SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2YE
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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