Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TLV522
SNOSD27 – MAY 2016
TLV522 Dual Nanopower, 500nA, RRIO CMOS Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The TLV522 500 nA dual, nanopower op amp offers
optimum price performance in TI's nanopower family
of operational amplifiers. The TLV522 provides 8 kHz
of gain bandwidth from 500 nA of quiescent current,
making it well suited for battery powered applications
found in building automation and remote sensing
nodes. Its CMOS input stage enables very low IBIAS,
reducing errors commonly introduced in Megaohm
feedback resistance topologies such as highimpedance
photodiode
and
charge
sense
applications. Additionally, built-in EMI protection
reduces sensitivity to unwanted RF signals from
sources like mobile phones, WiFi, radio transmitters
and RFID readers.
1
Unmatched Price Performance
Wide Supply Range 1.7 V to 5.5 V
Low Supply Current 500 nA
Good Offset Voltage 4 mV (max)
Good TcVos 1.5 µV/°C
Gain-Bandwidth 8 kHz
Rail-to-Rail Input and Output (RRIO)
Unity-Gain Stable
Low Input Bias Current 1 pA
EMI Hardened
Temperature Range –40°C to 125°C
8-pin VSSOP Package
The TLV522 is offered in the 8-pin VSSOP (MSOP)
package, and operates from –40°C to 125°C.
2 Applications
•
•
•
•
•
•
•
•
Personal Health Monitors
Battery Packs
Solar-Powered or Energy Harvested Systems
PIR, Smoke, Gas, and Fire Detection Systems
Battery Powered Internet of Things (IoT) Devices
Remote Sensors/Wireless Sensing Nodes
Wearables
Glucose Monitoring
Device Information(1)
PART NUMBER
TLV522
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
Nanopower Oxygen Sensor Amplifier
100 M
+
V
1M
+
VOUT
RL
OXYGEN SENSOR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV522
SNOSD27 – MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
3
3
4
5
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Ratings............................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application: 60 Hz Twin "T" Notch Filter..... 12
8.3 Do's and Don'ts ...................................................... 13
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
DATE
REVISION
NOTES
May 2016
*
Initial release.
5 Pin Configuration and Functions
8-Pin VSSOP
DGK Package
Top View
OUT A
1
8
V+
7
OUT B
A
-IN A
2
B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions
PIN
2
I/O
DESCRIPTION
PIN
NAME
1
OUT A
O
Channel A Output
2
–IN A
I
Channel A Inverting Input
3
+IN A
I
Channel A Non-Inverting Input
4
V–
P
Negative (lowest) power supply
5
+IN B
I
Channel B Non-Inverting Input
6
–IN B
I
Channel B Inverting Input
7
OUT B
O
Channel B Output
8
V+
P
Positive (highest) power supply
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
Supply voltage, V+ to V–
Voltage
Signal input pins
(2)
MIN
MAX
UNIT
-0.3
6
V
-
Current (2)
+
V – 0.3
V + 0.3
V
–10
10
mA
Continuous (4)
Output short current
Junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current-limited to 10 mA or less.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Short-circuit to V–.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply Voltage ( V+– V− )
1.7
5.5
V
Specified Temperature
–40
125
°C
6.4 Thermal Information
TLV522
THERMAL METRIC
(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
73.6
RθJB
Junction-to-board thermal resistance
104.1
ψJT
Junction-to-top characterization parameter
13.7
ψJB
Junction-to-board characterization parameter
102.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
182.5
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
3
TLV522
SNOSD27 – MAY 2016
www.ti.com
6.5 Electrical Characteristics
TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ , unless otherwise noted.
MIN
TYP (1)
MAX
VCM = 0.3 V
–4
±1
4
VCM = 3 V
–4
±1
4
PARAMETER
TEST CONDITIONS
UNIT
OFFSET VOLTAGE
Input offset voltage (VOS)
Drift (dVOS/dT)
Power-Supply Rejection Ratio
(PSRR)
V+ = 1.8 V to 3.3 V, VCM = 0.3 V
80
mV
1.5
µV/°C
109
dB
INPUT VOLTAGE RANGE
Common-Mode voltage range (VCM)
CMRR ≥ 62 dB
Common-Mode Rejection Ratio
(CMRR)
0 V < VCM < 3.3 V
0
62
0 V < VCM < 2.2V
3.3
90
V
dB
90
INPUT BIAS CURRENT
Input bias current (IBIAS)
±1
Input offset current (IOS)
±0.1
pA
INPUT IMPEDANCE
Differential
1013 || 2.5
Common mode
1013 || 2.5
Ω || pF
NOISE
Input voltage noise density, f = 1 kHz (en)
Current noise density, f = 1 kHz (in)
300
nV/√Hz
65
fA√Hz
101
dB
OPEN-LOOP GAIN
Open-loop voltage gain (AOL)
V+ = 5 V
RL = 100 kΩ to V+/2, 0.5 V < VO < 4.5 V
91
OUTPUT
Voltage output swing from positive rail
V+ = 1.8 V, RL = 100 kΩ to V+/2
+
+
3
20
2
20
Voltage output swing from negative rail
V = 1.8 V, RL = 100 kΩ to V /2
Output current sourcing
Sourcing, V+ = 1.8 V
VO to V–, VIN(diff) = 100 mV
1
3
Output current sinking
Sinking, V+ = 1.8 V
VO to V+, VIN(diff) = –100 mV
1
5
mV
mA
FREQUENCY RESPONSE
Gain-bandwidth product (GBWP)
CL = 20 pF
8
Slew rate (SR)
G = +1, Rising edge, 1Vp-p, CL = 20 pF
3.6
G = +1, Falling edge, 1Vp-p, CL = 20 pF
3.7
VCM = 0.3 V, IO = 0
500
kHz
V/ms
POWER SUPPLY
Quiescent current per channel (IQ)
(1)
4
800
nA
Refer to Typical Characteristics.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
6.6 Typical Characteristics
TA = 25 °C, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
1000
Supply Current per Channel (nA/Ch)
Supply Current per Channel (nA/Ch)
1000
VCM = 0.3V
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
1.5
2
2.5
3
3.5
4
4.5
5
No Output Load
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
1.5
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
VCM = 0.3 V
No Output Load
C001
VCM = (V+) – 0.3 V
Figure 2. Supply Voltage vs Supply Current per Channel,
High Vcm
1000
100
900
800
Output Current (mA)
10
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
1
0.1
-40°C
0.01
25°C
125°C
0.001
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
Common Mode Voltage (V)
1
10
100
1000
10000
Output Referred to V- (mV)
C001
No Output Load
SNK
VS = 3.3 V
Figure 3. Supply Current vs
Common Mode at 3.3 V
Figure 4. Output Sinking Current vs
Output Swing at 3.3 V
100
Short Circuit Current to V- (mA)
50
10
Output Current (mA)
2
C001
Figure 1. Supply Voltage vs Supply Current per Channel,
Low Vcm
Supply Current per Channel (nA/Ch)
800
5.5
Supply Voltage (V)
VCM = VS - 0.3V
900
1
0.1
-40°C
0.01
25°C
125°C
0.001
45
40
35
30
25
20
15
-40°C
10
25°C
5
125°C
0
1
10
100
1000
10000
Output Referred to V+ (mV)
1.5
VS = 3.3 V
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
SRC
5
SHR
Output set high (sourcing), shorted to V–
Figure 5. Output Sourcing Current vs
Output Swing at 3.3 V
Figure 6. Output Short Circuit Current to V- vs
Supply Voltage
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
5
TLV522
SNOSD27 – MAY 2016
www.ti.com
Typical Characteristics (continued)
50
0.10
45
0.08
40
0.06
Input Bias Current (pA)
Short Circuit Current to V+ (mA)
TA = 25 °C, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
35
30
25
20
0.04
0.02
0.00
-0.02
-0.04
15
-40°C
10
25°C
-0.06
5
125°C
-0.08
0
1.5
2
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
-0.10
-0.3
VS = 3.3 V
Figure 7. Output Short Circuit Current to V+ vs
Supply Voltage
1.5
2.1
2.7
3.3
C004
TA = 25°C
Figure 8. Input Bias Current vs
Common Mode Voltage at 3.3 V
2.0
50
1.5
40
Input Bias Current (pA)
Input Bias Current (pA)
0.9
Common Mode Voltage (V)
Ouput set low (sinking), shorted to V+
1.0
0.5
0.0
-0.5
-1.0
-1.5
30
20
10
0
-10
-20
-30
-40
-2.0
-0.3
0.3
0.9
1.5
2.1
2.7
VS = 3.3 V
-50
-0.3
3.3
Common Mode Voltage (V)
0.3
TA = 85°C
0.9
1.5
2.1
2.7
3.3
Common Mode Voltage (V)
C005
VS = 3.3 V
Figure 9. Input Bias Current vs
Common Mode Voltage at 3.3 V
C006
TA = 125°C
Figure 10. Input Bias Current vs
Common Mode Voltage at 3.3 V
10k
IN
VS = 5V
RL=100k
OUT
50 mV/div
Input Referred Voltage Noise (nV/SqRtHz)
0.3
SHR
1k
100
100m
1
10
100
1k
10k
VS = 5 V
RL = 100 kΩ
Time (100us/div)
100k
Frequency (Hz)
C001
C001
CL = 20 pF
VS = ±0.9 V
G = +1
Figure 11. Input Referred Voltage Noise
RL = 10 MΩ
VIN = ±100 mV
CL = 20 pF
Figure 12. Pulse Response, 200mVpp at 1.8 V
6
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
Typical Characteristics (continued)
TA = 25 °C, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
IN
OUT
OUT
50 mV/div
200 mV/div
IN
Time (200us/div)
Time (100us/div)
C002
C003
CL = 20 pF
VS = ±2.5 V
G = +1
Figure 13. Pulse Response, 1Vpp at 1.8V
RL = 10 MΩ
VIN = ±100 mV
Figure 14. Pulse Response, 200mVpp at 5V
40
IN
Gain (dB)
500 mV/div
30
20
10
45
0
0
100
1000
20
180
135
30
90
20
10
45
0
0
100
1000
10000
Frequency (Hz)
VS = 5 V
RL = 100 kΩ
C011
CL = 20 pF
-40°C
25°C
125°C
Gain
Phase
±10
RL = 100 kΩ
40
±45
100000
Gain (dB)
Gain (dB)
30
±45
100000
Figure 16. Gain and Phase vs
Temperature at 1.8 V
Phase (ƒ)
-40°C
25°C
125°C
10000
Frequency (Hz)
VS = 1.8 V
CL = 20 pF
Figure 15. Pulse Response, 2Vpp at 5V
Gain
135
90
C002
40
180
Phase
±10
Time (200us/div)
RL = 10 MΩ
VIN = ±1V
-40°C
25°C
125°C
Gain
OUT
VS = ±2.5 V
G = +1
CL = 20 pF
Phase (ƒ)
RL = 10 MΩ
VIN = ±500mV
135
90
Phase
10
45
0
0
±10
100
1000
10000
±45
100000
Frequency (Hz)
C008
CL = 20 pF
180
VS = 1.8 V
Figure 17. Gain and Phase vs
Temperature at 5 V
RL = 1 MΩ
Phase (ƒ)
VS = ±0.9 V
G = +1
C012
CL = 20 pF
Figure 18. Gain and Phase vs
Temperature at 1.8 V
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
7
TLV522
SNOSD27 – MAY 2016
www.ti.com
Typical Characteristics (continued)
TA = 25 °C, VOUT = VCM = VS/2, RLOAD = 1 MΩ connected to VS/2, and CL = 20 pF, unless otherwise noted.
135
30
90
20
Phase
10
45
0
0
±10
100
1000
±45
100000
10000
Frequency (Hz)
VS = 5 V
10
45
0
0
±10
100
1000
10000
Frequency (Hz)
VS = 1.8 V
Figure 19. Gain and Phase vs
Temperature at 5 V
RL = 10 MΩ
±45
100000
C013
CL = 20 pF
Figure 20. Gain and Phase vs
Temperature at 1.8 V
40
-40°C
25°C
125°C
Gain
30
20
180
135
90
Phase
10
45
0
0
±10
1000
10000
Frequency (Hz)
VS = 5 V
135
90
CL = 20 pF
100
180
Phase
C009
RL = 1 MΩ
Gain (dB)
-40°C
25°C
125°C
Gain
Phase (ƒ)
20
40
RL = 10 MΩ
Phase (ƒ)
Gain (dB)
30
180
Gain (dB)
-40°C
25°C
125°C
Gain
Phase (ƒ)
40
±45
100000
C010
CL = 20 pF
Figure 21. Gain and Phase vs
Temperature at 5 V
8
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
7 Detailed Description
7.1 Overview
The TLV522 dual op amplifier is unity-gain stable and can operate on a single supply, making it highly versatile
and easy to use.
The TLV522 is fully specified and tested from 1.7 V to 5.5 V. Parameters that vary significantly with operating
voltages or temperature are shown in the Typical Characteristics curves.
7.2 Functional Block Diagram
7.3 Feature Description
The amplifier's differential inputs consist of a non-inverting input (IN+) and an inverting input (IN–). The device
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ – IN–)
(1)
where AOL is the open-loop gain of the amplifier, typically around 100 dB.
7.4 Device Functional Modes
7.4.1 Rail-To-Rail Input
The input common-mode voltage range of the TLV522 extends to the supply rails. This is achieved with a
complementary input stage — an N-channel input differential pair in parallel with a P-channel differential pair.
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 800 mV to 200 mV above
the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to
approximately (V+) – 800 mV. There is a small transition region, typically (V+) – 1.2 V to (V+) – 0.8 V, in which
both pairs are on. This 400 mV transition region can vary 200 mV with process variation. Within the 400 mV
transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation
outside this region.
7.4.2 Supply Current Changes Over Common Mode
Because of the ultra-low supply current, changes in common mode voltages will cause a noticeable change in
the supply current as the input stages transition through the transition region, as shown in Figure 22 below.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
9
TLV522
SNOSD27 – MAY 2016
www.ti.com
Device Functional Modes (continued)
Supply Current per Channel (nA/Ch)
1000
900
800
700
600
500
400
125°C
85°C
25°C
0°C
-40°C
300
200
100
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Common Mode Voltage (V)
4.5
5.0
C001
Figure 22. Supply Current Change Over Common Mode at 5 V
For the lowest supply current operation, keep the input common mode range between V- and 1 V below V+.
7.4.3 Design Optimization With Rail-To-Rail Input
In most applications, operation is within the range of only one differential pair. However, some applications can
subject the amplifier to a common-mode signal in the transition region. Under this condition, the inherent
mismatch between the two differential pairs may lead to degradation of the CMRR and THD. The unity-gain
buffer configuration is the most problematic as it will traverse through the transition region if a sufficiently wide
input swing is required.
7.4.4 Design Optimization for Nanopower Operation
When designing for ultra-low power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors will react with stray capacitance in the circuit and the input capacitance
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. A
feedback capacitor may be required to assure stability and limit overshoot or gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors since large electolytics may have static leakage currents in the tens to hundreds
of nanoamps.
7.4.5 Common-Mode Rejection
The CMRR for the TLV522 is specified in two ways so the best match for a given application may be used. First,
the CMRR of the device in the common-mode range below the transition region (VCM < (V+) – 1.1 V) is given.
This specification is the best indicator of the capability of the device when the application requires use of one of
the differential input pairs. Second, the CMRR at VS = 3.3 V over the entire common-mode range is specified.
7.4.6 Output Stage
The TLV522 output voltage swings 3 mV from rails at 3.3 V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The TLV522 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load.
7.4.7 Driving Capacitive Load
The TLV522 is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be under damped which causes peaking in the transfer and, when there is too much peaking, the
op amp might start oscillating.
10
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
Device Functional Modes (continued)
In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in
Figure 23. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger
the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop
will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive.
-
RISO
VOUT
VIN
+
CL
Figure 23. Resistive Isolation of Capacitive Load
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
11
TLV522
SNOSD27 – MAY 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV522 is a ultra-low power operational amplifier that provides 8 kHz bandwidth with only 490 nA quiescent
current, and near precision offset and drift specifications at a low cost. These rail-to-rail input and output
amplifiers are specifically designed for battery-powered applications. The input common-mode voltage range
extends to the power-supply rails and the output swings to within millivolts of the rails, maintaining a wide
dynamic range.
8.2 Typical Application: 60 Hz Twin "T" Notch Filter
VBATT = 3V o 2V @ end of life
CR2032 Coin Cell
225 mAh = 5 circuits @ 9.5 yrs.
10 M:
10 M:
VBATT
-
Remote Sensor
10 M:
+
VIN
Signal
+
60 Hz
To ADC
VOUT
10 M:
270 pF
270 pF
10 M:
10 M:
Signal × 2
(No 60 Hz)
60 Hz Twin T Notch Filter
270 pF
AV = 2 V/V
270 pF
Figure 24. 60 Hz Notch Filter
8.2.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60 Hz
interference from AC power lines. The circuit of Figure 24 notches out the 60 Hz and provides a gain AV = 2 for
the sensor signal represented by a 1 kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd
harmonics of 60 Hz. Thanks to the nA power consumption of the TLV522, even 5 such circuits can run for 9.5
years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3 V and an end of life voltage
of 2 V. With an operating voltage from 1.7 V to 5.5 V the TLV522 can function over this voltage range.
8.2.2 Detailed Design Procedure
The notch frequency is set by:
F0 = 1 / 2πRC.
(2)
To achieve a 60 Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50 Hz noise, which is common in
European systems, use R = 11.8 MΩ and C = 270 pF.
The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency
path through the series input resistors and another separate high frequency path through the series input
capacitors. However, at frequencies around the notch frequency, the two paths have opposing phase angles and
the two signals will tend to cancel at the amplifier’s input.
12
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
Typical Application: 60 Hz Twin "T" Notch Filter (continued)
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter
needs to be as balanced as possible. To obtain circuit balance, while overcoming limitations of available
standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements
for the filter components that connect to ground.
To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water,
and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may
increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 24 can be done over a bandwidth of 2 kHz,
which takes the conservative approach of overestimating the bandwidth (TLV522 typical GBW/AV is lower). The
total noise at the output is approximately 800 µVpp, which is excellent considering the total consumption of the
circuit is only 900 nA. The dominant noise terms are op amp voltage noise , current noise through the feedback
network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total circuit's noise
is below 1/2 LSB of a 10-bit system with a 2 V reference, which is 1 mV.
8.2.3 Application Curve
Figure 25. 60 Hz Notch Filter Waveform
8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, MUX and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 KΩ per volt).
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
13
TLV522
SNOSD27 – MAY 2016
www.ti.com
9 Power Supply Recommendations
The TLV522 is specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 10 nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
If your application expects signals above (> 1 kHz) we recommend you use extra supply filtering.
Extra filtering on the power supply input is recommended when presence of signals with frequency above one
kHz (> 1 kHz) on the line is expected. Example of such signal sources are high-frequency switching supplies.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and
ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the V– pin. For best
performance the DAP should be connected to the exact same potential as the V– pin. Do not use the DAP as the
primary V– supply. Floating the DAP pad is not recommended. The DAP and V– pin should be joined directly as
shown in the Layout Example.
10.2 Layout Example
Place components close to
device and to each other to
reduce parasitic error
VOUTA
Place low-ESR ceramic
bypass capacitor close to
device
RF
Run the input traces as
far away from the supply
lines as possible
OUTA
V+
GND
-INA
OUTB
VIN
+INA
-INB
V-
+INB
GND
RG
Place low-ESR ceramic
bypass capacitor close to
device
GND
VS-
Figure 26. Layout Example (Top View)
14
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
TLV522
www.ti.com
SNOSD27 – MAY 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
TI FilterPro Filter Design software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-1798 Designing with Electro-Chemical Sensors, SNOA514
• AN-1803 Design Considerations for a Transimpedance Amplifier, SNOA515
• AN-1852 Designing With pH Electrodes, SNOA529
• Compensate Transimpedance Amplifiers Intuitively, SBOA055
• Transimpedance Considerations for High-Speed Operational Amplifiers, SBOA112
• Noise Analysis of FET Transimpedance Amplifiers, SBOA060
• Circuit Board Layout Techniques, SLOA089
• Handbook of Operational Amplifier Applications, SBOA092
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLV522
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV522DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
SL
V522
TLV522DGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
SL
V522
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
