TLV5619
www.ti.com
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Single Supply 2.7-V to 5.5-V Operation
± 0.4 LSB Differential Nonlinearity (DNL),
±1.5 LSB Integral Nonlinearity (INL)
12-Bit Parallel Interface
Compatible With TMS320 DSP
Internal Power On Reset
Settling Time 1 µs Typ
Low Power Consumption:
– 8 mW for 5-V Supply
– 4.3 mW for 3-V Supply
Reference Input Buffers
Voltage Output
Monotonic Over Temperature
Asynchronous Update
APPLICATIONS
•
•
•
•
•
•
•
•
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial Controls
Machine and Motion Control Devices
Cordless and Wireless Telephones
Speech Synthesis
Communication Modulators
Arbitrary Waveform Generation
DESCRIPTION
The TLV5619 is a 12-bit voltage output DAC with a
microprocessor and TMS320 compatible parallel
interface. The 12 data bits are double buffered so that
the output can be updated asynchronously using the
LDAC pin. During normal operation, the device dissipates 8 mW at a 5-V supply and 4.3 mW at a 3-V
supply. The power consumption can be lowered to 50
nW by setting the DAC to power-down mode.
The output voltage is buffered by a ×2 gain rail-to-rail
amplifier, which features a Class A output stage to
improve stability and reduce settling time.
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
20
19
18
17
16
15
14
13
12
11
D1
D0
CS
WE
LDAC
PD
GND
OUT
REFIN
VDD
AVAILABLE OPTIONS
PACKAGE
TA
SMALL
OUTLINE (DW)
TSSOP (PW)
0°C to 70°C
TLV5619CDW
TLV5619CPW
40°C to 85°C
TLV5619IDW
TLV5619IPW
40°C to 125°C
TLV5619QDW
—
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated
TLV5619
www.ti.com
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
REFIN
D0
12
+
_
19
20
D1
1
D2
2
D3
3
D4
4
D5
5
D6
6
D7
7
D8
8
D9
9
D10
10
D11
Resistor
String DAC
12
17
WE
12
x2
Power-On
Reset
Select
and
Control
Logic
18
CS
12-Bit
DAC
Latch
12-Bit
Input
Register
15
PD
16
LDAC
Terminal Functions
TERMINAL
NAME
CS
D0 (LSB)-D11 (MSB)
NO.
I/O
DESCRIPTION
18
I
Chip select
19, 20, 1-10
I
Parallel data input
GND
14
LDAC
16
I
Load DAC
OUT
13
O
Analog output
PD
15
I
When low, disables all buffer amplifier voltages to reduce supply current
REFIN
12
I
Voltage reference input
VDD
11
WE
17
2
Ground
Positive power supply
I
Write enable
13
OUT
TLV5619
www.ti.com
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage (VDD to GND)
7V
Analog input voltage range
- 0.3 V to VDD + 0.3 V
Reference input voltage
VDD + 0.3 V
Digital input voltage range to GND
Operating free-air temperature range, TA
- 0.3 V to VDD + 0.3 V
TLV5619C
0°C to 70°C
TLV5619I
-40°C to 85°C
TLV5619Q
-40°C to 125°C
Storage temperature range, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
Supply voltage, VDD (5-V Supply)
4.5
5
5.5
V
Supply voltage, VDD (3-V Supply)
2.7
3
3.3
V
High-level digital input voltage, VIH
DVDD = 2.7 V
2
DVDD = 5.5 V
2.4
V
DVDD = 2.7 V
Low-level digital input voltage, VIL
DVDD = 5.5 V
0.6
TLV5619C and TLV5619I
1
TLV5619Q
V
0.8
Reference voltage, Vref to REFIN terminal (5-V Supply)
0
2.048
VDD-1.5
Reference voltage, Vref to REFIN terminal (3-V Supply)
0
1.024
VDD-1.5
Load resistance, RL
2
10
Load capacitance, CL
Operating free-air temperature, TA
UNIT
V
V
kΩ
100
TLV5619C
0
70
TLV5619I
40
85
TLV5619Q
40
125
pF
°C
3
TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, sdupply voltages, and reference voltages (unless otherwise noted)
STATIC DAC SPECIFICATIONS
PARAMETER
EZS
EG
TEST CONDITIONS
MIN
Resolution
Vref(REFIN) = 2.048 V at 5 V, 1.024 V at 3 V
Integral nonlinearity (INL)
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
Differential nonlinearity (DNL)
TYP
MAX
12
UNIT
bits
See
(1)
±1.5
±4
LSB
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See
(2)
±0.4
±1
LSB
Zero-scale error (offset error at zero scale)
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See
(3)
±3
±20
mV
Zero-scale-error temperature coefficient
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See
(4)
3
Gain error
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See
(5)
±0.25
Gain error temperature coefficient
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See
(6)
1
PSRR Power-supply rejection ratio
Zero scale
Gain
See
(7)
and
ppm/°C
±0.5
ppm/°C
65
(8)
% of FS
voltage
dB
65
(1)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from
the line between zero and full scale excluding the effects of zero code and full-scale errors.
(2) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)
as a change in the digital input code.
(3) Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
(4) Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref× 106/(Tmax - Tmin).
(5) Gain error is the deviation from the ideal output (2 × Vref - 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
(6) Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref× 106/(Tmax - Tmin).
(7) Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this
signal imposed on the zero-code output voltage.
(8) Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
OUTPUT SPECIFICATIONS
PARAMETER
VO
Voltage output range
TEST CONDITIONS
RL = 10 kΩ
MIN
TYP
0
VDD-0.4
Output load regulation accuracy
VO(OUT)= 4.096 V, 2.048 V
RL = 2 kΩ
0.1
IOSC(source)
Output short circuit source current
VO(OUT) = 0 V, Full scale
code
5-V Supply
100
3-V Supply
25
IO(source)
Output source current
RL = 100Ω
5-V Supply
10
3-V Supply
10
4
MAX
0.29
UNIT
V
% of FS
voltage
mA
mA
TLV5619
www.ti.com
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
REFERENCE INPUT (REFIN)
PARAMETER
Vref
Reference input voltage
Ri
Reference input resistance
Ci
Reference input capacitance
TEST CONDITIONS
See
MIN
(1)
TYP
MAX
0
UNIT
VDD-1.5
V
10
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc at -3 dB
(2))
MΩ
5
pF
60
dB
1.4
MHz
DIGITAL INPUTS (D0-D11, CS, WE, LDAC, PD)
IIH
High-level digital input current
VI = VDD
1
µA
IIL
Low-level digital input current
VI = 0 V
1
µA
Ci
Input capacitance
8
pF
(1)
(2)
Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
Reference feedthrough is measured at the DAC output with an input code = 0x000 and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at
1 kHz.
POWER SUPPLY
PARAMETER
IDD
TEST CONDITIONS
Power supply current
No load, All inputs 0 V or VDD
MIN
TYP MAX
5-V Supply
1.6
3
3-V Supply
1.44
2.7
0.01
10
Power down supply current
UNIT
mA
µA
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
SR
Slew rate
TEST CONDITIONS
CL = 100 pF,
RL = 10 kΩ
Vref(REFIN) = 2.048 V,
Vref(REFIN) =1.024 V,
VO from 10% to 90%
VO from 90% to 10%
Output settling time (full
scale)
To ±0.5 LSB, RL = 10 kΩ, CL = 100 pF, See
Glitch energy
DIN = all 0s to all 1s
S/N
Signal to noise
fs = 480 kSPS, BW = 20 kHz, CL = 100 pF,
fOUT = 1 kHz, RL = 10 kΩ , TA = 25°C, See (2)
S/(N+D)
f = 480 kSPS, BW = 20 kHz, CL = 100 pF,
Signal to noise + distortion s
fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See (2)
ts
(1)
(2)
MIN
TYP
5-V
Supply
8
12
V/µs
3-V
Supply
6
9
V/µs
(1)
Total harmonic distortion
fs = 480 kSPS, BW = 20 kHz, CL = 100 pF,
fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See (2)
Spurious free dynamic
range
fs = 480 kSPS, BW = 20 kHz, CL = 100 pF,
fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See (2)
1
MAX
3
5
5-V
Supply
65
78
5-V
Supply
58
67
3-V
Supply
58
69
68
60
UNIT
µs
nV-s
dB
60
72
Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 32
to 4063 or 4063 to 32. Limits are ensured by design and characterization, but are not production tested.
1 kHz sinewave generated by DAC, reference voltage = 1.024 V at 3 V and 2.048 V at 5 V.
TIMING REQUIREMENTS
DIGITAL INPUTS
MIN
NOM
MAX
UNIT
tsu(CS-WE)
Setup time, CS low before positive WE edge
13
ns
tsu(D)
Setup time, data ready before positive WE edge
9
ns
th(D)
Hold time, data held after positive WE edge
0
ns
tsu(WE-LD)
Setup time, positive WE edge before LDAC low
0
ns
twh(WE)
Pulse width, WE high
25
ns
tw(LD)
Pulse width, LDAC low
25
ns
5
TLV5619
www.ti.com
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
D(0–11)
X
Data
tsu(D)
X
th(D)
CS
tsu(CE-WE)
twh(WE)
WE
tsu(WE-LD)
LDAC
Figure 1. Timing Diagram
6
tw(LD)
TLV5619
www.ti.com
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
MAXIMUM OUTPUT VOLTAGE
vs
LOAD
MAXIMUM OUTPUT VOLTAGE
vs
LOAD
5
3
VDD = 5 V, Vref = 2 V,
Input Code = 4095
VDD = 3 V, Vref = 1.2 V,
Input Code = 4095
2.5
VO – Output Voltage – V
VO – Output Voltage – V
4
3
2
2
1.5
1
1
100 k
10 k
1k
100
RL – Output Load – Ω
0.5
100 k
10
10 k
1k
100
RL – Output Load – Ω
Figure 2.
Figure 3.
TOTAL HARMONIC DISTORTION
vs
LOAD
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
0
VDD = 5 V, Vref = 2 V,
Tone at 1 kHz
VDD = 5 V
THD – Total Harmonic Distortion – dB
THD – Total Harmonic Distortion – dB
10
–20
–40
–60
–80
–10
–20
–30
–40
–50
–60
–70
–100
100 k
–80
10 k
1k
100
RL – Output Load – Ω
Figure 4.
10
0
5
10
15
20
25
30
35
f – Frequency – kHz
Figure 5.
7
TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE + DISTORTION
vs
FREQUENCY
SNRD – Signal-To-Noise Ratio + Distortion – dB
80
VDD = 5 V
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
f – Frequency – kHz
DNL - Differential Nonlinearity - LSB
Figure 6.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
500
1000
1500
2000
2500
3000
3500
4095
Code
INL - Integral Nonlinearity - LSB
Figure 7. Differential Nonlinearity
4
3
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-3
-4
0
500
1000
1500
2000
2500
Code
Figure 8. Integral Nonlinearity
8
3000
3500
4095
TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (continued)
POWER DOWN SUPPLY CURRENT
vs
TIME
1
I DD – Supply Current – mA
0.1
0.01
0.001
0.0001
0.00001
0.000001
0
100
200
300
400
500
600
t – Time – ms
Figure 9.
9
TLV5619
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
www.ti.com
APPLICATION INFORMATION
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
Differential Nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
Zero-Scale Error (EZS)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
Gain Error (EG)
Gain error is the error in slope of the DAC transfer function.
Signal-to-Noise Ratio + Distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
10
TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
APPLICATION INFORMATION (continued)
LINEARITY, OFFSET, AND GAIN ERROR SUING SINGLE END SUPPLIES
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 10.
Output
Voltage
0V
Negative
Offset
DAC Code
Figure 10. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full scale code and the lowest code that produces a positive output voltage.
GENERAL FUNCTION
The TLV5619 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, a power down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full
scale determined by reference) is given by:
2 REF CODE [V]
0x1000
Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on
reset initially puts the internal latches to a defined state (all bits zero).
11
TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
APPLICATION INFORMATION (continued)
PARALLEL INTERFACE
The device latches data on the positive edge of WE. It must be enabled with CS low. LDAC low updates the
DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate
update is not necessary. However, to control the DAC using the load feature, LDAC can be driven low after the
positive WE edge.
TMS320C2XX, 5X
A(0–15)
TLV5619
IS
Address
Decoder
CS
LDAC
WE
WE
D(0–11)
D(0–15)
Figure 11. Proposed Interface Between TLV5619 and TMS320C2XX, 5X DSPs
TMS320C3X
A(0–15)
TLV5619
Address
Decoder
TCLK0
CS
LDAC
R/W
WE
IOSTROBE
D(0–11)
D(0–15)
Figure 12. Proposed Interface Between TLV5619 and TMS320C3X DSPs
12
TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
APPLICATION INFORMATION (continued)
TLV5619 INTERFACED TO TMS320C203 DSP
Hardware Interface
Figure 13 shows an example of the connection between the TLV5619 and the TMS320C203 DSP. The only
other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using
this configuration, the DAC address is 0x0084 within the I/O memory space of the TMS320C203.
LDAC is held low so that the output voltage is updated with the rising WE edge. The power down mode is
deactivated permanently by pulling PD to VDD.
TMS320C203
74AC138
A2
A
A3
A4
B
C
Y1
5V
A6
IS
G1
G2A
G2B
TLV5619
D(0–11)
12
D(0–11)
VDD
PD
CS
OUT
WE
WE
REF191
Output
RLOAD
LDAC
REFIN
Figure 13. TLV5619 to TMS320C203 DSP Interface Connection
Software
No setup procedure is needed to access the TLV5619. The output voltage can be set using one command:
out data_addr,
DAC_addr
Where data_addr points to the address location (in this example 0x0060) holding the new output voltage data
and DAC_addr is the I/O space address of the TLV5619 (in this example 0x0084).
The following code shows, how to use the timer of the TMS320C203 as a time base to generate a voltage ramp
with the TLV5619. A timer interrupt is generated every 205 µs. The corresponding interrupt service routine
increments the output code (stored at 0x0060) for the DAC and writes the new code to the TLV5619. Only the 12
LSBs of the data in 0x0060 are used by the DAC, so that the resulting period of the saw waveform is:
• t = 4096 × 205 E-6 s = 0.84 s
13
TLV5619
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
APPLICATION INFORMATION (continued)
SOFTWARE LISTING
; File: ramp.asm
; Description: This program generates a ramp.
;------------- I/O and memory mapped regs ----------.include "regs.asm"
TLV5619
.equ
0084h
;------------- vectors ------------------------------.ps
0h
b
start
b
INT1
b
INT23
b
TIM_ISR
*********************************************************************
* Main Program
*********************************************************************
.ps
1000h
.entry
start:
ldp
; disable interrupts
setc
splk
splk
#0
; set data page to 0
INTM ; disable maskable interrupts
#0ffffh, IFR
#0004h,
IMR
; set up the timer
splk
splk
out
out
splk
out
#0000h,
#0042h,
61h. PRD
60h, TIM
#0c2fh,
62h, TCR
; enable interrupts
clrc
INTM ; enable maskable interrupts
60h
61h
62h
; loop forever!
next
idle
; wait for interrupt
b
next
; all else fails stop here
done
b
done ; hang there
*********************************************************************
* Interrupt Service Routines
*********************************************************************
INT1:
ret
; do nothing and return
INT23:
ret
; do nothing and return
TIM_ISR:
; useful code
add
#1h ; increment accumulator
sacl
60h
14
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TLV5619
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SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
APPLICATION INFORMATION (continued)
out
clrc
ret
.end
60h, TLV5619 ; write to DAC
intm; re-enable interrupts
; return from interrupt
15
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV5619CDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV5619C
Samples
TLV5619CDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV5619C
Samples
TLV5619CPW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV5619
Samples
TLV5619CPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV5619
Samples
TLV5619IDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV5619I
Samples
TLV5619IDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV5619I
Samples
TLV5619IPW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY5619
Samples
TLV5619IPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY5619
Samples
TLV5619QDWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
TLV5619Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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