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Design
TLV70018-Q1, TLV70012-Q1
SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
TLV700xx-Q1 300-mA, Low-IQ, Low-Dropout Regulator
1 Features
3 Description
•
•
The TLV70018-Q1 and TLV70012-Q1 low-dropout
(LDO) linear regulators are low quiescent current
devices with excellent line and load transient
performance. A precision band-gap and error
amplifier provides overall 2% accuracy. Low output
noise, high power-supply rejection ratio (PSRR), and
low-dropout voltage make this series of devices ideal
for powering power-sensitive loads. All device
versions have thermal shutdown and current limit for
detecting fault conditions.
1
•
•
•
•
•
•
(1)
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
2% Accuracy
Low IQ: 35 μA
Fixed-Output Voltages: 1.2 V and 1.8 V
High PSRR: 68 dB at 1 kHz
Stable With Effective Capacitance of 0.1 μF(1)
Thermal Shutdown and Overcurrent Protection
Furthermore, these devices are stable with an
effective output capacitance of only 0.1 μF. This
feature enables the use of cost-effective capacitors
that have higher bias voltages and temperature
derating. The devices regulate to specified accuracy
with no output load.
See the Input and Output Capacitor Requirements.
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Automotive Head Units
Camera Sensors and Modules
Heads-Up Displays (HUD)
Telematics Control Units
TLV70018-Q1
TLV70012-Q1
PACKAGE
SOT (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
SPACE
SPACE
SPACE
SPACE
SPACE
Typical Application
VIN
IN
OUT
CIN
COUT
VOUT
1 mF
Ceramic
TLV700xx
On
Off
EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV70018-Q1, TLV70012-Q1
SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 15
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
15
15
15
15
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2016) to Revision C
Page
•
Changed Fixed-Output Voltage Features bullet from Fixed-Output Voltage Combinations Possible from 1.2 V to 4.8
V to Fixed-Output Voltages: 1.2 V and 1.8 V ......................................................................................................................... 1
•
Changed Applications section ............................................................................................................................................... 1
•
Changed first paragraph of Description section: changed TLV700xx-Q1 series to TLV70018-Q1 and TLV70012-Q1,
deleted second sentence, changed a wide selection of battery-operated handheld equipment to powering powersensitive loads, and changed safety to detecting fault conditions.......................................................................................... 1
•
Deleted Fixed-Voltage Version from Typical Application title ................................................................................................ 1
•
Changed Input voltage parameter: changed symbol from VI to VIN, moved EN and OUT rows to standalone
parameters ............................................................................................................................................................................. 5
•
Changed maximum specification of Output voltage parameter from 5.5 V to 1.8 V ............................................................. 5
•
Added IOUT symbol to Current output parameter ................................................................................................................... 5
•
Deleted TLV70018-Q1 column from Thermal Information table ............................................................................................ 5
•
Added TLV70018-Q1 to TLV70012-Q1 column in Thermal Information table; all thermal values for TLV70018-Q1
changed to the TLV70012-Q1 thermal values........................................................................................................................ 5
•
Changed VOUT(TYP) to VOUT(NOM) in conditions statement of Electrical Characteristics table .................................................. 6
•
Changed symbols for Line regulation, Load regulation, and Output noise voltage parameters from ΔVO/ΔVIN to
ΔVOUT/ΔVIN, ΔVO/ΔIOUT to ΔVOUT/ΔIOUT, and VN to Vn (respectively) in Electrical Characteristics table.................................. 6
•
Changed VOUT(TYP) to VOUT(NOM) in Typical Characteristics conditions statement .................................................................. 7
•
Deleted Dropout Voltage vs Input Voltage and Dropout Voltage vs Output Current curves ................................................. 7
•
Changed TLV700xx-Q1 to TLV70018-Q1 and TLV70012-Q1 in Overview section ............................................................. 11
•
Added TLV70012-Q1 to sub-sections of Feature Description and Device Functional Modes sections .............................. 11
•
Changed 160°C to 165°C, 140°C to 145°C, and 35°C to 40°C in Thermal Shutdown section .......................................... 12
•
Changed Application Information section: changed first two sentences, deleted second paragraph ................................. 13
•
Changed Example Value column values for 2nd and 3rd rows in Design Parameters table............................................... 13
•
Added TLV70012-Q1 to Input and Output Capacitor Requirements section ....................................................................... 14
•
Deleted first and last paragraphs from Thermal Considerations section ............................................................................ 15
2
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Copyright © 2011–2017, Texas Instruments Incorporated
Product Folder Links: TLV70018-Q1 TLV70012-Q1
TLV70018-Q1, TLV70012-Q1
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SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
Revision History (continued)
•
Deleted second sentence from second paragraph of Power Dissipation section ............................................................... 15
•
Added TLV70012-Q1 to Power Dissipation section ............................................................................................................ 15
Changes from Revision A (March 2012) to Revision B
Page
•
Added ESD Ratings table, Recommended Operating Conditions table, Thermal Information table, Detailed
Description section, Application and Implementation section, Application and Implementation section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
•
Deleted the Dissipation Ratings table..................................................................................................................................... 5
Copyright © 2011–2017, Texas Instruments Incorporated
Product Folder Links: TLV70018-Q1 TLV70012-Q1
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TLV70018-Q1, TLV70012-Q1
SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
www.ti.com
5 Pin Configuration and Functions
DDC Package
5-Pin SOT
Top View
IN
1
GND
2
EN
3
5
OUT
4
NC
Pin Functions
PIN
NO.
DESCRIPTION
NAME
Input pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good
transient performance. (1)
1
IN
2
GND
3
EN
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown
mode and reduces operating current to 1 μA, nominal.
4
NC
No connection. This pin can be tied to ground to improve thermal dissipation.
5
OUT
(1)
4
Ground pin
Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability. (1)
See Input and Output Capacitor Requirements section for more details.
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SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted. (1)
Voltage
(2)
Current (source)
MIN
MAX
UNIT
IN
–0.3
6.0
V
EN
–0.3
6.0
V
OUT
–0.3
6.0
V
OUT
Internally Limited
Output short-circuit duration
Indefinite
Operating virtual junction, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
2000
Charged-device model (CDM), per AEC Q100-011
V
750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range, unless otherwise noted.
MIN
MAX
VIN
Input voltage
IN
2
5.5
UNIT
V
VEN
Enable voltage
EN
0
5.5
V
VOUT
Output voltage
OUT
0
1.8
V
IOUT
Current output
0
300
mA
TJ
Operating junction temperature
–40
150
°C
6.4 Thermal Information
THERMAL METRIC (1)
TLV70018-Q1,
TLV70012-Q1
DDC (SOT)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
262.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.2
°C/W
RθJB
Junction-to-board thermal resistance
81.6
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
80.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
NA
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Product Folder Links: TLV70018-Q1 TLV70012-Q1
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TLV70018-Q1, TLV70012-Q1
SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
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6.5 Electrical Characteristics
At VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1.0 μF, and TA = –40°C to 125°C,
unless otherwise noted. Typical values are at TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
VOUT
DC output accuracy
–40°C ≤ TA ≤ 125°C
ΔVOUT/ΔVIN
Line regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA
1
5
0 mA ≤ IOUT ≤ 300 mA, TLV70018-Q1
1
15
0 mA ≤ IOUT ≤ 300 mA, TLV70012-Q1
1
20
500
860
mA
35
55
μA
Load regulation
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
320
IOUT = 0 mA
IGND
Ground pin current
ISHDN
Ground pin current (shutdown)
PSRR
–2%
5.5
UNIT
Input voltage range
ΔVOUT/ΔIOUT
2
MAX
VIN
0.5%
IOUT = 300 mA, VIN = VOUT + 0.5 V
370
VEN ≤ 0.4 V, VIN = 2.0 V
400
V
2%
mV
mV
μA
nA
VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V, TA = –40°C to 85°C
1
2
μA
VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V, TA = 85°C to 125°C
1
2.5
μA
Power-supply rejection ratio
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz
68
dB
Vn
Output noise voltage
BW = 100 Hz to 100 kHz,
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
48
μVRMS
tSTR
Startup time (1)
COUT = 1.0 μF, IOUT = 300 mA
100
μs
VEN(HI)
Enable pin high (enabled)
0.9
VIN
VEN(LO)
Enable pin low (disabled)
0
0.4
IEN
Enable pin current
VIN = VEN = 5.5 V
UVLO
Undervoltage lockout
VIN rising
1.9
V
Shutdown, temperature increasing
165
°C
Reset, temperature decreasing
145
°C
TSD
Thermal shutdown temperature
TA
Operating temperature
(1)
6
0.04
–40
V
V
μA
125
°C
Startup time = time from EN assertion to 0.98 × VOUT(NOM).
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SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1.90
1.90
VOUT = 1.8 V
IOUT = 10 mA
1.88
1.86
1.84
1.84
1.82
1.82
VOUT (V)
VOUT (V)
1.86
1.80
1.78
1.76
1.72
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
VOUT = 1.8 V
IOUT = 300 mA
1.88
+125°C
+85°C
+25°C
-40°C
1.74
1.72
1.70
1.70
2.1
2.6
3.1
3.6
4.1
VIN (V)
4.6
5.1
2.3
5.6
Figure 1. Line Regulation 10 mA
3.1
3.9
VIN (V)
4.3
4.7
5.1
5.5
1.90
VOUT = 1.8 V
1.88
1.84
1.82
1.82
VOUT (V)
1.86
1.84
1.80
1.78
1.72
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
VOUT = 1.8 V
1.88
1.86
1.76
10mA
150mA
200mA
1.74
1.72
1.70
1.70
0
50
100
150
200
300
250
-40 -25 -10
IOUT (mA)
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 4. Output Voltage vs Temperature
Figure 3. Load Regulation
450
50
VOUT = 1.8 V
45
VOUT = 1.8 V
400
40
350
35
300
30
IGND (mA)
IGND (mA)
3.5
Figure 2. Line Regulation 300 mA
1.90
VOUT (V)
2.7
25
20
15
5
200
150
+125°C
+85°C
+25°C
-40°C
10
250
+125°C
+85°C
+25°C
-40°C
100
50
0
0
2.1
2.6
3.1
3.6
4.1
VIN (V)
4.6
5.1
5.6
Figure 5. Ground Pin Current vs Input Voltage
0
50
100
150
IOUT (mA)
200
250
300
Figure 6. Ground Pin Current vs Load
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SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
50
2.5
VOUT = 1.8 V
45
VOUT = 1.8 V
2
40
ISHDN (mA)
IGND (mA)
35
30
25
20
1.5
1
15
+125°C
+85°C
+25°C
-40°C
0.5
10
5
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
2.1
110 125
Figure 7. Ground Pin Current vs Temperature
2.6
3.1
3.6
4.1
VIN (V)
VOUT = 1.8 V
IOUT = 10 mA
90
80
500
IOUT = 150 mA
70
PSRR (dB)
ILIM (mA)
5.6
Figure 8. Shutdown Current vs Input Voltage
600
400
300
200
0
2.3
2.7
3.1
3.5
3.9
VIN (V)
4.3
4.7
5.1
10
Output Spectral Noise Density (mV/ÖHz)
VOUT = 1.8 V
50
100 kHz
30
20
10
0
2.2
2.3
2.4
100
2.5
10 k
100 k
2.6
2.7
2.8
10
1M
10 M
VOUT = 1.8 V
IOUT = 10 mA
CIN = COUT = 1 mF
1
0.1
0.01
0.001
10
100
Figure 11. Power-Supply Ripple Rejection vs Input Voltage
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Input Voltage (V)
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1k
Figure 10. Power-Supply Ripple Rejection vs Frequency
10 kHz
2.1
VIN - VOUT = 0.5 V
0
Frequency (Hz)
1 kHz
40
40
10
Figure 9. Current Limit vs Input Voltage
60
50
20
5.5
80
70
60
30
+125°C
+85°C
+25°C
-40°C
100
PSRR (dB)
5.1
100
700
8
4.6
Figure 12. Output Spectral Noise Density vs Frequency
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SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
tR = tF = 1 ms
IOUT
0 mA
VOUT
20 mA/div
200 mA
5 mV/div
50 mV/div
100 mA/div
tR = tF = 1 ms
10 mA
0 mA
IOUT
VOUT
VOUT = 1.8 V
VOUT = 1.8 V
10 ms/div
10 ms/div
Figure 13. Load Transient Response
Figure 14. Load Transient Response
tR = tF = 1 ms
200 mA/div
300 mA
IOUT
50 mA
0 mA
100 mV/div
20 mV/div
50 mA/div
tR = tF = 1 ms
VOUT
IOUT
0 mA
VOUT
VOUT = 1.8 V
VOUT = 1.8 V
10 ms/div
10 ms/div
Figure 16. Load Transient Response
Figure 15. Load Transient Response
1 V/div
2.9 V
VIN
Slew Rate = 1 V/ms
2.9 V
2.3 V
VIN
VOUT
VOUT = 1.8 V
IOUT = 300 mA
5 mV/div
2.3 V
5 mV/div
1 V/div
Slew Rate = 1 V/ms
VOUT
VOUT = 1.8 V
IOUT = 1 mA
1 ms/div
1 ms/div
Figure 17. Line Transient Response
Figure 18. Line Transient Response
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Typical Characteristics (continued)
Slew Rate = 1 V/ms
VOUT = 1.8 V
IOUT = 300 mA
5.5 V
VIN
10 mV/div
2.1 V
VOUT = 1.8 V
IOUT = 1 mA
VIN
1 V/div
1 V/div
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
VOUT
VOUT
1 ms/div
200 ms/div
Figure 19. Line Transient Response
10
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Figure 20. VIN Ramp Up, Ramp Down Response
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SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
7 Detailed Description
7.1 Overview
The TLV70018-Q1 and TLV70012-Q1 low-dropout (LDO) linear regulators are low-quiescent-current devices with
excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A
precision bandgap and error amplifier provides overall 2% accuracy together with low output noise, very high
power-supply rejection ratio (PSRR), and low dropout voltage.
7.2 Functional Block Diagrams
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
LOGIC
TLV700xx Series
GND
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV70018-Q1 and TLV70012-Q1 internal current limit helps to protect the regulator during fault conditions.
During current limit, the output sources a fixed amount of current that is largely independent of the output
voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass
transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the
device cools, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device
cycles between current limit and thermal shutdown. See the Thermal Considerations section for more details.
The PMOS pass element in the TLV70018-Q1 and TLV70012-Q1 has a built-in body diode that conducts current
when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of the rated output current is recommended.
7.3.2 Dropout Voltage
The TLV70018-Q1 and TLV70012-Q1 use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-tooutput resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current
because the PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
Figure 11 illustrates this effect.
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Feature Description (continued)
7.3.3 Undervoltage Lockout (UVLO)
The TLV70018-Q1 and TLV70012-Q1 use an undervoltage lockout circuit to keep the output shut off until internal
circuitry is operating properly.
7.3.4 Thermal Shutdown
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 40°C above the maximum expected ambient condition of the particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TLV70018-Q1 and TLV70012-Q1 has been designed to protect against
overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV70018-Q1 or
TLV70012-Q1 into thermal shutdown degrades device reliability.
7.4 Device Functional Modes
7.4.1 Shutdown
The enable pin (EN) is active high. The device is enabled when voltage at EN pin goes above 0.9 V. This
relatively lower value of voltage required to turn the LDO on can be exploited to power the LDO with a GPIO of
recent processors whose GPIO Logic 1 voltage level is lower than traditional microcontrollers. The device is
turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be
connected to the IN pin.
7.4.2 Operation with VIN Less than 2 V
The TLV70018-Q1 and TLV70012-Q1 devices operate with input voltages above 2 V. The typical UVLO voltage
is 1.9 V and the device operates at an input voltage above 2 V. When input voltage falls below UVLO voltage,
the device will shutdown.
7.4.3 Operation with VIN Greater than 2 V
When VIN is greater than 2 V, if input voltage is higher than desired output voltage plus dropout voltage, the
output voltage is equal to the desired value. Otherwise, output voltage will be VIN minus dropout voltage.
12
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Product Folder Links: TLV70018-Q1 TLV70012-Q1
TLV70018-Q1, TLV70012-Q1
www.ti.com
SLVSB67C – NOVEMBER 2011 – REVISED JUNE 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV70018-Q1 and TLV70012-Q1 consume low quiescent current and deliver excellent line and load
transient performance. These characteristics, combined with low noise and very good PSRR with little (VIN –
VOUT) headroom, make this family of devices ideal for portable RF applications. This family of regulators offers
current limit and thermal protection, and is specified from –40°C to 125°C.
8.2 Typical Application
VOUT
VIN
IN
EN
OUT
TLV700xx-Q1
1 uF
1 uF
GND
Figure 21. Simplified Schematic
8.2.1 Design Requirements
For this design example use, the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
2 V to 5.5 V
Output voltage
1.2 V, 1.8 V
Output current rating
300 mA
Effective output capacitor range
>0.1 µF
Maximum output capacitor ESR range
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