Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
TLV700xx-Q1 200-mA Low-IQ Low-Dropout Regulator for Portable Devices
1 Features
3 Description
•
•
The TLV700xx-Q1 family of low-dropout (LDO) linear
regulators are low-quiescent-current devices with
excellent line- and load-transient performance. These
LDOs are designed for power-sensitive applications.
A precision band-gap and error amplifier provides
overall 2% accuracy. Low output noise, very high
power-supply rejection ratio (PSRR), and low dropout
voltage make this series of devices ideal for most
battery-operated handheld equipment or for working
as a second-stage power supply for connecting
automotive battery applications. All device versions
have thermal shutdown and current limit for safety.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
2% Accuracy
Low IQ: 31 μA
Fixed Output Voltages
– TLV70033-Q1: 3.3 V
– TLV70030-Q1: 3 V
– TLV70025-Q1: 2.5 V
– TLV70012A-Q1: 1.2 V
High PSRR: 68 dB at 1 kHz
Stable With Effective Capacitance of 0.1 μF
Thermal Shutdown and Overcurrent Protection
Latch-Up Performance Meets 100 mA
Per AEC-Q100, Level I
Available in the SOT-5 (DDC) and SC70-5 (DCK)
Packages
Furthermore, these devices are stable with an
effective output capacitance of only 0.1 μF. This
feature enables the use of cost-effective capacitors
that have higher bias voltages and temperature
derating. The devices regulate to specified accuracy
with no output load.
The TLV700xx-Q1 LDOs are available in the SOT-5
(DDC) and the SC70-5 (DCK) packages.
Device Information(1)
PART NUMBER
2 Applications
Automotive Second-Stage Power Supply
PACKAGE
BODY SIZE (NOM)
TLV70012A-Q1
SC70 (5)
2.00 mm × 1.25 mm
TLV70025-Q1
SOT (5)
2.90 mm × 1.60 mm
TLV70030-Q1
SC70 (5)
2.00 mm × 1.25 mm
TLV70033-Q1
SOT (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit (Fixed-Voltage Versions)
VIN
IN
OUT
CIN
COUT
VOUT
1 µF
Ceramic
TLV700xx-Q1
On
Off
EN
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
4
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (September 2015) to Revision H
Page
•
Deleted all occurences of TLV70028-Q1 and TLV70032-Q1 throughout the data sheet ...................................................... 1
•
Added an I/O column to the Pin Functions table ................................................................................................................... 3
•
Added Recommended Operating Conditions table to the data sheet .................................................................................... 4
•
Moved "High-ESR capacitors..." sentence here from the former Board Layout Recommendations to Improve PSRR
and Noise Performance section 8.1.2 .................................................................................................................................. 12
•
Deleted the Board Layout Recommendations to Improve PSRR and Noise Performance section. Moved its nonredundant contents to Input and Output Capacitor Requirements or Layout Guidelines, as appropriate............................ 12
•
Changed Z to R in the equations ........................................................................................................................................ 14
•
Moved some layout information here from former Sectioni 8.1.2, Board Layout Recommendations to Improve PSRR
and Noise Performance ........................................................................................................................................................ 14
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 16
Changes from Revision F (August 2013) to Revision G
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Revision E (January 2013) to Revision F
Page
•
Changed CDM classification level from C3B to C4B in FEATURES list ................................................................................ 1
•
Changed Added TJ to the Absolute Maximum Ratings and moved TA to the Recommended Operating Conditions............ 3
•
Changed Ground pin current (shutdown) max value from 2 to 2.5 in Electrical Characteristics table................................... 4
•
Added TLV70028-Q1 and TLV70032-Q1 to document ........................................................................................................ 13
2
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
www.ti.com
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
5 Pin Configuration and Functions
DDC and DCK Packages
5-Pin SOT and SC70
Top View
IN
1
GND
2
EN
3
5
OUT
4
NC
Not to scale
NC – No internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
3
I
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into
shutdown mode and reduces operating current to 1 μA, nominal.
IN
1
I
Input pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and
good transient performance. See Input and Output Capacitor Requirements in the Application Information
section for more details.
GND
2
—
Ground pin
NC
4
—
No internal connection. This pin can be tied to ground to improve thermal dissipation.
OUT
5
O
Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure
stability. See Input and Output Capacitor Requirements in the Application Information section for more
details.
6 Specifications
6.1 Absolute Maximum Ratings
At TA = –40°C to 125°C (unless otherwise noted). All voltages are with respect to GND. (1)
MIN
MAX
UNIT
VIN
Input voltage
–0.3
6
V
VEN
Enable voltage
–0.3
6
V
VOUT
Output voltage
–0.3
6
V
IOUT
Maximum output current
Internally limited
Output short-circuit duration
Indefinite
TJ
Operating ambient temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
3
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input supply-voltage range
2
5.5
VOUT
Output voltage
1.2
4.8
V
V
IOUT
Oytput current
0
200
mA
VEN
Voltage on EN pin
0
VIN
V
TA
Operating ambient temperature
–40
125
°C
6.4 Thermal Information
TLV700xx-Q1
THERMAL METRIC (1)
DCK (SOT)
DDC (SOT)
5 Pins
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
307.6
262.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.1
68.2
°C/W
RθJB
Junction-to-board thermal resistance
93.7
81.6
°C/W
ψJT
Junction-to-top characterization parameter
1.3
1.1
°C/W
ψJB
Junction-to-board characterization parameter
92.8
80.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = VOUT(TYP) + 0.3 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to 125°C (unless
otherwise noted). Typical values are at TA = 25°C.
space
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT ≥ 1 V
–2%
2%
VOUT < 1 V
–20
20
mV
5
mV
VOUT
DC output accuracy
–40°C ≤ TA ≤ 125°C
ΔVO / ΔVIN
Line regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V
IOUT = 10 mA
ΔVO / ΔIOUT
Load regulation
1
0 mA ≤ IOUT ≤ 200 mA, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
15
0 mA ≤ IOUT ≤ 200 mA, TLV70012A-Q1
20
mV
VDO
Dropout voltage (1)
VIN = 0.98 × VOUT(NOM), IOUT = 200 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
IGND
Ground pin current
ISHDN
Ground pin current (shutdown)
VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V
PSRR
Power-supply rejection ratio
VIN = 2.3 V, VOUT = 1.8 V
IOUT = 10 mA, f = 1 kHz
68
dB
VN
Output noise voltage
BW = 100 Hz to 100 kHz
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
48
μVRMS
tSTR
Startup time (2)
COUT = 1 μF, IOUT = 200 mA
VEN(HI)
Enable pin high (enabled)
0.9
VIN
VEN(LO)
Enable pin low (disabled)
0
0.4
V
IEN
Enable pin current
VEN = 5.5 V , IOUT = 10 μA
0.5
μA
UVLO
Undervoltage lockout
VIN rising
(1)
(2)
4
220
IOUT = 0 mA
IOUT = 200 mA, VIN = VOUT + 0.5 V
175
250
mV
350
550
mA
31
55
μA
270
1
μA
2.5
100
0.04
1.9
μA
μs
V
V
VDO is measured for devices with VOUT(NOM) ≥ 2.35 V.
Startup time = time from EN assertion to 0.98 × VOUT(NOM).
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
www.ti.com
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
Electrical Characteristics (continued)
VIN = VOUT(TYP) + 0.3 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to 125°C (unless
otherwise noted). Typical values are at TA = 25°C.
space
PARAMETER
TSD
Thermal shutdown temperature
TA
Operating ambient temperature
Copyright © 2010–2016, Texas Instruments Incorporated
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shutdown, temperature increasing
160
°C
Reset, temperature decreasing
140
°C
–40
125
Submit Documentation Feedback
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
°C
5
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
6.6 Typical Characteristics
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless
otherwise noted). Typical values are at TJ = 25°C.
1.90
1.90
IOUT = 10 mA
1.88
1.88
1.86
1.84
1.82
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
Output Voltage (V)
Output Voltage (V)
1.86
IOUT = 200 mA
1.84
1.82
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
1.70
1.70
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
2.1
2.6
3.1
Input Voltage (V)
Figure 1. TLV700xx-Q1 Line Regulation
250
Output Voltage (V)
1.86
1.84
1.82
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
Dropout Voltage (mV)
1.88
40
60
80
100 120 140
160
5.6
200
150
100
+125°C
+85°C
+25°C
-40°C
0
2.25
180 200
2.75
3.25
3.75
4.25
4.75
Input Voltage (V)
Figure 3. TLV700xx-Q1 Load Regulation
Figure 4. TLV700xx-Q1 Dropout Voltage vs Input Voltage
180
1.90
160
1.88
140
1.86
120
100
80
60
+125°C
+85°C
+25°C
-40°C
40
20
Output Voltage (V)
Dropout Voltage (mV)
5.1
IOUT = 200 mA
Output Current (mA)
1.84
1.82
1.80
1.78
1.76
IOUT = 200 mA
IOUT = 10 mA
IOUT = 150 mA
1.74
1.72
1.70
0
0
30
60
90
120
150
180
210
Output Current (mA)
Figure 5. TLV700xx-Q1 Dropout Voltage vs Output Current
6
4.6
50
1.70
20
4.1
Figure 2. TLV700xx-Q1 Line Regulation
1.90
0
3.6
Input Voltage (V)
Submit Documentation Feedback
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 6. TLV700xx-Q1 Output Voltage vs Temperature
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
www.ti.com
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
Typical Characteristics (continued)
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless
otherwise noted). Typical values are at TJ = 25°C.
50
40
35
30
25
20
15
+125°C
+85°C
+25°C
-40°C
10
5
250
Ground Pin Current (mA)
Ground Pin Current (mA)
300
IOUT = 0 mA
45
200
150
100
+125°C
+85°C
+25°C
-40°C
50
0
0
2.1
2.6
3.1
3.6
4.1
4.6
5.1
0
5.6
20
40
60
40
2.0
35
1.8
Shutdown Current (mA)
Ground Pin Current (mA)
100 120 140 160 180 200
Figure 8. TLV700xx-Q1 Ground Pin Current vs Load
Figure 7. TLV700xx-Q1 Ground Pin Current vs Input Voltage
30
25
20
15
10
5
1.6
1.4
1.2
1.0
0.8
0.6
+125°C
+85°C
+25°C
0.4
0.2
IOUT = 0 mA
0
0
-40 -25 -10
5
20
35
50
65
80
95
110 125
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
Temperature (°C)
Input Voltage (V)
Figure 9. TLV70018 Ground Pin Current vs Temperature
Figure 10. TLV700xx-Q1 Shutdown Current vs Input Voltage
440
100
430
90
420
80
IOUT = 10 mA
IOUT = 150 mA
70
410
PSRR (dB)
Current Limit (mA)
80
Output Current (mA)
Input Voltage (V)
400
390
380
60
50
40
30
370
20
360
TA = +25°C
350
2.0
2.5
3.0
3.5
4.0
4..5
10
VIN - VOUT = 0.5 V
0
10
100
1k
10 k
100 k
1M
10 M
Input Voltage (V)
Frequency (Hz)
Figure 11. TLV700xx-Q1 Current Limit vs Input Voltage
Figure 12. TLV700xx-Q1 Power-Supply Ripple Rejection vs
Frequency
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
7
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
Typical Characteristics (continued)
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless
otherwise noted). Typical values are at TJ = 25°C.
1 kHz
70
60
PSRR (dB)
Output Spectral Noise Density (mV/ÖHz)
80
10 kHz
50
100 kHz
40
30
20
10
0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
10
1
0.1
0.01
IOUT = 10 mA
CIN = COUT = 1 mF
0
10
2.8
100
Figure 13. TLV700xx-Q1 Power-Supply Ripple Rejection vs
Input Voltage
100 k
VOUT
20 mA/div
0 mA
0 mA
IOUT
VOUT
VIN = 2.3 V
10 ms/div
10 ms/div
Figure 15. TLV700xx-Q1 Load Transient Response
Figure 16. TLV700xx-Q1 Load Transient Response
Slew Rate = 1 V/ms
IOUT
0 mA
1 V/div
50 mA
VIN
2.9 V
2.3 V
5 mV/div
50 mA/div
tR = tF = 1 ms
20 mV/div
10 M
10 mA
VIN = 2.1 V
VOUT
VIN = 2.3 V
10 ms/div
Figure 17. TLV700xx-Q1 Load Transient Response
8
1M
tR = tF = 1 ms
200 mA
IOUT
10 k
Figure 14. TLV700xx-Q1 Output Spectral Noise Density vs
Output Voltage
5 mV/div
50 mV/div
100 mA/div
tR = tF = 1 ms
1k
Frequency (Hz)
Input Voltage (V)
Submit Documentation Feedback
VOUT
IOUT = 200 mA
1 ms/div
Figure 18. TLV700xx-Q18 Line Transient Response
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
www.ti.com
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
Typical Characteristics (continued)
VIN
Slew Rate = 1 V/ms
Slew Rate = 1 V/ms
2.7 V
1 V/div
1 V/div
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless
otherwise noted). Typical values are at TJ = 25°C.
2.3 V
VIN
5.5 V
10 mV/div
5 mV/div
2.1 V
VOUT
VOUT
IOUT = 200 mA
IOUT = 1 mA
1 ms/div
1 ms/div
Figure 19. TLV700xx-Q1 Line Transient Response
Figure 20. TLV700xx-Q1 Line Transient Response
IOUT = 1 mA
1 V/div
VIN
VOUT
200 ms/div
Figure 21. TLV700xx-Q1 VIN Ramp-Up, Ramp-Down Response
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
9
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
7 Detailed Description
7.1 Overview
The TLV700xx-Q1 low-dropout (LDO) linear regulators are low-quiescent-current devices with excellent line- and
load-transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap
and error amplifier provides overall 2% accuracy together with low output noise, very high power-supply rejection
ratio (PSRR), and low dropout voltage.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Band Gap
Logic
TLV700xx-Q1
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV700xx-Q1 internal current limit helps to protect the regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the
output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) ×
ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the
internal thermal-shutdown circuit. If the fault condition continues, the device cycles between current limit and
thermal shutdown. See the Thermal Information section for more details.
The PMOS pass element in the TLV700xx-Q1 has a built-in body diode that conducts current when the voltage
at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting to 5% of the rated output current is recommended.
7.3.2 Shutdown
The enable pin (EN) is active-high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to the IN pin.
10
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
www.ti.com
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
Feature Description (continued)
7.3.3 Dropout Voltage
The TLV700xx-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the rDS(on) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
This effect is shown in Figure 13 in the Typical Characteristics section.
7.3.4 Undervoltage Lockout (UVLO)
The TLV700xx-Q1 uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is
operating properly.
7.4 Device Functional Modes
7.4.1 Operation With VIN Less than 2 V
The TLV700xx-Q1 family of devices operates with input voltages above 2 V. The typical UVLO voltage is 1.9 V,
and the device operates at an input voltage above 2 V. When input voltage falls below the UVLO voltage, the
device shuts down.
7.4.2 Operation With VIN Greater than 2 V
When VIN is greater than 2 V, if the input voltage is higher than the desired output voltage plus dropout voltage,
the output voltage is equal to the desired value. Otherwise, output voltage is VIN minus the dropout voltage.
Copyright © 2010–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
11
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV700xx-Q1 belongs to a new family of next-generation value LDO regulators. The device consumes low
quiescent current and delivers excellent line and load transient performance. These characteristics, combined
with low noise, very good PSRR with little (VIN – VOUT) headroom, make this device ideal for RF portable
applications. This family of regulators offers subband-gap output voltages down to 0.7 V, current limit, and
thermal protection, and is specified from –40°C to 125°C.
8.1.1 Input and Output Capacitor Requirements
Recommended capacitors are 1.0-μF X5R- and X7R-type ceramic because these capacitors have minimal
variation in value and equivalent series resistance (ESR) over temperature.
However, the TLV700xx-Q1 is designed to be stable with an effective capacitance of 0.1 μF or larger at the
output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective
capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance
refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the
capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the
use of cheaper dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use
of smaller-footprint capacitors that have higher derating in size- and space-constrained applications.
Note that using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective
capacitance under the specified operating conditions would be less than 0.1 μF. Maximum ESR should be less
than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1μF, low-ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast-rise-time load transients are anticipated, or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.
High-ESR capacitors may degrade PSRR performance.
8.1.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
8.1.3 Thermal Information
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of the particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
12
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1
TLV70012A-Q1, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
www.ti.com
SLVSA61H – FEBRUARY 2010 – REVISED AUGUST 2016
Application Information (continued)
The internal protection circuitry of the TLV700xx-Q1 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TLV700xx-Q1 into thermal shutdown
degrades device reliability.
8.2 Typical Application
The TLV700xx-Q1 devices are 200-mA, low quiescent current, low noise, high PSRR, fast-start-up LDO linear
regulators with excellent line and load transient response. The TLV700xxEVM-503 evaluation module (EVM)
helps designers evaluate the operation and performance of the TLV700xx-Q1 family.
Figure 22 shows a typical application for the TLV70033-Q1 device.
VOUT
VIN
IN
EN
OUT
TLV70033-Q1
1 µF
1 µF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 22. TLV70033-Q1 Typical Application
8.2.1 Design Requirements
Table 1 shows example design parameters and values for this typical application.
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage range
2 V to 5.5 V
Output voltage
1.2 V, 2.5 V, 3 V, 3.3 V
Output current rating
200 mA
Effective output
capacitor range
>0.1 µF
Maximum output
capacitor ESR range
工商网监
湘ICP备2023018690号
