TLV761
SBVS349B – FEBRUARY 2020 – REVISED FEBRUARY 2023
TLV761 16-V, 1-A, Fixed Output Linear Voltage Regulator
1 Features
3 Description
•
The TLV761 is a linear voltage regulator that improves
the functionality of a traditional x1117 regulator
(TLV1117 or LM1117) with tighter output accuracy and
low quiescent current (IQ) to lower the standby power
consumption. The TLV761 is pin-to-pin compatible
with other fixed SOT-223 regulators.
•
•
•
•
•
•
•
•
•
•
•
Pin-compatible with industry-standard LM1117 and
TLV1117 (x1117) devices in select packages
Input voltage range VIN: 2.5 V to 16 V
Output voltage range VOUT:
– 0.8 V to 13 V (fixed, 100-mV steps)
Output current: Up to 1 A
Low quiescent current IQ:
– 60 μA (typical, ~1.5 μA in shutdown)
1% output accuracy over line, load and
temperature
High PSRR: 60 dB at 1 kHz, 40 dB at 1 MHz
Internal soft-start time: 500 µs (typical)
Foldback current limiting and thermal protection
Stable with 1-µF ceramic output capacitors
Temperature range: –40°C to +125°C
Package: 4-pin, 6.50-mm × 3.50-mm SOT-223
2 Applications
Appliances
Home theater and entertainment
Motor drives
HVAC and building security systems
Smart meters
The wide bandwidth PSRR performance of the
TLV761 is typically greater than 60 dB at 1 kHz
and 40 dB at 1 MHz, which helps attenuate the
switching frequency of an upstream DC/DC converter
and minimizes post regulator filtering.
Additionally, the TLV761 has an internal soft start
feature to reduce inrush current during start-up,
which can help save space and cost in a design by
minimizing input capacitance. The TLV761 features a
foldback current limit that limits the power dissipation
of the device during high-load current faults or
shorting events.
Package Information(1)
PART NUMBER
TLV761
(1)
9
0.75
8
0.5
7
0.25
6
0
5
-0.25
VIN
IIN
VOUT
4
3
-0.5
-0.75
2
-1
1
-1.25
0
-1.5
-1
PACKAGE
DCY (SOT-223, 4)
BODY SIZE (NOM)
6.50 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
VOUT
IN
OUT
TLV761
Current (A)
Voltage (V)
•
•
•
•
•
The TLV761 input voltage range is from 2.5 V to 16 V
and provides an output voltage range from 0.8 V to
13 V to support a wide variety of applications.
CIN
1µF
GND
COUT
2.2µF
Typical Application Circuit
-1.75
0
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
Inrush Current With 22 µF at COUT
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV761
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 15
8.3 Best Design Practices...............................................16
8.4 Power Supply Recommendations.............................16
8.5 Layout....................................................................... 17
9 Device and Documentation Support............................18
9.1 Device Support......................................................... 18
9.2 Documentation Support............................................ 18
9.3 Receiving Notification of Documentation Updates....18
9.4 Support Resources................................................... 18
9.5 Trademarks............................................................... 18
9.6 Electrostatic Discharge Caution................................18
9.7 Glossary....................................................................18
10 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2022) to Revision B (February 2023)
Page
• Deleted ISHUTDOWN curves and all data below VIN < 3.0 V in Electrical Characteristics table and Typical
Characteristics section........................................................................................................................................6
Changes from Revision * (February 2020) to Revision A (December 2022)
Page
• Changed document status from Advance Information to Production Data ........................................................1
2
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OUT
5 Pin Configuration and Functions
3
IN
2
OUT
1
GND
Figure 5-1. DCY Package, 4-Pin SOT-223 (Top View)
Table 5-1. Pin Functions
NO.
NAME
FUNCTION
1
GND
—
Ground pin
2, Tab
OUT
O
Output pin. Use the recommended capacitor value as listed in the Recommended
Operating Conditions table. Place the output capacitor as close to the OUT and GND
pins of the device as possible.
IN
I
Input pin. Use the recommended capacitor value as listed in the Recommended
Operating Conditions table. Place the input capacitor as close to the IN and GND
pins of the device as possible.
3
DESCRIPTION
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
Voltage (2)
VIN
VOUT
(3)
Current
Maximum output current
Power
Power dissipation
Temperature
(1)
(2)
(3)
(4)
MAX
–0.3
18
–0.3
VIN + 0.3
UNIT
V
Internally limited
A
Package limited (4)
W
Operating junction (TJ)
–50
150
Storage (TSTG)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages with respect to GND.
VIN + 0.3 V or 18 V (whichever is smaller).
See thermal information for further details.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Input voltage
2.5
16
VOUT
Output voltage
0.8
13.5
IOUT
Output current (2.5 V ≤ VIN < 3 V)
0
0.8
IOUT
Output current (VIN ≥ 3 V)
0
1
COUT ESR
Output capacitor ESR
2
COUT
Output capacitor(1)
1
CIN
Input capacitor(2)
TJ
Junction temperature
(1)
(2)
4
NOM
VIN
500
2.2
220
1
–40
125
UNIT
V
A
mΩ
µF
°C
Effective output capacitance of 0.47 µF minimum required for stability.
An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum is
recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of systemlevel
instability such as ringing or oscillation, especially in the presence of load transients
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6.4 Thermal Information
TLV761
THERMAL
METRIC(1)
UNIT
DCY (SOT223)
4 PINS
RθJA
Junction-to-ambient thermal resistance
165.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.6
°C/W
RθJB
Junction-to-board thermal resistance
37.9
°C/W
ΨJT
Junction-to-top characterization parameter
11.6
°C/W
ΨJB
Junction-to-board characterization parameter
37.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
6.5 Electrical Characteristics
specified at TJ = –40°C to 125°C, VIN = VOUT(nom) + 1.5 V or VIN = 2.5 V (whichever is greater), IOUT = 10 mA, CIN = 1.0 µF
and COUT = 1.0 µF (unless otherwise noted); typical values are at TJ= 25ºC
PARAMETER
TEST CONDITIONS
VOUT
Nominal output accuracy
TJ = 25°C
VOUT
Output accuracy over temperature
VIN ≥ 3.0 V, 1 mA ≤ IOUT ≤ 1 A
ΔVOUT(ΔVIN)
Line
regulation(1)
MIN
TYP MAX
–1
1
%
–1.75
1.75
%
VOUT(NOM) +1.5 V ≤ VIN ≤ 16 V, IOUT = 10 mA
ΔVOUT(ΔIOUT) Load regulation
1 mA ≤ IOUT ≤ 1 A, VIN ≥ 3.0 V
voltage(2)
VDO
Dropout
ICL
Output current limit
VOUT = 0.9 x VOUT(NOM) , VIN ≥ 3.0 V
1.1
ISC
Short-circuit current limit
VOUT = 0 V
150
IQ
Quiescent current
IOUT = 0 mA
current(3)
VIN ≥ 3.0V, IOUT = 1 A
0.02
%/V
0.1
0.75
%/A
0.9
1.6
V
1.6
A
250
350
mA
65
100
µA
1.1
mA
IPULLDOWN
Output pulldown
PSRR
Power-supply rejection ratio
VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA, f = 120 Hz
70
dB
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VIN = 3.3 V, VOUT = 0.8 V,
IOUT = 100 mA
60
µVRMS
VUVLO+
UVLO threshold rising
VIN rising
VUVLO(HYS)
UVLO hysteresis
VUVLO-
UVLO threshold falling
VIN falling
TSD(shutdown)
Thermal shutdown temperature
TSD(reset)
Thermal shutdown reset temperature
(1)
(2)
(3)
VIN = 1.8 V, VOUT = 2.5 V
UNIT
0.7
2.2
2.4
V
130
mV
Temperature increasing
180
ºC
Temperature falling
160
ºC
1.9
V
Line regulation is measured with VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater).
VDO is measured with VIN = 95% x VOUT(nom) for fixed output devices. VDO is not measured for fixed output devices when VOUT < 2.5 V.
IPULLDOWN is measured with VIN = 1.8 V (lower than UVLO falling threshold, with LDO in disabled state) and 2.5 V applied on VOUT
externally.
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, CIN = 1.0 µF, and
COUT = 1.0 µF (unless otherwise noted)
For VIN ≥ 3.0 V
IOUT = 10 mA
Figure 6-1. VOUT Accuracy vs IOUT
Figure 6-2. VOUT Accuracy vs VIN
IOUT = 0 mA
Figure 6-3. IQ vs Temperature
IOUT = 0 mA
Figure 6-4. IQ Increase Below Minimum VIN
For VIN ≥ 3.0 V
Figure 6-5. IGND vs IOUT
6
VIN = 5 V, VOUT = 3.3 V, ramp rate = 0.4 A/µs
Figure 6-6. IOUT Transient From 0 mA to 100 mA
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, CIN = 1.0 µF, and
COUT = 1.0 µF (unless otherwise noted)
VIN = 5 V, VOUT = 3.3 V, ramp rate = 0.5 A/µs
Figure 6-7. IOUT Transient From 1 mA to 1 A
VIN = 5 V VOUT = 3.3 V, IOUT = 1 A, VIN ramp rate = 0.6 V/µs
Figure 6-9. VIN Transient in Dropout From 4 V to 13 V
VIN = 5 V, VOUT = 3.3 V, ramp rate = 0.8 A/µs
Figure 6-8. IOUT Transient From 250 mA to 850 mA
VOUT = 3.3 V, IOUT = 33 µA, VIN ramp rate = 1.6 V/µs
Figure 6-10. VIN Transient From 5 V to 16 V
IOUT = 1.0 A
IOUT = 0.8 A
Figure 6-11. VDO vs VIN
Figure 6-12. VDO vs VIN
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, CIN = 1.0 µF, and
COUT = 1.0 µF (unless otherwise noted)
For VIN ≥ 3.0 V
Figure 6-13. UVLO Thresholds vs Temperature
Figure 6-14. VDO vs IOUT
For VIN ≥ 3.0 V
Figure 6-15. Foldback Current Limit vs Temperature
Figure 6-16. Foldback Current Limit vs Temperature
VOUT = 1.8 V, VIN = 3.3 V
VOUT = 1.8 V, IOUT = 0.55 A
Figure 6-17. PSRR vs IOUT
8
Figure 6-18. PSRR vs VIN
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6.6 Typical Characteristics (continued)
9
0.75
8
0.5
7
0.25
6
0
5
-0.25
VIN
IIN
VOUT
4
3
-0.5
-0.75
2
-1
1
-1.25
0
-1.5
-1
-1.75
0
0.5
IOUT = 0.1 A, RMS noise BW = 10 Hz to 100 kHz
Figure 6-19. Output Noise (Vn) vs VOUT
Current (A)
Voltage (V)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, CIN = 1.0 µF, and
COUT = 1.0 µF (unless otherwise noted)
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
IOUT = 0.1 A, COUT = 22 µF
Figure 6-20. Inrush Current With 22 µF at COUT
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7 Detailed Description
7.1 Overview
The TLV761 is a low quiescent current, high PSRR linear regulator capable of sourcing load current up to 1 A.
This device is designed for high current applications such as appliances where there are increasingly stringent
requirements for standby and active power consumption.
This device features integrated foldback current limit, thermal shutdown, internal output pulldown, and
undervoltage lockout (UVLO). This device delivers excellent line and load transient performance. The TLV761
is low noise and exhibits very good PSRR. The operating ambient temperature range of the device is –40°C to
+125°C.
7.2 Functional Block Diagram
VIN
VOUT
R1
Current
Limit
R2
+
–
UVLO
GND
Internal
Controller
Bandgap
Reference
VREF = 0.8 V
Output
Pull-down
GND
GND
Thermal
Shutdown
GND
7.3 Feature Description
7.3.1 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
10
VDO
IRATED
(1)
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7.3.2 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall-foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 50% × VOUT(nom).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application note.
Figure 7-1 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
ISC
IRATED
ICL
Figure 7-1. Foldback Current Limit
7.3.3 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
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7.3.4 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start-up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start-up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
12
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output
capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance
of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
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Figure 8-1 shows one approach for protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 8-1. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
14
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8.1.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ). As described in the following equations, use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(4)
where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(5)
where:
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
8.2 Typical Application
The TLV761 is a low quiescent current linear regulator designed for high current applications. Unlike most typical
high current linear regulators, the TLV761 consumes significantly less quiescent current. This device delivers
excellent line and load transient performance. The device is low noise and exhibits a very good PSRR. As a
result, the TLV761 is designed for high current applications that require very sensitive power-supply rails.
This regulator offers both current limit and thermal protection. The operating ambient temperature range of the
device is –40°C to +125°C.
Figure 8-2 shows a typical application circuit for this device.
VIN
VOUT
IN
OUT
TLV761
CIN
1µF
GND
COUT
2.2µF
Figure 8-2. Typical Application Circuit
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8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V
Output voltage
5V
Output current
50 mA
8.2.2 Detailed Design Procedure
For this design example, the 3.3-V, fixed-version TLV76133 is selected and is powered by a standard 12-V input
supply. The dropout voltage (VDO) is kept within the TLV761 dropout voltage specification for the 3.3-V output
voltage option to keep the device in regulation under all load and temperature conditions for this design. A
1.0-µF output capacitor is recommended for excellent load transient response. The input capacitor is optional
and is used to reduce the input impedance of the circuit and improve the transient response.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude.
8.3 Best Design Practices
Place input and output capacitors as close to the device as possible.
Use a ceramic output capacitor.
Do not exceed the device absolute maximum ratings.
8.4 Power Supply Recommendations
Connect a low output impedance power supply directly to the INPUT pin of the device . Inductive impedances
between the input supply and the INPUT pin can create significant voltage excursions at the INPUT pin during
start-up or load transient events.
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8.5 Layout
8.5.1 Layout Guidelines
Place input and output capacitors as close to the device pins as possible. To improve characteristic AC
performance such as PSRR, output noise, and transient response, design the board with separate ground
planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the
ground connection for the output capacitor must be connected directly to the GND pin of the device. Higher
value ESR capacitors can degrade PSRR performance.
8.5.2 Layout Example
OUT
GND
Tab
COUT
CIN
1
2
3
GND
IN
Figure 8-3. Layout Example
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Device Nomenclature
Table 9-1. Available Options(1) (2)
PRODUCT
TLV761xxyyyz
(1)
(2)
VOUT
xx is the nominal output voltage (for example 33 = 3.3 V).
yyy is the package designator.
z is the package quantity.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
The device is available in factory-programmable fixed output voltage increments of 50 mV upon request.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TLV1117 Adjustable and Fixed Low-Dropout Voltage Regulator data sheet
• Texas Instruments, LM1117 800-mA Low-Dropout Linear Regulator data sheet
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PLV76133DCYR
ACTIVE
SOT-223
DCY
4
PTLV76118DCYR
OBSOLETE
SOT-223
DCY
4
TLV76133DCYR
ACTIVE
SOT-223
DCY
4
TLV76150DCYR
ACTIVE
SOT-223
DCY
4
2500
TBD
Call TI
Call TI
-40 to 125
TBD
Call TI
Call TI
-40 to 125
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
76133C
Samples
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
76150C
Samples
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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