TLV803E, TLV809E, TLV810E
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
TLV803E, TLV809E, TLV810E Low Power 250-nA IQ and Small Size Supply Voltage
Supervisors
1 Features
3 Description
•
•
The TLV803E, TLV809E, and TLV810E are enhanced
alternatives to the TLV803, TLV853, TLV809, LM809,
TPS3809 and TLV810. TLV80xE and TLV81xE offer
low quiescent current IQ, higher accuracy, wider
temperature range, and lower power-on-reset (VPOR)
for increased system reliability.
•
•
•
•
•
•
Ensured RESET/RESET for VDD = 0.7 V to 6 V
Fixed time delay: 40 µs, 10 ms, 50 ms, 100 ms,
200 ms, 400 ms
Supply current (IDD): 250 nA (typical)
– 1 µA (maximum for VDD = 3.3 V)
Output topology:
– TLV809E: push-pull, active-low
– TLV803E: open-drain, active-low
– TLV810E: push-pull, active-high
Under voltage detection:
– High accuracy: ±0.5% (typical)
– (VIT–): 1.7 V, 1.8 V, 1.9 V, 2.25V, 2.4 V, 2.64 V,
2.93 V, 3.08 V, 3.3V, 4.2V, 4.38 V, 4.55V, 4.63 V
Package:
– SOT23-3 (DBZ) (with pin 1 = GND)
– SOT23-3 (DBZ) (with pin 1 = RESET/RESET)
– SOT23-3 (DBZ) (with pin 3 = GND)
– SC-70 (DCK)
– X2SON-5 (DPW)
Temperature range: –40°C to +125°C
Pin-to-pin compatible with MAX803/809/810,
APX803/809/810
The TLV80xE and TLV81xE family are low IQ (250 nA
typical, 1 µA max), voltage supervisory circuits (reset
IC) that monitor VDD voltage level. These devices
initiate a reset signal whenever supply voltage VDD
drops below the factory programmed falling threshold
voltage, VIT–. The reset output remains low for a fixed
reset time delay tD after the VDD voltage rises above
the rising voltage threshold (VIT+) which is equivalent
to the falling threshold voltage (VIT-) plus hysteresis
(VHYS).
These devices have integrated glitch immunity to
ignore fast transients on the VDD pin. The low
IQ and high accuracy (±0.5% typical) makes these
voltage supervisors ideal for use in low-power and
portable applications. The TLV80xE and TLV81xE
devices are specified to have the defined output logic
state for supply voltages down to VPOR = 0.7 V.
The TLV80xE and TLV81xE devices are available
in industry standard 3-pin SOT23 (DBZ) and SC70
(DCK) packages and very compact X2SON (DPW)
package.
2 Applications
•
•
•
•
•
•
Electricity meters
Factory Automation
Portable, battery-powered equipment
Set-top boxes and TVs
Building automation
Notebook/desktop computers, servers
Device Information (1)
PART NUMBER
TLV803E, TLV809E,
TLV810E
(1)
IN
OUT
TLV803E
RESET
VDD
BODY SIZE (NOM)
2.90 mm × 1.30 mm
SC-70 (3)
2.00 mm × 1.25 mm
X2SON (5)
0.8 mm x 0.8 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
*Rpu ll-up
LDO
PACKAGE
SOT-23 (3)
GND
VDD
FPGA, ASIC, DSP
RESET
GND
*Pull-up resistor no t requir ed for TLV809E, TLV810E
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................8
7.6 Timing Requirements ................................................. 9
7.7 Timing Diagrams....................................................... 10
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................19
9 Application and Implementation.................................. 20
9.1 Application Information............................................. 20
9.2 Typical Application - Voltage Rail Monitoring............ 20
9.3 Typical Application - Overvoltage Monitoring............22
10 Power Supply Recommendations..............................23
11 Layout........................................................................... 24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................26
12.1 Device Support....................................................... 26
12.2 Documentation Support.......................................... 27
12.3 Receiving Notification of Documentation Updates..27
12.4 Support Resources................................................. 27
12.5 Trademarks............................................................. 27
12.6 Electrostatic Discharge Caution..............................27
12.7 Glossary..................................................................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (Feb 2021) to Revision J (May 2021)
Page
• Updated Device Naming Nomenclature figure by adding Pinout Indicator (DBZ Package Only) from Pinout
Indicator ............................................................................................................................................................. 3
• Updated pin numbering of Figure 6-5 (X2SON) package and updated Pin Functions Table............................. 4
• Updated X2SON (DPW) Layout Example........................................................................................................ 24
Changes from Revision H (December 2020) to Revision I (February 2021)
Page
• Remove duplicate package.............................................................................................................................. 27
Changes from Revision G (October 2020) to Revision H (December 2020)
Page
• Added Reset time delay variant F specification..................................................................................................9
Changes from Revision F (June 2020) to Revision G (October 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Added additional threshold voltages (VIT-) and new package information .........................................................1
• Updated Device Naming Nomenclature figure to include (DBZ) V pinout option .............................................. 3
• Added new (DBZ) package option (Pin 3 = GND, V pinout) and updated Pin Functions Table..........................4
• Added layout example for (DBZ) V pinout package..........................................................................................24
• Modified Device Naming Convention table to include additional threshold voltages (VIT-), reset time delay
options and pinout indicator options................................................................................................................. 26
Changes from Revision E (April 2020) to Revision F (June 2020)
Page
• Changed DPW package from Advanced Information to Production Data.......................................................... 1
• Changed DPW package Information ................................................................................................................. 4
Changes from Revision D (February 2020) to Revision E (April 2020)
Page
• Added X2SON (DPW) package option .............................................................................................................. 3
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
Changes from Revision C (November 2019) to Revision D (February 2020)
Page
• Added device nomenclature figure .................................................................................................................... 3
• Added timing diagram for TLV810E .................................................................................................................10
• Added Figure 6, Figure 23, Figure 24 .............................................................................................................. 11
• Added typical application for TLV810E ............................................................................................................ 22
Changes from Revision B (July 2019) to Revision C (November 2019)
Page
• Changed device status from Advance Information to Production Data.............................................................. 1
5 Device Comparison
Figure 5-1 shows the device naming nomenclature to compare the difference device variants. See Table 12-1 for
a more detailed explanation.
TLV XXXX X XX X XXX
OUTPUT TYPE
803E: Open-Drain Acve-Low
809E: Push-Pull Ac ve-Low
810E: Push-Pull Acve-High
DELAY OPTIONS
A: 200 ms
B: 40 µs
C: 10 ms
D: 50 ms
E: 100 ms
F: 400 ms
THRESHOLD VOLTAGE
17: 1.7 V
...
46: 4.63 V
PINOUT INDICATOR (DBZ PACKAGE ONLY)
R: Pin 1 = RESET, Pin 2 = GND
V: Pin 1 = RESET, Pin 3 = GND
Package
DBZ: SOT23
DCK: SC70
DPW: X2SON
Figure 5-1. Device Naming Nomenclature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
3
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
6 Pin Configuration and Functions
GND
1
GND
3
RESET
RESET
VDD
3
2
RESET
RESET
1
3
GND
VDD
2
Figure 6-2. DCK Package
3-Pin SC-70
Top View
(TLV810E)
Figure 6-1. DBZ Package
(Pin 1 = GND)
3-Pin SOT-23
Top View
RESET
1
1
VDD
3
2
VDD
Figure 6-3. DBZ Package
(Pin 1 = RESET, R pinout)
3-Pin SOT-23
Top View
GND
2
Figure 6-4. DBZ Package
(Pin 3 = GND, V pinout)
3-Pin SOT-23
Top View
RESET
RESET
1
5
VDD
4
GND
(TLV810E)
PAD
3
MR
2
Top View
Figure 6-5. DPW Package
5-Pin X2SON
See Table 6-1
Top View
4
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
Table 6-1. Pin Functions
PIN
NAME
GND
RESET
DCK, DBZ
DBZ
(V PINOUT)
DBZ
(R PINOUT)
DPW
1
3
2
4
2
1
1
1
I/O
DESCRIPTION
—
Ground
O
Active-low output reset signal: This pin is driven
low logic when VDD voltage falls below the
negative voltage threshold (VIT–). RESET remains
low (asserted) for the delay time period (tD) after
VDD voltage rise above VIT+.
RESET
2
1
1
1
O
Active-High output reset signal (TLV810E only):
This pin is driven high logic when VDD voltage falls
below the negative voltage threshold (VIT–). RESET
remains high (asserted) for the delay time period (tD)
after VDD voltage rise above VIT+.
VDD
3
2
3
5
I
Input supply voltage. TLV803E, TLV809E,
TLV810E monitor VDD voltage.
MR
N/A
N/A
N/A
2
I
Active-low manual reset input. Pull this pin to a
logic low (VMR_L) to assert a reset signal in the output
pin. After the MR pin is left floating or pulled to VMR_H
the output goes to the nominal state after the reset
delay time (tD) expires. MR can be left floating when
not in use.
PAD
N/A
N/A
N/A
3
—
No Connection. Thermal pad helps with thermal
dissipation. PAD does not need to be soldered down.
PAD can be connected to GND.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
5
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
Voltage
MAX
UNIT
VDD pin
–0.3
6.5
V
RESET (TLV809E), RESET (TLV810E)
–0.3
VDD + 0.3 (2)
V
RESET (TLV803E)
–0.3
6.5
V
Voltage
MR
–0.3
VDD + 0.3(2)
V
Current
Output sink and source current
-20
20
Operating ambient, TA
–40
125
Storage, Tstg
–65
150
Temperature(3)
(1)
(2)
(3)
mA
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions (above the Recommended Operating
Conditions) for extended periods may affect device reliability.
The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller.
As a result of the low dissipated power in this device, the junction temperature is assumed to be equal to the ambient temperature.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
± 2000
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
1.7
NOM
MAX
Input supply voltage
VRESET, VRESET
RESET pin and RESET pin voltage
0
6
V
IRESET, IRESET
RESET pin and RESET pin current
0
±5
mA
TJ
Junction temperature (free air temperature)
–40
125
°C
VMR
Manual reset pin voltage
0
VDD
V
Submit Document Feedback
6
UNIT
VDD
V
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.4 Thermal Information
TLV803E, TLV809E, TLV810E
THERMAL
METRIC(1)
DPW (X2SON)
DCK (SC70-3)
DBZ (SOT23-3)
5 PINS
3 PINS
3 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
457.1
300.5
254.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
201.6
178.2
150.5
°C/W
RθJB
Junction-to-board thermal resistance
320.4
166.5
140.1
°C/W
ψJT
Junction-to-top characterization parameter
22.8
70
48.1
°C/W
ψJB
Junction-to-board characterization parameter
318.8
165.2
139.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
7
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.5 Electrical Characteristics
over operating range (TA = –40℃ to 125℃), 1.7 V ≤ VDD ≤ 6 V, Rpull-up = 10 kΩ to 6 V, 10 pF load at RESET pin, unless
otherwise noted. Typical values are at 25℃, VDD = 3.3V and VIT– = 2.93 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
1.7
6
V
VIT–
Input threshold voltage accuracy
TA= –40℃ to 125℃
–2
0.5
2
%
VHYS
Hysteresis voltage
Hysteresis from VIT–
0.9
1.2
1.5
%
IDD
Supply current into VDD pin
0.25
1
µA
0.4
1.2
µA
RMR
Manual reset pin internal pull-up
resistance
VMR_L
Manual reset pin logic low input
VMR_H
Manual reset pin logic high input
VDD = 3.3 V; VDD > VIT+ (1)
VDD = 6 V
100
X2SON (DPW) package only
kΩ
0.4
0.8VDD
V
V
TLV809E (Push-Pull Active-Low)
Power on reset voltage (2)
VPOR
Low level output voltage
VOL
High level output voltage
VOH
VOL ≤ 300 mV, IOUT(Sink) = 15 µA
700
mV
VDD = 1.7 V, VDD < VIT–, IOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, VDD < VIT–, IOUT(Sink) = 2 mA
300
mV
VDD = 6 V, VDD > VIT+, IOUT(Source) = 4 mA
0.8VDD
V
VDD = 3.3 V, VDD > VIT+, IOUT(Source) = 2 mA
0.8VDD
V
TLV803E (Open-Drain Active-Low)
VPOR
VOL
Power on reset voltage (2)
VOL ≤ 300 mV, IOUT(Sink) = 15 µA
700
mV
Low level output voltage
VDD = 1.7 V, VDD < VIT–, IOUT(Sink) = 500 µA
300
mV
300
mV
Open drain output leakage current
VDD = VPULLUP = 6 V, VDD > VIT+
350
nA
VDD = 3.3 V, VDD < VIT–, IOUT(Sink) = 2 mA
Ilkg(OD)
100
TLV810E (Push-Pull Active-High)
VOH
VPOR
VOL
(1)
(2)
8
High level output voltage
Power on Reset Voltage
Low level output voltage
VDD = 3.3 V, VDD < VIT–, IOUT(Source) = 2 mA
0.8VDD
VDD = 1.7 V, VDD < VIT–, IOUT(Source) = 500 µA
0.8VDD
V
V
VOH ≥ 720 mV, IOUT(Source) = 15 µA
900
mV
VDD = 6 V, VDD > VIT+, IOUT(Sink) = 2 mA
300
mV
VDD = 3.3 V, VDD > VIT+, IOUT(Sink) = 500 µA
300
mV
VIT+ = VIT– + VHYS
Minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.6 Timing Requirements
over operating range (TA = –40℃ to 125℃), 1.7 V ≤ VDD ≤ 6 V, Rpull-up = 10 kΩ to 6 V (Open Drain only), 10 pF load at
RESET pin, Overdrive = 10%, unless otherwise noted. Typical values are at 25℃, VDD = 3.3 V and VIT– = 2.93 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI
Glitch immunity
5 % Overdrive(1)
10
tPD_HL
Propagation delay from VDD falling below
VIT– to RESET
VDD = (VIT+ + 30%) to (VIT– –
10%)
30
50
µs
200
270
ms
45
90
µs
40
80
µs
6.5
10
13.5
ms
33
50
67
ms
260
400
540
ms
Reset time delay variant A (2)
130
Reset time delay variant B (2);
RUP = 100 kΩ, CL = 100 pF, 30%
Overdrive (3)
tD
Release time or reset timeout period
Reset time delay variant B (2)
Reset time delay variant C (2)
Reset time delay variant D (2)
Reset time delay variant F (2)
tMR_PW (4)
MR pin pulse duration to initiate RESET,
RESET
tMR_RES (4)
Propagation delay from MR low to RESET,
RESET
VDD = 4.5 V, VMR : VMR_H to
VMR_L
tMR_tD (4)
Delay from release MR to deasert RESET,
RESET
VDD = 4.5 V, VMR : VMR_L to
VMR_H
(1)
(2)
(3)
(4)
tD_MIN
µs
500
ns
700
ns
tD_TYP
tD_MAX
ms
Overdrive = [(VDD/ VIT–) - 1] × 100%. Refer to section on VDD glitch immunity
Refer to Device nomenclature table. VDD: (VIT--10%) to (VIT+ + 10%)
Specified by design
X2SON Package only
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
9
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.7 Timing Diagrams
VIT+
VIT-
VHYS
VDD(MIN)
VDD
VPOR
tPD_HL
tPD_HL
tD
RESET
Undefined output VDD < VPOR
Diagram not to scale
Figure 7-1. TLV803E, TLV809E Timing Diagram
VIT+
VIT-
VDD
VHYS
VDD(MIN)
VPOR
tD
tPD_HL
tD
tPD_HL
RESET
Undefined output VDD < VPOR
Diagram not to scale
Figure 7-2. TLV810E Timing Diagram
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.8 Typical Characteristics
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
0.45
0.4
0.5
25°C
-40°C
125°C
0.45
25°C
-40°C
125°C
0.4
0.35
IDD (µA)
IDD (µA)
0.35
0.3
0.25
0.3
0.25
0.2
0.2
0.15
0.1
1.5
2
2.5
3
3.5
4
VDD (V)
4.5
5
5.5
0.1
1.5
6
2
2.5
3
IDD_
3.5
4
VDD (V)
4.5
5
5.5
6
IDD_
Figure 7-3. Supply Current Versus Supply Voltage for
TLV803EA29
Figure 7-4. Supply Current Versus Supply Voltage for
TLV809EA29
0.45
0.32
0.4
0.35
25°C
-40°C
125°C
0.31
TLV803EA29
0.3
0.29
0.3
0.28
0.25
0.27
IDD (µA)
IDD (µA)
0.15
0.2
0.26
0.25
0.15
0.24
0.1
0.23
0.22
0.05
0.21
0
1.5
2
2.5
3
3.5
4
VDD (V)
4.5
5
5.5
0.2
-40
6
Figure 7-5. Supply Current Versus Supply Voltage for
TLV810EA29
27
40
60
80
Temperature (°C)
100
120
140
IDD_
TLV803EA29
24
0.29
0.28
21
0.27
18
ILKG (nA)
IDD (µA)
20
30
TLV809EA29
0.3
0.26
0.25
0.24
15
12
9
0.23
6
0.22
0.21
0.2
-40
0
Figure 7-6. Supply Current Verses Temperature for
TLV803EA29, VDD = 3.3 V
0.32
0.31
-20
IDDv
3
-20
0
20
40
60
80
Temperature (°C)
100
120
140
Figure 7-7. Supply Current Verses Temperature for
TLV809EA29, VDD = 3.3 V
0
-40
-20
0
IDD_
20
40
60
80
Temperature (°C)
100
120
140
ILKG
Figure 7-8. Leakage Current Verses Temperature for
TLV803EA29
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
11
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
1
1.3
TLV803EA29
0.92
1.1
1
0.76
VIT- Accuracy (%)
VIT- Accuracy (%)
0.84
0.68
0.6
0.52
0.44
0.9
0.8
0.7
0.6
0.5
0.4
0.36
0.3
0.28
0.2
0.2
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0.1
-40
140
20
40
60
80
Temperature (°C)
100
120
140
VIT-
0.55
-40°C
-20°C
85°C
105°C
125°C
0.64
0.56
-40°C
-20°C
85°C
105°C
125°C
0.5
0.45
0.4
0.35
VOL (V)
0.48
0.4
0.32
0.3
0.25
0.2
0.24
0.15
0.16
0.1
0.08
0.05
0
0
0
0.002
0.004
0.006
IRESET (A)
0.008
0.01
0
0.004
0.006
IRESET (A)
0.008
0.01
VOLx
Figure 7-12. Low Voltage Output Versus Output Current for
TLV809EA29, VDD = 1.7 V
25
25
TLV803EA29
TLV809EA29
24.5
24
24
23.5
23.5
VOL (mV)
24.5
23
22.5
23
22.5
22
22
21.5
21.5
21
-40
0.002
VOLx
Figure 7-11. Low Voltage Output Versus Output Current for
TLV803EA29, VDD = 1.7 V
VOL (mV)
0
Figure 7-10. Voltage Threshold Accuracy Verses Temperature
for TLV809EA29
0.8
0.72
-20
0
20
40
60
80
Temperature (qC)
100
120
140
21
-40
-20
0
VOLx
Figure 7-13. Low Voltage Output Verses Temperature for
TLV803EA29, VDD = 1.7 V
12
-20
VIT-
Figure 7-9. Voltage Threshold Accuracy Verses Temperature for
TLV803EA29
VOL (V)
TLV809EA29
1.2
20
40
60
80
Temperature (qC)
100
120
140
VOLx
Figure 7-14. Low Voltage Output Verses Temperature for
TLV809EA29, VDD = 1.7 V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
6
3.12
-40°C
-20°C
25°C
85°C
105°C
125°C
5.9
5.8
5.6
3.11
3.105
3.1
VOH (V)
VOH (V)
5.7
TLV809EA29
3.115
5.5
5.4
3.095
3.09
3.085
5.3
3.08
5.2
3.075
3.07
5.1
3.065
-40
5
0
0.002
0.004
0.006
IRESET (A)
0.008
0.01
VOHx
Figure 7-15. High Voltage Output Versus Output Current for
TLV809EA29, VDD = 6 V
0
20
40
60
80
Temperature (qC)
100
120
140
VOHx
Figure 7-16. High Voltage Output Verses Temperature for
TLV809EA29, VDD = 3.3 V
6
0.12
TLV803EA29
5.5
-20
25°C
5
0.1
4.5
0.08
VRESET (V)
VRESET (V)
4
3.5
3
2.5
0.06
0.04
2
1.5
0.02
1
0.5
0
0
0
0.5
1
1.5
2
2.5 3 3.5
VDD (V)
4
4.5
5
5.5
0
6
0.1
0.2
0.3
VCC_
Figure 7-17. Reset Voltage Output Versus Voltage Input for
TLV803EA29, Vpull-up = VDD, Rpull-up = 10 kΩ
0.4
0.5 0.6
VDD (V)
0.7
0.8
0.9
1
Vpor
Figure 7-18. Reset Voltage Output Versus Voltage Input for
TLV803EA29, Rpull-up = 10 kΩ
173
2
TLV803EA29
VDD
RESET
172
1.6
tD (ms)
Voltage (V)
171
1.2
170
0.8
169
0.4
168
0
0
6
12
18
Time (µs)
24
30
VRES
Figure 7-19. Transient Power-on-Reset Voltage for TLV809EA30,
IRESET = 15 µA
167
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
Rese
Figure 7-20. Reset Delay Time Verses Temperature for
TLV803EA29
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
13
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
171.5
TLV809EA29
171
170.5
170
tD (µs)
tD (ms)
169.5
169
168.5
168
167.5
167
166.5
166
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
16.25
16.2
16.15
16.1
16.05
16
15.95
15.9
15.85
15.8
15.75
15.7
15.65
15.6
-40
TLV803EB29
-20
0
20
tD__
Figure 7-21. Reset Delay Time Verses Temperature for
TLV809EA29
40
60
80
Temperature (°C)
100
120
140
Rese
Figure 7-22. Reset Delay Time Verses Temperature for
TLV803EB29
9
25
TLV803EC29
TLV803EA29
24.75
8.8
24.5
8.6
tPHL (µs)
tD (ms)
24.25
8.4
24
23.75
23.5
23.25
23
8.2
22.75
8
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
22.5
-40
140
Rese
0
20
40
60
80
Temperature (°C)
100
120
140
tPHL
Figure 7-24. High-to-Low Propagation Delay Verses
Temperature for TLV803EA29
Figure 7-23. Reset Delay Time Verses Temperature for
TLV803EC29
26
13
TLV809EA29
25°C
-40°C
125°C
12
25.5
11
Glitch Immunity (µs)
25
tPHL (µs)
-20
24.5
24
23.5
23
10
9
8
7
6
5
22.5
22
-40
4
-20
0
20
40
60
80
Temperature (°C)
100
120
140
Figure 7-25. High-to-Low Propagation Delay Verses
Temperature for TLV809EA29
14
3
5
10
15
tPHL
20
25
30
35
Overdrive (%)
40
45
50
tGI_
Figure 7-26. Glitch Immunity Versus Overdrive for TLV803EA29
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
13
25°C
-40°C
125°C
12
Glitch Immunity (µs)
11
10
9
8
7
6
5
4
3
5
10
15
20
25
30
35
Overdrive (%)
40
45
50
tGI_
Figure 7-27. Glitch Immunity Versus Overdrive for TLV809EA29
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
15
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
8 Detailed Description
8.1 Overview
The TLV803E, TLV809E, TLV810E is a family of easy to implement low power, small size voltage supervisors
(Reset ICs) with fixed threshold voltage and fixed reset delay. The TLV803E has open-drain active-low output
topology which requires an external pull-up resistor, TLV809E has push-pull active-low output topology and
TLV810E has push-pull active-high output topology. This family of devices features include integrated resistor
divider threshold with hysteresis and a glitch immunity filter.
These devices are available in SOT-23 (3) and SC70 (3) industry standard package and pinout as well as a very
small X2SON (5) package.
8.2 Functional Block Diagram
VDD
RMR
MR
Push-pull TLV809E,
TLV810E variants
DPW package only
VDD
+
VDD
Reference
Voltage
RESET
LOGIC
TIMER
±
RESET
(TLV803E, TLV809E)
RESET
(TLV810E)
GND
GND
8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator with integrated reference to indicate when VDD falls below the
fixed threshold voltage. VDD also functions as the supply for the following:
•
•
•
•
•
Internal bandgap (reference voltage)
Internal regulator
State machine
Buffers
Other control logic blocks
Good design practice involves placing a 0.1-µF to 1-µF bypass capacitor at VDD input for noisy applications and
to ensure enough charge is available for the device to power up correctly. The reset output is undefined when
VDD is below VPOR.
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
8.3.2 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the
VDD pin falls below the falling voltage threshold VIT–, the output reset is asserted. When the voltage at the VDD
pin rises above the rising voltage threshold (VIT+) equivalent to VIT– plus hysteresis (VHYS), the output reset is
deasserted after tD reset time delay.
8.3.3 VDD Glitch Immunity
These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on
both pulse duration (tGI) found in Section 7.6 and transient overdrive. Overdrive is defined by how much VDD
exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as
shown in Equation 1.
Overdrive = | (VDD / (VIT– – 1)) × 100% |
(1)
where
•
•
VIT– is the threshold voltage
VDD is the input voltage crossing VIT–
VDD
VIT+
VITOverdrive
Pulse
Duration
Figure 8-1. Overdrive Versus Pulse Duration
TLV803E, TLV809E, and TLV810E devices have built-in glitch immunity (tGI) of 10 µs typical as shown in
Section 7.6. Figure 8-2 shows that VDD must fall below VIT- for tGI, otherwise the faling transistion is ignored.
When VDD falls below VIT- for tGI, RESET transitions low to indicate a fault condition after the propagation delay
high-to-low (t PDHL). When VDD rises above VIT+, RESET only deasserts to logic high indicating there is no more
fault condition only if VDD remains above VIT+ for longer than the reset delay (tD).
VDD remains above VIT+ for only 199 ms
VDD
RESET
VIT+
VIT-
VDD drops below VIT- so
RESET transitions low after
Propagation Delay (tPDHL)
VDD transition to above VIT+ ignored when less than
Reset Delay (tD) so RESET remains unchanged
Figure 8-2. Glitch Immunity when VDD Rises Above VIT+ for Less than RESET Delay (TLV803EA29)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
17
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
8.3.4 Manual Reset (MR) Input for X2SON (DPW) Package Only
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR
with pulse duration longer than tMR_RES will cause reset output to assert. After MR returns to a logic high
(VMR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
If MR is not controlled externally, then MR can be left disconnected. MR is internally connected to VDD through
a pull-up resistor RMR shown in Section 8.2. If the logic signal controlling MR is less than VDD, then additional
current flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND.
VMR should not be higher than VDD voltage.
VDD
VIT+
VIT+
VHYS
VIT-
VHYS
VIT-
tP_HL
tD
tMR_tD
RESET
tMR_RES
MR
(2)
VMR_H
VMR_L
(1)
tMR_PW
Time
(1) MR pulse width too small to assert RESET
(2) MR voltage not low enough to assert RESET
Figure 8-3. Timing Diagram MR and RESET for X2SON (DPW) Package
8.3.5 Output Logic
8.3.5.1 RESET Output, Active-Low
RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT–). If VDD falls below the
negative threshold (VIT–), then reset is asserted and RESET transistions to logic low (VOL).
When VDD rises above VIT+, the delay circuit holds RESET active and logic low for the specified reset delay
period (tD). When the reset delay has elapsed, the RESET pin transistions to high voltage (VOH).
The open-drain version requires an external pull-up resistor to hold the RESET pin high because the internal
MOSFET turns off causing RESET output to pull-up to the pull-up voltage. Connect the pull-up resistor to the
desired interface voltage logic. RESET can be pulled up to any voltage up to maximum voltage independent
of the VDD voltage. To ensure proper voltage levels, take care when choosing the pull-up resistor values.
The pull-up resistor value is determined by VOL, the output capacitive loading, and the output leakage current
(Ilkg(OD)).
The push-pull variant does not require an external pull-up resistor.
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
8.3.5.2 RESET Output, Active-High
RESET remains logic low (deasserted) as long as VDD is above the positive threshold (VIT+). If VDD falls below
the negative threshold (VIT–), then reset is asserted and RESET transistions to logic high (VOH).
When VDD rises above VIT+, the delay circuit holds RESET active and logic high for the specified reset delay
period (tD). When the reset delay has elapsed the RESET pin transistions to low voltage (VOL).
8.4 Device Functional Modes
Table 8-1 summarizes the various functional modes of the device.
Table 8-1. Truth Table
VDD
(1)
MR (X2SON package only)
RESET (Active-High)
RESET(Active-Low)
VDD < VPOR
N/A
Undefined
Undefined
VPOR < VDD < VIT– (1)
N/A
H
L
VDD ≥ VIT–
L
H
L
VDD ≥ VIT–
H
L
H
When VDD falls below VDD(MIN), output reset is held asserted until VDD falls below VPOR.
8.4.1 Normal Operation (VDD > VDD(min))
When VDD voltage is greater than VDD(min), the reset signal is determined by the voltage on the VDD pin with
respect to the trip point (VIT–) and the MR pin voltage (X2SON package only).
8.4.2 VDD Between VPOR and VDD(min)
When the voltage on VDD is less than the VDD(min) voltage and greater than the power-on-reset voltage (VPOR),
the reset signal is asserted.
8.4.3 Below Power-On-Reset (VDD < VPOR)
When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the
asserted output low or high and reset voltage level is undefined.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
19
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLV803E, TLV809E, and TLV810E devices are used for voltage monitoring. These devices have only three
pins: VDD, GND, and RESET (or RESET for TLV810E). There are at the most two external components: a
capacitor on the VDD pin and a pull-up resistor on the RESET/RESET to VDD or another pull-up voltage for
the open-drain variants. The design involves choosing the device with the desired voltage threshold and output
topology and adding these components, if needed, as explained in the following sections.
9.2 Typical Application - Voltage Rail Monitoring
A typical application for TLV803E, TLV809E, and TLV810E devices is voltage rail monitoring. This rail can be the
input power supply or the output of an LDO or DC/DC converter. Figure 9-1 shows the TLV803EA29 monitoring
the supply rail for a DSP, FPGA, or ASIC. This rail is at 3.3 V and generated by an LDO with an input power
supply of 5 V. The supervisor is needed to make sure that the supply to the MCU/ASIC/FPGA/DSP is above
a certain voltage threshold. If the supply voltage drops below a certain threshold, supervisor generates a reset
output to indicate to the MCU that the supply is going down so that the MCU can take actions to save register
data before supply enters brown-out conditions.
LDO
5V
IN
3.3 V
OUT
10 kŸ
VDD
RESET
TLV803E
GND
VDD
FPGA, ASIC,
DSP
RESET
GND
Figure 9-1. The Output of LDO Powering the MCU is Monitored by the TLV803EA29
9.2.1 Design Requirements
This design monitors a 3.3-V rail and flags an undervoltage fault at the RESET output when supply rail falls
approximately 12% below the nominal rail voltage. The TLV803E device has an open-drain output topology so
an external pull-up resistor is required and is calculated to ensure that VOL does not exceed max limit given the
IRESET/RESET spec of ±5 mA is not violated at the expected supply voltage. Section 7.5 table provides 500 µA
Isink for 1.7 V VDD, which is the closest voltage to this design example. Using 500 µA of Isink and 300 mV
max VOL, gives us 5.36kΩ for the external pull-up resistor. Any value greater than 5.36kΩ would ensure that VOL
will not exceed 300 mV max specification. If you are using the TLV809E device variant, no pull-up resistor is
required because TLV809E has push-pull output topology.
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
9.2.2 Detailed Design Procedure
Select the TLV803EA29DBZR to satisfy the voltage threshold requirement for 3.3-V rail monitoring. As
mentioned in Table 12-1, the TLV803EA29DBZR triggers an undervoltage fault at the RESET output when
VDD falls below VIT- which is 2.93 V for this device variant. Place a pull-up resistor on RESET to VDD to satisfy
the output logic requirement while not violating the IRESET recommended limit.
9.2.3 Application Curves
Figure 9-2 and Figure 9-3 show the TLV803EA29 functionality. In Figure 9-2, the VDD supply voltage drops
from 30% above VIT- = 3.8 V to 10% below VIT- = 2.6 V with a 0.1-µF capacitor on VDD. The RESET output
is connected to VDD through the pull-up resistor so when the VDD supply voltage drops. The RESET output
discharges down to the VDD supply voltage through the pull-up resistor and RESET pin capacitance. Once the
high-to-low propagation delay tPD_HL expires, the internal MOSFET turns on and asserts RESET to logic low.
Note that tPD_HL varies with VDD specifically on how much VDD drops and how quickly in addition to the VDD
and RESET pin capacitances. In Figure 9-3, VDD rises from 2 V to 4 V and the RESET output deasserts to logic
high after the reset delay time (tD) expires.
VDD
VDD
Propagation Delay from VDD falling below VIT- to Reset
(tPD_HL) = 25 µs
Reset Delay (tD) = 200 ms
RESET
RESET
Figure 9-2. Propagation Delay when Fault Occurs
after VDD Falls Below VIT- (TLV803EA29 No
Load) (1) (2)
Figure 9-3. RESET Delay when Returning from
Fault after VDD Rises Above VIT+ (TLV803EA29)
1. Typical tPD_HL= 30 µs for VDD falling from (VIT+ + 30%) to (VIT- - 10%).
2. VDD does not fall all the way to 0 V so RESET momentarily discharges to VDD until tPD_HL expires.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
21
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
9.3 Typical Application - Overvoltage Monitoring
A typical use case for the push-pull active-high device variant TLV810E is overvoltage monitoring. The TLV810E
can monitor a power supply, a MCU power rail, or a battery during charging for example. The VDD pin monitors
the voltage rail and once VDD rises above VIT+, the RESET output deactivates to logic low after the reset delay
time tD. If VDD falls below VIT-, the RESET output activates to logic high after the propagation delay (tPD_HL).
The voiltage thresholds and the reset delay time depends on the device variant. See Section 5 for device variant
naming nomenclature.
VDD
3V
Battery Charger
VDD
RESET
TLV810EA29
ENABLE
GND
GND
Figure 9-4. TLV810E Overvoltage Monitor Circuit for Battery Charger
9.3.1 Design Requirements
In this application design, the TLV810E device is monitoring a 3 V battery connected to a battery charger. The
battery charger turns on when the battery voltage is below 2.93 V and turns off once the battery charges to
2.96 V and remains above 2.96 V for at least 200 ms. The design must be low power and not consume more
than 500 nA typical.
9.3.2 Detailed Design Procedure
Select the TLV810EA29 to accomplish this design. The TLV810EA29 is a push-pull active-high device with a
VIT- = 2.9 V and VIT+ = 2.9 + 1.2% = 2.93 V. Because the device is a push-pull output and the device threshold
meets the design requirements, no external resistors are needed. The TLV810EA29 device variant comes with
200 ms reset delay time meaning VDD must be above VIT+ for at least 200 ms for the RESET output to
transistion to logic low to turn off the battery charger. This device meets the low power requirement because the
TLV810E only consumes 250 nA typical.
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
10 Power Supply Recommendations
These devices are designed to operate from an input supply range of 1.7 V to 6 V. An input supply capacitor
is recommended between the VDD pin and GND pin. If the voltage supply that provides power to VDD is
susceptible to any large voltage transient that can exceed VDD maximum, the user must take additional
precautions.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
23
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a minimum 0.1-µF ceramic capacitor as close to the VDD pin as possible. A pull-up resistor is required
for the open-drain output. Place the pull-up resistor on the RESET pin as close to the pin as possible.
11.2 Layout Example
GND
1
GND
CIN
VDD
RESET
RESET
2
RESET
RESET
3
VDD
(TLV803E, TLV809E)
(TLV810E)
R
pull-up
Figure 11-1. TLV803E, TLV809E, and TLV810E
SOT23 (DBZ) Layout Example
Pull-up resistor required for Open-Drain output
Pinout Option V
RESET
RESET
1
RESET (TLV803E, TLV809E)
RESET (TLV810E)
GND
Rpull-up
2
3
VDD
CIN
Pull-up resistor required for Open-Drain output
Figure 11-2. TLV803E, TLV809E, and TLV810E SOT23 (DBZ) V pinout Layout Example
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
Rpull-up
RESET
1
5
VDD
CIN
TIPAD
Gray
3
GND
MR
2
4
Top View
Pull-up resistor required for Open-Drain output
Connection between PAD and GND is optional
Figure 11-3. TLV803E, TLV809E, and TLV810E X2SON (DPW) Layout Example
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
25
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Table 12-1 shows how to decode the function of the device based on its part number. For example:
TLV803EA29DBZR is open-drain, active-low, 200 ms reset delay, 2.93 V threshold voltage, Pin 1 = GND,
SOT23-3 pin package, and large reel option.
Table 12-1 shows all the possible variants of the TLV80xE and TLV81xE. Refer to the orderable device
information table for the options available to order. Contact Texas Instruments for the details and availability
of devices not in the orderable device information table.
Table 12-1. Device Naming Convention
DESCRIPTION
Part Number
Reset Time Delay Option
Threshold Voltage Option
Pinout Indicator (DBZ Package Only)
Package Option
Reel
26
NOMENCLATURE
VALUE
TLV803E
Open-Drain, Active-Low
TLV809E
Push-Pull, Active-Low
TLV810E
Push-Pull, Active-High
A
200 ms
B
40 µs
C
10 ms
D
50 ms
F
400 ms
17
1.7 V
18
1.8 V
19
1.9 V
22
2.25 V
24
2.4 V
26
2.64 V
29
2.93 V
30
3.08 V
33
3.3 V
42
4.2 V
43
4.38 V
45
4.55 V
46
4.63 V
R
Pin 1 = RESET, Pin 2 = GND, Pin 3 = VDD
V
Pin 1 = RESET, Pin 2 = VDD, Pin 3 = GND
DBZ
SOT23-3 pin
DCK
SC70-3 pin
DPW
X2SON-5 pin
R
Large reel
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
www.ti.com
SLVSES2J – AUGUST 2018 – REVISED MAY 2021
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TLV803EA29EVM User Guide
• Texas Instruments, Voltage Supervisors (Reset ICs): Frequenctly Asked Questions (FAQs)
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV803E TLV809E TLV810E
27
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV803EA17DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IT
TLV803EA18DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IV
TLV803EA22DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
322A
TLV803EA24DCKR
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
34A
TLV803EA26DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
326A
TLV803EA26DCKR
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
32A
TLV803EA26DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IW
TLV803EA26RDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
36AR
TLV803EA29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
329A
TLV803EA29DCKR
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
39A
TLV803EA29DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IX
TLV803EA29RDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
39AR
TLV803EA30DCKR
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
30A
TLV803EA42RDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
3DAR
TLV803EA43DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
343A
TLV803EA43RDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
34AR
TLV803EA43VDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
34AV
TLV803EB26RDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
36BR
TLV803EB29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
329B
TLV803EB33VDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
3CBV
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
5-Nov-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV803EB42VDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
3DBV
TLV803EB46DCKR
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
36B
TLV803EC29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
329C
TLV803EC30DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
330C
TLV803EC43DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
343C
TLV803ED17DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IS
TLV803ED18DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IU
TLV803ED29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
329D
TLV803EF26DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
326F
TLV803EF29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
329F
TLV809EA22DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
922A
TLV809EA26DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
926A
TLV809EA26DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IZ
TLV809EA29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
929A
TLV809EA29DCKR
ACTIVE
SC70
DCK
3
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
99A
TLV809EA29DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
J1
TLV809EA30DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
930A
TLV809EA43DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
943A
TLV809EA45DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
945A
TLV809EA46DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
946A
TLV809EA46DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
J2
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
5-Nov-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV809EC26DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
926C
TLV809EC46DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
946C
TLV809ED29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
929D
TLV809EF30DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
930F
TLV810EA29DBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
029A
TLV810EA29DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
J3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
