TLV9101, TLV9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp
1 Features
3 Description
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The TLV910x family (TLV9101, TLV9102, and
TLV9104) is a family of 16-V general purpose
operational amplifiers. This family offers excellent DC
precision and AC performance, including rail-to-rail
input/output, low offset (±300 µV, typ), low offset drift
(±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Rail-to-rail input and output
Wide bandwidth: 1.1-MHz GBW
Low quiescent current: 120 µA per amplifier
Low offset voltage: ±300 µV
Low offset voltage drift: ±0.6 µV/°C
Low noise: 28 nV/√Hz at 10 kHz
High common-mode rejection: 110 dB
Low bias current: ±10 pA
High slew rate: 4.5 V/µs
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: 77 dB at 1.8 GHz
2 Applications
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Optical modules
Portable test and measurement
Macro remote radio unit (RRU)
Baseband unit (BBU)
Appliances
Wide differential and common-mode input-voltage
range, high output current (±80 mA, typ), high slew
rate (4.5 V/µs, typ), low power operation (115 µA,
typ) and shutdown functionality make the TLV910x
a robust, low-power, high-performance operational
amplifier for industrial applications.
The TLV910x family of op amps is available in microsize packages, as well as standard packages, and is
specified from –40°C to 125°C.
Device Information
PART NUMBER (1)
TLV9101
RG
RF
R1
VOUT
VIN
TLV9102
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
TLV910x in a Single-Pole, Low-Pass Filter
TLV9104
(1)
(2)
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOT-553 (5)(2)
1.60 mm × 1.20 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (8)
2.90 mm × 1.60 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
WSON (8)
2.00 mm × 2.00 mm
X2QFN (10)
1.50 mm × 1.50 mm
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
WQFN (16)
3.00 mm × 3.00 mm
X2QFN (14)
2.00 mm × 2.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
This package is preview only.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9101, TLV9102, TLV9104
www.ti.com
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings ..................................... 10
6.2 ESD Ratings ............................................................ 10
6.3 Recommended Operating Conditions ......................10
6.4 Thermal Information for Single Channel .................. 10
6.5 Thermal Information for Dual Channel ..................... 11
6.6 Thermal Information for Quad Channel ....................11
6.7 Electrical Characteristics ..........................................12
6.8 Typical Characteristics.............................................. 15
7 Detailed Description......................................................23
7.1 Overview................................................................... 23
7.2 Functional Block Diagram......................................... 23
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................31
8 Application and Implementation ................................. 32
8.1 Application Information............................................. 32
8.2 Typical Applications.................................................. 32
9 Power Supply Recommendations................................34
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................37
11.1 Device Support........................................................37
11.2 Documentation Support.......................................... 37
11.3 Receiving Notification of Documentation Updates.. 37
11.4 Support Resources................................................. 37
11.5 Trademarks............................................................. 37
11.6 Electrostatic Discharge Caution.............................. 37
11.7 Glossary.................................................................. 37
12 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2021) to Revision E (August 2021)
Page
• Removed preview notation from TLV9102 VSSOP (8) package from Device Information table........................ 1
• Removed preview notation from TLV9102 VSSOP-8 (DGK) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview note and added thermal data for VSSOP-8 (DGK) package in Thermal Information for Dual
Channel. ...........................................................................................................................................................11
• Added clarifying statement regarding logic low signal for SHDN pin in the Shutdown section ........................30
• Corrected statement on shutdown enable and disable times in the Shutdown section from 30 μs and 3 μs to
11 μs and 2.5 μs, respectively, to match the Electrical Characteristics section................................................ 30
Changes from Revision C (May 2020) to Revision D (June 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Removed preview notation from TLV9104 SOIC (14) package from Device Information table.......................... 1
• Removed preview notation from TLV9104 TSSOP (14) package from Device Information table...................... 1
• Removed preview notation from TLV9102 SOT-23 (8) package from Device Information table........................ 1
• Removed preview notation from TLV9104 WQFN (16) package from Device Information table........................1
• Removed preview notation from TLV9101 DBV package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Adjusted DRL pinout in the Pin Configuration and Functions section................................................................ 4
• Removed preview notation from TLV9101 DCK package (SC70) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview notation from TLV9101S DBV package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Clarified shutdown notation in the Pin Configuration and Functions section...................................................... 4
• Removed preview notation from TLV9102 DDF package (SOT-23-8) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview notation from TLV9104 SOIC (D) and TSSOP (PW) packages in the Pin Configuration and
Functions section................................................................................................................................................4
• Removed preview notation from TLV9104 X2QFN (RUC) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
2
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Product Folder Links: TLV9101 TLV9102 TLV9104
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TLV9101, TLV9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
Removed preview notation from TLV9104 WQFN (RTE) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed preview notation from TLV9104S WQFN (RTE) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed Table of Graphs from the Specifications section.............................................................................. 10
Removed preview note from WQFN (RTE) package in thermal information for quad channel........................11
Removed Related Links section from the Device and Documentation Support section...................................37
Changes from Revision B (May 2020) to Revision C (May 2020)
Page
• Removed preview notation from TLV9102 VSSOP (10) package from Device Information table...................... 1
• Removed preview notation from TLV9102 X2QFN (10) package from Device Information table.......................1
• Removed preview notation from TLV9102 DGS package (VSSOP) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview notation from TLV9102 RUG package (X2QFN) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Changes from Revision A (April 2019) to Revision B (May 2020)
Page
• Changed the TLV9101 and TLV9104 device statuses from Advance Information to Production Data ..............1
• Removed preview notation from TLV9101 SOT-23 (5) package from Device Information table........................ 1
• Removed preview notation from TLV9101 SOT-23 (6) package from Device Information table........................ 1
• Removed preview notation from TLV9101 SC70 (5) package from Device Information table............................1
• Removed preview notation from TLV9102 TSSOP (8) package from Device Information table........................ 1
• Removed preview notation from TLV9102 WSON (8) package from Device Information table......................... 1
• Removed preview notation from TLV9102 DSG package (WSON) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Added SHUTDOWN to Electrical Characteristics ............................................................................................12
• Added Packages With an Exposed Thermal Pad to the Feature Description ................................................. 30
Changes from Revision * (February 2019) to Revision A (April 2019)
Page
• Changed the TLV9102 device status from Advance Information to Production Data ........................................1
• Removed preview notation from TLV9102 SOIC (8) package from Device Information table............................ 1
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
Figure 5-1. TLV9101 DBV Package
5-Pin SOT-23
Top View
A.
Package is preview only.
Figure 5-2. TLV9101 DCK and DRL Package(A)
5-Pin SC70 and SOT-553
Top View
Table 5-1. Pin Functions: TLV9101
PIN
NAME
DBV
DCK and DRL
+IN
3
1
–IN
4
OUT
1
V+
V–
I/O
DESCRIPTION
I
Noninverting input
3
I
Inverting input
4
O
Output
5
5
—
Positive (highest) power supply
2
2
—
Negative (lowest) power supply
OUT
1
6
V+
V–
2
5
SHDN
+IN
3
4
–IN
Not to scale
Figure 5-3. TLV9101S DBV Package
6-Pin SOT-23
Top View
Table 5-2. Pin Functions: TLV9101S
PIN
NAME
4
NO.
IN+
3
IN–
OUT
I/O
DESCRIPTION
I
Noninverting input
4
I
Inverting input
1
O
Output
SHDN
5
I
Shutdown: low = amplifier enabled, high = amplifier disabled. See Section
7.3.10 for more information.
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Figure 5-4. TLV9102 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23, TSSOP, and VSSOP
Top View
Not to scale
A.
Connect thermal pad to V–. See Section 7.3.9 for more
information.
Figure 5-5. TLV9102 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3. Pin Functions: TLV9102
PIN
NAME
NO.
I/O
DESCRIPTION
IN1+
3
I
Noninverting input, channel 1
IN1–
2
I
Inverting input, channel 1
IN2+
5
I
Noninverting input, channel 2
IN2–
6
I
Inverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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IN1+
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
1
10
V+
IN1–
2
9
OUT2
IN1+
3
8
IN2–
V–
4
7
IN2+
SHDN1
5
6
SHDN2
V–
1
9
IN1–
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
5
10
OUT1
Not to scale
Figure 5-6. TLV9102S DGS Package
10-Pin VSSOP
Top View
IN2–
Not to scale
Figure 5-7. TLV9102S RUG Package
10-Pin X2QFN
Top View
Table 5-4. Pin Functions: TLV9102S
PIN
NAME
6
I/O
DESCRIPTION
VSSOP
X2QFN
IN1+
3
10
I
Noninverting input, channel 1
IN1–
2
9
I
Inverting input, channel 1
IN2+
7
4
I
Noninverting input, channel 2
IN2–
8
5
I
Inverting input, channel 2
OUT1
1
8
O
Output, channel 1
OUT2
9
6
O
Output, channel 2
SHDN1
5
2
I
Shutdown, channel 1: low = amplifier enabled, high = amplifier
disabled. See Section 7.3.10 for more information.
SHDN2
6
3
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier
disabled. See Section 7.3.10 for more information.
V+
10
7
—
Positive (highest) power supply
V–
4
1
—
Negative (lowest) power supply
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IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN1+
1
V+
2
IN4±
13
13
2
OUT4
IN1±
14
OUT4
OUT1
14
15
1
IN1±
OUT1
16
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
8
OUT3
IN2±
4
8
7
OUT3
OUT2
Pad
7
3
NC
IN2+
6
IN3±
NC
9
5
6
OUT2
IN2±
Not to scale
Figure 5-8. TLV9104 D and PW Package
14-Pin SOIC and TSSOP
Top View
A.
Not to scale
Connect thermal pad to V–. See Section 7.3.9 for more
information.
IN4±
2
11
IN4+
V+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
OUT3
OUT2
7
IN1+
13
12
14
1
6
IN1±
OUT4
OUT1
Figure 5-9. TLV9104 RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Not to scale
Figure 5-10. TLV9104 RUC Package
14-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-5. Pin Functions: TLV9104
PIN
I/O
DESCRIPTION
SOIC and
TSSOP
WQFN
X2QFN
IN1+
3
1
2
I
Noninverting input, channel 1
IN1–
2
16
1
I
Inverting input, channel 1
IN2+
5
3
4
I
Noninverting input, channel 2
IN2–
6
4
5
I
Inverting input, channel 2
NAME
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Table 5-5. Pin Functions: TLV9104 (continued)
PIN
NAME
IN3+
8
I/O
DESCRIPTION
SOIC and
TSSOP
WQFN
X2QFN
10
10
9
I
Noninverting input, channel 3
IN3–
9
9
8
I
Inverting input, channel 3
IN4+
12
12
11
I
Noninverting input, channel 4
IN4–
13
13
12
I
Inverting input, channel 4
NC
—
6, 7
—
—
Do not connect
OUT1
1
15
14
O
Output, channel 1
OUT2
7
5
6
O
Output, channel 2
OUT3
8
8
7
O
Output, channel 3
OUT4
14
14
13
O
Output, channel 4
V+
4
2
3
—
Positive (highest) power supply
V–
11
11
10
—
Negative (lowest) power supply
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IN1+
1
V+
2
IN1–
OUT1
OUT4
IN4–
16
15
14
13
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
12
IN4+
11
V–
10
IN3+
9
IN3–
Thermal
A.
6
7
8
SHDN34
OUT3
4
SHDN12
IN2–
Pad
5
3
OUT2
IN2+
Not to scale
Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-11. TLV9104S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6. Pin Functions: TLV9104S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
SHDN12
6
I
Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers
disabled. See Section 7.3.10 for more information.
SHDN34
7
I
Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers
disabled. See Section 7.3.10 for more information.
V+
2
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX
0
20
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode
voltage(3)
Differential voltage(3)
Signal input pins
VS + 0.2
Current(3)
Shutdown pin voltage
Output short-circuit(2)
10
mA
V–
V+
V
150
°C
150
°C
150
°C
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
–10
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to ground, one amplifier per package.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
2.7
16
V
Input voltage range
(V–) – 0.2
(V+) + 0.2
V
VIH
High level input voltage at shutdown pin (amplifier disabled)
(V–) + 1.1
V+
V
VIL
Low level input voltage at shutdown pin (amplifier enabled)
V–
(V–) + 0.2
V
TA
Specified temperature
–40
125
°C
VS
Supply voltage, (V+) – (V–)
VI
UNIT
6.4 Thermal Information for Single Channel
TLV9101, TLV9101S
DBV
(SOT-23)
THERMAL METRIC(1)
DCK
(SC70)
DRL(2)
(SOT-553)
UNIT
5 PINS
6 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
192.2
174.6
204.7
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
113.7
113.5
116.6
TBD
°C/W
RθJB
Junction-to-board thermal resistance
60.6
55.9
51.9
TBD
°C/W
ψJT
Junction-to-top characterization parameter
37.4
39.7
24.9
TBD
°C/W
ψJB
Junction-to-board characterization parameter
60.4
55.7
51.6
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
TBD
°C/W
(1)
10
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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(2)
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
This package option is preview for TLV9101.
6.5 Thermal Information for Dual Channel
TLV9102, TLV9102S
THERMAL
METRIC(1)
D
(SOIC)
DDF
(SOT-23-8)
DGK
(VSSOP)
DGS
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
RUG
(X2QFN)
UNIT
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient
thermal resistance
138.7
150.4
189.3
152.2
81.6
188.4
149.6
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
78.7
85.6
75.8
67.3
101.6
77.1
58.3
°C/W
RθJB
Junction-to-board thermal
resistance
82.2
70.0
111.0
95.5
48.3
119.1
77.7
°C/W
ψJT
Junction-to-top
characterization
parameter
27.8
8.1
15.4
67.9
6.0
14.2
1.3
°C/W
ψJB
Junction-to-board
characterization
parameter
81.4
69.6
109.3
94.3
48.3
117.4
77.5
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
22.8
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
TLV9104, TLV9104S
THERMAL
METRIC(1)
D
(SOIC)
PW
(TSSOP)
RTE
(WQFN)
RUC
(WQFN)
UNIT
14 PINS
14 PINS
16 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
105.2
134.7
53.5
143.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.2
55.0
58.3
46.4
°C/W
RθJB
Junction-to-board thermal resistance
61.1
79.0
28.6
81.8
°C/W
ψJT
Junction-to-top characterization parameter
21.4
9.2
2.1
1.0
°C/W
ψJB
Junction-to-board characterization parameter
60.7
78.1
28.6
81.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
12.6
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
Input offset voltage versus
power supply
VCM = V–
Channel separation
f = 0 Hz
±0.3
VCM = V–
TA = –40°C to 125°C
±1.5
±1.75
TA = –40°C to 125°C
±0.6
TA = –40°C to 125°C
±0.1
mV
µV/℃
±0.7
5
µV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±10
pA
IOS
Input offset current
±5
pA
NOISE
EN
Input voltage noise
eN
Input voltage noise density
iN
Input current noise
f = 0.1 Hz to 10 Hz
6
µVPP
1
µVRMS
f = 1 kHz
30
f = 10 kHz
28
f = 1 kHz
2
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) – 0.2
VS = 16 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair)
CMRR
Common-mode rejection ratio
VS = 4 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair)
VS = 2.7 – 16 V, (V+) – 1 V < VCM
< (V+) + 0.1 V (Aux input pair)
(V+) + 0.2
90
110
75
95
V
dB
TA = –40°C to 125°C
(V+) – 2 V < VCM < (V+) – 1 V
80
See Offset Voltage (Transition Region) in the Typical
Characteristics section
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
12
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100 || 3
MΩ || pF
6 || 1
TΩ || pF
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
115
135
dB
104
125
dB
1.1
MHz
4.5
V/µs
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
VS = 16 V, G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
4
To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
2
To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
5
To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
THD+N
Phase margin
G = +1, RL = 10 kΩ, CL = 20 pF
Overload recovery time
VIN × gain > VS
Total harmonic distortion +
noise
VS = 16 V, VO = 1 VRMS, G = -1, f = 1 kHz
µs
3
60
°
600
ns
0.0028%
OUTPUT
VS = 16 V, RL = no load
Voltage output swing from rail
ISC
Positive and negative rail
headroom
3
VS = 16 V, RL = 10 kΩ
45
60
VS = 16 V, RL = 2 kΩ
200
300
VS = 2.7 V, RL = no load
1
VS = 2.7 V, RL = 10 kΩ
5
20
VS = 2.7 V, RL = 2 kΩ
25
50
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output impedance
±80
mV
mA
See Small-Signal Overshoot vs Capacitive Load in the Typical
Characteristics section
f = 1 MHz, IO = 0 A
600
Ω
POWER SUPPLY
IQ
Quiescent current per amplifier
IO = 0 A
115
TA = –40°C to 125°C
150
160
µA
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
30
UNIT
SHUTDOWN
IQSD
Quiescent current per amplifier
VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V+
ZSHDN
Output impedance during
shutdown
VS = 2.7 V to 16 V, amplifier disabled, SHDN = V+
VIH
Logic high threshold voltage
(amplifier disabled)
For valid input high, the SHDN pin voltage should be greater than the
maximum threshold but less than or equal to V+
VIL
Logic low threshold voltage
(amplifier enabled)
For valid input low, the SHDN pin voltage should be less than the
minimum threshold but greater than or equal to V–
(1)
10 || 12
(V–) + 0.8
(V–) + 0.2
GΩ || pF
(V–) + 1.1
V
(V–) + 0.8
V
tON
Amplifier enable time
11
µs
tOFF
Amplifier disable time (1)
VCM = V–, VO = VS / 2
2.5
µs
SHDN pin input bias current
(per pin)
VS = 2.7 V to 16 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V
500
VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
150
(1)
14
G = +1, VCM = V–, VO = 0.1 × VS / 2
µA
nA
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6.8 Typical Characteristics
25%
25%
20%
20%
Population (%)
15%
10%
15%
10%
5%
Offset Voltage (PV)
Offset Voltage Drift (PV/qC)
Distribution from 13, 481 amplifiers; TA = 25°C
Distribution from 175 amplifiers
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
D001
0.4
0
0.2
1200
900
1050
750
600
450
300
0
150
-150
-300
-450
-600
-750
-900
-1050
-1200
0
5%
0
Population (%)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
D002
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
1000
800
800
600
Offset Voltage (µV)
Offset Voltage (µV)
600
400
200
0
-200
-400
400
200
0
-200
-400
-600
-600
-800
-1000
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-800
-40
140
VCM = V+
Each color represents one sample device.
20
40
60
80
Temperature (°C)
100
120
140
D004
Figure 6-4. Offset Voltage vs Temperature
800
800
600
600
400
400
Offset Voltage (µV)
Offset Voltage (µV)
0
VCM = V–
Each color represents one sample device.
Figure 6-3. Offset Voltage vs Temperature
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-8
-20
D003
-800
-6
-4
-2
0
2
4
Common Mode Voltage (V)
6
8
4
4.5
5
D005
TA = 25°C
Each color represents one sample device.
Figure 6-5. Offset Voltage vs Common-Mode Voltage
5.5
6
6.5
7
Common Mode Voltage (V)
7.5
8
D005
TA = 25°C
Each color represents one sample device.
Figure 6-6. Offset Voltage vs Common-Mode Voltage
(Transition Region)
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6.8 Typical Characteristics (continued)
1000
800
800
600
600
400
400
200
Offset Voltage (µV)
200
0
-200
-400
0
-200
-400
-600
-600
-800
-800
-1000
-1000
-8
-6
-4
-2
0
2
4
Common Mode Voltage (V)
6
-1200
-8
8
-6
-4
D006
-2
0
2
4
Common Mode Voltage (V)
8
D007
TA = –40°C
Each color represents one sample device.
TA = 125°C
Each color represents one sample device.
Figure 6-8. Offset Voltage vs Common-Mode Voltage
Figure 6-7. Offset Voltage vs Common-Mode Voltage
750
100
150
Gain
Phase
600
80
450
300
150
Gain (dB)
Offset Voltage (µV)
6
0
-150
-300
125
60
100
40
75
20
50
0
25
-450
Phase (q)
Offset Voltage (µV)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
-600
-750
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
-20
100
0
1k
10k
100k
Frequency (Hz)
D008
VCM = V–
Each color represents one sample device.
Figure 6-10. Open-Loop Gain and Phase vs Frequency
3
70
Closed-Loop Gain (dB)
50
40
Input Bias and Offset Current (pA)
G=1
G = -1
G = 10
G = 100
G = 1000
60
30
20
10
0
-10
-20
1k
10k
100k
Frequency (Hz)
2.5
2
1M
IB
IB+
IOS
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-8
-6
-4
C001
Figure 6-11. Closed-Loop Gain and Phase vs Frequency
16
C002
CLOAD = 15 pF
Figure 6-9. Offset Voltage vs Power Supply
-30
100
1M
-2
0
2
4
Common Mode Voltage (V)
6
8
D010
Figure 6-12. Input Bias Current vs Common-Mode Voltage
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SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
V+
IB
IB+
IOS
280
240
Output Voltage (V)
Input Bias and Offset Current (pA)
320
200
160
120
80
40
0
-40
-40
V+
1V
V+
2V
V+
3V
V+
4V
V+
5V
V+
6V
V+
7V
V+
8V
V+
9V
V+
-20
0
20
40
60
80
Temperature (°C)
100
120
0
20
30
40
50
60
70
Output Current (mA)
80
90
100
D012
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
5
-40°C
25°C
85°C
125°C
V +9V
4
Output Voltage (V)
V +8V
-40qC
4.5
V +7V
V +6V
V +5V
V +4V
V +3V
3.5
25qC
125qC
3
2.5
85qC
2
1.5
V +2V
1
V +1V
0.5
0
V
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
0
100
100
4
90
PSRR and CMRR (dB)
110
3.5
85qC
125qC
2
1.5
1
25qC
0.5
20
30
40
50
60
70
Output Current (mA)
40
50
60
70
Output Current (mA)
80
90
100
D013
PSRR+
PSRRCMRR
80
70
60
50
40
30
20
-40qC
10
0
10
30
Figure 6-16. Output Voltage Swing vs Output Current (Sourcing)
5
2.5
20
VS = 5 V, RL connected to V–
4.5
3
10
D012
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
Output Voltage (V)
10
D011
V + 10 V
Output Voltage (V)
10 V
140
Figure 6-13. Input Bias Current vs Temperature
0
-40°C
25°C
85°C
125°C
80
90
100
0
100
1k
10k
100k
Frequency (Hz)
1M
D013
10M
C003
VS = 5 V, RL connected to V+
Figure 6-17. Output Voltage Swing vs Output Current (Sinking)
Figure 6-18. CMRR and PSRR vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
120
145
VS = 16 V
VS = 4 V
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
124
116
112
108
104
100
96
92
88
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
144
143
142
141
140
139
138
137
136
135
-40
140
-20
0
20
D015
Input Voltage Noise Spectral Density (nV/rHz)
Voltage (1uV/div)
Time (1s/Div)
Figure 6-21. 0.1-Hz to 10-Hz Noise
D016
110
100
90
80
70
60
50
40
30
20
10
0
10
100
1k
Frequency (Hz)
10k
100k
C017
Figure 6-22. Input Voltage Noise Spectral Density vs Frequency
-40
-30
RL = 10 k:
RL = 2 k:
RL = 600 :
RL = 128 :
-40
-50
THD+N (dB)
THD+N (dB)
140
120
C015
-70
-80
-60
-70
-90
-80
-100
-90
-110
100
1k
Frequency (Hz)
RL = 10 k
RL = 2 k
RL = 549
RL = 128
-100
0.001
10k
0.01
C012
BW = 80 kHz, VOUT = 3.5 VRMS
Figure 6-23. THD+N Ratio vs Frequency
18
120
Figure 6-20. PSRR vs Temperature (dB)
Figure 6-19. CMRR vs Temperature (dB)
-60
100
f = 0 Hz
f = 0 Hz
-50
40
60
80
Temperature (°C)
0.1
Amplitude (VRMS)
1
8
C023
BW = 80 kHz, f = 1 kHz
Figure 6-24. THD+N vs Output Amplitude
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6.8 Typical Characteristics (continued)
130
127.5
125
125
120
122.5
Quiescent current (µA)
Quiescent current (µA)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
115
110
105
100
95
120
117.5
115
112.5
110
107.5
90
105
85
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
102.5
-40
Figure 6-25. Quiescent Current per Channel vs Supply Voltage
20
40
60
80
Temperature (°C)
100
120
140
D022
780
Open Loop Output Impedance (:)
VS = 16 V
VS = 4 V
144
Open Loop Voltage Gain (dB)
0
Figure 6-26. Quiescent Current per Channel vs Temperature
146
142
140
138
136
134
132
130
128
126
124
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
720
660
600
540
480
420
360
300
240
180
120
100
140
1k
10k
100k
Frequency (Hz)
D023
Figure 6-27. Open-Loop Voltage Gain vs Temperature (dB)
33
55
30
50
27
45
24
40
21
18
15
12
1M
10M
C013
Figure 6-28. Open-Loop Output Impedance vs Frequency
Overshoot (%)
Overshoot (%)
-20
D021
35
30
25
20
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
9
6
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
15
10
3
5
0
40
80
120
160 200 240
Cap Load (pF)
280
320
360
0
40
80
120
C007
G = –1, 100-mV output step
Figure 6-29. Small-Signal Overshoot vs Capacitive Load
160 200 240
Cap Load (pF)
280
320
360
C008
G = 1, 100-mV output step
Figure 6-30. Small-Signal Overshoot vs Capacitive Load
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
64
Input
Output
60
56
Amplitude (2V/div)
Phase Margin (q)
52
48
44
40
36
32
28
24
20
0
100
200
300
400 500 600
Cap Load (pF)
700
800
Time (20µs/Div)
900 1000
C016
C009
G = –1, 100-mV output step
Figure 6-32. No Phase Reversal
Voltage (5V/div)
Voltage (5V/div)
Figure 6-31. Small-Signal Overshoot vs Capacitive Load
Input
Output
Input
Output
Time (500ns/div)
Time (500ns/div)
C018
C018
G = –10
G = –10
Figure 6-33. Positive Overload Recovery
Figure 6-34. Negative Overload Recovery
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Input
Output
Time (1µs/div)
Time (2Ps/div)
C011
C010
CL = 20 pF, G = 1, 20-mV step response
Figure 6-35. Small-Signal Step Response
20
RL = 1 kΩ, CL = 20 pF, G = –1, 10-mV step response
Figure 6-36. Small-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Input
Output
Time (1µs/div)
Time (1µs/div)
C005
C005
CL = 20 pF, G = 1
CL = 20 pF, G = 1
Figure 6-37. Large-Signal Step Response (Falling)
Figure 6-38. Large-Signal Step Response (Rising)
Large Signal Step Response (2V/div)
100
Short-Circuit Current (mA)
80
Input
Output
60
40
20
0
Sourcing
Sinking
-20
-40
-60
-80
-100
-40
Time (2µs/div)
-20
0
C021
20
40
60
80
Temperature (°C)
100
120
140
D038
CL = 10 pF, G = –1
Figure 6-40. Short-Circuit Current vs Temperature
Figure 6-39. Large-Signal Step Response
-60
20
-70
Channel Seperation (dB)
Maximum Output Swing (V)
VS = 15 V
VS = 2.7 V
15
10
5
-80
-90
-100
-110
-120
0
1k
10k
100k
Frequency (Hz)
1M
10M
-130
100
1k
C020
Figure 6-41. Maximum Output Voltage vs Frequency
10k
100k
Frequency (Hz)
1M
10M
C014
Figure 6-42. Channel Separation vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 6-43. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The TLV910x family (TLV9101, TLV9102, and TLV9104) is a family of 16-V general purpose operational
amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±300 µV, typ), low offset drift (±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (4.5
V/µs), low power operation (120 µA, typ), and shutdown functionality make the TLV910x a robust, low-power,
high-performance operational amplifier for industrial applications.
7.2 Functional Block Diagram
V+
Reference
Current
V
IN+
V
INÛ
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
VÛ
(Ground)
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV910x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV910x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-1 shows the results of this testing on the TLV910x. Table 7-1 shows the EMIRR IN+ values for the TLV910x at
particular frequencies commonly encountered in real-world applications. Table 7-1 lists applications that can be
centered on or operated near the particular frequency shown. The EMI Rejection Ratio of Operational Amplifiers
application report contains detailed information on the topic of EMIRR performance as it relates to op amps and
is available for download from www.ti.com.
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 7-1. TLV910x EMIRR Testing
Table 7-1. TLV910x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
5 GHz
7.3.2 Phase Reversal Protection
The TLV910x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV910x is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-2.
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Amplitude (2V/div)
Input
Output
Time (20µs/Div)
C016
Figure 7-2. No Phase Reversal
7.3.3 Thermal Protection
16 V
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV910x is 150°C.
Exceeding this temperature causes damage to the device. The TLV910x has a thermal protection feature that
prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 7-3 shows an application example
for the TLV9101 that has significant self heating (154°C) because of its power dissipation (0.39 W). Thermal
calculations indicate that for an ambient temperature of 100°C, the device junction temperature must reach
154°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-3
shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer
so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the
thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor
RL.
3V
TA = 100°C
PD = 0.39W
0V
JA = 138.7°C/W
TJ = 138.7°C/W × 0.39W + 100°C
TJ = 154.1°C (expected)
Normal
Operation
Output
High-Z
150°C
IOUT = 30 mA
+
±
VIN
3V
+
RL
3V
100 Ÿ ±
Temperature
TLV9101
140ºC
Figure 7-3. Thermal Protection
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7.3.4 Capacitive Load and Stability
55
33
50
30
45
27
40
24
Overshoot (%)
Overshoot (%)
The TLV910x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-4 and Figure 7-5. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
35
30
25
21
18
15
12
20
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
15
10
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
9
6
3
5
0
40
80
120
160 200 240
Cap Load (pF)
280
320
0
360
40
80
120
C008
160 200 240
Cap Load (pF)
280
320
360
C007
Figure 7-5. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step, G = –1)
Figure 7-4. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step, G = 1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10
Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 7-6. This resistor significantly reduces
ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel
with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and
slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally
negligible at low output levels. A high capacitive load drive makes the TLV910x well suited for applications such
as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-6 uses an
isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for
increased phase margin.
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 7-6. Extending Capacitive Load Drive With the TLV9101
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7.3.5 Common-Mode Voltage Range
The TLV910x is a 16-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 7-7. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region,
typically (V+) –2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with
process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance
can be degraded compared to operation outside this region. To achieve best performance with the TLV910x
family, avoid this transition region when possible.
V+
INPMOS
PMOS
IN+
NMOS
NMOS
V-
Figure 7-7. Rail-to-Rail Input Stage
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7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but can involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV910x (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
±
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
TLV960x
±
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
VSS
+
±
±VS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent damage caused by turning
on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and
TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV910x is approximately 1 µs.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like the input offset voltage of an amplifier.
These deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage
this information to guardband their system, even when there is not a minimum or maximum specification in
Section 6.7.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1
-41
-31
1
-21
1
-1
1
1
+1
1
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,
or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ–σ to µ+σ).
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Depending on the specification, values listed in the typical column of Section 6.7 are represented in different
ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, gain bandwidth),
then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like
input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to
most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV910x,
the typical input voltage offset is 300 µV, so 68.2% of all TLV910x devices are expected to have an offset from
–300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV910x family has a maximum offset voltage of 1.5
mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI
assures that any unit with larger offset than 1.5 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance and can be an
option as a wide guardband to design a system around. In this case, the TLV910x family does not have a
maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.6 µV/°C in
Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When designing for
worst-case system conditions, this value can be used to estimate the worst possible offset across temperature
without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV910x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE), which feature
an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.3.10 Shutdown
The TLV910xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high. The amplifier
is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V+. The shutdown
pin circuitry includes a pulldown resistor, which will inherently pull the voltage of the pin to the negative supply
rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid
logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage
allowed at the SHDN pins is V+ or V– + 20 V, whichever is lower. Exceeding this voltage level will damage the
device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature can be used to greatly reduce the average current and extend battery life. The
typical enable time out of shutdown is 11 µs; disable time is 2.5 µs. When disabled, the output assumes a
high-impedance state. This architecture allows the TLV910xS family to operate as a gated amplifier, multiplexer,
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or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load
to midsupply (VS / 2) is required. If using the TLV910xS without a load, the resulting turnoff time significantly
increases.
7.4 Device Functional Modes
The TLV910x has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the TLV910x is 16 V (±8 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV910x family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz
bandwidth and high output drive. These features make the TLV910x a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 High Voltage Precision Comparator
Many different systems require controlled voltages across numerous system nodes to ensure robust operation.
A comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an
input voltage and providing an output when the input crosses this threshold.
The TLV910x family of op amps make excellent high voltage, precision comparators due to their robust input
stage, low typical offset, and high slew rate. Previous generation high-voltage op amps often use back-to-back
diodes across the inputs to prevent damage to the op amp which greatly limits these op amps to be used as
comparators, but the patented input stage of the TLV910x allows the device to have a wide differential voltage
between the inputs.
V+
+
VIN
VOUT
VTH
V+
R1
R2
Figure 8-1. Typical Comparator Application
8.2.1.1 Design Requirements
The primary objective is to design a 15-V precision comparator.
•
•
•
•
•
•
32
System supply voltage (V+): 15 V
Resistor 1 value: 100 kΩ
Resistor 2 value: 100 kΩ
Reference threshold voltage (VTH): 7.5 V
Input voltage range (VIN): 2.5 V – 12.5 V
Output voltage range (VOUT): 0 V – 15 V
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8.2.1.2 Detailed Design Procedure
This noninverting comparator circuit applies the input voltage (VIN) to the noninverting terminal of the op amp.
Two resistors (R1 and R2) divide the supply voltage (V+) to create a mid-supply threshold voltage (VTH) as
calculated in Equation 1. The circuit is shown in Figure 8-1. When VIN is less then VTH, the output voltage
transitions to the negative supply and equals the low-level output voltage. When VIN is greater than VTH, the
output voltage transitions to the positive supply and equals the high-level output voltage.
In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 7.5 V.
However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. The values of resistor 1 and
2 have also been selected to reduce power consumption, but these values can be further increased to reduce
power consumption, or reduced to improve noise performance.
VTH
R2
R1 R2
uV
(1)
8.2.1.3 Application Curve
16
Input
Output
14
12
Voltage (V)
10
8
6
4
2
0
-2
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
2
comp
Figure 8-2. Comparator Output Response to Input Voltage
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9 Power Supply Recommendations
The TLV910x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C.
CAUTION
Supply voltages larger than 20 V can permanently damage the device; see Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section
10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 10-1. Schematic Representation
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Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
V+
INPUT
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration
GND
GND
OUT
V-
GND
GND
OUTPUT A
Figure 10-3. Example Layout for SC70 (DCK) Package
GND
GND
V+
INPUT A
VGND
GND
INPUT B
OUTPUT B
GND
Figure 10-4. Example Layout for VSSOP-8 (DGK) Package
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GND
V+
GND
OUT A
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
GND
OUT B
- +
+ -
+IN A
V-
+IN B
GND
GND
GND
Figure 10-5. Example Layout for WSON-8 (DSG) Package
36
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Product Folder Links: TLV9101 TLV9102 TLV9104
TLV9101, TLV9102, TLV9104
www.ti.com
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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37
TLV9101, TLV9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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Product Folder Links: TLV9101 TLV9102 TLV9104
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV9101IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T91V
TLV9101IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1FO
TLV9101SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T91S
TLV9102IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T91F
TLV9102IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2HBT
TLV9102IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9102D
TLV9102IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T912
TLV9102IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9102P
TLV9102SIDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T910
TLV9102SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
HBF
TLV9104IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV9104D
TLV9104IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
(PTL91PW, TLV91PW)
TLV9104IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
TLV9104IRUCR
ACTIVE
QFN
RUC
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
FOF
TLV9104SIRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9104S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
T91RT
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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