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OPA858
SBOS629A – APRIL 2018 – REVISED JULY 2018
OPA858 5.5-GHz Gain Bandwidth Product, Gain of 7 V/V Stable, FET Input Amplifier
1 Features
3 Description
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The OPA858 is a wideband, low-noise, operational
amplifier with CMOS inputs for wideband
transimpedance and voltage amplifier applications.
When the device is configured as a transimpedance
amplifier (TIA), the 5.5-GHz gain bandwidth product
(GBWP) enables applications requiring high closedloop bandwidths at transimpedance gains in the tens
to hundreds of kΩs range.
High Gain Bandwidth Product: 5.5 GHz
Decompensated, Gain ≥ 7 V/V (Stable)
Ultra-Low Bias Current MOSFET Inputs: 10 pA
Low Input Voltage Noise: 2.5 nV/√Hz
Slew rate: 2000 V/µs
Low Input Capacitance:
– Common-Mode: 0.6 pF
– Differential: 0.2 pF
Wide Input Common-Mode Range:
– 1.4 V from Positive Supply
– Includes Negative Supply
2.5 VPP Output Swing in TIA Configuration
Supply Voltage Range: 3.3 V to 5.25 V
Quiescent Current: 20.5 mA
Available in 8-Pin WSON Package
Temperature Range: –40 to +125°C
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2 Applications
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High-Speed Transimpedance Amplifier
Laser Distance Measurement
Lidar Receivers
Level Transmitter (Optical)
Optical Time Domain Reflectometry (OTDR)
Distributed Temperature Sensing
3D Scanner
Time-of-Flight (ToF) Systems
Autonomous Driving Systems
spacer
High-Speed Time-of-Flight Receiver
The graph below demonstrates the bandwidth and
noise performance of the OPA858 as a function of
the photodiode capacitance when the amplifier is
configured as a TIA. The total noise is calculated over
a bandwidth range extending from DC to the
calculated f-3dB frequency on the left-hand scale. The
OPA858 package features a feedback pin (FB) that
simplifies the feedback network connection between
the input and the output.
The OPA858 is optimized for use in optical Time-ofFlight (ToF) systems like the one shown in the figure
below where the OPA858 is used with the TDC7201
time-to-digital converter. The OPA858 can be used in
high-resolution LIDAR systems with a high-speed
analog-to-digital converter (ADC) and a differential
output amplifier like the THS4541 or LMH5401 to
drive the ADC.
Device Information(1)
PART NUMBER
OPA858
PACKAGE
WSON (8)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Photodiode Capacitance vs. Bandwidth and Noise
CF
450
5V
TLV3501
±
+
3.5 V
OPA858
+
Stop 2
VREF
±
Start 2
Object
CF
RF
VBIAS
5V
TLV3501
±
TDC7201
(Time-toDigital
Converter)
+
3.5 V
+
OPA858
Stop 1
VREF
±
Start 1
Closed-loop Bandwidth, f -3dB (MHz)
Rx
Lens
110
RF
VBIAS
f-3dB , R F = 10 k:
f-3dB , R F = 20 k:
IRN , R F = 10 k:
IRN , R F = 20 k:
400
350
100
90
300
80
250
70
200
60
150
50
100
40
50
30
0
Tx
Lens
Pulsed Laser
Diode
MSP430
Controller
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
20
20
Integrated Input Referred Noise, I RN (nA RMS )
1
D209
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA858
SBOS629A – APRIL 2018 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics .............................................
8
Parameter Measurement Information ................ 14
9
Detailed Description ............................................ 15
8.1 Parameter Measurement Information ..................... 14
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 22
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 25
13 Device and Documentation Support ................. 27
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2018) to Revision A
•
2
Page
Changed device status from "Advance Information" to "Production Data" ........................................................................... 1
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SBOS629A – APRIL 2018 – REVISED JULY 2018
5 Device Comparison Table
DEVICE
INPUT TYPE
MINIMUM STABLE
GAIN
VOLTAGE NOISE
(nV/√Hz)
INPUT
CAPACITANCE (pF)
GAIN BANDWIDTH
(GHz)
OPA858
CMOS
7 V/V
2.5
0.8
5.5
OPA855
Bipolar
7 V/V
0.98
0.8
8
LMH6629
Bipolar
10 V/V
0.69
5.7
4
6 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
FB
1
NC
2
IN±
3
IN+
4
Thermal
Pad
8
PD
7
VS+
6
OUT
5
VS±
Not to scale
NC - no internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
FB
1
I
Feedback connection to output of amplifier
IN–
3
I
Inverting input
IN+
4
I
Noninverting input
NC
2
—
Do not connect
OUT
6
O
Amplifier output
PD
8
I
Power down connection. PD = logic low = power off mode; PD = logic high = normal
operation
VS–
5
—
Negative voltage supply
VS+
7
—
Positive voltage supply
—
Connect the thermal pad to VS–
Thermal pad
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SBOS629A – APRIL 2018 – REVISED JULY 2018
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VS
Total supply voltage (VS+ – VS–)
VIN+, VIN–
Input voltage
VID
Differential input voltage
VOUT
Output voltage
IIN
Continuous input current
±10
IOUT
Continuous output current (2)
±100
TJ
Junction temperature
150
TA
Operating free-air temperature
TSTG
Storage temperature
(1)
(2)
UNIT
5.5
(VS–) – 0.5
(VS+) + 0.5
V
1
(VS–) – 0.5
(VS+) + 0.5
mA
125
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
Total supply voltage (VS+ – VS–)
MIN
NOM
MAX
UNIT
3.3
5
5.25
V
7.4 Thermal Information
OPA858
THERMAL METRIC (1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
80.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
100
°C/W
RθJB
Junction-to-board thermal resistance
45
°C/W
ψJT
Junction-to-top characterization parameter
6.8
°C/W
ψJB
Junction-to-board characterization parameter
45.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
22.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS629A – APRIL 2018 – REVISED JULY 2018
7.5 Electrical Characteristics
VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
SSBW
Small-signal bandwidth
VOUT = 100 mVPP
1.2
GHz
C
LSBW
Large-signal bandwidth
VOUT = 2 VPP
600
MHz
C
GBWP
Gain-bandwidth product
5.5
GHz
C
130
MHz
C
2000
V/µs
C
Bandwidth for 0.1-dB flatness
SR
Slew rate (10% - 90%)
VOUT = 2-V step
tr
Rise time
VOUT = 100-mV step
0.3
ns
C
tf
Fall time
VOUT = 100-mV step
0.3
ns
C
Settling time to 0.1%
VOUT = 2-V step
8
ns
C
Settling time to 0.001%
VOUT = 2-V step
3000
ns
C
Overshoot or undershoot
VOUT = 2-V step
7%
Overdrive recovery
2x output overdrive (0.1% recovery)
200
f = 10 MHz, VOUT = 2 VPP
88
f = 100 MHz, VOUT = 2 VPP
64
f = 10 MHz, VOUT = 2 VPP
86
f = 100 MHz, VOUT = 2 VPP
68
C
ns
C
dBc
C
dBc
C
HD2
Second-order harmonic distortion
HD3
Third-order harmonic distortion
en
Input-referred voltage noise
f = 1 MHz
2.5
nV/√Hz
C
ZOUT
Closed-loop output impedance
f = 1 MHz
0.15
Ω
C
72
75
dB
A
–5
±0.8
DC PERFORMANCE
AOL
Open-loop voltage gain
VOS
Input offset voltage
TA = 25°C
ΔVOS/ΔT
Input offset voltage drift
TA = –40°C to +125°C
IBN, IBI
Input bias current
TA = 25°C
±0.4
IBOS
Input offset current
TA = 25°C
±0.01
CMRR
Common-mode rejection ratio
VCM = ±0.5 V, referenced to
midsupply
5
mV
A
µV/°C
B
5
pA
A
5
pA
A
90
dB
A
±2
70
INPUT
Common-mode input resistance
CCM
Common-mode input capacitance
Differential input resistance
CDIFF
Differential input capacitance
VIH
Common-mode input range (high)
CMRR > 66 dB, VS+ = 3.3 V
VIL
Common-mode input range (low)
CMRR > 66 dB, VS+ = 3.3 V
CMRR > 66 dB
VIH
Common-mode input range (high)
VIL
Common-mode input range (low)
TA = –40°C to +125°C, CMRR > 66
dB
VOH
Output voltage (high)
TA = 25°C, VS+ = 3.3 V
VOH
Output voltage (high)
VOL
Output voltage (low)
1.7
1
GΩ
C
0.62
pF
C
1
GΩ
C
0.2
pF
C
V
A
V
A
1.9
0
3.4
TA = –40°C to +125°C, CMRR > 66
dB
0.4
3.6
A
V
3.4
CMRR > 66 dB
0
0.4
A
V
0.35
B
B
OUTPUT
(1)
TA = 25°C
2.3
2.4
3.95
4.1
TA = –40°C to +125°C
3.9
TA = 25°C, VS+ = 3.3 V
1.05
V
V
1.15
V
A
A
B
A
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
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Electrical Characteristics (continued)
VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
VOL
Output voltage (low)
Linear output drive (sink and
source)
ISC
TEST CONDITIONS
MIN
TA = 25°C
TA = –40°C to +125°C
RL = 10 Ω, AOL > 60 dB
MAX
1.05
1.15
1.2
65
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 60 dB
Output short-circuit current
TYP
85
UNIT
V
80
TEST
LEVEL (1)
A
B
A
64
mA
B
105
mA
A
POWER SUPPLY
VS
Operating voltage
IQ
Quiescent current
VS+ = 5 V
3.3
V
A
18
20.5
5.25
24
mA
A
IQ
Quiescent current
VS+ = 3.3 V
IQ
Quiescent current
VS+ = 5.25 V
17.5
20
23.5
mA
A
18
21
24
mA
IQ
Quiescent current
TA = 125°C
A
24.5
mA
IQ
Quiescent current
TA = –40°C
B
18.5
mA
B
PSRR+
Positive power-supply rejection
ratio
74
84
PSRR–
Negative power-supply rejection
ratio
70
80
dB
A
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Enable voltage threshold
Amplifier ON above this voltage
V
A
1.5
1.8
V
A
Power-down quiescent current
70
140
µA
A
PD bias current
70
200
µA
A
13
ns
C
120
ns
C
Turnon time delay
Time to VOUT = 90% of final value
Turnoff time delay
6
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1
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SBOS629A – APRIL 2018 – REVISED JULY 2018
7.6 Typical Characteristics
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
3
4
0
0
Normalized Gain (dB)
Normalized Gain (dB)
2
-2
-4
-6
-8
-10
-12
1M
Gain = +7 V/V
Gain = +10 V/V
Gain = +20 V/V
Gain = 7 V/V
10M
-3
-6
-9
VS = 5 V
VS = 3.3 V
100M
Frequency (Hz)
1G
-12
1M
5G
10M
100M
Frequency (Hz)
D100
VOUT = 100 mVPP; see Figure 43 and Figure 44 for circuit
configuration
1G
5G
D102
VOUT = 100 mVPP
Figure 2. Small-Signal Frequency Response vs Supply
Voltage
Figure 1. Small-Signal Frequency Response vs Gain
2
3
1
0
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
-6
-9
10M
-2
-3
-4
-5
TA = 40qC
TA = 0qC
TA = 25qC
TA = 85qC
TA = 125qC
-6
RL = 200 :
RL = 400 :
RL = 100 :
-12
1M
-1
-7
100M
Frequency (Hz)
1G
-8
1M
5G
10M
100M
Frequency (Hz)
D103
VOUT = 100 mVPP
4
2
2
0
0
Normalized Gain (dB)
Normalized Gain (dB)
Figure 4. Small-Signal Frequency Response vs Ambient
Temperature
4
-2
-4
-6
-10
-12
1M
RS = 24 :, C L = 10 pF
RS = 10 :, C L = 47 pF
RS = 5.6 :, C L = 100 pF
RS = 1.8 :, C L = 1 nF
10M
100M
Frequency (Hz)
D104
VOUT = 100 mVPP
Figure 3. Small-Signal Frequency Response vs Output Load
-8
1G
-2
-4
-6
-8
-10
-12
1M
1G
D105
VOUT = 100 mVPP; see Figure 45 for circuit configuration
Figure 5. Small-Signal Frequency Response vs Capacitive
Load
Gain = 7 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 7 V/V
10M
100M
Frequency (Hz)
1G
D106
VOUT = 2 VPP
Figure 6. Large-Signal Frequency Response vs Gain
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Typical Characteristics (continued)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
0.4
4
0.3
2
0
Normalized Gain (dB)
Normalized Gain (dB)
0.2
0.1
0
-0.1
-0.2
-0.3
-2
-4
-6
-8
-0.4
-10
-0.5
10M
100M
Frequency (Hz)
-12
1M
1G
VOUT = 2 VPP
VS = 3.3 V
Figure 7. Large-Signal Response for 0.1-dB Gain Flatness
Open-Loop Magnitude (dB)
0.1
1M
10M
Frequency (Hz)
-45
45
-90
30
-135
15
-180
0
-225
100k
1M
D109
Small-Signal Response
Figure 9. Closed-Loop Output Impedance vs Frequency
1G
-270
10G
D500
Figure 10. Open-Loop Magnitude and Phase vs Frequency
3.2
Input Referred Voltage Noise (nV/ —Hz)
Input Referred Voltage Noise (nV/ —Hz)
10M
100M
Frequency (Hz)
Small-Signal Response
100
10
1
1k
D108
60
-15
10k
100M
5G
45
AOL magnitude (dB)
AOL phase (q)
0
75
1
1G
VOUT = 1 VPP
90
Gain = 7 V/V
Gain = 20 V/V
10
100M
Frequency (Hz)
Figure 8. Large-Signal Frequency Response
100
Closed-Loop Output Impedance (:)
10M
D107
Open-Loop Phase (q)
-0.6
1M
10k
100k
1M
Frequency (Hz)
10M
100M
3
2.8
2.6
2.4
2.2
2
1.8
-40
D111
-20
0
20
40
60
80
Ambient Temperature (qC)
100
120
140
D112
Frequency = 10 MHz
Figure 11. Voltage Noise Density vs Frequency
8
Figure 12. Voltage Noise Density vs Ambient Temperature
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Typical Characteristics (continued)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
-40
-60
-70
-80
-90
-100
-110
-120
1M
10M
Frequency (Hz)
-80
-90
-100
10M
Frequency (Hz)
D113
HD2, RL = 100 :
HD2, RL = 200 :
HD2, RL = 400 :
-70
-80
-90
-100
-110
HD3, RL = 100 :
HD3, RL = 200 :
HD3, RL = 400 :
-60
-70
-80
-90
-100
-110
10M
Frequency (Hz)
-120
1M
100M
10M
Frequency (Hz)
D115
VOUT = 2 VPP
Figure 15. Harmonic Distortion (HD2) vs Output Load
D116
Figure 16. Harmonic Distortion (HD3) vs Output Load
-40
HD2, G = 7 V/V
HD2, G = 7 V/V
HD2, G = 20 V/V
HD3, G = 7 V/V
HD3, G = 7 V/V
HD3, G = 20 V/V
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
100M
VOUT = 2 VPP
-40
-60
-70
-80
-90
-100
-60
-70
-80
-90
-100
-110
-110
-120
1M
D114
Figure 14. Harmonic Distortion (HD3) vs Output Swing
-50
-60
-50
100M
-40
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-70
-120
1M
100M
Figure 13. Harmonic Distortion (HD2) vs Output Swing
-120
1M
-60
-110
-40
-50
HD3, VOUT = 0.5 VPP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 VPP
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-40
HD2, VOUT = 0.5 VPP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 VPP
10M
Frequency (Hz)
100M
-120
1M
10M
Frequency (Hz)
D117
VOUT = 2 VPP
100M
D118
VOUT = 2 VPP
Figure 17. Harmonic Distortion (HD2) vs Gain
Figure 18. Harmonic Distortion (HD3) vs Gain
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Typical Characteristics (continued)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
80
60
1.25
Input
Output
Input
Output
1
Voltage Swing (V)
Voltage Swing (mV)
0.75
40
20
0
-20
0.5
0.25
0
-0.25
-0.5
-40
-0.75
-60
-1
-80
-1.25
Time (5 ns/div)
Time (5 ns/div)
D119
Average Rise and Fall Time (10% - 90%) = 450 ps
Figure 19. Small-Signal Transient Response
Figure 20. Large-Signal Transient Response
3
80
60
Measured Output
Ideal Output
2
40
Voltage Swing (V)
Voltage Swing (mV)
D120
Average Rise and Fall Time (10% - 90%) = 750 ps
20
0
-20
-40
-60
RS = 24 :, CL = 10 pF
RS = 10 :, CL = 47 pF
RS = 5.6 :, CL = 100 pF
RS = 1.8 :, CL = 1 nF
1
0
-1
-2
-3
-80
0
Time (5 ns/div)
10
D121
20
30
40
50
60
Time (ns)
70
80
90
100
D122
2x Output Overdrive
Figure 22. Output Overload Response
5
5
4.5
4.5
4
4
3.5
3.5
Voltage Swing (V)
Voltage Swing (V)
Figure 21. Small-Signal Transient Response vs Capacitive
Load
3
2.5
2
1.5
1
Power Down (PD)
Output
3
2.5
2
1.5
1
Power Down (PD)
Output
0.5
0.5
0
0
Time (5 ns/div)
Time (5 ns/div)
D123
VS+ = 5 V, VS– = Ground
Figure 23. Turnon Transient Response
10
D124
VS+ = 5 V, VS– = Ground
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Figure 24. Turnoff Transient Response
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Typical Characteristics (continued)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
100
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
100
80
60
40
20
0
-20
10k
100k
1M
10M
Frequency (Hz)
100M
PSRR
PSRR+
80
60
40
20
0
-20
-40
10k
1G
100k
D125
Small-Signal Response
22.5
25
22
21.5
21
20.5
20
19.5
19
3.75
4
4.25 4.5
Total Supply Voltage (V)
D126
4.75
5
24
23
22
21
20
Unit 1 (VS = 3.3 V)
Unit 1 (VS = 5 V)
Unit 2 (VS = 3.3 V)
Unit 2 (VS = 5 V)
19
Unit1
Unit2
3.5
1G
Figure 26. Power Supply Rejection Ratio vs Frequency
26
Quiescent Current (mA)
Quiescent Current (mA)
Figure 25. Common-Mode Rejection Ratio vs Frequency
3.25
100M
Small-Signal Response
23
3
1M
10M
Frequency (Hz)
18
-40
5.25
-20
0
D160
2 Typical Units
20
40
60
80
Ambient Temperature (qC)
100
120
D161
2 Typical Units
Figure 27. Quiescent Current vs Supply Voltage
Figure 28. Quiescent Current vs Ambient Temperature
85
1.5
0.9
80
Offset Voltage (mV)
Quiescent Current (PA)
1.2
75
70
Unit 1
Unit 2
Unit 3
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
65
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D162
-1.5
3
3.25
30 Units Tested
3.5
3.75
4
4.25 4.5
Total Supply Voltage (V)
4.75
5
5.25
D163
3 Typical Units
Figure 29. Quiescent Current (Amplifier Disabled) vs
Ambient Temperature
Figure 30. Offset Voltage vs Supply Voltage
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Typical Characteristics (continued)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
4
0.8
Unit 1
Unit 2
Unit 3
3.5
0.6
Offset Voltage (mV)
Offset Voltage (mV)
3
0.4
0.2
0
-0.2
-0.4
2.5
2
1.5
1
0.5
0
-0.5
-0.6
-1
-0.8
-40
-1.5
-20
0
µ = 1 µV/°C
20
40
60
80
Ambient Temperature (qC)
σ = 2.2 µV/°C
100
120
0
140
D164
VS = 3.3 V
28 Units Tested
3
D165
3 Typical Units
2
Unit 1
Unit 2
Unit 3
2.5
1.6
1.2
Offset Voltage (mV)
2
1.5
1
0.5
0
-0.5
0.8
0.4
0
-0.4
-0.8
-1
-1.2
-1.5
-1.6
-2
TA = 40qC
TA = 25qC
TA = 125qC
-2
0
0.5
1
VS = 5 V
1.5
2
2.5
3
3.5
Common-Mode Voltage (V)
4
4.5
0
0.4
0.8
D166
1.2 1.6
2
2.4 2.8
Common-Mode Voltage (V)
3.2
3.6
4
D167
3 Typical Units
Figure 33. Offset Voltage vs Input Common-Mode Voltage
Figure 34. Offset Voltage vs Input Common-Mode Voltage
vs Ambient Temperature
2.5
4
2
3
1.5
2
Offset Voltage (mV)
Offset Voltage (mV)
2.25 2.5 2.75
Figure 32. Offset Voltage vs Input Common-Mode Voltage
Figure 31. Offset Voltage vs Ambient Temperature
Offset Voltage (mV)
0.25 0.5 0.75 1 1.25 1.5 1.75 2
Common-Mode Voltage (V)
1
0
-1
Unit 1
Unit 2
Unit 3
1
0.5
0
-0.5
-1
-2
-1.5
Unit 1
Unit 2
Unit 3
-3
-2
-4
1
1.2
VS = 3.3 V
1.4
1.6
1.8
2
Output Voltage (V)
2.2
2.4
2.6
-2.5
0.8
3 Typical Units
VS = 5 V
Figure 35. Offset Voltage vs Output Swing
12
1.2
D168
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1.6
2
2.4
2.8
Output Voltage (V)
3.2
3.6
4
D169
3 Typical Units
Figure 36. Offset Voltage vs Output Swing
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Typical Characteristics (continued)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
1.5
1000
100
Input Bias Current (pA)
Offset Voltage (mV)
1
0.5
0
-0.5
-1.5
0.8
1.2
1.6
2
2.4
2.8
Output Voltage (V)
3.2
3.6
1
0.1
TA = 40qC
TA = 25qC
TA = 125qC
-1
10
Unit 1
Unit 2
Unit 3
0.01
-40
4
-20
0
20
40
60
80
Ambient Temperature (qC)
D170
100
120
140
D171
3 Typical Units
Figure 38. Input Bias Current vs Ambient Temperature
5
4000
0
3500
3000
-5
Amplifiers (Count)
-10
-15
-20
2500
2000
1500
1000
-25
µ = 20.35 mA
σ = 0.2 mA
24
23
23.5
22.5
D140
Quiescent Current (mA)
D172
Figure 39. Input Bias Current vs Input Common-Mode
Voltage
4555 units tested
Figure 40. Quiescent Current Distribution
1750
1200
1500
750
Offset Voltage (mV)
µ = –0.28 mV
σ = 0.8 mV
D141
4555 units tested
D142
Input Bias Current (pA)
µ = –0.1 pA
Figure 41. Offset Voltage Distribution
σ = 0.39 pA
4555 units tested
Figure 42. Input Bias Current Distribution
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1.5
1
1.25
0.75
0.5
0
0
0.25
0
-0.25
250
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
200
-0.5
500
-1
400
1000
-0.75
600
1250
-1.25
800
-1.5
Amplifiers (Count)
1000
Amplifiers (Count)
22
4
21
3.5
21.5
1.5
2
2.5
3
Common-Mode Voltage (V)
20.5
1
20
0.5
19
0
19.5
0
-30
18.5
500
18
Input Bias Current (pA)
Figure 37. Offset Voltage vs Output Swing vs Ambient
Temperature
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8 Parameter Measurement Information
8.1 Parameter Measurement Information
The various test setup configurations for the OPA858 are shown below
GND
50
2.5 V
50
50Source
169
+
±
í2.5 V
RG
50
71.5
453
50Measurement
System
GND
GND
GND
RG values depend on gain configuration
Figure 43. Noninverting Configuration
2.5 V
169
+
GND
50Source
50Measurement
System
±
í2.5 V
50
64
50
71.5
GND
453
GND
220
GND
Figure 44. Inverting Configuration (Gain = –7 V/V)
GND
50
50Source
2.5 V
50
+
RS
1k
±
í2.5 V
75
GND
453
CL
GND
50
53.6
50Measurement
System
GND
GND
Figure 45. Capacitive Load Driver Configuration
14
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9 Detailed Description
9.1 Overview
The ultra-wide, 5.5-GHz gain bandwidth product (GBWP) of the OPA858, combined with the broadband voltage
noise of 2.5 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data
acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends.
The OPA858 combines multiple features to optimize dynamic performance. In addition to the wide, small-signal
bandwidth, the OPA858 has 600 MHz of large signal bandwidth (VOUT = 2 VPP) and a slew rate of 2000 V/µs.
The OPA858 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a simple
feedback network connection between the amplifiers output and inverting input. Excess capacitance on an
amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of very
wideband amplifiers like the OPA858. To reduce the effects of stray capacitance on the input node, the OPA858
pinout features an isolation pin (NC) between the feedback and inverting input pins that increases the physical
spacing between them thereby reducing parasitic coupling at high frequencies. The OPA858 also features a very
low capacitance input stage with only 0.8-pF of total input capacitance.
9.2 Functional Block Diagram
The OPA858 is a classic, voltage feedback operational amplifier (op amp) with two high-impedance inputs and a
low-impedance output. Standard application circuits are supported, like the two basic options shown in Figure 46
and Figure 47. The DC operating point for each configuration is level-shifted by the reference voltage (VREF),
which is typically set to midsupply in single-supply operation. VREF is typically connected to ground in split-supply
applications.
VSIG
VS+
VREF
VIN
(1 + RF / RG) × VSIG
+
VOUT
VREF
±
RG
VS±
VREF
RF
Figure 46. Noninverting Amplifier
VS+
VREF
VSIG
VREF
±(RF / RG) × VSIG
+
VOUT
VIN
RG
VREF
±
VS±
RF
Figure 47. Inverting Amplifier
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9.3 Feature Description
9.3.1 Input and ESD Protection
The OPA858 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as Figure 48 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
±
VINí
FB
VSí
Figure 48. Internal ESD Structure
9.3.2 Feedback Pin
The OPA858 pin layout is optimized to minimize parasitic inductance and capacitance, which is critical in highspeed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The FB pin is
separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin must be
left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see
Figure 49) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
RF
FB 1
8
PD
NC 2
7
VS+
6
OUT
5
VS±
±
+
IN± 3
IN+ 4
Figure 49. RF Connection Between FB and IN– Pins
16
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Feature Description (continued)
9.3.3 Wide Gain-Bandwidth Product
Figure 10 shows the open-loop magnitude and phase response of the OPA858. Calculate the gain bandwidth
product of any op amp by determining the frequency at which the AOL is 60 dB and multiplying that frequency by
a factor of 1000. The second pole in the AOL response occurs before the magnitude crosses 0 dB, and the
resultant phase margin is less than 0°. This indicates instability at a gain of 0 dB (1 V/V). Amplifiers that are not
unity-gain stable are known as decompensated amplifiers. Decompensated amplifiers typically have higher gainbandwidth product, higher slew rate, and lower voltage noise, compared to a unity-gain stable amplifier with the
same amount of quiescent power consumption.
Figure 50 shows the open-loop magnitude (AOL) of the OPA858 as a function of temperature. The results show
minimal variation over temperature. The phase margin of the OPA858 configured in a noise gain of 7 V/V (16.9
dB) is close to 55° across temperature. Similarly Figure 51 shows the AOL magnitude of the OPA858 as a
function of process variation. The results show the AOL curve for the nominal process corner and the variation
one standard deviation from the nominal. The simulated results suggest less than 1° of phase margin difference
within a standard deviation of process variation when the amplifier is configured in a gain of 7 V/V.
One of the primary applications for the OPA858 is as a high-speed transimpedance amplifier (TIA), as Figure 59
shows. The low-frequency noise gain of a TIA is 0 dB (1 V/V). At high frequencies the ratio of the total input
capacitance and the feedback capacitance set the noise gain. To maximize the TIA closed-loop bandwidth, the
feedback capacitance is typically smaller than the input capacitance, which implies that the high-frequency noise
gain is greater than 0 dB. As a result, op amps configured as TIAs are not required to be unity-gain stable, which
makes a decompensated amplifier a viable option for a TIA. What You Need To Know About Transimpedance
Amplifiers – Part 1 and What You Need To Know About Transimpedance Amplifiers – Part 2 describe
transimpedance amplifier compensation in greater detail.
90
90
AOL at 40qC
AOL at 25qC
AOL at +125qC
60
45
30
15
0
-15
100k
AOL ( V)
AOL (Typ.)
AOL ( V)
75
Open-Loop Gain (dB)
Open-Loop Gain (dB)
75
60
45
30
15
0
1M
10M
100M
Frequency (Hz)
1G
10G
-15
100k
1M
D204
Figure 50. Open-Loop Gain vs Temperature
10M
100M
Frequency (Hz)
1G
10G
D205
Figure 51. Open-Loop Gain vs Process Variation
9.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA858 features a high slew rate of 2000 V/µs . The slew rate is a critical
parameter in high-speed pulse applications with narrow sub 10-ns pulses such as Optical Time-Domain
Reflectometry (OTDR) and LIDAR. The high slew rate of the OPA858 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge as seen in Figure 20. The wide bandwidth and slew rate of the OPA858
make it an ideal amplifier for high-speed, signal-chain front ends.
Figure 52 shows the open-loop output impedance of the OPA858 as a function of frequency. To achieve high
slew rates and low output impedance across frequency, the output swing of the OPA858 is limited to
approximately 3 V. The OPA858 is typically used in conjunction with high-speed pipeline ADCs and flash ADCs
that have limited input ranges. Therefore, the OPA858 output swing range coupled with the class-leading voltage
noise specification maximizes the overall dynamic range of the signal chain.
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Feature Description (continued)
Open-Loop Output Impedance (ohms)
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M
100M
Frequency (Hz)
1G
10G
D601
Figure 52. Open-Loop Output Impedance (ZOL) vs Frequency
9.3.5 Current Noise
The input impedance of CMOS and JFET input amplifiers at low frequencies exceed several GΩs. However, at
higher frequencies, the transistors parasitic capacitance to the drain, source, and substrate reduces the
impedance. The high impedance at low frequencies eliminates any bias current and the associated shot noise. At
higher frequencies, the input current noise increases (see Figure 53) as a result of capacitive coupling between
the CMOS gate oxide and the underlying transistor channel. This phenomenon is a natural artifact of the
construction of the transistor and is unavoidable.
100p
Current Noise (A/—Hz)
10p
1p
100f
10f
1f
1k
10k
100k
1M
10M
Frequency (Hz)
100M
1G
D607
Figure 53. Input Current Noise (IBN and IBI) vs Frequency
18
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9.4 Device Functional Modes
9.4.1 Split-Supply and Single-Supply Operation
The OPA858 can be configured with single-sided supplies or split-supplies as shown in Figure 63. Split-supply
operation using balanced supplies with the input common-mode set to ground eases lab testing because most
signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference inputs and
outputs to ground. Split-supply operation is preferred in systems where the signals swing around ground.
However, the system requires two supply rails. In split-supply operation, the thermal pad must be connected to
the negative supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA858 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. To
change the circuit from a split-supply to a single-supply configuration, level shift all the voltages by half the
difference between the power supply rails. In this case, the thermal pad must be connected to ground.
9.4.2 Power-Down Mode
The OPA858 features a power-down mode to reduce the quiescent current to conserve power. Figure 23 and
Figure 24 show the transient response of the OPA858 as the PD pin toggles between the disabled and enabled
states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65-V supplies, then
the disable and enable threshold voltages are at –1 V and 0.15 V, respectively. If the amplifier is configured with
±2.5-V supplies, then the threshold voltages are at –1.85 V and –0.7 V.
25
25
20
20
Quiescent Current (mA)
Quiescent Current (mA)
Figure 54 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state
to the disabled state. Similarly Figure 55 shows the switching behavior of a typical amplifier as the PD pin is
swept up from the disabled state to the enabled state. The small difference in the switching thresholds between
the down sweep and the up sweep is due to the hysteresis designed into the amplifier to increase its immunity to
noise on the PD pin.
15
10
5
15
10
5
TA = -40qC
TA = 25qC
TA = 125qC
0
TA = -40qC
TA = 25qC
TA = 125qC
0
-2
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
-2
D200
Figure 54. Switching Threshold (PD Pin Swept from HIGH
to LOW)
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
D201
Figure 55. Switching Threshold (PD Pin Swept from LOW
to HIGH)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA858 uses internal,
back-to-back protection diodes between the inverting and noninverting input pins as Figure 48 shows. When the
differential voltage between the input pins of the amplifier exceeds a diode voltage drop, an additional lowimpedance path is created between the inputs.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Using the OPA858 as a Transimpedance Amplifier
The OPA858 design has been optimized to meet the industry's growing demand for wideband, low-noise
photodiode amplifiers. The closed-loop bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance. This includes the photodiode capacitance, input capacitance of the amplifier
(common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP), and,
3. The transimpedance gain RF.
5V
+
100 V
3.4 V
+
OPA858
±
±
GND
GND
RF
CF
Figure 56. Transimpedance Amplifier Circuit
Figure 56 shows the OPA858 configured as a TIA with the avalanche photodiode (APD) reverse biased such that
its cathode is tied to a large positive bias voltage. In this configuration the APD sources current into the op amp
feedback loop so that the output swings in a negative direction relative to the input common-mode voltage. To
maximize the output swing in the negative direction, the OPA858 common-mode is set close to the positive limit,
1.6 V from the positive supply rail.
The feedback resistance RF and the input capacitance form a zero in the noise gain that results in instability if left
unchecked. To counteract the effect of the zero, a pole is inserted by adding the feedback capacitor (CF.) into the
noise gain transfer function. The Transimpedance Considerations for High-Speed Amplifiers application report
discusses theories and equations that show how to compensate a transimpedance amplifier for a particular gain
and input capacitance. The bandwidth and compensation equations from the application report are available in a
Microsoft Excel ™ calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a
link to the calculator.
20
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400
350
100
90
300
80
250
70
200
60
150
50
100
40
50
30
0
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
20
20
350
300
100
250
80
200
60
150
40
100
20
50
0
100
10
Feedback Resistance (k:)
D209
Figure 57. Bandwidth and Noise Performance vs
Photodiode Capacitance
120
f-3dB , C F = 1 pF
f-3dB , C F = 2 pF
IRN , C F = 1 pF
IRN , C F = 2 pF
Integrated Input Referred Noise, I RN (nA RMS )
110
f-3dB , R F = 10 k:
f-3dB , R F = 20 k:
IRN , R F = 10 k:
IRN , R F = 20 k:
Closed-loop Bandwidth, f -3dB (MHz)
Closed-loop Bandwidth, f -3dB (MHz)
450
Integrated Input Referred Noise, I RN (nA RMS )
Application Information (continued)
D210
Figure 58. Bandwidth and Noise Performance vs Feedback
Resistance
The equations and calculators in the application report and blog posts referenced above are used to model the
bandwidth (f-3dB) and noise (IRN) performance of the OPA858 configured as a TIA. The resultant performance is
shown in Figure 57 and Figure 58. The left side Y-axis shows the closed-loop bandwidth performance, while the
right side of the graph shows the integrated input referred noise. The noise bandwidth to calculate IRN, for a fixed
RF and CPD is set equal to the f–3dB frequency.
Figure 57 shows the amplifier performance as a function of photodiode capacitance (CPD) for RF = 10 kΩ and 20
kΩ. Increasing CPD decreases the closed-loop bandwidth. It is vital to reduce any stray parasitic capacitance from
the PCB to maximize bandwidth. The OPA858 is designed with 0.8 pF of total input capacitance to minimize the
effect on system performance.
Figure 58 shows the amplifier performance as a function of RF for CPD = 1 pF and 2 pF. Increasing RF results in
lower bandwidth. To maximize the signal-to-noise ratio (SNR) in an optical front-end system, maximize the gain
in the TIA stage. Increasing RF by a factor of "X" increases the signal level by "X", but only increases the resistor
noise contribution by "√X", thereby improving SNR.
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21
OPA858
SBOS629A – APRIL 2018 – REVISED JULY 2018
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10.2 Typical Application
The high GBWP, low input voltage noise and high slew rate of the OPA858 makes the device a viable wideband,
high input impedance voltage amplifier.
2.5 V
169
+
GND
±
í2.5 V
50
50Source
226
50
71.5
453
50Measurement
System
GND
GND
62
Supply decoupling not shown
GND
GND
Figure 59. OPA858 in a Gain of –2V/V (No Noise Gain Shaping)
2.5 V
+
GND
50Source
169
í2.5 V
50
226
62
50
71.5
453
GND
GND
2.7 pF
GND
GND
50Measurement
System
±
Supply decoupling not shown
0.5 pF
GND
Figure 60. OPA858 in a Gain of –2V/V (With Noise Gain Shaping)
10.2.1 Design Requirements
Design a high-bandwidth, high-gain, voltage amplifier with the design requirements listed in Table 1. An inverting
amplifier configuration is chosen here; however, the theory is applicable to a noninverting configuration as well.
In an inverting configuration the signal gain and noise gain transfer functions are not equal, unlike the
noninverting configuration.
Table 1. Design Requirements
TARGET BANDWIDTH
(MHz)
SIGNAL GAIN (V/V)
> 750
–2
FEEDBACK RESISTANCE
(Ω)
453
FREQUENCY
PEAKING (dB)
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