TLV9151, TLV9152, TLV9154
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TLV915x family (TLV9151, TLV9152, and
TLV9154) is a family of 16-V, general purpose
operational
amplifiers.
These
devices
offer
exceptional DC precision and AC performance,
including rail-to-rail output, low offset (±125 µV,
typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz
bandwidth.
•
•
Low offset voltage: ±125 µV
Low offset voltage drift: ±0.3 µV/°C
Low noise: 10.5 nV/√ Hz at 1 kHz
High common-mode rejection: 120 dB
Low bias current: ±10 pA
Rail-to-rail input and output
Wide bandwidth: 4.5-MHz GBW
High slew rate: 20 V/µs
Low quiescent current: 560 µA per amplifier
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: EMI/RFI filters on
input pins
Differential and common-mode input voltage range
to supply rail
Industry standard packages:
– Single in SOT-23-5, SC70-5, and SOT553
– Dual in SOIC-8, SOT-23-8, TSSOP-8,
VSSOP-8, WSON-8, and X2QFN-10
– Quad in SOIC-14, TSSOP-14, WQFN-14, and
WQFN-16
2 Applications
•
•
•
•
•
Professional microphones and wireless systems
Multiplexed data-acquisition systems
Test and measurement equipment
Factory automation and control
High-side and low-side current sensing
RG
Convenient features such as wide differential inputvoltage range, high output current (±75 mA), high
slew rate (20 V/μs), and low noise (10.5 nV/√ Hz)
make the TLV915x a robust, low-noise operational
amplifier for industrial applications.
The TLV915x family of op amps is available in
standard packages and is specified from –40°C to
125°C.
Device Information
PART NUMBER (1)
TLV9151
TLV9152
RF
TLV9154
R1
VOUT
VIN
(1)
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (8)
2.90 mm × 1.60 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
2.00 mm × 2.00 mm
X2QFN (10)
1.50 mm × 1.50 mm
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
X2QFN (14)
2.00 mm × 2.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1
2pR1C1
(
TLV915x in a Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV9151, TLV9152, TLV9154
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SBOS986D – OCTOBER 2019 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications................................................................ 11
6.1 Absolute Maximum Ratings ..................................... 11
6.2 ESD Ratings .............................................................11
6.3 Recommended Operating Conditions ...................... 11
6.4 Thermal Information for Single Channel .................. 11
6.5 Thermal Information for Dual Channel .....................12
6.6 Thermal Information for Quad Channel ................... 12
6.7 Electrical Characteristics ..........................................13
6.8 Typical Characteristics.............................................. 17
7 Detailed Description......................................................24
7.1 Overview................................................................... 24
7.2 Functional Block Diagram......................................... 24
7.3 Feature Description...................................................25
7.4 Device Functional Modes..........................................32
8 Application and Implementation.................................. 33
8.1 Application Information............................................. 33
8.2 Typical Applications.................................................. 33
9 Power Supply Recommendations................................35
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 36
11 Device and Documentation Support..........................37
11.1 Device Support........................................................37
11.2 Documentation Support.......................................... 37
11.3 Related Links.......................................................... 37
11.4 Receiving Notification of Documentation Updates.. 37
11.5 Support Resources................................................. 37
11.6 Trademarks............................................................. 38
11.7 Electrostatic Discharge Caution.............................. 38
11.8 Glossary.................................................................. 38
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2020) to Revision D (May 2021)
Page
• Changed VSSOP (8) package status on Device Information from Preview to Active ....................................... 1
• Removed preview notation on VSSOP-8 (DGK) package in Pin Configurations and Functions ....................... 4
• Removed VSSOP-10 (DGS) package in Pin Configurations and Functions ..................................................... 4
Changes from Revision B (May 2020) to Revision C (December 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document ..................1
• Changed SOT-23 (5) package status on Device Information from Preview to Active ....................................... 1
• Changed SC70 (5) package status on Device Information from Preview to Active ...........................................1
• Changed SOT-23 (6) package status on Device Information from Preview to Active ....................................... 1
• Changed SOT-23 (8) package status on Device Information from Preview to Active ....................................... 1
• Changed VSSOP (8) package status on Device Information from Preview to Active ....................................... 1
• Changed SOIC (14) package status on Device Information from Preview to Active ......................................... 1
• Changed TSSOP (14) package status on Device Information from Preview to Active ......................................1
• Changed X2QFN (14) package status on Device Information from Preview to Active ......................................1
• Removed preview notation on SOT-23-5 (DBV), SC70-5 (DCK) SOT-23-6 (DBV), and SOT-23-8 (DDF)
packages in Pin Configurations and Functions ..................................................................................................4
• Removed preview notation on SOIC-14 (D) package in Pin Configurations and Functions ..............................4
• Removed preview notation on TSSOP-14 (PW) package in Pin Configurations and Functions ....................... 4
• Removed preview notation on X2QFN-14 (RUC) package in Pin Configurations and Functions ..................... 4
Changes from Revision A (March 2020) to Revision B (May 2020)
Page
• Changed X2QFN (10) package status on Device Information from Preview to Active ......................................1
• Removed preview notation on X2QFN (RUG) package in Pin Configurations and Functions .......................... 4
• Added VIH and VIL in Recommended Operating Conditions section.................................................................11
• Added SHUTDOWN in Electrical Characteristics table.....................................................................................11
2
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TLV9151, TLV9152, TLV9154
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
Changes from Revision * (October 2019) to Revision A (March 2020)
Page
• Changed document status from Advance Information to Production Data ........................................................1
• Changed SOIC (8) package status on Device Information from Preview to Active ........................................... 1
• Changed TSSOP (8) package status on Device Information from Preview to Active ........................................1
• Changed WSON (8) package status on Device Information from Preview to Active .........................................1
• Removed preview notation on SOIC-8 (D), TSSOP-8 (PW), and WSON-8 (DSG) packages in Pin
Configurations and Functions ............................................................................................................................ 4
• Added Typical Characteristics section in Specifications section.......................................................................17
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SBOS986D – OCTOBER 2019 – REVISED MAY 2021
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
A.
5
V+
4
OUT
Not to scale
Figure 5-2. TLV9151 DCK
5-Pin SC70 and SOT-553
Top View
DRL package is preview only.
Figure 5-1. TLV9151 DBV and DRL Package(A)
5-Pin SOT-23
Top View
Table 5-1. Pin Functions: TLV9151
PIN
NAME
4
DBV, DRL
DCK
I/O
DESCRIPTION
+IN
3
1
I
Noninverting input
–IN
4
3
I
Inverting input
OUT
1
4
O
Output
V+
5
5
—
Positive (highest) power supply
V–
2
2
—
Negative (lowest) power supply
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SBOS986D – OCTOBER 2019 – REVISED MAY 2021
OUT
1
6
V+
V–
2
5
SHDN
+IN
3
4
–IN
Not to scale
A.
DRL package is preview only.
Figure 5-3. TLV9151S DBV and DRL Package(A)
6-Pin SOT-23 and SOT-563
Top View
Table 5-2. Pin Functions: TLV9151S
PIN
NAME
DBV, DRL
+IN
3
–IN
OUT
I/O
DESCRIPTION
I
Noninverting input
4
I
Inverting input
1
O
Output
SHDN
5
I
Shutdown: low = amplifier enabled, high = amplifier disabled. See Shutdown
for more information.
V+
6
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
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SBOS986D – OCTOBER 2019 – REVISED MAY 2021
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Figure 5-4. TLV9152 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP
Top View
Not to scale
A.
Connect thermal pad to V–. See Packages with and Exposed
Thermal Pad for more information.
Figure 5-5. TLV9152 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3. Pin Functions: TLV9152
PIN
NAME
6
SOIC, SOT-23-8,
TSSOP, VSSOP,
WSON
I/O
DESCRIPTION
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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IN1+
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
1
9
IN1–
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
5
10
V–
IN2–
Not to scale
Figure 5-6. TLV9152S RUG Package
10-Pin X2QFN
Top View
Table 5-4. Pin Functions: TLV9152S
PIN
NAME
X2QFN
I/O
DESCRIPTION
+IN A
10
I
Noninverting input, channel A
+IN B
4
I
Noninverting input, channel B
–IN A
9
I
Inverting input, channel A
–IN B
5
I
Inverting input, channel B
OUT A
8
O
Output, channel A
OUT B
6
O
Output, channel B
SHDN1
2
I
Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See
Shutdown for more information.
SHDN2
3
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See
Shutdown for more information.
V+
7
—
Positive (highest) power supply
V–
1
—
Negative (lowest) power supply
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IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN1+
1
V+
2
IN4±
13
13
2
OUT4
IN1±
14
OUT4
OUT1
14
15
1
IN1±
OUT1
16
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
8
OUT3
IN2±
4
8
7
OUT3
OUT2
Pad
7
3
NC
IN2+
6
IN3±
NC
9
5
6
OUT2
IN2±
Not to scale
Figure 5-7. TLV9154 D and PW Package
14-Pin SOIC and TSSOP
Top View
A.
Not to scale
Connect thermal pad to V–. See Packages with and Exposed
Thermal Pad for more information.
Package is preview only.
B.
IN4±
2
11
IN4+
V+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
OUT3
OUT2
7
IN1+
13
12
14
1
6
IN1±
OUT4
OUT1
Figure 5-8. TLV9154 RTE Package(A)(B)
16-Pin WQFN With Exposed Thermal Pad
Top View
Not to scale
Figure 5-9. TLV9154 RUC Package
14-Pin X2QFN With Exposed Thermal Pad
Top View
Table 5-5. Pin Functions: TLV9154
PIN
NAME
8
SOIC,
TSSOP
WQFN
X2QFN
I/O
DESCRIPTION
IN1+
3
1
2
I
Noninverting input, channel 1
IN1–
2
16
1
I
Inverting input, channel 1
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Table 5-5. Pin Functions: TLV9154 (continued)
PIN
NAME
IN2+
I/O
DESCRIPTION
SOIC,
TSSOP
WQFN
X2QFN
5
3
4
I
Noninverting input, channel 2
IN2–
6
4
5
I
Inverting input, channel 2
IN3+
10
10
9
I
Noninverting input, channel 3
IN3–
9
9
8
I
Inverting input, channel 3
IN4+
12
12
11
I
Noninverting input, channel 4
IN4–
13
13
12
I
NC
—
6, 7
—
—
Do not connect
OUT1
1
15
14
O
Output, channel 1
OUT2
7
5
6
O
Output, channel 2
Inverting input, channel 4
OUT3
8
8
7
O
Output, channel 3
OUT4
14
14
13
O
Output, channel 4
V+
4
2
3
—
Positive (highest) power supply
V–
11
11
10
—
Negative (lowest) power supply
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IN1+
1
V+
2
IN1–
OUT1
OUT4
IN4–
16
15
14
13
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
12
IN4+
11
V–
10
IN3+
9
IN3–
Thermal
A.
6
7
8
SHDN34
OUT3
4
SHDN12
IN2–
Pad
5
3
OUT2
IN2+
Not to scale
Package is preview only.
Figure 5-10. TLV9154S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6. Pin Functions: TLV9154S
PIN
NAME
RTE
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
SHDN12
6
I
Shutdown, channel 1 & 2: low = amplifiers enabled, high = amplifiers disabled.
See Shutdown for more information.
SHDN34
7
I
Shutdown, channel 3 & 4: low = amplifiers enabled, high = amplifiers disabled.
See Shutdown for more information.
VCC+
2
—
Positive (highest) power supply
VCC–
11
—
Negative (lowest) power supply
10
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SBOS986D – OCTOBER 2019 – REVISED MAY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
20
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage
(3)
Differential voltage (3)
Signal input pins
VS + 0.2
Current (3)
–10
Output short-circuit (2)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to ground, one amplifier per package.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
VS
Supply voltage, (V+) – (V–)
VI
Input voltage range
MIN
MAX
2.7
16
UNIT
V
(V–) – 0.1
(V+) + 0.1
V
VIH
High level input voltage at shutdown pin (amplifier enabled)
1.1
(V+)
V
VIL
Low level input voltage at shutdown pin (amplifier disabled)
(V–)
0.2
V
TA
Specified temperature
–40
125
°C
6.4 Thermal Information for Single Channel
TLV9151, TLV9151S
DBV
(SOT-23)
THERMAL METRIC (1)
DCK
(SC70)
5 PINS
6 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
185.7
167.8
202.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
108.2
107.9
101.5
°C/W
RθJB
Junction-to-board thermal resistance
54.5
49.7
47.8
°C/W
ψJT
Junction-to-top characterization parameter
31.2
33.9
18.8
°C/W
ψJB
Junction-to-board characterization parameter
54.2
49.5
47.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Thermal Information for Dual Channel
TLV9152, TLV9152S
THERMAL METRIC (1)
D
(SOIC)
DDF
(SOT-23-8)
DGK
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
RUG
(X2QFN)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
138.7
143.5
176.5
77.6
185.1
142.3
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
78.7
79.9
68.1
93.7
74.0
53.5
°C/W
RθJB
Junction-to-board thermal
resistance
82.2
61.6
98.2
43.9
115.7
68.5
°C/W
ψJT
Junction-to-top
characterization parameter
27.8
5.7
12.0
4.4
12.3
1.0
°C/W
ψJB
Junction-to-board
characterization parameter
81.4
61.3
96.7
43.9
114.0
68.4
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
19.0
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
TLV9154, TLV9154S
THERMAL METRIC
(1)
D
(SOIC)
PW
(TSSOP)
RUC
(WQFN)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
101.4
131.4
125.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.6
51.8
39.8
°C/W
RθJB
Junction-to-board thermal resistance
57.3
75.8
68.0
°C/W
ψJT
Junction-to-top characterization parameter
18.5
7.9
0.8
°C/W
ψJB
Junction-to-board characterization parameter
56.9
74.8
67.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
12
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
TLV9151, TLV9152
VCM = V–
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
Input offset voltage
versus power supply
VCM = V–, VS = 2.7 V to 16 V(2)
Channel separation
f = 0 Hz
±125
TA = –40°C to 125°C
±125
TLV9154
VCM = V–
TA = –40°C to 125°C
±830
µV
±880
TA = –40°C to 125°C
VCM = V–, VS = 4 V to 16 V
±750
±780
±0.3
TA = –40°C to 125°C
µV/℃
±0.3
±1
±1
±5
5
μV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±10
pA
IOS
Input offset current
±10
pA
NOISE
1.8
μVPP
0.3
µVRMS
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
eN
Input voltage noise
density
f = 1 kHz
10.8
f = 10 kHz
9.4
iN
Input current noise
f = 1 kHz
nV/√Hz
2
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = 16 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
CMRR
Common-mode rejection
ratio
VS = 4 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
VS = 2.7 V, (V–) – 0.1 V < VCM <
(V+) – 2 V (Main input pair)(2)
(V+) + 0.1
109
130
84
100
75
95
TA = –40°C to 125°C
VS = 2.7 V to 16 V, (V+) – 1 V < VCM
< (V+) + 0.1 V (Aux input pair)
V
dB
85
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 3
MΩ || pF
6 || 1
TΩ || pF
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
120
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V(2)
104
130
dB
125
101
TA = –40°C to 125°C
145
142
120
118
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
4.5
MHz
VS = 16 V, G = +1, CL = 20 pF
21
V/μs
To 0.01%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF
2.5
To 0.01%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF
1.5
To 0.1%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF
2
To 0.1%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF
THD+N
Phase margin
G = +1, RL = 10 kΩ
Overload recovery time
VIN × gain > VS
Total harmonic distortion
+ noise
VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz
μs
1
60
°
400
ns
0.00021%
OUTPUT
VS = 16 V, RL = no load(2)
Voltage output swing from
Positive and negative rail headroom
rail
5
10
VS = 16 V, RL = 10 kΩ
50
55
VS = 16 V, RL = 2 kΩ
200
250
1
6
VS = 2.7 V, RL = 10 kΩ
5
12
VS = 2.7 V, RL = 2 kΩ
25
40
VS = 2.7 V, RL = no load(2)
mV
ISC
Short-circuit current
±75
mA
CLOAD
Capacitive load drive
1000
pF
ZO
Open-loop output
impedance
525
Ω
f = 1 MHz, IO = 0 A
POWER SUPPLY
IQ
14
Quiescent current per
amplifier
IO = 0 A
560
TA = –40°C to 125°C
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750
µA
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
30
45
UNIT
SHUTDOWN
IQSD
Quiescent current per
amplifier
ZSHDN
Output impedance during
VS = 2.7 V to 16 V, amplifier disabled
shutdown
VIH
Logic high threshold
voltage (amplifier
disabled)
For valid input high, the SHDN pin voltage should be greater than
the maximum threshold but less than or equal to V+
VIL
Logic low threshold
voltage (amplifier
enabled)
For valid input low, the SHDN pin voltage should be less than the
minimum threshold but greater than or equal to V–
tON
Amplifier enable time
tOFF
Amplifier disable time (1)
SHDN pin input bias
current (per pin)
VS = 2.7 V to 16 V, (V+) ≥ SHDN ≥ (V–) + 0.9 V
500
VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
150
(1)
(2)
VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V–
(1)
10 || 2
(V–) + 0.8
(V–) + 0.2
µA
GΩ || pF
(V–) + 1.1
V
(V–) + 0.8
V
G = +1, VCM = V-, VO = 0.1 × VS/2
8
µs
VCM = V-, VO = VS/2
3
µs
nA
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Specified by characterization only.
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Table 6-1. Table of Graphs
16
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 6-1
Offset Voltage Drift Distribution
Figure 6-2
Offset Voltage vs Temperature
Figure 6-3, Figure 6-4
Offset Voltage vs Common-Mode Voltage
Figure 6-5, Figure 6-6, Figure 6-7, Figure 6-8
Offset Voltage vs Power Supply
Figure 6-9
Open-Loop Gain and Phase vs Frequency
Figure 6-10
Closed-Loop Gain and Phase vs Frequency
Figure 6-11
Input Bias Current vs Common-Mode Voltage
Figure 6-12
Input Bias Current vs Temperature
Figure 6-13
Output Voltage Swing vs Output Current
Figure 6-14, Figure 6-15,
CMRR and PSRR vs Frequency
Figure 6-16
CMRR vs Temperature
Figure 6-17
PSRR vs Temperature
Figure 6-18
0.1-Hz to 10-Hz Noise
Figure 6-19
Input Voltage Noise Spectral Density vs Frequency
Figure 6-20
THD+N Ratio vs Frequency
Figure 6-21
THD+N vs Output Amplitude
Figure 6-22
Quiescent Current vs Supply Voltage
Figure 6-23
Quiescent Current vs Temperature
Figure 6-24
Open Loop Voltage Gain vs Temperature
Figure 6-25
Open Loop Output Impedance vs Frequency
Figure 6-26
Small Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 6-27, Figure 6-28
Phase Margin vs Capacitive Load
Figure 6-29
No Phase Reversal
Figure 6-30
Positive Overload Recovery
Figure 6-31
Negative Overload Recovery
Figure 6-32
Small-Signal Step Response (100 mV)
Figure 6-33, Figure 6-34
Large-Signal Step Response
Figure 6-35, Figure 6-36, Figure 6-37
Short-Circuit Current vs Temperature
Figure 6-38
Maximum Output Voltage vs Frequency
Figure 6-39
Channel Separation vs Frequency
Figure 6-40
EMIRR vs Frequency
Figure 6-41
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6.8 Typical Characteristics
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
50
33
30
27
40
Population (%)
Population (%)
24
21
18
15
12
30
20
9
10
6
0.8
0.7
0.6
0.5
0.4
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
900
400
700
300
500
Offset Voltage (µV)
200
300
100
-100
-300
100
0
-100
-500
-200
-700
-300
-900
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-400
-40
140
-20
0
20
40
60
80
Temperature (°C)
D004
100
120
VCM = V–
Figure 6-3. Offset Voltage vs Temperature
Figure 6-4. Offset Voltage vs Temperature
800
800
600
600
400
400
200
0
-200
140
D003
VCM = V+
Offset Voltage (µV)
Offset Voltage (µV)
0.3
Distribution from 60 amplifiers
Distribution from 15462 amplifiers, TA = 25°C
Offset Voltage (µV)
D002
Offset Voltage Drift (µV/C)
D001
Offset Voltage (µV)
200
0
-200
-400
-400
-600
-600
-800
-8
0.2
600
480
360
240
120
0
-120
-240
-360
-480
-600
0.1
0
0
0
3
-800
-6
-4
-2
0
VCM
2
4
6
8
4
4.5
5
D005
5.5
6
VCM
6.5
7
7.5
8
D005
TA = 25°C
TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.8 Typical Characteristics (continued)
800
800
600
600
400
400
Offset Voltage (µV)
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-8
-6
-4
-2
0
VCM
2
4
6
-800
-8
8
-6
-4
D006
TA = 125°C
4
6
8
D007
600
100
500
90
400
80
200
Gain (dB) 175
Phase ( )
150
300
70
125
200
60
100
50
75
40
50
30
25
20
0
Gain (dB)
Offset Voltage (µV)
2
Figure 6-8. Offset Voltage vs Common-Mode Voltage
100
0
-100
-200
10
-25
0
-50
-400
-10
-75
-500
-20
100
-300
-600
2
4
6
8
10
12
Supply Voltage (V)
14
16
1k
18
10k
100k
Frequency (Hz)
-100
10M
1M
C002
CL = 20 pF
D008
Figure 6-9. Offset Voltage vs Power Supply
Figure 6-10. Open-Loop Gain and Phase vs Frequency
80
6
60
50
Input Bias and Offset Current (pA)
G= 1
G=1
G = 10
G = 100
G = 1000
70
Closed-Loop Gain (dB)
0
VCM
TA = –40°C
Figure 6-7. Offset Voltage vs Common-Mode Voltage
40
30
20
10
0
-10
-20
100
1k
10k
100k
Frequency (Hz)
1M
10M
C001
Figure 6-11. Closed-Loop Gain vs Frequency
18
-2
Phase ( )
Offset Voltage (µV)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
4.5
3
1.5
0
-1.5
-3
-4.5
IB
IB+
IOS
-6
-7.5
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4
Common Mode Voltage (V)
5
6
7
8
D010
Figure 6-12. Input Bias Current vs Common-Mode Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
V+
IB
IB+
IOS
125
100
V+
Output Voltage (V)
Input Bias and Offset Current (pA)
150
75
50
25
0
-25
-50
-75
V+
2V
V+
3V
V+
4V
V+
5V
V+
6V
V+
7V
V+
8V
V+
9V
V+
-100
-40
-40°C
25°C
125°C
10 V
0
-20
0
20
40
60
80
Temperature (°C)
100
120
10
20
140
D011
Figure 6-13. Input Bias Current vs Temperature
30
40
50
60
70
Output Current (mA)
80
90
100
D012
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
135
V +8V
-40°C
25°C
125°C
V +7V
CMRR
PSRR+
PSRR
120
CMRR and PSRR (dB)
V +6V
Output Voltage (V)
1V
V +5V
V +4V
V +3V
V +2V
V +1V
105
90
75
60
45
30
15
V
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
0
100
D012
1k
10k
100k
Frequency (Hz)
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
1M
10M
C003
Figure 6-16. CMRR and PSRR vs Frequency
170
130
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
135
125
120
115
110
PMOS (VCM
NMOS (VCM
V+
V+
1.5 V)
1.5 V)
105
100
95
90
85
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
165
160
155
150
145
140
-40
-20
0
D015
f = 0 Hz
20
40
60
80
Temperature (°C)
100
120
140
D016
f = 0 Hz
Figure 6-17. CMRR vs Temperature (dB)
Figure 6-18. PSRR vs Temperature (dB)
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6.8 Typical Characteristics (continued)
Input Voltage Noise Spectral Density (nV/ Hz)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
1
0.8
Amplitude (uV)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
200
100
10
1
1
Time (1s/div)
10
100
1k
Frequency (Hz)
C019
-32
C017
-20
RL = 10 k
RL = 2 k
RL = 604
RL = 128
-40
-48
-30
-40
-50
THD+N (dB)
-56
THD+N (dB)
100k
Figure 6-20. Input Voltage Noise Spectral Density vs Frequency
Figure 6-19. 0.1-Hz to 10-Hz Noise
-64
-72
-80
-60
-70
-80
-90
-88
RL = 10 k
RL = 2 k
RL = 604
RL = 128
-100
-96
-110
-104
-120
1m
-112
100
1k
Frequency (Hz)
10k
570
675
560
650
Quiescent current (µA)
700
550
540
530
520
510
575
550
525
490
475
480
14
C023
600
500
8
10
12
Supply Voltage (V)
10
625
500
6
1
Figure 6-22. THD+N vs Output Amplitude
580
4
100m
Amplitude (Vrms)
BW = 80 kHz, f = 1 kHz
Figure 6-21. THD+N Ratio vs Frequency
2
10m
C012
BW = 80 kHz, VOUT = 1 VRMS
Quiescent current (µA)
10k
16
18
450
-40
-20
0
D021
20
40
60
80
Temperature (°C)
100
120
140
D022
Figure 6-24. Quiescent Current vs Temperature
VCM = V–
Figure 6-23. Quiescent Current vs Supply Voltage
20
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
700
140
Open-loop output impedance (ohms)
Open Loop Voltage Gain (dB)
VS = 4 V
VS = 16 V
135
130
125
120
115
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D023
Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)
650
600
550
500
450
400
350
300
250
200
150
100
1k
10k
100k
Frequency (Hz)
1M
10M
C013
Figure 6-26. Open-Loop Output Impedance vs Frequency
80
60
70
50
Overshoot (%)
Overshoot (%)
60
40
30
20
40
30
20
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
50
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
0
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C007
G = –1, 10-mV output step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C008
G = 1, 10-mV output step
Figure 6-28. Small-Signal Overshoot vs Capacitive Load
60
Input
Output
Amplitude (2V/div)
Phase Margin (Degree)
50
40
30
20
10
0
Time (20us/div)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C009
Figure 6-29. Phase Margin vs Capacitive Load
C016
VIN = ±8 V; VS = VOUT = ±17 V
Figure 6-30. No Phase Reversal
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Voltage (5V/div)
Input
Output
Voltage (5V/div)
Input
Output
Time (100ns/div)
Time (100ns/div)
C018
C018
G = –10
G = –10
Figure 6-31. Positive Overload Recovery
Figure 6-32. Negative Overload Recovery
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Input
Output
Time (1µs/div)
Time (300ns/div)
C011
C010
CL = 20 pF, G = 1, 20-mV step response
CL = 20 pF, G = 1, 20-mV step response
Figure 6-34. Small-Signal Step Response, Falling
Figure 6-33. Small-Signal Step Response, Rising
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Input
Output
Time (300ns/div)
Time (300ns/div)
C005
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response (Rising)
22
C005
CL = 20 pF, G = 1
Figure 6-36. Large-Signal Step Response (Falling)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Large Signal Step Response (2V/div)
100
80
60
Output Current (mA)
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
-40
Time (2µs/div)
-20
0
C021
20
40
60
80
Temperature (°C)
100
120
140
D014
Figure 6-38. Short-Circuit Current vs Temperature
CL = 20 pF, G = –1
Figure 6-37. Large-Signal Step Response
20
-50
VS = 15 V
VS = 2.7 V
-60
16
Channel Seperation (dB)
Maximum Output Swing (V)
18
14
12
10
8
6
-70
-80
-90
-100
-110
4
-120
2
0
1k
10k
100k
Frequency (Hz)
1M
-130
100
10M
C020
Figure 6-39. Maximum Output Voltage vs Frequency
1k
10k
100k
Frequency (Hz)
1M
10M
C014
Figure 6-40. Channel Separation vs Frequency
110
100
Gain(dB)
90
80
70
60
50
40
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The TLV915x family (TLV9151, TLV9152, and TLV9154) is a family of 16-V general purpose operational
amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (21
V/µs), low power operation (560 µA, typ) and shutdown functionality make the TLV915x a robust, high-speed,
high-performance operational amplifier for industrial applications.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV915x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV915x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-1 shows the results of this testing on the TLV915x. Table 7-1 shows the EMIRR IN+ values for the TLV915x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 7-1. EMIRR Testing
Table 7-1. TLV9151 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
2.4 GHz
3.6 GHz
5 GHz
Bluetooth®,
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
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7.3.2 Thermal Protection
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV915x is 150°C.
Exceeding this temperature causes damage to the device. The TLV915x has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 170°C. Figure 7-2 shows an application example for
the TLV9151 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations
indicate that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual
device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-2 shows how
the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output
is 3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
Normal
Operation
3V
TA = 100°C
PD = 0.39W
JA = 138.7°C/W
0V
TJ = 138.7°C/W × 0.39W + 100°C
TJ = 154.1°C (expected)
16 V
Output
High-Z
150°C
TLV9151
+
–
+
RL
3V
100 –
VIN
3V
140ºC
Temperature
IOUT = 30 mA
Figure 7-2. Thermal Protection
7.3.3 Capacitive Load and Stability
55
33
50
30
45
27
40
24
Overshoot (%)
Overshoot (%)
The TLV915x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-3 and Figure 7-4. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
35
30
25
21
18
15
12
20
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
15
10
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
9
6
3
5
0
40
80
120
160 200 240
Cap Load (pF)
280
320
360
0
40
80
C008
Figure 7-3. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = 1)
120
160 200 240
Cap Load (pF)
280
320
360
C007
Figure 7-4. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-5. This resistor significantly reduces ringing
and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
26
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capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the TLV915x well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-5 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 7-5. Extending Capacitive Load Drive With the TLV9151
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7.3.4 Common-Mode Voltage Range
The TLV915x is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends
200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and
P-channel differential input pairs, as shown in Figure 7-6. The N-channel pair is active for input voltages close to
the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs
from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically
(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process
variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be
degraded compared to operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
INPMOS
PMOS
NMOS
IN+
NMOS
V-
Figure 7-6. Rail-to-Rail Input Stage
7.3.5 Phase Reversal Protection
The TLV915x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV915x is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-7. For more information on phase reversal, see Op
Amps With Complementary-Pair Input Stages application note.
Amplitude (2V/div)
Input
Output
Time (20us/div)
C016
Figure 7-7. No Phase Reversal
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7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV915x (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
–
RF
+VS
VDD
R1
RS
IN–
100
IN+
100
TLV915x
–
+
Power Supply
ESD Cell
ID
VIN
RL
+
–
VSS
+
–
–VS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV915x is approximately 500 ns.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
1
-41
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
-31
1
-21
1
-1
1
1
+1
1
0.13185% 0.00312% 0.00002%
1
1
1
+21 +31 +41 +51 +61
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,
or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ – σ to µ + σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean
(for example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV915x,
the typical input voltage offset is 125 µV, so 68.2% of all TLV915x devices are expected to have an offset from
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–125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than ±500 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV915x family has a maximum offset voltage of 675
µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely unlikely,
TI assures that any unit with larger offset than 675 µV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be
an option as a wide guardband to design a system around. In this case, the TLV915x family does not have a
maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in the
Electrical Characteristics table, it can be calculated that the 6 σ value for offset voltage drift is about 1.8 µV/°C.
When designing for worst-case system conditions, this value can be used to estimate the worst possible offset
across temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV915x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an
exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive
compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either
be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and
performance of the device is not assured when doing so.
7.3.10 Shutdown
The TLV915xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V+. The shutdown
pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the negative supply
rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid
logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage
allowed at the SHDN pins is V+. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The
typical enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a
high-impedance state. This architecture allows the TLV915xS family to operate as a gated amplifier, multiplexer,
or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load
to midsupply (VS / 2) is required. If using the TLV915xS without a load, the resulting turnoff time significantly
increases.
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7.4 Device Functional Modes
The TLV915x has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the TLV915x is 16 V (±8 V).
The TLV915xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Shutdown section for more information.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV915x family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz
bandwidth and high output drive. These features make the TLV915x a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
Figure 8-1 shows the TLV9151 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
12 V
LOAD
+
TLV9151
VOUT
–
ILOAD
RSHUNT
100 m
LM7705
RF
360 k
RG
7.5 k
Figure 8-1. TLV9151 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
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8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1.
VOUT
ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
RSHUNT
VSHUNT _ MAX
100mV
1A
ILOAD _ MAX
100m:
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV9151 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9151 to
produce the necessary output voltage is calculated using Equation 3.
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the TLV9151 to 49 V/V.
Gain 1
RF
RG
(4)
Choosing R F as 360 kΩ, R G is calculated to be 7.5 kΩ. R F and R G were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.
8.2.1.3 Application Curves
5
Output (V)
4
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 8-2. Low-Side, Current-Sense, Transfer Function
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9 Power Supply Recommendations
The TLV915x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 16 V can permanently damage the device; see the Absolute Maximum
Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to the
Layout section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 10-1. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The TLV915x is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers.
Texas Instruments, AN31 amplifier circuit collection.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV9152
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV9151 TLV9152 TLV9154
37
TLV9151, TLV9152, TLV9154
www.ti.com
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
11.6 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
38
This glossary lists and explains terms, acronyms, and definitions.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV9151 TLV9152 TLV9154
TLV9151, TLV9152, TLV9154
www.ti.com
SBOS986D – OCTOBER 2019 – REVISED MAY 2021
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLV9151 TLV9152 TLV9154
39
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV9151IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T51V
TLV9151IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1HD
TLV9151SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T91S
TLV9152IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T52F
TLV9152IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
27TT
TLV9152IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9152D
TLV9152IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T52G
TLV9152IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9152P
TLV9152SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
GSF
TLV9154IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV9154D
TLV9154IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TL9154PW
TLV9154IRUCR
ACTIVE
QFN
RUC
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I5F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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