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TMDS181, TMDS181I
SLASE75D – AUGUST 2015 – REVISED SEPTEMBER 2017
TMDS181x 6 Gbps TMDS Retimer
1 Features
3 Description
•
The TMDS181x is a digital video interface (DVI) or
high-definition multimedia interface (HDMI™) retimer.
The TMDS181x supports four TMDS channels, audio
return channel (SPDIF_IN/ARC_OUT), and digital
display control (DDC) interfaces. The TMDS181x
supports signaling rates up to 6 Gbps to allow for the
highest resolutions of 4k2k60p 24 bits per pixel and
up to WUXGA 16-bit color depth or 1080p with higher
refresh rates. The TMDS181x can be configured to
support the HDMI2.0a standard. The TMDS181x
automatically configures itself as a redriver at low
data rate ( DR < 3.4 Gbps – 150 to 300 Ω differential near end termination
DR < 2 Gbps – no termination
Note: If left floating will be in automatic select mode.
SWAP/POL
1
I
3 level
Input lane SWAP and polarity control pin
SWAP/POL = H: receive lanes polarity swap (retimer mode only)
SWAP/POL = L: receive lanes swap (redriver and retimer mode)
SWAP/POL = No Connect: normal operation
18, 40
NA
NC
No connect
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
Supply voltage (3)
VCC
–0.3
4
VDD
–0.3
1.4
VCC - 0.75V
VCC + 0.3V
TMDS outputs ( OUT_Dx)
–0.3
4
HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0,
I2C_EN/PIN, SIG_EN, TX_TERM_CTL,
–0.3
4
HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC
–0.3
6
Main link input differential voltage (IN_Dx, IN_CLKx) IIN = 15mA
Voltage
Input Current IIN
Main link input current (IN_Dx, IN_CLKx)
15
Continuous power dissipation
Tstg
(1)
(2)
(3)
MAX
UNIT
V
V
mA
See Thermal Information
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
±500
UNIT
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
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SLASE75D – AUGUST 2015 – REVISED SEPTEMBER 2017
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VCC
Supply voltage nominal value 3.3 V
3.135
3.3
3.465
VDD
Supply voltage nominal value 1.2 V
1.1
1.2
1.27
V
TCASE
Case temperature
92.7
°C
TA
Operating free-air
temperature
TMDS181
0
85
°C
TMDS181I
–40
85
°C
75
1560
mVpp
VCC – 0.4
VCC +
0.1
V
MAIN LINK DIFFERENTIAL PINS
VID_PP
Peak-to-peak input differential voltage
VIC
Input common mode voltage
dR
Data rate
RVSADJ
TMDS compliant swing voltage bias resistor nominal
0.25
4.5
6
7.06
Gbps
kΩ
CONTROL PINS
VI-DC
DC input voltage
VIL (1)
Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL
pins only
Control pins
–0.3
0.3
Low-level input voltage at OE
0.8
VIM (1)
Mid-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL
pins only
VIH (1)
High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL,
OE (2) pins only
VOL
Low-level output voltage
VOH
High-level output voltage
2.4
IIH
High-level input current
IIL
1
3.6
1.2
1.4
2.6
V
V
V
V
0.4
V
–30
30
µA
Low-level input current
–25
25
µA
IOS
Short-circuit output current
–50
50
mA
IOZ
High impedance output current
ROEPU
Pullup resistance on OE pin
(1)
(2)
150
V
10
µA
250
kΩ
These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the
internal bias to the proper voltage level which will not match the values shown here.
This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup
resistor will set OE pin properly, but may have a different value than shown due to internal biasing.
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SLASE75D – AUGUST 2015 – REVISED SEPTEMBER 2017
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6.4 Thermal Information
TMDS181x
THERMAL METRIC (1) (2)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
31.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.2
°C/W
RθJB
Junction-to-board thermal resistance
8.1
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
8.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.2
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Test conditions for ΨJB and ΨJT are clarified in the Semiconductor and IC Package Thermal Metrics.
6.5 Power Supply Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX (2)
UNIT
800
900
mW
PD1 (3) (4)
Device power dissipation
(retimer operation)
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern, VI = 3.3 V,
I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= NC,
SDA_CTL/CLK_CTL = 0 V
PD2 (3) (4)
Device power dissipation
(redriver operation)
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 2.97 Gbps TMDS pattern, VI = 3.3 V,
I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= H,
SDA_CTL/CLK_CTL = 0 V
500
600
mW
PSD1 (3) (4) (5)
Device power in standby
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V, HPD = H, No
valid input signal
50
100
mW
Device power in power down
OE = L, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
10
30
mW
ICC1 (3) (4)
VCC supply current (TMDS
6Gpbs retimer mode)
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC,
SDA_CTL/CLK_CTL = 0 V
131
150
mA
IDD1 (3) (4)
VDD supply current (TMDS
6Gpbs retimer mode)
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC,
SDA_CTL/CLK_CTL = 0 V
332
350
mA
ICC2 (3) (4)
VCC supply current (TMDS
6Gpbs redriver mode)
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 2.97 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H,
SDA_CTL/CLK_CTL = 0 V
92
mA
IDD2 (3) (4)
VDD supply current (TMDS
6Gpbs redriver mode)
OE = H, VCC= 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H,
SDA_CTL/CLK_CTL = 0 V
187
mA
Standby current
OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2
V/1.27 V, HPD = H: No valid signal on
IN_CLK
3.3 V rail (3)
ISD1 (5)
ISD2 (5)
Power-down current
OE = L, VCC = 3.3 V/3.465 V, VDD = 1.2
V/1.27 V
3.3 V rail (3)
PSD2
(1)
(2)
(3)
(4)
(5)
8
(3) (4) (5)
1.2 V rail
1.2 V rail
6
15
40
50
2
5
3.5
15
mA
mA
The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature unless otherwise noted
The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted
ICC is a direct result of the source design as the TMDS181x integrated receive termination resistor accounts for 85 to 110 mA.
IDD is impacted by ARC usage. Connecting a 500 kΩ resistor to GND at SPDIF reduces the value by more than 20 mA
The measurements were made with no active source connected.
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SLASE75D – AUGUST 2015 – REVISED SEPTEMBER 2017
6.6 TMDS Differential Input Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX (2)
UNIT
DR_RX_DATA_R TMDS data lanes data rate
(Retimer Mode)
T
0.25
6
Gbps
DR_RX_DATA_R TMDS data lanes data rate
(Redriver Mode)
D
0.25
3.4
Gbps
340
MHz
DR_RX_CLK
TMDS clock lanes clock rate
tRX_DUTY
Input clock duty circle
tCLK_JIT
Input clock jitter tolerance
tDATA_JIT
Input data jitter tolerance
Test the TTP2, see Figure 12
tRX_INTRA
Input intrapair skew tolerance
Test at TTP2 when DR = 1.6 Gbps, see
Figure 12
tRX_INTER
Input interpair skew tolerance
EQH(D)
Fixed EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0 = H; fixed EQ gain, test at 6
Gbps
15
dB
EQL(D)
Fixed EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0 = L; fixed EQ gain, test at 6
Gbps
7.5
dB
EQZ(D)
Adaptive EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0 = NC; adaptive EQ
(Retimer Mode Only)
EQ(c)
EQ gain for clock lane IN_CLKn/p
EQ_SEL/A0 = H,L,NC
RINT
Input differential termination
impedance
VITERM
Input termination voltage
(1)
(2)
25
40%
50%
60%
0.3
Tbit
150
ps
112
ps
1.8
2
15
3
85
OE = H
ns
dB
dB
100
115
Ω
3.3
3.465
V
The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted
The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
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6.7 TMDS Differential Output Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
VSWING_DA
VSWING_CLK
TEST CONDITIONS
TYP (1)
MAX (2)
Single-ended high level output
PRE_SEL = NC; TX_TERM_CTL = H; OE
voltage
= H; DR = 750 Mbps; VSadj = 7.06 kΩ;
Data rate ≤1.65 Gbps
VCC – 10
VCC + 10
Single-ended high level output
voltage
PRE_SEL = NC; TX_TERM_CTL = NC;
Data rate >1.65 Gbps and
OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;
3.4 Gbps and < 6
= H; DR = 6 Gbps; VSadj = 7.06 kΩ;
(2)
Gbps
VCC – 400
VCC + 10
Single-ended low level output
voltage
Data rate ≤1.65 Gbps
PRE_SEL = NC; TX_TERM_CTL = H; OE
= H; DR = 750 Mbps; VSadj = 7.06 kΩ;
VCC – 600
VCC – 400
Single-ended low level output
voltage
Data rate >1.65 Gbps and
3.4 Gbps and < 6
Gbps (2)
PRE_SEL = NC; TX_TERM_CTL = L; OE
= H; DR = 6 Gbps; VSadj = 7.06 kΩ;
VCC – 1000
VCC – 400
Single-ended output voltage
swing on data lane
PRE_SEL = NC; TX_TERM_CTL =
H/NC/L; OE = H; DR = 270 Mbps/2.97/6
Gbps VSadj = 7.06 kΩ;
400
500
600
PRE_SEL = NC; TX_TERM_CTL = H; OE
= H; Data rate ≤ 3.4 Gbps; VSadj = 7.06
kΩ;
400
500
600
PRE_SEL = NC; TX_TERM_CTL = NC;
OE = H; Data rate > 3.4 Gbps; VSadj =
7.06 kΩ;
200
Single-ended output voltage
swing on clock lane
ΔVSWING
Change in single-end output
voltage swing per 100 Ω
ΔVSadj
ΔVOCM(SS)
Change in steady state output
common mode voltage
between logic levels
VOD(PP)
Output differential voltage
before pre-emphasis
VOD(SS)
Steady state output differential VSADJ = 7.06 kΩ; PRE_SEL = L, see
voltage
Figure 11
VOD_range
MIN
Total TMDS data lanes output
differential voltage for
HDMI2.0. Retimer Mode Only
See Figure 14
V
V
mV
mV
300
400
20
VSADJ = 7.06 kΩ; PRE_SEL = NC see
Figure 10
UNIT
mV
–5
5
mV
800
1200
mV
600
1075
mV
3.4 Gbps < Rbit ≤ 3.712 Gps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H; VSadj = 7.06 kΩ;
335
3.712 Gbps < Rbit < 5.94 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H; VSadj = 7.06 kΩ;
–19.66 ×
(Rbit2) +
(106.74 × Rbit)
+ 209.58
5.94 Gbps ≤ Rbit ≤ 6.0 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H; VSadj = 7.06 kΩ;
150
mV
IOS
Short-circuit current limit
Main link output shorted to GND
50
mA
ILEAK
Failsafe condition leakage
current
VCC = 0 V; VDD = 0 V; TMDS Outputs
pulled to 3.3 V through 50 Ω resistor;
45
μA
RTERM
Source termination resistance
for HDMI2.0
150
Ω
(1)
(2)
10
75
The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted
The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
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6.8 DDC, I2C, HPD, and ARC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX (2)
UNIT
2
DDC AND I C
VI-DC
VIL
SCL/SDA_SNK, SCL/SDA_SRC DC
input voltage
–0.3
5.5
V
SCL/SDA_CTL, DC input voltage
–0.3
3.6
V
SCL/SDA_SNK, SCL/SDA_SRC Low
level input voltage
0.3 x VCC
V
SCL/SDA_CTL Low level input
voltage
0.3 x VCC
V
SCL/SDA_SNK, SCL/SDA_SRC high
level input voltage
VIH
SCL/SDA_CTL high level input
voltage
3
V
0.7 x VCC
V
I0 = 3 mA and VCC > 2 V
0.4
I0 = 3 mA and VCC < 2 V
0.2 x VCC
VOL
SCL/SDA_CTL, SCL/SDA_SRC low
level output voltage
fSCL
SCL clock frequency fast I2C mode
for local I2C control
400
kHz
Cbus
Total capacitive load for each bus line
(DDC and local I2C pins)
400
pF
V
HPD
VIH
High-level input voltage
HPD_SNK
VIL
Low-level input voltage
HPD_SNK
VOH
High-level output voltage
IOH = –500 µA; HPD_SRC,
VOL
Low-level output voltage
IOL = 500 µA; HPD_SRC,
Failsafe condition leakage current
VCC = 0 V; VDD = 0 V; HPD_SNK =
5 V;
Device powered; VIH = 5 V;
IH_HPD includes RpdHPD resistor
current
40
Device powered; VIL = 0.8 V;
IL_HPD includes RpdHPD resistor
current
30
ILEAK
IH_HPD
RpdHPD
High-level input current
HPD input termination to GND
VCC = 0 V
2.1
V
0.8
V
2.4
3.6
V
0
0.1
V
40
μA
µA
150
190
220
kΩ
SPDIF AND ARC
VEL
Operating DC voltage for single mode
Test at ARC_OUT, see Figure 22
ARC output
VIN_DC
Operating DC voltage for SPDIF input
VSP_SW
Signal amplitude of SPDIF input
VElSWING
Signal amplitude on the ARC output
Test at ARC_OUT, 55 Ω external
termination resistor, see Figure 22
CLK_ARC
Signal frequency on ARC
Test at ARC_OUT, see Figure 22
Duty cycle
Output clock duty cycle
Data rate
SPDIF input DR
tEDGE
Rise/fall time for ARC output
R_IN_SPDIF
Input termination resistance for
SPDIF
Rest
Single mode output termination
resistance
(1)
(2)
0
5
V
0.05
V
0.2
0.5
0.6
V
0.4
0.5
0.6
V
3.687
5.645
±0.1%
13.517
45%
50%
55%
7.373
11.29
27.034
From 10% to 90% voltage level
0.4
75
0.1 MHz to 128× the maximum
frame rate
36
55
MHz
Mbps
UI
Ω
75
Ω
The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted
The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
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6.9 Power-Up and Operation Timing Requirements
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
NOM
UNIT
200
µs
td1
VDD stable before VCC
td2
VDD and VCC stable before OE assertion
td3
CDR active operation after retimer mode initial
15
ms
td4
CDR turn off time after retimer mode de-assert
120
ns
VDD_ramp
VDD supply ramp up requirements
100
ms
VCC_ramp
VCC supply ramp up requirements
100
ms
(1)
0
MAX
100
µs
See Operation Timing for more information
td2
OE
VCC / VDD
td1
VDD / VCC
Figure 1. Power-Up Timing for TMDS181
td3
CDR Active
td4
Retimer mode
OE De-assert or
HPD_SNK De-assert or
Redriver mode
Figure 2. CDR Timing for TMDS181
12
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6.10 TMDS Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX (2)
UNIT
REDRIVER MODE
dR
Data rate (redriver mode)
250
3400
Mbps
tPLH
Propagation delay time (low to
high)
250
600
ps
tPHL
Propagation delay time (high to
low)
250
800
ps
tT1(1.4b)
Transition time (rise and fall
time); measured at 20% and
80% levels for data lanes.
TMDS clock meets tT3 for all
three times.
tT3
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H; 1.48 Gbps and 2.97 Gbps data
lines, 148 MHz and 297 MHz clock
75
ps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H; 1.48 Gbps, 2.97 Gbps
100
ps
tSK_INTRA
Intra-pair output skew
Default setting for internal intra-pair skew
adjust, TX_TERM_CTL = NC; PRE_SEL =
NC; 1.48 Gbps, 2.97 Gbps; See Figure 8
40
ps
tSK_INTER
Inter-pair output skew
Default setting for internal inter-pair skew
adjust, TX_TERM_CTL = NC; PRE_SEL =
NC; 1.48 Gbps, 2.97 Gbps; See Figure 8
100
ps
tJITD1(1.4b)
Total output data jitter
HDMI1.4b
DR = 2.97 Gbps, PRE_SEL = NC,
EQ_SEL/A0 = NC ; . See Figure 12 at
TTP3
0.2
Tbit
tJITC1(1.4b)
Total output clock jitter
CLK = 25 MHz, 74.25 MHz, 75 MHz, 150
MHz, 297 MHz
0.25
Tbit
RETIMER MODE
dR
Data rate (retimer mode)
dXVR
Automatic redriver to retimer
crossover (when selected)
fCROSSOVER
Crossover frequency hysteresis
PLLBW
Data retimer PLL bandwidth
tACQ
Input clock frequency detection
and retimer acquisition time
IJT1
Input clock jitter tolerance
tT1(2.0)
tT1
(1.4b)
Transition time (rise and fall
time); measured at 20% and
80% levels for data lanes.
TMDS clock meets tT3 for all
three times.
tT3
tDCD
0.25
Measured with input signal applied = 200
mVpp
0.75
1
6
Gbps
1.25
Gbps
250
Default loop bandwidth setting
0.4
MHz
1
180
Tested when data rate >1.0Gbps
MHz
µs
0.3
Tbit
TX_TERM_CTL = L; PRE_SEL = NC; 6
Gbps data lines,
45
ps
TX_TERM_CTL = NC; PRE_SEL = NC;
1.48 Gbps and 2.97 Gbps data lines, 148
MHz and 297 MHz clock
75
ps
TX_TERM_CTL = NC; PRE_SEL = NC;
1.48 Gbps, 2.97 Gbps, 6 Gbps data lines,
148 MHz, 297 MHz clock
100
ps
OUT_CLK ± duty cycle
40%
50%
60%
Inter-pair output skew
Default setting for internal inter-pair skew
adjust, TX_TERM_CTL = NC; PRE_SEL =
NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data
lines, 148 MHz, 297 MHz clock; See
Figure 8
0.2
Tch
tSK_INTRA
Intra-pair output skew
Default setting for internal intra-pair skew
adjust, TX_TERM_CTL = NC; PRE_SEL =
NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data
lines, 148 MHz, 297 MHz clock; See
Figure 8
0.15
Tbit
tJITC1(1.4b)
Total output clock jitter
CLK = 25 MHz, 74.25 MHz, 75 MHz, 150
MHz, 297 MHz
0.25
Tbit
tSK_INTER
(1)
(2)
The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted
The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
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TMDS Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tJITC1(2.0)
Total output data jitter
See Figure 14
tJITD2
TEST CONDITIONS
MIN
TYP (1)
MAX (2)
DR = 6 Gbps: CLK = 150 MHz
0.3
3.4 Gbps < Rbit ≤ 3.712 Gps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H
0.4
3.712 Gbps < Rbit < 5.94 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H
–0.0332Rbit2 +
0.2312Rbit +
0.1998
5.94 Gbps ≤ Rbit ≤ 6.0 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC;
OE = H
0.6
UNIT
Tbit
Tbit
6.11 HPD Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPD(HPD)
Propagation delay from HPD_SNK to
HPD_SRC; rising edge and falling edge (2)
See Figure 16; not valid during
switching time
tT(HPD)
HPD logical disconnected timeout
See Figure 17
(1)
(2)
MIN
TYP (1)
MAX (2)
40
120
2
UNIT
ns
ms
The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted
The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
6.12 DDC and I2C Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
UNIT
300
ns
300
ns
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tHIGH
Pulse duration, SCL high
tLOW
Pulse duration, SCL low
1.3
μs
tSU1
Setup time, SDA to SCL
100
ns
Setup time, SCL to start condition
0.6
μs
tHD,STA
Hold time, start condition to SCL
0.6
μs
tST,STO
Setup time, SCL to stop condition
0.6
μs
t(BUF)
Bus free time between stop and start condition
1.3
μs
tPLH1
Source to sink: 100kbps pattern;
Propagation delay time, low-to-high-level output
Cb(Sink) = 400 pF (1); see Figure 20
360
ns
tPHL1
Propagation delay time, high-to-low-level output
230
ns
tPLH2
Sink to source: 100kbps pattern;
Propagation delay time, low-to-high-level output
Cb(Source) = 100 pF (1); see Figure 21
250
ns
tPHL2
Propagation delay time, high-to-low-level output
200
ns
tST,
(1)
14
STA
VCC = 3.3 V
MAX
0.6
μs
Cb = total capacitance of one bus line in pF.
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6.13 Typical Characteristics
350
200
325
180
300
275
Current (mA)
Current (mA)
160
140
120
1.2V
3.3V
100
250
225
200
1.2V
3.3V
175
150
125
80
100
60
75
50
40
0
0.5
1
1.5
2
Data Rate (Gbps)
2.5
3
0
3.5
0.5
1
1.5
2
D001
Figure 3. Current vs Data Rate Redriver Mode
2.5 3 3.5 4
Data Rate (Gbps)
4.5
5
5.5
6
D002
Figure 4. Current vs Data Rate Retimer Mode
1600
1400
VOD (mV)
1200
1000
800
600
400
VOD No Term
VOD 150 to 300 :
VOD 75 to 150 :
200
0
4
4.5
5
5.5
6
6.5
VSADJ (k:)
7
7.5
8
D003
Figure 5. VSADJ vs VOD
7 Parameter Measurement Information
VCC
3.3 V
50 Ÿ
50 Ÿ
50 Ÿ
50 Ÿ
0.5 pF
D+
VD+
VID
Receiver
Driver
Dt
VD±
Y
VY
Z
VID = VD+ ± VD±
VOD = VY ± VZ
VICM = (VD+ + VD±)
2
VOC = (VY + VZ)
2
VZ
Figure 6. TMDS Main Link Test Circuit
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Parameter Measurement Information (continued)
4.0 V
VCC
VID
2.6 V
VID+
VID(pp)
0V
VID±
tPHL
tPLH
80%
80%
VOD
VOD(pp)
0V
20%
tf
20%
tr
Figure 7. Input/Output Timing Measurements
tSK_INTRA
tSK_INTRA
TMDS_OUTxp
50%
TMDS_OUTxn
tSK_INTER
TMDS_OUTyp
TMDS_OUTyn
Figure 8. TMDS Output Skew Measurements
VOC
ûVOC(SS)
Figure 9. HDMI/DVI TMDS Output Common Mode Measurement
16
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Parameter Measurement Information (continued)
VOD(PP)
PRE_SEL=Z
Vsadj = 7.06 DR < 3.4 Gbps – 150 Ω to 300 Ω differential near-end termination
•
DR < 2 Gbps – No termination
8.3.10 TMDS Outputs
A 1% precision resistor, 7.06 kΩ, is recommended to be connected from VSADJ pin to ground to allow the
differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10
mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.
AVCC
VCC
TMDS181
Zo = RT
Zo = RT
TMDS DRIVER
TMDS RECEIVER
Figure 28. TMDS Driver and Termination Circuit
Referring to Figure 28, if VCC (TMDS181 supply) and AVCC (sink termination supply) are both powered, the
TMDS output signals are high impedance when OE = high. The normal operating condition is that both supplies
are active. Refer to Figure 28, if VCC is on and AVCC is off, the TMDS outputs source a typical 5-mA current
through each termination resistor to ground. A total of 33 mW of power is consumed by the terminations
independent of the OEB logical selection. When AVCC is powered on, normal operation (OE controls output
impedance) is resumed. When the power source of the device is off and the power source to termination is on,
the IO(off) output leakage current specification ensures the leakage current is limited to 45 μA or less. The VOD of
the clock and data lanes can be reduced through I2C. See Table 12 for details. Figure 3 shows the different
output voltages based on the different VSADJ settings.
8.3.11 Pre-Emphasis/De-Emphasis
The TMDS181 provides de-emphasis as a way to compensate for ISI loss between the TMDS181 outputs to a
TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL
pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal
pre-conditioning to offset interconnect losses from the TMDS181 device to the TMDS receiver. De-emphasis is
recommended to be set at 0 dB while connecting to a receiver through short PCB route. When pulled to ground
though a 65 kΩ resistor - 2 dB can be realized, see Figure 11. When using I2C, reg0Ch[1:0] is used to make
these adjustments.
As there are times that true pre-emphasis may be the best solution there are two ways to accomplish this. If pin
strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the VOD swing
and then pulling the PRE_SEL pin to ground using the 65 kΩ resistor, see Figure 29. If using I2C there are two
methods to accomplish this. The first is similar to pin strapping by reducing the VSADJ resistor value and then
implementing - 2 dB de-emphasis. The second method is to set reg0Ch[7:5] = 011 and set reg0Ch[1:0] = 01
which will accomplish the same pre-emphasis setting, see Figure 30.
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NOTE
De-emphasis is only implement able during retimer mode. In redriver mode this function is
not available.
PRE_SEL = Z
Vsadj = 7.06
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