TMS320DM6437
Digital Media Processor
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
1 TMS320DM6437 Digital Media Processor
1.1 Features
•
•
•
•
High-Performance Digital Media Processor
(DM6437)
– 2.5-, 2.-, 1.67-, 1.51-, 1.43-ns Instruction
Cycle Time
– 400-, 500-, 600, 660-, 700-MHz C64x+™
Clock Rate
– Eight 32-Bit C64x+ Instructions/Cycle
– 3200, 4000, 4800, 5280, 5600 MIPS
– Fully Software-Compatible With C64x
– Commercial and Automotive (Q or S suffix)
Grades
– Low-Power Device (L suffix)
VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Auto-Focus Module Operation
C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality
– C64x+ Extensions
• Compact 16-bit Instructions
• Additional Instructions to Support
Complex Multiplies
C64x+ L1/L2 Memory Architecture
– 256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
•
•
•
– 640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
– 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
Supports Little Endian Mode Only
Video Processing Subsystem (VPSS)
– Front End Provides:
• CCD and CMOS Imager Interface
• BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
• Preview Engine for Real-Time Image
Processing
• Glueless Interface to Common Video
Decoders
• Histogram Module
• Auto-Exposure, Auto-White Balance and
Auto-Focus Module
• Resize Engine
– Resize Images From 1/4x to 4x
– Separate Horizontal/Vertical Control
– Back End Provides:
• Hardware On-Screen Display (OSD)
• Four 54-MHz DACs for a Combination of
– Composite NTSC/PAL Video
– Luma/Chroma Separate Video
(S-video)
– Component (YPbPr or RGB) Video
(Progressive)
• Digital Output
– 8-/16-bit YUV or up to 24-Bit RGB
– HD Resolution
– Up to 2 Video Windows
External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
• Supports up to 333-MHz (data rate) Bus
and Interfaces With DDR2-400 SDRAM
– Asynchronous 8-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
• Flash Memory Interfaces
– NOR (8-Bit-Wide Data)
– NAND (8-Bit-Wide Data)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
•
•
•
•
•
•
•
•
•
•
•
2
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
Two UARTs (One with RTS and CTS Flow
Control)
Master/Slave Inter-Integrated Circuit (I2C
Bus™)
Two Multichannel Buffered Serial Ports
(McBSPs)
– I2S and TDM
– AC97 Audio Codec Interface
– SPI
– Standard Voice Codec Interface (AIC12)
– Telecom Interfaces – ST-Bus, H-100
– 128 Channel Mode
Multichannel Audio Serial Port (McASP0)
– Four Serializers and SPDIF (DIT) Mode
16-Bit Host-Port Interface (HPI)
High-End CAN Controller (HECC)
32-Bit 33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
10/100 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
TMS320DM6437 Digital Media Processor
www.ti.com
•
•
•
•
•
•
•
•
•
•
•
•
– Supports Media Independent Interface (MII)
– Management Data I/O (MDIO) Module
VLYNQ™ Interface (FPGA Interface)
Three Pulse Width Modulator (PWM) Outputs
On-Chip ROM Bootloader
Individual Power-Savings Modes
Flexible PLL Clock Generators
IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
Up to 111 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
Packages:
– 361-Pin Pb-Free PBGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
– 376-Pin Plastic BGA Package
(ZDU Suffix), 1.0-mm Ball Pitch
0.09-µm/6-Level Cu Metal Process (CMOS)
3.3-V and 1.8-V I/O, 1.2-V Internal
(-7/-6/-5/-4/-L/-Q6/-Q5/-Q4)
3.3-V and 1.8-V I/O, 1.05-V Internal
(-7/-6/-5/-4/-L/-Q5)
Applications
– Digital Media
– Networked Media Encode/Decode
– Video Imaging
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Digital Media Processor
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
1.2 Description
The TMS320C64x+™ DSPs (including the TMS320DM6437 device) are the highest-performance
fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6437 device is based on the
third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture
developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media
applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the
C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction
set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS. For more details
on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6437 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6437 core uses a two-level
cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory
space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D)
consists of a 640K-bit memory space —384K-bit of which is mapped memory and 256K-bit of which can
be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be
configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a
management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an
inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel
audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2
independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up
to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes,
multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse
width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; 1
peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an
asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed
synchronous memory interface for DDR2.
The DM6437 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging
peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing
Back-End (VPBE) output.
The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine
(Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The
CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices
(CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS
sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules
provide statistical information on the raw color data for use by the DM6437. The Resizer accepts image
data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is
between 64 and 1024.
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TMS320DM6437
Digital Media Processor
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The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a
Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate
OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window
allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz,
providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC
also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of
8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6437 and
the network. The DM6437 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)
and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)
support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow DM6437 to easily control peripheral devices and/or communicate with
host processors.
The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a
harsh environment to communicate serially with other controllers, typically in automotive applications.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The DM6437 has a complete set of development tools. These include C compilers, a DSP assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
4
TMS320DM6437 Digital Media Processor
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Digital Media Processor
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1.3
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the DM6437 device.
BT.656,
Y/C,
Raw (Bayer)
JTAG Interface
16b
System Control
Input
Clock(s)
Video Processing Subsystem (VPSS)
DSP Subsystem
OSC
Front End
C64x+ t DSP CPU
PLLs/Clock Generator
128 KB L2 RAM
32 KB
L1 Pgm
Power/Sleep Controller
Pin Multiplexing
Back End
Resizer
CCD
Controller Histogram/
3A
Video
Preview
Interface
80 KB
L1 Data
8b BT.656,
Y/C,
24b RGB
On-Screen Video 10b DAC
Display Encoder 10b DAC
(OSD)
(VENC) 10b DAC
10b DAC
Boot ROM
NTSC/
PAL,
S-Video,
RGB,
YPbPr
Switched Central Resource (SCR)
Peripherals
Serial Interfaces
McASP
McBSP
I2 C
System
HECC
UART
GeneralPurpose
Timer
Watchdog
Timer
PWM
GPIO
EDMA
Program/Data Storage
Connectivity
PCI
(33 MHz)
VLYNQ
EMAC
With
MDIO
HPI
DDR2
Mem Ctlr
(32b)
Async EMIF/
NAND/
(8b)
Figure 1-1. TMS320DM6437 Functional Block Diagram
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Contents
1
TMS320DM6437 Digital Media Processor ........... 1
1.1
Features .............................................. 1
1.2
Description ............................................ 3
1.3
Functional Block Diagram ............................ 5
6
Revision History ............................................... 7
2 Device Overview ......................................... 8
2.1
Device Characteristics ................................ 8
2.2
CPU (DSP Core) Description ......................... 9
2.3
C64x+ CPU.......................................... 12
2.4
Memory Map Summary
2.5
2.6
2.7
2.8
2.9
3
4
6
Power Supplies .................................... 163
Enhanced Direct Memory Access (EDMA3)
Controller ........................................... 170
6.5
Reset ............................................... 183
6.6
........
Clock PLLs .........................................
Interrupts ...........................................
External Memory Interface (EMIF) .................
Video Processing Sub-System (VPSS) Overview .
6.8
25
6.9
70
6.10
6.11
Device and Development-Support Tool
Nomenclature ....................................... 70
Documentation Support ............................. 72
3.2
Power Considerations ............................... 74
3.3
Clock Considerations ................................ 77
3.4
Boot Sequence ...................................... 80
3.5
Configurations At Reset ............................. 92
3.6
Configurations After Reset .......................... 95
3.7
Multiplexed Pin Configurations ...................... 99
3.8
Device Initialization Sequence After Reset ........ 152
3.9
Debugging Considerations ......................... 154
Absolute Maximum Ratings Over Operating
Temperature Range (Unless Otherwise Noted) ... 158
Recommended Operating Conditions ............. 159
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) ........... 160
7
194
200
203
211
Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 234
Inter-Integrated Circuit (I2C) ....................... 237
Host-Port Interface (HPI) Peripheral ............... 241
6.14
6.15
Multichannel Buffered Serial Port (McBSP)........ 246
Multichannel Audio Serial Port (McASP0)
Peripheral .......................................... 256
High-End Controller Area Network Controller
(HECC) ............................................. 264
Ethernet Media Access Controller (EMAC) ........ 270
..........
6.19 Timers ..............................................
6.20 Peripheral Component Interconnect (PCI) .........
6.21 Pulse Width Modulator (PWM).....................
6.22 VLYNQ .............................................
6.23 General-Purpose Input/Output (GPIO).............
6.24 IEEE 1149.1 JTAG .................................
Mechanical Data.......................................
7.1
Thermal Data for ZWT .............................
7.1.1 Thermal Data for ZDU .............................
7.1.2 Packaging Information.............................
6.18
Device Operating Conditions....................... 158
192
6.13
6.17
System Interconnect Block Diagram ............... 156
External Clock Input From MXI/CLKIN Pin
6.12
6.16
System Interconnect ................................. 156
Contents
6.3
6.4
6.7
System Module Registers ........................... 73
5.2
5.3
Parameter Information ............................. 162
Recommended Clock and Control Signal Transition
Behavior............................................ 163
17
3.1
5.1
6.1
6.2
13
Device Configurations................................. 73
4.1
5
.............................
Pin Assignments ....................................
Terminal Functions ..................................
Device Support ......................................
Peripheral Information and Electrical
Specifications ......................................... 162
Management Data Input/Output (MDIO)
277
278
281
287
289
293
297
299
299
300
300
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the SPRS345C device-specific
data manual to make it an SPRS345D revision.
Scope: Applicable updates to the TMS320DM643x DMP, specifically relating to the TMS320DM6437
device, have been incorporated.
• Added 660- and 700-MHz C64x+™ device speeds.
• Added designators for low-power (-L) devices.
SEE
Global
ADDITIONS/MODIFICATIONS/DELETIONS
•
•
Updated/Changed signal name from "C_WE" to "C_WE"
Updated/Changed signal name from "C_WEN" to "C_WE"
Section 1.1
Added "5280, 5600 MIPS" to "High-Performance Digital Signal Processor (DM6437)" bullet
Section 1.2
•
Section 2.6
Table 2-24, Multichannel Audio Serial Port (McASP0) Terminal Functions:
• Updated/Changed AFSR0/DR0/GP[100] pin description from "... frame synchronization AFSX0..." to
"...frame synchronization AFSR0..."
• Updated/Changed AFSX0/DX1/GP[107] pin description from "...frame synchronization AFSR0..." to
"...frame synchronization AFSX0..."
In first paragraph, updated/changed the following:
– First sentence from "With performance up to 4800 million instructions per second (MIPS) at a clock
rate of 600 MHz..." to "With performance up to 5600 million instructions per second (MIPS) with a
clock rate of 700 MHz..."
– Fifth sentence from "The DSP core can produce...for a total of 2400 million MACs per second...or a
total of 4800 MMACS."to "The DSP core can produce...for a total of 2800 million MACs per
second...or a total of 5600 MMACS."
Table 2-21, DAC [Part of VPBE] Terminal Functions:
• Updated/Changed VDDA_1P1V description
Section 2.8
Updated/Changed Figure 2-10, Device Nomenclature, to reflect new device speeds and low-power
designator (-L suffix).
Section 5
Added footnote to Section 5.1, Absolute Maximum Ratings Over Operating Temperature Range (Unless
Otherwise Noted).
Section 5
Updated/Changed ICDD and IDDD test conditions and footnote in Section 5.3, Electrical Characteristics Over
Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted).
Section 6.7.1
Section 5.2
Table 6-15, PLLC1 Clock Frequency Ranges:
• Updated/Changed PLLOUT 1.2V-CVDD max value from "700 MHz" to "600 MHz" for
-6/-5/-4/-L/-Q6/-Q5/-Q4 devices.
• Updated/Changed SYSCLK1 1.05V-CVDD max value from "560 MHz" to "520 MHz" for -7 devices.
Deleted "Future variants..." footnote from table
Section 6.7.1
Updated/Changed sentence from "TI requires EMI filter manufacturer Murata..." to "TI recommends EMI
filter manufacturer Murata..."
Section 6.7.4
Deleted "(-4, -4Q, -4S, -5, -5Q, -5S, -6)" from Table 6-19 title, Timing Requirements for MXI/CLKIN.
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TMS320DM6437
Digital Media Processor
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2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the TMS320DM6437 DSP. The tables show significant features of the
DM6437 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
Table 2-1. Characteristics of the DM6437 Processor
HARDWARE FEATURES
DM6437
DDR2 Memory Controller
(16-/32-bit bus width) [1.8 V I/O]
Asynchronous EMIF [EMIFA]
EDMA3
1 (64 independent channels, 8 QDMA channels)
Timers
2 64-bit General Purpose
(configurable as 2 64-bit or 4 32-bit)
1 64-bit Watch Dog
UARTs
2 (one with RTS and CTS flow control)
I2C
Peripherals
Not all peripherals pins
are available at the same
time (For more detail, see
the Device Configurations
section).
1 (Master/Slave)
McBSPs
2
McASP
1 (4 serailizers)
10/100 Ethernet MAC (EMAC) with
Management Data Input/Output (MDIO)
VLYNQ
General-Purpose Input/Output Port (GPIO)
PWM
1
1
Up to 111 pins
3 outputs
HPI (16-bit)
1
PCI (32-bit), [33-MHz]
1
Configurable Video Ports
HECC
On-Chip Memory
Asynchronous (8-bit bus width),
RAM, Flash, (8-bit NOR or 8-bit NAND)
1 Input (VPFE)
1 Output (VPBE)
1
Size (Bytes)
240KB RAM, 64KB ROM
Organization
32K-Byte (32KB) L1 Program (L1P) RAM/Cache
(Cache up to 32KB)
80KB L1 Data (L1D) RAM/Cache (Cache up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
64KB Boot ROM
MegaModule Rev ID
Revision ID Register (MM_REVID.[15:0])
(address location: 0x0181 2000)
CPU ID + CPU Rev ID
Control Status Register (CSR.[31:16])
See the TMS320DM6437/35/33/31 Digital Media
Processor (DMP) [Silicon Revisions 1.1 and 1.0]
Silicon Errata (literature number SPRZ250).
JTAG BSDL_ID
JTAGID register
(address location: 0x01C4 0028)
See Section 6.24.1, JTAG ID (JTAGID) Register
Description(s)
CPU Frequency (1) (2)
Cycle Time
(1)
(2)
8
(1) (2)
MHz
ns
700 (-7)
660 (-Q6)
600 (-6/-L)
500 (-5/-Q5)
400 (-4/-Q4)
2.5 ns (-4/-Q4)
2 ns (-5/-Q5)
1.67 ns (-6/-L)
1.51 ns (-Q6)
1.43 ns (-7)
Performance numbers assume core voltage is set to 1.2V.
Applies to "tape and reel" part number counterparts as well. For more information, see Section 2.8, Device and Development-Support
Tool Nomenclature.
Device Overview
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Table 2-1. Characteristics of the DM6437 Processor (continued)
HARDWARE FEATURES
Core (V)
Voltage (2)
I/O (V)
MXI/CLKIN frequency multiplier
(27 MHz reference)
PLL Options
BGA Package(s)
Process Technology
Product Status
(3)
(3)
DM6437
1.2 V
(-7/ -6/-5/ -4/-L/-Q6/-Q5/-Q4)
1.05 V
(-7/-6/-5/-4/-L/-Q5)
1.8 V, 3.3 V
x1 (Bypass), x14 to x 30
16 x 16 mm, 0.8 mm pitch
361-Pin BGA (ZWT)
23 x 23 mm, 1.0 mm pitch
376-Pin BGA (ZDU)
µm
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
0.09 µm
PD
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2.2 CPU (DSP Core) Description
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for audio and other
high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
•
•
•
•
•
•
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SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
• TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871)
• TMS320C64x to TMS320C64x+ CPU Migration Guide Application Report (literature number SPRAA84)
• TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)
10
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ÁÁ
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
src1
Odd
register
file A
(A1, A3,
A5...A31)
src2
.L1
odd dst
Even
register
file A
(A0, A2,
A4...A30)
(D)
even dst
long src
ST1b
ST1a
32 MSB
32 LSB
long src
Data path A
.S1
8
8
even dst
odd dst
src1
(D)
src2
LD1b
LD1a
32 LSB
DA2
32
32
src2
32 MSB
DA1
LD2a
LD2b
Á
Á
Á
Á
Á
Á
.M1
dst2
dst1
src1
(A)
(B)
(C)
dst
.D1
src1
src2
2x
1x
Odd
register
file B
(B1, B3,
B5...B31)
src2
.D2
32 LSB
32 MSB
src1
dst
src2
.M2
Even
register
file B
(B0, B2,
B4...B30)
(C)
src1
dst2
32
(B)
dst1
32
(A)
src2
src1
.S2 odd dst
even dst
long src
Data path B
ST2a
ST2b
32 MSB
32 LSB
long src
even dst
.L2
(D)
8
8
(D)
odd dst
src2
src1
Control Register
A.
B.
C.
D.
On .M unit, dst2 is 32 MSB.
On .M unit, dst1 is 32 LSB.
On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
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2.3 C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P)
consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The
Level 1 Data memory/cache (L1D) consists of 80 KB—48 KB of which is mapped memory and 32 KB of
which can be configured as mapped memory or 2-way set associated cache. The Level 2 memory/cache
(L2) consists of a 128 KB memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.
Table 2-2. C64x+ Cache Registers
HEX ADDRESS RANGE
REGISTER ACRONYM
0x0184 0000
L2CFG
0x0184 0020
L1PCFG
0x0184 0024
L1PCC
0x0184 0040
L1DCFG
0x0184 0044
L1DCC
DESCRIPTION
L2 Cache configuration register
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
0x0184 0048 - 0x0184 0FFC
-
0x0184 1000
EDMAWEIGHT
Reserved
0x0184 1004 - 0x0184 1FFC
-
0x0184 2000
L2ALLOC0
L2 allocation register 0
0x0184 2004
L2ALLOC1
L2 allocation register 1
0x0184 2008
L2ALLOC2
L2 allocation register 2
0x0184 200C
L2ALLOC3
L2 allocation register 3
L2 EDMA access control register
Reserved
0x0184 2010 - 0x0184 3FFF
-
0x0184 4000
L2WBAR
L2 writeback base address register
0x0184 4004
L2WWC
L2 writeback word count register
0x0184 4010
L2WIBAR
L2 writeback invalidate base address register
0x0184 4014
L2WIWC
L2 writeback invalidate word count register
0x0184 4018
L2IBAR
L2 invalidate base address register
0x0184 401C
L2IWC
L2 invalidate word count register
0x0184 4020
L1PIBAR
L1P invalidate base address register
0x0184 4024
L1PIWC
L1P invalidate word count register
0x0184 4030
L1DWIBAR
L1D writeback invalidate base address register
0x0184 4034
L1DWIWC
L1D writeback invalidate word count register
0x0184 4038
-
0x0184 4040
L1DWBAR
L1D Block Writeback
0x0184 4044
L1DWWC
L1D Block Writeback
0x0184 4048
L1DIBAR
L1D invalidate base address register
0x0184 404C
L1DIWC
L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF
-
0x0184 5000
L2WB
0x0184 5004
L2WBINV
0x0184 5008
L2INV
0x0184 500C - 0x0184 5027
-
0x0184 5028
L1PINV
0x0184 502C - 0x0184 5039
-
12
0x0184 5040
L1DWB
0x0184 5044
L1DWBINV
0x0184 5048
L1DINV
Device Overview
Reserved
Reserved
Reserved
L2 writeback all register
L2 writeback invalidate all register
L2 Global Invalidate without writeback
Reserved
L1P Global Invalidate
Reserved
L1D Global Writeback
L1D Global Writeback with Invalidate
L1D Global Invalidate without writeback
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-2. C64x+ Cache Registers (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
0x0184 8000 - 0x0184 80BC
MAR0 - MAR47
Reserved (corresponds to byte address 0x0000 0000 - 0x2FFF FFFF)
DESCRIPTION
0x0184 80C0 - 0x0184 80FC
MAR48 - MAR63
Memory Attribute Registers for PCI Data (corresponds to byte address
0x3000 0000 - 0x3FFF FFFF)
0x0184 8100 - 0x0184 8104
MAR64 - MAR65
Reserved (corresponds to byte address 0x4000 0000 - 0x41FF FFFF)
0x0184 8108 - 0x0184 8124
MAR66 - MAR73
Memory Attribute Registers for EMIFA
(corresponds to byte address 0x4200 0000 - 0x49FF FFFF)
0x0184 8128 - 0x0184 812C
MAR74 - MAR75
Reserved (corresponds to byte address 0x4A00 0000 - 0x4BFF FFFF)
0x0184 8130 - 0x0184 813C
MAR76 - MAR79
Memory Attribute Registers for VLYNQ (corresponds to byte address
0x4C00 0000 - 0x4FFF FFFF)
0x0184 8140- 0x0184 81FC
MAR80 - MAR127
Reserved (corresponds to byte address 0x5000 0000 - 0x7FFF FFFF)
0x0184 8200 - 0x0184 823C
MAR128 - MAR143
Memory Attribute Registers for DDR2
(corresponds to byte address 0x8000 0000 - 0x8FFF FFFF)
0x0184 8240 - 0x0184 83FC
MAR144 - MAR255
Reserved (corresponds to byte address 0x9000 0000 - 0xFFFF FFFF)
2.4 Memory Map Summary
Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of
the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories
associated with its two processors and various subsystems. To help simplify software development a
unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.
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Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
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Table 2-3. Memory Map Summary
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
C64x+
MEMORY MAP
0x0000 0000
0x000F FFFF
1M
Reserved
0x0010 0000
0x0010 FFFF
64K
Boot ROM
0x0011 0000
0x007F FFFF
7M-64K
Reserved
0x0080 0000
0x0081 FFFF
128K
L2 RAM/Cache (1)
0x0082 0000
0x00E0 7FFF
6048K
Reserved
0x00E0 8000
0x00E0 FFFF
32K
L1P RAM/Cache (1)
0x00E1 0000
0x00F0 3FFF
976K
Reserved
0x00F0 4000
0x00F0 FFFF
48K
L1D RAM
0x00F1 0000
0x00F1 7FFF
32K
L1D RAM/Cache (1)
0x00F1 8000
0x017F FFFF
9120K
Reserved
0x0180 0000
0x01BF FFFF
4M
CFG Space
0x01C0 0000
0x01FF FFFF
4M
CFG Bus Peripherals
0x0200 0000
0x100F FFFF
225M
Reserved
0x1010 0000
0x1010 FFFF
64K
Boot ROM
0x1011 0000
0x107F FFFF
7M-48K
Reserved
0x1080 0000
0x1081 FFFF
128K
0x1082 0000
0x10E0 7FFF
0x10E0 8000
0x10E0 FFFF
0x10E1 0000
EDMA PERIPHERAL
MEMORY MAP
VPSS
MEMORY MAP
PCI
MEMORY MAP
Reserved
Reserved
CFG Bus Peripherals
CFG Bus Peripherals
Reserved
Reserved
L2 RAM/Cache (1)
L2 RAM/Cache (1)
L2 RAM/Cache (1)
6048K
Reserved
Reserved
Reserved
32K
L1P RAM/Cache (1)
L1P RAM/Cache (1)
L1P RAM/Cache (1)
0x10F0 3FFF
976K
Reserved
Reserved
0x10F0 4000
0x10F0 FFFF
48K
L1D RAM
L1D RAM
L1D RAM
0x10F1 0000
0x10F1 7FFF
32K
L1D RAM/Cache (1)
L1D RAM/Cache (1)
L1D RAM/Cache (1)
0x10F1 8000
0x10FF FFFF
1M-96K
Reserved
Reserved
Reserved
0x1100 0000
0x1FFF FFFF
240M
Reserved
Reserved
Reserved
0x2000 0000
0x2000 7FFF
32K
DDR2 Control Regs
DDR2 Control Regs
DDR2 Control Regs
0x2000 8000
0x2FFF FFFF
256M-32K
Reserved
Reserved
Reserved
0x3000 0000
0x3FFF FFFF
256M
PCI Data
PCI Data
0x4000 0000
0x41FF FFFF
32M
Reserved
Reserved
0x4200 0000
0x42FF FFFF
16M
EMIFA Data (CS2) (2)
EMIFA Data (CS2) (2)
0x4300 0000
0x43FF FFFF
16M
Reserved
Reserved
0x4400 0000
0x44FF FFFF
16M
EMIFA Data (CS3) (2)
EMIFA Data (CS3) (2)
0x4500 0000
0x45FF FFFF
16M
Reserved
Reserved
0x4600 0000
0x46FF FFFF
16M
EMIFA Data (CS4) (2)
EMIFA Data (CS4) (2)
0x4700 0000
0x47FF FFFF
16M
Reserved
Reserved
0x4800 0000
0x48FF FFFF
16M
EMIFA Data (CS5) (2)
EMIFA Data (CS5) (2)
0x4900 0000
0x49FF FFFF
16M
Reserved
Reserved
0x4A00 0000
0x4BFF FFFF
32M
Reserved
Reserved
0x4C00 0000
0x4FFF FFFF
64M
VLYNQ (Remote Data)
VLYNQ (Remote Data)
0x5000 0000
0x7FFF FFFF
768M
Reserved
Reserved
0x8000 0000
0x8FFF FFFF
256M
DDR2 Memory Controller
DDR2 Memory Controller
DDR2 Memory Controller
DDR2 Memory Controller
0x9000 0000
0xFFFF FFFF
1792M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1)
(2)
14
For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,
BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the
bootloader code, all C64x+ memories are configured as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and
L1DCFG.L1DMODE = 0h). If cache use is required, the application code must explicitly enable the cache. For more information on boot
modes, see Section 3.4.1, Boot Modes. For more information on the bootloader, see the Using the TMS320DM643x Bootloader
Application Report (literature number SPRAAG0). For the EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100, FASTBOOT = 0), the
bootloader is not executed—that is, L2 RAM/Cache defaults to all RAM (L2CFG.L2MODE = 0h); L1P RAM/Cache defaults to all cache
(L1PCFG.L1PMODE = 7h); and L1D RAM/Cache defaults to all cache (L1DCFG.L1DMODE = 7h).
The EMIFA CS0 and CS1 are not functionally supported on the DM6437 device, and therefore, are not pinned out.
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Table 2-4. Configuration Memory Map Summary
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
C64x+
0x0180 0000
0x0180 FFFF
64K
C64x+ Interrupt Controller
0x0181 0000
0x0181 0FFF
4K
C64x+ Powerdown Controller
0x0181 1000
0x0181 1FFF
4K
C64x+ Security ID
0x0181 2000
0x0181 2FFF
4K
C64x+ Revision ID
0x0182 0000
0x0182 FFFF
64K
C64x+ EMC
0x0183 0000
0x0183 FFFF
64K
Reserved
0x0184 0000
0x0184 FFFF
64K
C64x+ Memory System
0x0185 0000
0x0187 FFFF
192K
Reserved
0x0188 0000
0x01BB FFFF
3328K
Reserved
0x01BC 0000
0x01BC 00FF
256
Reserved
0x01BC 0100
0x01BC 01FF
256
Pin Manager and Trace
0x01BC 0400
0x01BF FFFF
255K
Reserved
0x01C0 0000
0x01C0 FFFF
64K
EDMA CC
0x01C1 0000
0x01C1 03FF
1K
EDMA TC0
0x01C1 0400
0x01C1 07FF
1K
EDMA TC1
0x01C1 0800
0x01C1 0BFF
1K
EDMA TC2
0x01C1 0C00
0x01C1 9FFF
5K
Reserved
0x01C1 A000
0x01C1 A7FF
2K
PCI Control Register (1)
0x01C1 A800
0x01C1 FFFF
22K
Reserved
0x01C2 0000
0x01C2 03FF
1K
UART0
0x01C2 0400
0x01C2 07FF
1K
UART1
0x01C2 0800
0x01C2 0FFF
2K
Reserved
0x01C2 1000
0x01C2 13FF
1K
I2C
0x01C2 1400
0x01C2 17FF
1K
Timer0
0x01C2 1800
0x01C2 1BFF
1K
Timer1
0x01C2 1C00
0x01C2 1FFF
1K
Timer2 (Watchdog)
0x01C2 2000
0x01C2 23FF
1K
PWM0
0x01C2 2400
0x01C2 27FF
1K
PWM1
0x01C2 2800
0x01C2 2BFF
1K
PWM2
0x01C2 2C00
0x01C2 2FFF
1K
Reserved
0x01C2 3000
0x01C2 3FFF
4K
HECC Control (2)
0x01C2 4000
0x01C2 53FF
5K
HECC RAM
0x01C2 5400
0x01C3 FFFF
107K
Reserved
0x01C4 0000
0x01C4 07FF
2K
System Module
0x01C4 0800
0x01C4 0BFF
1K
PLL Controller 1
0x01C4 0C00
0x01C4 0FFF
1K
PLL Controller 2
0x01C4 1000
0x01C4 1FFF
4K
Power and Sleep Controller
0x01C4 2000
0x01C6 6FFF
148K
Reserved
0x01C6 7000
0x01C6 77FF
2K
GPIO
0x01C6 7800
0x01C6 7FFF
2K
HPI
0x01C6 8000
0x01C6 FFFF
32K
Reserved
0x01C7 0000
0x01C7 3FFF
16K
VPSS Registers
0x01C7 4000
0x01C7 FFFF
48K
Reserved
0x01C8 0000
0x01C8 0FFF
4K
EMAC Control Registers
(1)
(2)
Access to certain PCI registers when there is no active PCI clock may hang the device. For more information, see the TMS320DM643x
Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU985).
Software must not access "Reserved" locations of the HECC. Access to HECC "Reserved" locations may hang the device.
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
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Table 2-4. Configuration Memory Map Summary (continued)
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
C64x+
0x01C8 1000
0x01C8 1FFF
4K
EMAC Control Module Registers
0x01C8 2000
0x01C8 3FFF
8K
EMAC Control Module RAM
0x01C8 4000
0x01C8 47FF
2K
MDIO Control Registers
0x01C8 4800
0x01CF FFFF
494K
Reserved
0x01D0 0000
0x01D0 07FF
2K
McBSP0
0x01D0 0800
0x01D0 0FFF
2K
McBSP1
0x01D0 1000
0x01D0 13FF
1K
McASP0 Control
0x01D0 1400
0x01D0 17FF
1K
McASP0 Data
0x01D0 1800
0x01DF FFFF
1018K
Reserved
0x01E0 0000
0x01E0 0FFF
4K
EMIFA Control
0x01E0 1000
0x01E0 1FFF
4K
VLYNQ Control Registers
0x01E0 2000
0x0FFF FFFF
226M-8K
Reserved
16
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2.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 3.7, Multiplexed Pin Configurations of this document.
2.5.1
Pin Map (Bottom View)
Figure 2-2 through Figure 2-5 show the bottom view of the ZWT package pin assignments in four
quadrants (A, B, C, and D). Figure 2-6 through Figure 2-9 show the bottom view of the ZDU package pin
assignments in four quadrants (A, B, C, and D).
1
2
3
4
5
6
7
8
9
10
W
VSS
VSS
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK
DDR_CLK
DDR_A[12]
DDR_A[11]
W
V
DVDDR2
DDR_D[4]
DDR_D[6]
DDR_D[8]
DDR_D[11]
DDR_D[13]
DDR_D[15]
DDR_CKE
DDR_BA[1]
DDR_A[8]
V
U
DDR_D[2]
DDR_D[3]
DDR_D[5]
DDR_DQS[0]
DDR_D[10]
DDR_DQS[1]
DDR_RAS
DDR_BA[0]
DDR_BA[2]
DDR_A[10]
U
T
DDR_D[0]
DDR_D[1]
PCIEN
DDR_DQM[0]
DVDDR2
DDR_DQM[1]
DDR_CAS
DDR_WE
DDR_CS
DDR_ZN
T
R
VSS
TRST
TMS
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
R
P
DVDD33
EMU0
TDO
TDI
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
VSS
P
N
TCK
EMU1
RESETOUT
POR
VSS
DVDD33
VSS
CVDD
VSS
CVDD
N
M
CLKOUT0/
PWM2/
GP[84]
SCL
SDA
RESET
DVDD33
VSS
CVDD
VSS
CVDD
VSS
M
L
UCTS0/
GP[87]
URXD0/
GP[85]
URTS0/
PWM0/
GP[88]
HECC_RX/
TINP1L/
URXD1/
GP[56]
RSV3
DVDD33
VSS
CVDD
VSS
CVDD
L
K
VSS
CLKS1/
TINP0L/
GP[98]
UTXD0/
GP[86]
HECC_TX/
TOUT1L/
UTXD1/
GP[55]
RSV2
VSS
CVDD
VSS
CVDD
VSS
K
1
2
3
4
5
6
7
8
9
10
Figure 2-2. ZWT Pin Map [Quadrant A]
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12
13
14
15
16
17
18
19
W
DDR_A[6]
DDR_A[5]
DDR_A[0]
DDR_D[16]
DDR_D[18]
DDR_D[21]
DDR_D[27]
DVDDR2
DVDDR2
W
V
DDR_A[7]
DDR_A[4]
DDR_A[2]
DDR_D[17]
DDR_D[19]
DDR_D[22]
DDR_D[24]
DDR_D[29]
VSS
V
U
DDR_A[9]
DDR_A[3]
DDR_A[1]
DDR_DQS[2]
DDR_D[20]
DDR_DQS[3]
DDR_D[25]
DDR_D[28]
DDR_D[30]
U
T
DDR_ZP
DDR_DQM[2]
DDR_VREF
DDR_DQM[3]
DDR_D[23]
DDR_D[26]
DDR_D[31]
T
R
VSS
DVDDR2
RSV5
DVDDR2
VSS
DVDDR2
VSS
VSS
VSS
R
P
DVDDR2
VSS
DVDDR2
VSS
VSSA_1P1V
VSSA_1P8V
VDDA_1P8V
DAC_IOUT_B
DAC_IOUT_A
P
N
VSS
CVDD
VSS
VSS
VDDA_1P1V
DAC_RBIAS
DAC_IOUT_D
DAC_IOUT_C
DAC_VREF
N
M
CVDD
VSS
CVDD
VSS
DVDD33
VSS
VSS
VSS
VSS
M
L
VSS
CVDD
VSS
DVDDR2
RSV4
PLLPWR18
VSS
MXV DD
VSS
L
K
CVDD
VSS
CVDD
VSS
DVDD33
VSS
DVDD33
MXV SS
MXI/
CLKIN
K
11
12
13
14
15
16
17
18
19
DDR_VDDDLL DDR_VSSDLL
Figure 2-3. ZWT Pin Map [Quadrant B]
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Device Overview
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Digital Media Processor
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
11
12
13
14
15
16
17
18
19
J
VSS
CVDD
VSS
DVDD33
VSS
DVDD33
VSS
VSS
MXO
J
H
CVDD
VSS
CVDD
VSS
YOUT7/
GP[29]
YOUT6/
GP[28]
YOUT5/
GP[27]
DVDD33
VSS
H
G
VSS
DVDD33
VSS
DVDD33
VSS
VPBECLK/
GP[30]
G
F
DVDD33
VSS
DVDD33
VSS
YOUT1/
GP[23]/
(BOOTMODE1)
COUT6/
EM_D[6]/
GP[20]
COUT7/
EM_D[7]/
GP[21]
YOUT0/
GP[22]/
(BOOTMODE0)
HSYNC/
EM_CS5/
GP[33]
F
E
AD28
AD30
VSS
EM_WE
EM_WAIT/
(RDY/BSY)
COUT3/
EM_D[3]/
GP[17]
COUT5/
EM_D[5]/
GP[19]
COUT4/
EM_D[4]/
GP[18]
VSYNC/
EM_CS4/
GP[32]
E
D
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/
GP[46]
C_FIELD/
EM_A[21]/
GP[34]
C_WE/
EM_R/W/
GP[35]
YI4(CCD4)/
GP[40]
EM_OE
COUT0/
EM_D[0]/
GP[14]
COUT2/
EM_D[2]/
GP[16]
COUT1/
EM_D[1]/
GP[15]
VCLK/
GP[31]
D
C
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/
GP[48]
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/
GP[44]
YI5(CCD5)/
GP[41]
YI2(CCD2)/
GP[38]
YI0(CCD0)/
GP[36]
B2/
EM_BA[1]/
GP[5]/
(AEM0)
R2/
EM_BA[0]/
GP[6]/
(AEM1)
LCD_OE/
EM_CS3/
GP[13]
G0/
EM_CS2/
GP[12]
C
B
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/
GP[49]
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/
GP[45]
YI6(CCD6)/
GP[42]
YI3(CCD3)/
GP[39]
YI1(CCD1)/
GP[37]
B1/
EM_A[2]/
(CLE)/GP[8]/
(AEAW0/
PLLMS0)
R1/
EM_A[0]/
GP[7]/
(AEM2)
B0/
LCD_FIELD/
EM_A[3]/
GP[11]
VSS
B
A
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/
GP[47]
YI7(CCD7)/
GP[43]
VD/
GP[53]
PCLK/
GP[54]
HD/
GP[52]
G1/
EM_A[1]/
(ALE)/GP[9]/
(AEAW1/
PLLMS1)
R0/
EM_A[4]/
GP[10]/
(AEAW2/
PLLMS2)
DVDD33
VSS
A
11
12
13
14
15
16
17
18
19
YOUT3/
YOUT4/
YOUT2/
GP[26]/
GP[24]/
GP[25]/
(BOOTMODE2) (BOOTMODE3) (FASTBOOT)
Figure 2-4. ZWT Pin Map [Quadrant C]
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Device Overview
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
1
2
3
4
J
DVDD33
AHCLKR0/
CLKR0/
GP[101]
AXR0[1]/
DX0/
GP[104]
CLKS0/
TOUT0L/
GP[97]
H
ACLKR0/
CLKX0/
GP[99]
AXR0[0]/
FSR1/
GP[105]
AXR0[2]/
FSX0/
GP[103]
AFSR0/
DR0/
GP[100]
AFSX0/
DX1/
GP[107]
AMUTE0/
DR1/
GP[110]
AXR0[3]/
FSR0/
GP[102]
G
AHCLKX0/
CLKR1/
GP[108]
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5
6
7
8
9
10
DVDD33
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
H
DVDD33
VSS
DVDD33
VSS
DVDD33
G
DVDD33
VSS
DVDD33
VSS
DVDD33
VSS
F
DVDD33
VSS
DVDD33
VSS
AD26
E
EM_A[6]/
AD20/
GP[95]
EM_A[9]/
PIDSEL/
GP[92]
EM_A[12]/
PCBE3/
GP[89]
D
HD4/
VLYNQ_RXD3/
PFRAME/
GP[62]
HD0/
VLYNQ_
SCRUN/
AD18/
GP[58]
EM_A[7]/
AD22/
GP[94]
EM_A[11]/
AD24/
GP[90]
C
HD7/
HD3/
VLYNQ_TXD2/ VLYNQ_RXD2/
PDEVSEL/
PCBE2/
GP[65]
GP[61]
EM_A[5]/
AD19/
GP[96]
EM_A[8]/
AD21/
GP[93]
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/
GP[51]
B
VLYNQ_
CLOCK/
PCICLK/
GP[57]
HD2/
VLYNQ_RXD1/
AD17/
GP[60]
EM_A[10]/
AD23/
GP[91]
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/
GP[50]
A
7
8
9
10
VSS
DVDD33
VSS
F
ACLKX0/
CLKX1/
GP[106]
AMUTEIN0/
FSX1/
GP[109]
GP[4]/
PWM1
VSS
E
AD0/
GP[0]
AD1/
GP[1]
AD2/
GP[2]
AD4/
GP[3]
RSV1
D
HAS/
MDIO/
AD3/
GP[83]
HRDY/
MRXD2/
PCBE0/
GP[80]
HCNTL1/
MTXEN/
AD11/
GP[75]
HD14/
MTXD0/
AD15/
GP[72]
HD12/
MTXD2/
PPAR/
GP[70]
C
HCS/
MDCLK/
AD5/
GP[81]
HINT/
MRXD3/
AD6/
GP[82]
HDS2/
MRXD0/
AD9/
GP[78]
HHWIL/
MRXDV/
AD13/
GP[74]
HD11/
MTXD3/
PCBE1/
GP[69]
B
VSS
HDS1/
MRXD1/
AD7/
GP[79]
HCNTL0/
MRXER/
AD10/
GP[76]
HD13/
MTXD1/
AD14/
GP[71]
HD10/
MCRS/
PSERR/
GP[68]
A
DVDD33
DVDD33
HR/W/
MRXCLK/
AD8/
GP[77]
HD15/
MTXCLK/
AD12/
GP[73]
1
2
3
4
HD6/
HD1/
VLYNQ_TXD1/ VLYNQ_RXD0/
PTRDY/
AD16/
GP[64]
GP[59]
HD9/
MCOL/
PSTOP/
GP[67]
HD8/
HD5/
VLYNQ_TXD3/ VLYNQ_TXD0/
PPERR/
PIRDY/
GP[66]
GP[63]
5
6
J
Figure 2-5. ZWT Pin Map [Quadrant D]
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Device Overview
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Digital Media Processor
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AB
AA
Y
W
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
1
2
3
VSS
VSS
DDR_D[6]
DDR_D[8]
DDR_D[12]
DDR_D[15]
DDR_CLK0
DDR_CLK0
DDR_BS[1]
DDR_BS[2]
DDR_A[10]
DVDDR2
DDR_D[3]
DDR_D[4]
DDR_DQS[0]
DDR_D[10]
DDR_D[13]
DDR_DQS[1]
DDR_CKE
DDR_BS[0]
DDR_A[12]
DDR_A[11]
DDR_D[0]
DDR_D[1]
DDR_D[5]
DDR_DQM[0]
DDR_D[11]
DDR_D[14]
DDR_DQM[1]
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
VSS
DDR_D[2]
PCIEN
DDR_D[7]
DDR_D[9]
VSS
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
5
6
DVDDR2
TRST
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
VSS
TCK
TDO
EMU0
DVDDR2
VSS
TDI
VSS
DVDDR2
EMU1
RESETOUT
DVDD33
VSS
CLKOUT0/
PWM2/
GP[84]
POR
RESET
VSS
DVDD33
R
UCTS0/
GP[87]
SDA
HECC_RX/
TINP1L/
URXD1/
GP[56]
DVDD33
VSS
P
N
UTXD0/
GP[86]
SCL
HECC_TX/
TOUT1L/
UTXD1/
GP[55]
VSS
DVDD33
M
VSS
URXD0/
GP[85]
URTS0/
PWM0/
GP[88]
RSV3
VSS
1
2
3
4
V
U
TMS
4
T
R
P
7
8
9
10
11
AB
AA
Y
W
V
9
10
VSS
CVDD
CVDD
N
CVDD
VSS
VSS
N
M
CVDD
CVDD
VSS
M
10
11
U
6
7
8
11
T
5
9
P
Figure 2-6. ZDU Pin Map [Quadrant A]
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Device Overview
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
12
AB
AA
13
14
www.ti.com
15
16
17
18
19
20
21
22
DDR_A[7]
DDR_A[4]
DDR_A[1]
DDR_A[0]
DDR_D[18]
DDR_D[21]
DDR_D[22]
DDR_D[25]
DDR_D[28]
DVDDR2
DVDDR2
AB
DDR_A[9]
DDR_A[6]
DDR_A[3]
DDR_DQS[2]
DDR_D[16]
DDR_D[19]
DDR_DQS[3]
DDR_D[23]
DDR_D[26]
DDR_D[30]
VSS
AA
DDR_A[2]
DDR_DQM[2]
DDR_D[17]
DDR_D[20]
DDR_DQM[3]
DDR_D[24]
DDR_D[27]
DDR_D[29]
DDR_D[31]
Y
Y
DDR_A[8]
DDR_A[5]
W
DDR_ZN
DDR_ZP
DDR_VDDDLL
DDR_VSSDLL
RSV5
DVDDR2
DDR_VREF
DVDDR2
VSS
VSS
VSS
W
V
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
VSS
DVDDR2
VSS
VDDA_1P8V
DAC_IOUT_A
DAC_VREF
V
U
VSS
VSS
VSSA_1P8V
DAC_RBIAS DAC_IOUT_B
U
T
VSS
VSSA_1P1V
VDDA_1P1V
DAC_IOUT_C DAC_IOUT_D
T
VSS
VSS
VSS
VSS
VSS
R
12
13
14
15
16
17
R
P
CVDD
CVDD
VSS
P
DVDD33
RSV4
DVDD33
VSS
DVDD33
P
N
VSS
VSS
CVDD
N
VSS
DVDD33
PLLPWR18
MXV DD
MXI/
CLKIN
N
M
VSS
VSS
CVDD
M
DVDD33
VSS
DVDD33
MXV SS
MXO
M
12
13
14
18
19
20
21
22
Figure 2-7. ZDU Pin Map [Quadrant B]
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Device Overview
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TMS320DM6437
Digital Media Processor
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
L
12
13
14
VSS
CVDD
CVDD
L
18
19
VSS
YOUT5/
GP[27]
K
VSS
VSS
CVDD
K
DVDD33
J
CVDD
CVDD
VSS
J
VSS
20
21
22
YOUT2/
GP[24]/
DVDD33
VSS
YOUT7/
GP[29]
VPBECLK/
GP[30]
YOUT6/
GP[28]
HSYNC/
EM_CS5/
GP[33]
YOUT4/
YOUT1/
GP[26]/
GP[23]/
(FASTBOOT) (BOOTMODE1)
DVDD33
YOUT0/
GP[22]/
(BOOTMODE0)
H
VSS
DVDD33
L
(BOOTMODE2)
YOUT3/
GP[25]/
COUT7/
EM_D[7]/
GP[21]
(BOOTMODE3)
VSYNC/
EM_CS4/
GP[32]
K
J
H
G
VSS
DVDD33
COUT1/
EM_D[1]/
GP[15]
COUT4/
EM_D[4]/
GP[18]
VCLK/
GP[31]
G
F
DVDD33
VSS
COUT3/
EM_D[3]/
GP[17]
COUT6/
EM_D[6]/
GP[20]
COUT5/
EM_D[5]/
GP[19]
F
12
13
14
15
16
17
VSS
DVDD33
VSS
DVDD33
VSS
DVDD33
VSS
DVDD33
R2/
EM_BA[0]/
GP[6]/
(AEM1)
COUT0/
EM_D[0]/
GP[14]
COUT2/
EM_D[2]/
GP[16]
E
D
AD26
AD28
AD30
VSS
DVDD33
VSS
DVDD33
EM_OE
EM_WAIT/
(RDY/BSY)
B0/
LCD_FIELD/
EM_A[3]/
GP[11]
LCD_OE/
EM_CS3/
GP[13]
D
C
EM_A[11]/
AD24/
GP[90]
C_FIELD/
EM_A[21]/
GP[34]
C_WE/
EM_R/W/
GP[35]
YI4(CCD4)/
GP[40]
EM_WE
B2/
EM_BA[1]/
GP[5[/
(AEM0)
R1/
EM_A[0]/
GP[7]/
(AEM2)
G0/
EM_CS2/
GP[12]
C
B
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/
GP[45]
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/
GP[47]
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/
GP[44]
EM_A[12]/
PCBE3/
GP[89]
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/
GP[49]
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/
GP[48]
YI6(CCD6)/
GP[42]
YI5(CCD5)/
GP[41]
YI2(CCD2)
GP[38]
YI1(CCD1)/
GP[37]
YI0(CCD0)/
GP[36]
G1/
EM_A[1]/
(ALE)/GP[9]/
(AEAW1/
PLLMS1)
R0/
EM_A[4]/
GP[10]/
(AEAW2/
PLLMS2)
VSS
B
A
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/
GP[51]
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/
GP[50]
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/
GP[46]
YI7(CCD7)/
GP[43]
YI3(CCD3)/
GP[39]
VD/
GP[53]
PCLK/
GP[54]
HD/
GP[52]
B1/
EM_A[2]/
(CLE)/GP[8]/
(AEAW0/
PLLMS0)
DVDD33
VSS
A
12
13
14
15
16
17
18
19
20
21
22
E
Figure 2-8. ZDU Pin Map [Quadrant C]
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Device Overview
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
1
2
3
4
5
L
DVDD33
CLKS1/
TINP0L/
GP[98]
CLKS0/
TOUT0L/
GP[97]
RSV2
DVDD33
L
K
AHCLKR0/
CLKR0/
GP[101]
AXR0[1]/
DX0/
GP[104]
AFSR0/
DR0/
GP[100]
DVDD33
VSS
J
ACLKR0/
CLKX0/
GP[99]
AXR0[2]/
FSX0/
GP[103]
AXR0[3]/
FSR0/
GP[102]
VSS
H
AHCLKX0/
CLKR1/
GP[108]
AXR0[0]/
FSR1/
GP[105]
AMUTE0/
DR1/
GP[110]
G
ACLKX0/
CLKX1/
GP[106]
AFSX0/
DX1/
GP[107]
AD2/
GP[2]
AD4/
GP[3]
E
AD0/
GP[0]
AD1/
GP[1]
DVDD33
VSS
D
HCS/
MDCLK/
AD5/
GP[81]
HINT/
MRXD3/
AD6/
GP[82]
HHWIL/
MRXDV/
AD13/
GP[74]
C
HAS/
MDIO/
AD3/
GP[83]
HDS2/
MRXD0/
AD9/
GP[78]
B
A
F
9
10
11
CVDD
VSS
VSS
L
K
CVDD
VSS
VSS
K
DVDD33
J
VSS
CVDD
CVDD
J
DVDD33
VSS
H
AMUTEIN0/
FSX1/
GP[109]
VSS
DVDD33
G
GP[4]/
PWM1
DVDD33
VSS
F
6
7
8
9
10
11
DVDD33
VSS
DVDD33
VSS
DVDD33
VSS
DVDD33
RSV1
VSS
DVDD33
DVDD33
VSS
DVDD33
VSS
D
HRDY/
MRXD2/
PCBE0/
GP[80]
HCNTL1/
MTXEN/
AD11/
GP[75]
HD12/
MTXD2/
PPAR/
GP[70]
HD9/
MCOL/
PSTOP/
GP[67]
EM_A[7]/
AD22/
GP[94]
EM_A[9]/
PIDSEL/
GP[92]
C
DVDD33
HCNTL0/
MRXER/
AD10/
GP[76]
HDS1/
MRXD1/
AD7/
GP[79]
HD13/
MTXD1/
AD14/
GP[71]
HD14/
MTXD0/
AD15/
GP[72]
HD10/
MCRS/
PSERR/
GP[68]
EM_A[6]/
AD20/
GP[95]
EM_A[10]/
AD23/
GP[91]
B
VSS
DVDD33
HR/W/
MRXCLK/
AD8/
GP[77]
HD15/
MTXCLK/
AD12/
GP[73]
HD11/
MTXD3/
PCBE1/
GP[69]
EM_A[5]/
AD19/
GP[96]
EM_A[8]/
AD21/
GP[93]
A
1
2
3
4
5
10
11
HD8/
VSS
HD6/
HD4/
HD1/
VLYNQ_TXD1/
VLYNQ_RXD3/
VLYNQ_RXD0 /
PTRDY/
GP[64]
PFRAME/
GP[62]
AD16/
GP[59]
HD7/
HD3/
VLYNQ_TXD2/
VLYNQ_RXD2/
PDEVSEL/
GP[65]
PCBE2/
GP[61]
HD5/
PPERR/
GP[66]
RDY/
GP[63]
VLYNQ_
CLOCK/
PCICLK/
GP[57]
6
7
8
VLYNQ_TXD3/ VLYNQ_TXD0/ PI
HD0/
VLYNQ_
SCRUN/
AD18/
GP[58]
HD2/
VLYNQ_RXD1/
AD17/
GP[60]
9
E
Figure 2-9. ZDU Pin Map [Quadrant D]
24
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2.6 Terminal Functions
The terminal functions tables (Table 2-5 through Table 2-32) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see the Device Configurations section of this data manual.
All device boot and configuration pins (except PCIEN) are multiplexed configuration pins— meaning they
are multiplexed with functional pins. These pins function as device boot and configuration pins only during
device reset. The input states of these pins are sampled and latched into the BOOTCFG register when
device reset is deasserted (see Note below). After device reset is deasserted, the values on these
multiplexed pins no longer have to hold the configuration.
The PCIEN pin is a standalone configuration pin. Its value is latched into the BOOTCFG register when
device reset is deasserted (see Note below). Unlike the multiplexed device boot and configuration pins,
the value on the PCIEN pin even after device reset is deasserted must hold the configuration.
For proper device operation, external pullup/pulldown resistors may be required on these device boot and
configuration pins. Section 3.9.1, Pullup/Pulldown Resistors discusses situations where external
pullup/pulldown resistors are required.
Note: Internal to the chip, the two device reset pins RESET and POR are logically AND’d together for the
purpose of latching device boot and configuration pins. The values on all device boot and configuration
pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from
low-to-high.
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Table 2-5. BOOT Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
BOOT
YOUT3/GP[25]/
(BOOTMODE3)
G16
H21
G15
L20
I/O/Z
IPD
DVDD33
Bootmode configuration bits. These bootmode functions along with
the FASTBOOT function determine what device bootmode
configuration is selected.
The DM6437 device supports several types of bootmodes along with
a FASTBOOT option; for more details on the types/options, see
Section 3.4.1, Boot Modes.
F15
K20
F18
J20
YOUT4/GP26]/
(FASTBOOT)
G17
K19
I/O/Z
IPD
DVDD33
Fast Boot
0 = Not Fast Boot
1 = Fast Boot
R0/EM_A[4]/
GP[10]/
(AEAW2/PLLMS2)
A17
B21
I/O/Z
IPD
DVDD33
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
A20
I/O/Z
IPD
DVDD33
R1/EM_A[0]/
GP[7]/(AEM2)
B17
C21
I/O/Z
IPD
DVDD33
R2/EM_BA[0]/
GP[6]/(AEM1)
C17
E20
I/O/Z
IPD
DVDD33
B2/EM_BA[1]/
GP[5]/(AEM0)
C16
C20
I/O/Z
IPD
DVDD33
YOUT2/GP[24]/
(BOOTMODE2)
YOUT1/GP[23]/
(BOOTMODE1)
YOUT0/GP[22]/
(BOOTMODE0)
EMIFA Address Bus Width (AEAW) and Fast Boot PLL Multiplier
Select (PLLMS).
These configuration pins serve two purposes which are based on
AEM[2:0] settings.
For AEM[2:0] = 001 [8-bit EMIFA (Async) Pinout Mode 1], the
AEAW/PLLMS pins serve as the AEAW function to select EMIFA
Address Bus Width.
For all other AEM modes, the AEAW/PLLMS pins select the PLL
multiplier for fast boot.
For more details, see Section 3.5.1.2, EMIFA Address Width Select
(AEAW) and Fast Boot PLL Multipler Select (PLLMS).
Selects EMIFA Pinout Mode
The DM6437 supports the following EMIFA Pinout Modes:
AEM[2:0]
AEM[2:0]
AEM[2:0]
AEM[2:0]
AEM[2:0]
= 000,
= 001,
= 011,
= 100,
= 101,
No EMIFA
8-bit EMIFA (Async) Pinout Mode 1
8-bit EMIFA (Async) Pinout Mode 3
8-bit EMIFA (NAND) Pinout Mode 4
8-bit EMIFA (NAND) Pinout Mode 5
This signal doesn't actually affect the EMIFA module. It only affects
how the EMIFA is pinned out.
YOUT6/
GP[28]
H16
J21
PCIEN
T3
W3
YOUT5/GP[27]
(1)
(2)
(3)
26
H17
L19
I/O/Z
IPD
DVDD33
For proper DM6437 device operation, if this pin is both routed and
3-stated (not driven) during device reset, it must be pulled down via
an external resistor. For more detailed information on
pullup/pulldown resistors, see Section 3.9.1, Pullup/Pulldown
Resistors.
I
IPD
DVDD33
PCI Enable
0 = PCI pin function is disabled [default]
1 = PCI pin function is enabled
I/O/Z
IPU
DVDD33
For proper DM6437 device operation, if this pin is both routed and
3-stated (not driven) during device reset, it must be pulled up via an
external resistor. For more detailed information on pullup/pulldown
resistors, see Section 3.9.1, Pullup/Pulldown Resistors.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-6. Oscillator/PLL Terminal Functions
SIGNAL
ZWT
NO.
NAME
ZDU
NO.
TYPE (1)
OTHER (2)
DESCRIPTION
OSCILLATOR, PLL
(1)
(2)
(3)
(4)
MXI/
CLKIN
K19
N22
I
MXVDD
Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz).
If the internal oscillator is bypassed, this is the external oscillator clock
input. (3)
MXO
J19
M22
O
MXVDD
Crystal output for MX oscillator
MXVDD
L18
N21
S
(4)
1.8 V power supply for MX oscillator. On the board, this pin can be
connected to the same 1.8 V power supply as DVDDR2.
MXVSS
K18
M21
GND
(4)
Ground for MX oscillator
PLLPWR18
L16
N20
S
(4)
1.8 V power supply for PLLs
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
Specifies the operating I/O supply voltage for each signal
For more information on external board connections, see Section 6.6, External Clock Input From MXI/CLKIN Pin.
For more information, see the Recommended Operating Conditions table
Table 2-7. Clock Generator Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
CLOCK GENERATOR
CLKOUT0/
PWM2/GP[84]
(1)
(2)
(3)
M1
R1
I/O/Z
IPD
DVDD33
This pin is multiplexed between the System Clock generator (PLL1), PWM2,
and GPIO.
For the System Clock generator (PLL1), it is clock output CLKOUT0. This is
configurable for 27 MHz or other 27 MHz-divided-down (/1 to /32) clock
outputs.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-8. RESET and JTAG Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
Device reset
DESCRIPTION
RESET
RESET
M4
R3
I
IPU
DVDD33
RESETOUT
N3
T3
O/Z
–
DVDD33
Reset output status pin. The RESETOUT pin indicates when the
device is in reset.
POR
N4
R2
I
IPU
DVDD33
Power-on reset.
JTAG test-port mode select input.
For proper device operation, do not oppose the IPU on this pin.
JTAG
(1)
(2)
(3)
28
TMS
R3
V3
I
IPU
DVDD33
TDO
P3
U2
O/Z
–
DVDD33
JTAG test-port data output
TDI
P4
U3
I
IPU
DVDD33
JTAG test-port data input
TCK
N1
U1
I
IPU
DVDD33
JTAG test-port clock input
TRST
R2
V2
I
IPD
DVDD33
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see
the IEEE 1149.1 JTAG compatibility statement portion of this data
sheet
EMU1
N2
T2
I/O/Z
IPU
DVDD33
Emulation pin 1
EMU0
P2
T1
I/O/Z
IPU
DVDD33
Emulation pin 0
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-9. EMIFA Terminal Functions (Boot Configuration)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
EMIFA: BOOT CONFIGURATION
R0/EM_A[4]/
GP[10]/
(AEAW2/PLLMS2)
A17
B21
I/O/Z
IPD
DVDD33
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
A20
I/O/Z
DVDD33
B2/EM_BA[1]/
GP[5]/(AEM0)
C16
C20
I/O/Z
IPD
DVDD33
R2/EM_BA[0]/
GP[6]/(AEM1)
C17
E20
I/O/Z
IPD
DVDD33
R1/ EM_A[0]/
GP[7]/(AEM2)
B17
C21
I/O/Z
IPD
DVDD33
(1)
(2)
(3)
These pins are multiplexed between the VPBE (VENC), EMIFA, and
GPIO. When RESET or POR is asserted, these pins function as
EMIFA configuration pins. At reset if AEM[2:0] = 001 (EMIFA in 8-bit
Async mode), then the input states of AEAW[2:0] are sampled to set
the EMIFA Address Bus Width. After reset, these pins function as
VPBE (VENC), EMIFA, or GPIO pin functions based on pin mux
selection.
For more details on the AEAW/PLLMS functions, see Section 3.5.1.2,
EMIFA Address Bus Width (AEAW) and Fast Boot PLL Multiplier
Select (PLLMS).
These pins are multiplexed between the VPBE (VENC), EMIFA, and
GPIO. When RESET or POR is asserted, these pins function as
EMIFA configuration pins. At reset, the input states of AEM[2:0] are
sampled to set the EMIFA Pinout Mode.
For more details, see Section 3.5.1, Configurations at Reset. After
reset, these pins function as VPBE (VENC), EMIFA, or GPIO pin
functions based on pin mux selection.
For more details on the AEM functions, see Section 3.5.1.1, EMIFA
Pinout Mode (AEM[2:0]).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR (EMIFA Pinout Mode 1, AEM[2:0] = 001)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). For
more details, see Section 3.7, Multiplexed Pin Configurations.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
asynchronous memories (i.e., NOR flash).
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with
asynchronous memories (i.e., NOR flash).
HSYNC/EM_CS5/
GP[33]
F19
J22
I/O/Z
IPD
DVDD33
C_WE/EM_R/W/
GP[35]
C17
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
D13
For EMIFA (ASYNC/NOR), this pin is wait state extension input
EM_WAIT.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
For EMIFA, it is read/write output EM_R/W.
EM_WAIT/
(RDY/BSY)
E15
D20
I/O/Z
IPU
DVDD33
EM_OE
D15
D19
I/O/Z
IPU
DVDD33
For EMIFA, it is output enable output EM_OE.
EM_WE
E14
C19
I/O/Z
IPU
DVDD33
For EMIFA, it is write enable output EM_WE.
I/O/Z
IPD
DVDD33
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
R2/EM_BA[0]/
GP[6]/(AEM1)
C17
E20
For EMIFA, this is the Bank Address 0 output (EM_BA[0]). When
connected to an 8-bit asynchronous memory, this pin is the lowest
order bit of the byte address.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
B2/EM_BA[1]/
GP[5]/(AEM0)
(1)
(2)
(3)
30
C16
C20
For EMIFA, this is the Bank Address 1 output EM_BA[1]. When
connected to an 8-bit asynchronous memory, this pin is the 2nd bit of
the address.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
C_FIELD/
EM_A[21]/GP[34]
D12
C16
I/O/Z
IPD
DVDD33
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/GP[49]
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/GP[50]
C12
B12
D11
A11
C11
B11
A10
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/GP[51]
B10
EM_A[12]/PCBE3/
GP[89]
D10
EM_A[11]/AD24/
GP[90]
C10
EM_A[10]/AD23/
GP[91]
A9
EM_A[9]/PIDSEL/
GP[92]
D9
EM_A[8]/AD21/
GP[93]
B9
EM_A[7]/AD22/
GP[94]
C9
EM_A[6]/AD20/
GP[95]
D8
C15
C14
A14
B14
B13
C13
A13
A12
B12
C12
B11
C11
A11
C10
B10
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I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
DESCRIPTION
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
For EMIFA, it is address bit 21 output EM_A[21].
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 20 output
EM_A[20] if AEAW[2:0] = 100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 19 output
EM_A[19] if AEAW[2:0] = 100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 18 output
EM_A[18] if AEAW[2:0] = 011/100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 17 output
EM_A[17] if AEAW[2:0] = 011/100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 16 output
EM_A[16] if AEAW[2:0] = 010/011/100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 15 output
EM_A[15] if AEAW[2:0] = 010/011/100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 14 output
EM_A[14] if AEAW[2:0] = 001/010/011/100b.
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 001), this pin is address bit 13 output
EM_A[13] if AEAW[2:0] = 001/010/011/100b.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA, this pin is address bit 12 output EM_A[12].
For EMIFA, this pin is address bit 11 output EM_A[11].
For EMIFA, this pin is address bit 10 output EM_A[10].
For EMIFA, this pin is address bit 9 output EM_A[9].
For EMIFA, this pin is address bit 8 output EM_A[8].
For EMIFA, this pin is address bit 7 output EM_A[7].
For EMIFA, this pin is address bit 6 output EM_A[6].
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Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
EM_A[5]/AD19/
GP[96]
A10
I/O/Z
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
B8
R0/EM_A[4]/
GP[10]/
(AEAW2/PLLMS2)
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
A17
B0/LCD_FIELD/
EM_A[3]/GP[11]
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
B18
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
B16
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
A16
B21
D21
A20
B20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DESCRIPTION
For EMIFA, this pin is address bit 5 output EM_A[5].
For EMIFA, this pin is address bit 4 output EM_A[4].
For EMIFA, this pin is address bit 3 output EM_A[3].
For EMIFA, this pin is address bit 2 output EM_A[2].
When used for EMIFA, this pin is address output EM_A[1].
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, this pin is Address output EM_A[0], which is the least
significant bit on a 32-bit word address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the
address.
R1/ EM_A[0]/
GP[7]/(AEM2)
B17
C21
I/O/Z
IPD
DVDD33
COUT0/EM_D0/
GP[14]
D16
E21
I/O/Z
IPD
DVDD33
COUT1/EM_D1/
GP[15]
D18
G20
I/O/Z
IPD
DVDD33
COUT2/EM_D2/
GP[16]
D17
E22
I/O/Z
IPD
DVDD33
COUT3/EM_D3/
GP[17]
E16
F20
I/O/Z
IPD
DVDD33
These pins are multiplexed between VPBE (VENC), EMIFA, and
GPIO.
COUT4/EM_D4/
GP[18]
E18
G21
I/O/Z
IPD
DVDD33
For EMIFA (AEM[2:0] = 001), these pins are the 8-bit bi-directional
data bus (EM_D[7:0]).
COUT5/EM_D5/
GP[19]
E17
F22
I/O/Z
IPD
DVDD33
COUT6/EM_D6/
GP[20]
F16
F21
I/O/Z
IPD
DVDD33
COUT7/EM_D7/
GP[21]
F17
H20
I/O/Z
IPD
DVDD33
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 1, AEM[2:0] = 001)
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
EM_WAIT/
(RDY/BSY)
E15
D20
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is ready/busy input
(RDY/BSY).
EM_OE
D15
D19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is read enable output (RE).
EM_WE
E14
C19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is write enable output (WE).
32
Device Overview
A20
I/O/Z
IPD
DVDD33
When used for EMIFA (NAND), this pin is the Command Latch Enable
output (CLE).
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use
with NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use
with NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DVDD33
For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
F19
COUT0/EM_D0/
GP[14]
D16
E21
I/O/Z
IPD
DVDD33
COUT1/EM_D1/
GP[15]
D18
G20
I/O/Z
IPD
DVDD33
COUT2/EM_D2/
GP[16]
D17
E22
I/O/Z
IPD
DVDD33
COUT3/EM_D3/
GP[17]
E16
F20
I/O/Z
IPD
DVDD33
These pins are multiplexed between VPBE (VENC), EMIFA (NAND),
and GPIO.
COUT4/EM_D4/
GP[18]
E18
G21
I/O/Z
IPD
DVDD33
For EMIFA (NAND) AEM[2:0] = 001, these are the 8-bit bi-directional
data bus (EM_D[7:0]).
COUT5/EM_D5/
GP[19]
E17
F22
I/O/Z
IPD
DVDD33
COUT6/EM_D6/
GP[20]
F16
F21
I/O/Z
IPD
DVDD33
COUT7/EM_D7/
GP[21]
F17
H20
I/O/Z
IPD
DVDD33
J22
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I/O/Z
IPD
DVDD33
For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with
NAND flash.
HSYNC/EM_CS5/
GP[33]
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
Device Overview
33
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR with Reduced Address Reach (EMIFA Pinout Mode 3, AEM[2:0] = 011)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). For
more details, see Section 3.7, Multiplexed Pin Configurations.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
asynchronous memories (i.e., NOR flash).
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIOD.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with
asynchronous memories (i.e., NOR flash).
HSYNC/EM_CS5/
GP[33]
F19
J22
I/O/Z
IPD
DVDD33
C_WE/EM_R/W/
GP[35]
C17
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
D13
For EMIFA (ASYNC/NOR), this pin is wait state extension input
EM_WAIT.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
For EMIFA, it is read/write output EM_R/W.
EM_WAIT/
(RDY/BSY)
E15
D20
I/O/Z
IPU
DVDD33
EM_OE
D15
D19
I/O/Z
IPU
DVDD33
For EMIFA, it is output enable output EM_OE.
EM_WE
E14
C19
I/O/Z
IPU
DVDD33
For EMIFA, it is write enable output EM_WE.
I/O/Z
IPD
DVDD33
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
R2/EM_BA[0]/
GP[6]/(AEM1)
C17
E20
For EMIFA, this is the Bank Address 0 output (EM_BA[0]). When
connected to an 8-bit asynchronous memory, this pin is the lowest
order bit of the byte address.
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
B2/EM_BA[1]/
GP[5]/(AEM0)
(1)
(2)
(3)
34
C16
C20
For EMIFA, this is the Bank Address 1 output EM_BA[1]. When
connected to an 8-bit asynchronous memory, this pin is the 2nd bit of
the address.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Device Overview
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
C12
C15
I/O/Z
IPD
DVDD33
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
B12
C14
I/O/Z
IPD
DVDD33
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
D11
A14
I/O/Z
IPD
DVDD33
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
A11
B14
I/O/Z
IPD
DVDD33
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
C11
B13
I/O/Z
IPD
DVDD33
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/GP[49]
B11
C13
I/O/Z
IPD
DVDD33
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/GP[50]
A10
A13
I/O/Z
IPD
DVDD33
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/GP[51]
B10
A12
I/O/Z
IPD
DVDD33
EM_A[12]/PCBE3/
GP[89]
B12
I/O/Z
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
D10
EM_A[11]/AD24/
GP[90]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
C10
EM_A[10]/AD23/
GP[91]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
A9
EM_A[9]/PIDSEL/
GP[92]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
D9
EM_A[8]/AD21/
GP[93]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
B9
EM_A[7]/AD22/
GP[94]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
C9
EM_A[6]/AD20/
GP[95]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
D8
EM_A[5]/AD19/
GP[96]
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
B8
R0/EM_A[4]/
GP[10]/
(AEAW2/PLLMS2)
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
A17
C12
B11
C11
A11
C10
B10
A10
B21
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I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DESCRIPTION
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 011], these pins are the 8-bit bi-directional
data bus (EM_D[7:0]).
For EMIFA, it is address bit 12 output EM_A[12].
For EMIFA, it is address bit 11 output EM_A[11].
For EMIFA, it is address bit 10 output EM_A[10].
For EMIFA, it is address bit 9 output EM_A[9].
For EMIFA, it is address bit 8 output EM_A[8].
For EMIFA, it is address bit 7 output EM_A[7].
For EMIFA, it is address bit 6 output EM_A[6].
For EMIFA, it is address bit 5 output EM_A[5].
For EMIFA, it is address bit 4 output EM_A[4].
Device Overview
35
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
B0/LCD_FIELD/
EM_A[3]/GP[11]
D21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
B18
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
B16
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
A16
R1/ EM_A[0]/
GP[7]/(AEM2)
B17
A20
B20
C21
I/O/Z
I/O/Z
I/O/Z
IPD
DVDD33
DESCRIPTION
For EMIFA, it is address bit 3 output EM_A[3].
For EMIFA, it is address bit 2 output EM_A[2].
For EMIFA, it is address output EM_A[1].
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
For EMIFA, this is Address output EM_A[0], which is the least
significant bit on a 32-bit word address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the
address.
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 3, AEM[2:0] = 011)
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
EM_WAIT/
(RDY/BSY)
E15
D20
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
EM_OE
D15
D19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is read enable output (RE).
EM_WE
E14
C19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is write enable output (WE).
A20
I/O/Z
IPD
DVDD33
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
VSYNC/EM_CS4/
GP[32]
36
E19
Device Overview
H22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
HSYNC/EM_CS5/
GP[33]
F19
CI7(CCD15) /
EM_A[13]/
AD25/
EM_D[0]/GP[51]
B10
A12
I/O/Z
IPD
DVDD33
CI6(CCD14) /
EM_A[14]/
AD27/
EM_D[1]/GP[50]
A10
A13
I/O/Z
IPD
DVDD33
CI5(CCD13) /
EM_A[15]/
AD29/
EM_D[2]/GP[49]
B11
C13
I/O/Z
IPD
DVDD33
CI4(CCD12) /
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
C11
B13
I/O/Z
IPD
DVDD33
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
A11
B14
I/O/Z
IPD
DVDD33
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
D11
A14
I/O/Z
IPD
DVDD33
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
B12
C14
I/O/Z
IPD
DVDD33
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
C12
C15
I/O/Z
IPD
DVDD33
J22
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I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
These pins are multiplexed between VPFE (CCDC), EMIFA (NAND),
PCI, and GPIO.
For EMIFA (NAND) AEM[2:0] = 011, these pins are the 8-bit
bi-directional data bus (EM_D[7:0]).
Device Overview
37
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 4, AEM[2:0] = 100)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 4, AEM[2:0] = 100)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). For
more details, see Section 3.7, Multiplexed Pin Configurations.
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
EM_WAIT/
(RDY/BSY)
E15
D20
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
EM_OE
D15
D19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is read enable output (RE).
EM_WE
E14
C19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is write enable output (WE).
A20
I/O/Z
IPD
DVDD33
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
HSYNC/EM_CS5/
GP[33]
(1)
(2)
(3)
38
F19
J22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 4, AEM[2:0] = 100) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
CI7(CCD15) /
EM_A[13]/
AD25/
EM_D[0]/GP[51]
B10
A12
I/O/Z
IPD
DVDD33
CI6(CCD14) /
EM_A[14]/
AD27/
EM_D[1]/GP[50]
A10
A13
I/O/Z
IPD
DVDD33
CI5(CCD13) /
EM_A[15]/
AD29/
EM_D[2]/GP[49]
B11
C13
I/O/Z
IPD
DVDD33
CI4(CCD12) /
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
C11
B13
I/O/Z
IPD
DVDD33
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
A11
B14
I/O/Z
IPD
DVDD33
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
D11
A14
I/O/Z
IPD
DVDD33
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
B12
C14
I/O/Z
IPD
DVDD33
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
C12
C15
I/O/Z
IPD
DVDD33
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DESCRIPTION
These pins are multiplexed between VPFE (CCDC), EMIFA (NAND),
PCI, and GPIO.
For EMIFA (NAND) AEM[2:0] = 100, these pins are the 8-bit
bi-directional data bus (EM_D[7:0]).
Device Overview
39
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 5, AEM[2:0] = 101)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). For
more details, see Section 3.7, Multiplexed Pin Configurations.
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
EM_WAIT/
(RDY/BSY)
E15
D20
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
EM_OE
D15
D19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is read enable output (RE).
EM_WE
E14
C19
I/O/Z
IPU
DVDD33
When used for EMIFA (NAND), this pin is write enable output (WE).
A20
I/O/Z
IPD
DVDD33
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
NAND flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
HSYNC/EM_CS5/
GP[33]
(1)
(2)
(3)
40
F19
J22
I/O/Z
IPD
DVDD33
For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND
flash.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
COUT0/EM_D0/
GP[14]
D16
E21
I/O/Z
IPD
DVDD33
COUT1/EM_D1/
GP[15]
D18
G20
I/O/Z
IPD
DVDD33
COUT2/EM_D2/
GP[16]
D17
E22
I/O/Z
IPD
DVDD33
COUT3/EM_D3/
GP[17]
E16
F20
I/O/Z
IPD
DVDD33
These pins are multiplexed between VPBE (VENC), EMIFA (NAND),
and GPIO.
COUT4/EM_D4/
GP[18]
E18
G21
I/O/Z
IPD
DVDD33
For EMIFA (NAND) AEM[2:0] = 101, these are the 8-bit bi-directional
data bus (EM_D[7:0]).
COUT5/EM_D5/
GP[19]
E17
F22
I/O/Z
IPD
DVDD33
COUT6/EM_D6/
GP[20]
F16
F21
I/O/Z
IPD
DVDD33
COUT7/EM_D7/
GP[21]
F17
H20
I/O/Z
IPD
DVDD33
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DESCRIPTION
Device Overview
41
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-14. DDR2 Memory Controller Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DDR_CLK
W7
AB7
I/O/Z
DVDDR2
DDR2 Clock Output
DDR_CLK
W8
AB8
I/O/Z
DVDDR2
DDR2 Differential Clock Output
DDR_CKE
V8
AA8
I/O/Z
DVDDR2
DDR2 Clock Enable Output
DDR_CS
T9
Y11
I/O/Z
DVDDR2
DDR2 Active Low Chip Select Output
DDR_WE
T8
Y10
I/O/Z
DVDDR2
DDR2 Active Low Write Enable Output
DDR_DQM[3]
T16
Y18
I/O/Z
DVDDR2
DDR_DQM[2]
T14
Y15
I/O/Z
DVDDR2
DDR_DQM[1]
T6
Y7
I/O/Z
DVDDR2
DDR_DQM[0]
T4
Y4
I/O/Z
DVDDR2
DDR2 Data Mask Outputs
DQM3: For upper byte data bus DDR_D[31:24]
DQM2: For DDR_D[23:16]
DQM1: For DDR_D[15:8]
DQM0: For lower byte DDR_D[7:0]
DDR_RAS
U7
Y8
I/O/Z
DVDDR2
DDR2 Row Access Signal Output
DDR_CAS
T7
Y9
I/O/Z
DVDDR2
DDR2 Column Access Signal Output
DDR_DQS[0]
U4
AA4
I/O/Z
DVDDR2
Data Strobe Input/Outputs for each byte of the 32-bit data bus. They
are outputs to the DDR2 memory when writing and inputs when
reading. They are used to synchronize the data transfers.
DQS3 : For upper byte DDR_D[31:24]
DQS2: For DDR_D[23:16]
DQS1: For DDR_D[15:8]
DQS0: For bottom byte DDR_D[7:0]
DESCRIPTION
DDR2 Memory Controller
(1)
(2)
(3)
42
DDR_DQS[1]
U6
AA7
I/O/Z
DVDDR2
DDR_DQS[2]
U14
AA15
I/O/Z
DVDDR2
DDR_DQS[3]
U16
AA18
I/O/Z
DVDDR2
DDR_BA[0]
U8
AA9
DDR_BA[1]
V9
AB9
I/O/Z
DVDDR2
Bank Select Outputs (BA[2:0]). Two are required to support 1Gb DDR2
memories.
DDR_BA[2]
U9
AB10
DDR_A[12]
W9
AA10
DDR_A[11]
W10
AA11
DDR_A[10]
U10
AB11
DDR_A[9]
U11
AA12
DDR_A[8]
V10
Y12
DDR_A[7]
V11
AB12
DDR_A[6]
W11
AA13
I/O/Z
DVDDR2
DDR2 Address Bus Output
DDR_A[5]
W12
Y13
DDR_A[4]
V12
AB13
DDR_A[3]
U12
AA14
DDR_A[2]
V13
Y14
DDR_A[1]
U13
AB14
DDR_A[0]
W13
AB15
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Fore more information, see the Recommended Operating Conditions table
Device Overview
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-14. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
DDR_D[31]
T19
Y22
DDR_D[30]
U19
AA21
DDR_D[29]
V18
Y21
DDR_D[28]
U18
AB20
DDR_D[27]
W17
Y20
DDR_D[26]
T18
AA20
DDR_D[25]
U17
AB19
DDR_D[24]
V17
Y19
DDR_D[23]
T17
AA19
DDR_D[22]
V16
AB18
DDR_D[21]
W16
AB17
DDR_D[20]
U15
Y17
DDR_D[19]
V15
AA17
DDR_D[18]
W15
AB16
DDR_D[17]
V14
Y16
DDR_D[16]
W14
AA16
DDR_D[15]
V7
AB6
DDR_D[14]
W6
Y6
DDR_D[13]
V6
AA6
DDR_D[12]
W5
AB5
DDR_D[11]
V5
Y5
DDR_D[10]
U5
AA5
DDR_D[9]
W4
W5
DDR_D[8]
V4
AB4
DDR_D[7]
W3
W4
DDR_D[6]
V3
AB3
DDR_D[5]
U3
Y3
DDR_D[4]
V2
AA3
DDR_D[3]
U2
AA2
DDR_D[2]
U1
W2
DDR_D[1]
T2
Y2
DDR_D[0]
T1
Y1
DDR_VREF
T15
W18
TYPE (1)
OTHER (2) (3)
I/O/Z
DVDDR2
I
(3)
Reference voltage input for the SSTL_18 I/O buffers
Ground for the DDR2 DLL
DESCRIPTION
DDR2 bi-directional data bus can be configured as 32-bits wide or
16-bits wide.
DDR_VSSDLL
T13
W15
GND
(3)
DDR_VDDDLL
T12
W14
S
(3)
Power (1.8 Volts) for the DDR2 Digital Locked Loop
Impedance control for DDR2 outputs. This must be connected via a
200-Ω resistor to DVDDR2.
Impedance control for DDR2 outputs. This must be connected via a
200-Ω resistor to VSS.
DDR_ZN
T10
W12
(3)
DDR_ZP
T11
W13
(3)
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Device Overview
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TMS320DM6437
Digital Media Processor
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www.ti.com
Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
PCI
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
C11
B13
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI,
and GPIO.
In PCI mode, this pin is PCI bus grant (I)
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
D11
A14
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI,
and GPIO.
In PCI mode, this pin is PCI reset (I)
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
B12
C14
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI,
and GPIO.
In PCI mode, this pin is the PCI bus request (O/Z)
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
C12
C15
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI,
and GPIO.
In PCI mode, this pin is the PCI interrupt A (O/Z)
EM_A[12]/PCBE3/
GP[89]
D10
B12
I/O/Z
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 3 (I/O/Z).
HD3/VLYNQ_RXD2/
PCBE2 /GP[61]
B7
B8
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 2 (I/O/Z)
HD11/MTXD3/
PCBE1/GP[69]
C5
A5
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In PCI mode, this pin is the PCI command/byte enable 1 (I/O/Z)
HRDY/MRXD2/
PCBE0/GP[80]
D2
C3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 0 (I/O/Z)
EM_A[9]/PIDSEL/
GP[92]
D9
C11
I/O/Z
IPD
DVDD33
This pin is multiplexed between EMIFA, PCI, and GPIO.
In PCI mode, this pin is the PCI initialization device select (I)
VLYNQ_CLOCK/
PCICLK/GP[57]
A7
A8
I/O/Z
IPU
DVDD33
This pin is multiplexed between VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI clock (I)
HD4/VLYNQ_RXD3/
PFRAME/GP[62]
C7
C8
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI frame (I/O/Z)
HD5/VLYNQ_TXD0/
PIRDY/GP[63]
A6
A7
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI initiator ready (I/O/Z)
HD6/VLYNQ_TXD1/
PTRDY/GP[64]
D6
C7
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI target ready (I/O/Z)
HD7/VLYNQ_TXD2/
PDEVSEL/GP[65]
B6
B7
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI device select (I/O/Z)
HD8/VLYNQ_TXD3/
PPERR/GP[66]
A5
A6
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI parity error (I/O/Z)
HD9/MCOL/
PSTOP/GP[67]
C6
C6
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In PCI mode, this pin is the PCI stop (I/O/Z)
HD10/MCRS/
PSERR/GP[68]
B5
B6
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In PCI mode, this pin is the PCI system error (I/O/Z)
HD12/MTXD2/
PPAR/GP[70]
D5
C5
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In PCI mode, this pin is the PCI parity (I/O/Z)
(1)
(2)
(3)
44
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
A11
B14
I/O/Z
IPD
DVDD33
AD30
E12
D14
I/O/Z
IPD
DVDD33
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/GP[49]
B11
C13
I/O/Z
IPD
DVDD33
AD28
E11
D13
I/O/Z
IPD
DVDD33
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/GP[50]
A10
A13
I/O/Z
IPD
DVDD33
AD26
E10
D12
I/O/Z
IPD
DVDD33
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/GP[51]
B10
A12
I/O/Z
IPD
DVDD33
EM_A[11]/AD24/GP[90]
C10
C12
I/O/Z
IPD
DVDD33
EM_A[10]/AD23/GP[91]
A9
B11
I/O/Z
IPD
DVDD33
EM_A[7]/AD22/GP[94]
C9
C10
I/O/Z
IPD
DVDD33
EM_A[8]/AD21/GP[93]
B9
A11
I/O/Z
IPD
DVDD33
EM_A[6]/AD20/GP[95]
D8
B10
I/O/Z
IPD
DVDD33
EM_A[5]/AD19/GP[96]
B8
A10
I/O/Z
IPD
DVDD33
HD0/VLYNQ_SCRUN/
AD18/GP[58]
C8
B9
I/O/Z
IPU
DVDD33
HD2/VLYNQ_RXD1/
AD17/GP[60]
A8
A9
I/O/Z
IPD
DVDD33
HD1/VLYNQ_RXD0/
AD16/GP[59]
D7
C9
I/O/Z
IPD
DVDD33
HD14/MTXD0/
AD15/GP[72]
D4
B5
I/O/Z
IPD
DVDD33
HD13/MTXD1/
AD14/GP[71]
B4
B4
I/O/Z
IPD
DVDD33
HHWIL/MRXDV/
AD13/GP[74]
C4
D3
I/O/Z
IPD
DVDD33
HD15/MTXCLK/
AD12/GP[73]
A4
A4
I/O/Z
IPD
DVDD33
HCNTL1/MTXEN/
AD11/GP[75]
D3
C4
I/O/Z
IPD
DVDD33
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DESCRIPTION
These pins are multiplexed between VPFE (CCDC), PCI, EMIFA,
HPI, VLYNQ, EMAC (MII), and GPIO.
For PCI, these pins are PCI data-address bus [31:0] (I/O/Z)
Device Overview
45
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
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Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL
46
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
HCNTL0/MRXER/
AD10/GP[76]
B3
B2
I/O/Z
IPD
DVDD33
HDS2/MRXD0/
AD9/GP[78]
C3
C2
I/O/Z
IPU
DVDD33
HR/W/MRXCLK/
AD8/GP[77]
A3
A3
I/O/Z
IPD
DVDD33
HDS1/MRXD1/
AD7/GP[79]
B2
B3
I/O/Z
IPU
DVDD33
HINT/MRXD3/
AD6/GP[82]
C2
D2
I/O/Z
IPU
DVDD33
HCS/MDCLK/
AD5/GP[81]
C1
D1
I/O/Z
IPU
DVDD33
AD4/GP[3]
E4
F2
I/O/Z
IPD
DVDD33
HAS/MDIO/
AD3/GP[83]
D1
C1
I/O/Z
IPU
DVDD33
AD2/GP[2]
E3
F1
I/O/Z
IPD
DVDD33
AD1/GP[1]
E2
E2
I/O/Z
IPD
DVDD33
AD0/GP[0]
E1
E1
I/O/Z
IPD
DVDD33
Device Overview
DESCRIPTION
These pins are multiplexed between VPFE (CCDC), PCI, EMIFA,
HPI, VLYNQ, EMAC (MII), and GPIO.
For PCI, these pins are PCI data-address bus [31:0] (I/O/Z)
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Table 2-16. EMAC and MDIO Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
EMAC
HCNTL1/MTXEN/
AD11/GP[75]
D3
C4
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Enable output MTXEN.
HD15/MTXCLK/
AD12/GP[73]
A4
A4
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Clock input MTXCLK.
HD9/MCOL/
PSTOP/GP[67]
C6
C6
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Collision Detect input MCOL.
HD11/MTXD3/
PCBE1/GP[69]
C5
A5
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 3 output MTXD3.
HD12/MTXD2/
PPAR/GP[70]
D5
C5
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 2 output MTXD2.
HD13/MTXD1/
AD14/GP[71]
B4
B4
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 1 output MTXD1.
HD14/MTXD0/
AD15/GP[72]
D4
B5
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 0 output MTXD0.
HR/W/MRXCLK/
AD8/GP[77]
A3
A3
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Clock input MRXCLK.
HHWIL/MRXDV/
AD13/GP[74]
C4
D3
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data Valid input MRXDV.
HCNTL0/MRXER/
AD10/GP[76]
B3
B2
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Error input MRXER.
HD10/MCRS/
PSERR/GP[68]
B5
B6
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Carrier Sense input MCRS.
HINT/MRXD3/
AD6/GP[82]
C2
D2
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data 3 input MRXD3.
HRDY/MRXD2/
PCBE0/GP[80]
D2
C3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data 2 input MRXD2.
HDS1/MRXD1/
AD7/GP[79]
B2
B3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive data 1 input MRXD1.
HDS2/MRXD0/
AD9/GP[78]
C3
C2
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data 0 input MRXD0.
MDIO
(1)
(2)
(3)
HCS/MDCLK/
AD5/GP[81]
C1
D1
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, MDIO, PCI, and GPIO.
In Ethernet MAC mode, it is Management Data Clock output
MDCLK.
HAS/MDIO/
AD3/GP[83]
D1
C1
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, MDIO, PCI, and GPIO.
In Ethernet MAC mode, it is Management Data I/O MDIO (I/O/Z).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-17. VLYNQ Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
This pin is multiplexed between VLYNQ, PCI, and GPIO.
For VLYNQ, it is the clock VLYNQ_CLOCK (I/O/Z).
DESCRIPTION
VLYNQ
VLYNQ_CLOCK/
PCICLK/GP[57]
A7
A8
I/O/Z
IPU
DVDD33
HD0/VLYNQ_SCRUN/
AD18/GP[58]
C8
B9
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN
(I/O/Z).
HD8/VLYNQ_TXD3/
PPERR/GP[66]
A5
A6
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.
HD7/VLYNQ_TXD2/
PDEVSEL/GP[65]
B6
B7
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.
HD6/VLYNQ_TXD1/
PTRDY/GP[64]
D6
C7
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.
HD5/VLYNQ_TXD0/
PIRDY/GP[63]
A6
A7
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 0 output VLYNQ_TXD0.
HD4/VLYNQ_RXD3/
PFRAME/GP[62]
C7
C8
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.
HD3/VLYNQ_RXD2/
PCBE2/GP[61]
B7
B8
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.
HD2/VLYNQ_RXD1/
AD17/GP[60]
A8
A9
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.
HD1/VLYNQ_RXD0/
AD16/GP[59]
D7
C9
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.
(1)
(2)
(3)
48
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Device Overview
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Digital Media Processor
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-18. Host-Port Interface Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
Host-Port Interface (HPI)
HD0/VLYNQ_SCRUN/
AD18/GP[58]
C8
B9
HD1/VLYNQ_RXD0/
AD16/GP[59]
D7
C9
HD2/VLYNQ_RXD1/
AD17/GP[60]
A8
A9
HD3/VLYNQ_RXD2/
PCBE2/GP[61]
B7
B8
HD4/VLYNQ_RXD3/
PFRAME/GP[62]
C7
C8
HD5/VLYNQ_TXD0/
PIRDY/GP[63]
A6
A7
HD6/VLYNQ_TXD1/
PTRDY/GP[64]
D6
C7
HD7/VLYNQ_TXD2/
PDEVSEL/GP[65]
B6
B7
HD8/VLYNQ_TXD3/
PPERR/GP[66]
A5
A6
HD9/MCOL/
PSTOP/GP[67]
C6
C6
HD10/MCRS/
PSERR/GP[68]
B5
B6
HD11/MTXD3/
PCBE1/GP[69]
C5
A5
HD12/MTXD2/
PPAR/GP[70]
D5
C5
HD13/MTXD1/
AD14/GP[71]
B4
B4
HD14/MTXD0/
AD15/GP[72]
D4
B5
HD15/MTXCLK/
AD12/GP[73]
A4
A4
HHWIL/MRXDV/
AD13/GP[74]
C4
D3
HCNTL1/MTXEN/
AD11/GP[75]
(1)
(2)
(3)
IPU
DVDD33
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ or EMAC, PCI,
and GPIO.
In HPI mode, these pins are host-port data pins HD[15:0]
(I/O/Z) and are multiplexed internally with the HPI address
lines.
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is half-word identification input HHWIL
(I).
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is control input 1 HCNTL1 (I). The state
of HCNTL1 and HCNTL0 determines if address, data, or
control information is being transmitted between an external
host and the DM6437.
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is control input 0 HCNTL0 (I). The state
of HCNTL1 and HCNTL0 determines if address, data, or
control information is being transmitted between an external
host and the DM6437.
I/O/Z
D3
C4
HCNTL0/MRXER/
AD10/GP[76]
B3
B2
I/O/Z
IPD
DVDD33
HR/W/MRXCLK/
AD8/GP[77]
A3
A3
I/O/Z
IPD
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host read or write select input
HR/W(I).
HDS2/MRXD0/
AD9/GP[78]
C3
C2
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host data strobe input 2 HDS2 (I).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 2-18. Host-Port Interface Terminal Functions (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
HDS1/MRXD1/
AD7/GP[79]
B2
B3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host data strobe input 1 HDS1 (I).
HRDY/MRXD2/
PCBE0/GP[80]
D2
C3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host ready output from DSP to host
(O/Z).
HCS/MDCLK/
AD5/GP[81]
C1
D1
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, MDIO, PCI, and GPIO.
In HPI mode, this pin is HPI active low chip select input HCS
(I).
HINT/RXD3/
AD6/GP[82]
C2
D2
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host interrupt output HINT (O/Z).
I/O/Z
IPU
DVDD33
This pin is multiplexed between HPI, MDIO, PCI, and GPIO.
In HPI mode, this pin is host address strobe HAS (I).
For proper HPI operation, if this pin is routed out, it must be
pulled up via an external resistor.
HAS/MDIO/
AD3/GP[83]
50
Device Overview
D1
C1
DESCRIPTION
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-19. VPFE Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
VIDEO/IMAGE IN (VPFE)
PCLK/GP[54]
VD/GP[53]
HD/GP[52]
A14
A13
A15
A18
A17
A19
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC) and GPIO.
In VPFE mode, this pin is the pixel clock input (PCLK) used to load
image data into the CCD Controller (CCDC) on pins CI[7:0] and
YI[7:0].
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC) and GPIO.
In VPFE mode, this pin is the vertical synchronization signal (VD) that
can be either an input (slave mode) or an output (master mode),
which signals the start of a new frame to the CCDC.
I/O/Z
IPD
DVDD33
This pin is multiplexed between the VPFE (CCDC) and GPIO.
In VPFE mode, this pin is the horizontal synchronization signal (HD)
that can be either an input (slave mode) or an output (master mode),
which signals the start of a new line to the CCDC.
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/GP[51]
B10
A12
I/O/Z
IPD
DVDD33
When used by the CCDC as input CI7, it supports several modes:
In 16-bit CCD Raw mode, it is input CCD15.
In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and
CR7 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/GP[50]
A10
A13
I/O/Z
IPD
DVDD33
When used by the CCDC as input CI6, it supports several modes:
In 16-bit CCD Raw mode, it is input CCD14.
In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and
CR6 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/GP[49]
B11
C13
I/O/Z
IPD
DVDD33
When used by the CCDC as input CI5, it supports several modes:
In 16-bit CCD Raw mode, it is input CCD13.
In 16-bit YCbCr mode, it is time multiplexed between CB5, and CR5
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and
CR5 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
(1)
(2)
(3)
(4)
When used by the CCDC as input CI4, it supports several modes:
C11
B13
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD12.
In 16-bit YCbCr mode, it is time multiplexed between CB4, and CR4
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and
CR4 of the upper 8-bit channel. (4)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
In addition to these default functions, in YCbCr mode, the VPFE CCD Configuration register CCDCFG.YCINSWP bit field allows the
user to swap the function of the YI[7:0] and CI[7:0] pins.
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TMS320DM6437
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Table 2-19. VPFE Terminal Functions (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
When used by the CCDC as input CI3, it supports several modes:
A11
B14
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD11.
In 16-bit YCbCr mode, it is time multiplexed between CB3, and CR3
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and
CR3 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
This pin is CCDC input CI2 and it supports several modes:
D11
A14
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD10.
In 16-bit YCbCr mode, it is time multiplexed between CB2, and CR2
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and
CR2 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
This pin is CCDC input CI1 and it supports several modes:
B12
C14
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD9.
In 16-bit YCbCr mode, it is time multiplexed between CB1, and CR1
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and
CR1 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and
GPIO.
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
This pin is CCDC input CI0 and it supports several modes:
C12
C15
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD8.
In 16-bit YCbCr mode, it is time multiplexed between CB0, and CR0
inputs. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and
CR0 of the upper 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
This pin is CCDC input YI7 and it supports several modes:
YI7(CCD7)/
GP[43]
A12
A15
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD7.
In 16-bit YCbCr mode, it is input Y7. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and
CR7 of the lower 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
This pin is CCDC input YI6 and it supports several modes:
YI6(CCD6)/
GP[42]
B13
B15
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD6.
In 16-bit YCbCr mode, it is input Y6. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and
CR6 of the lower 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
This pin is CCDC input YI5 and it supports several modes:
YI5(CCD5)/
GP[41]
52
C13
Device Overview
B16
I/O/Z
IPD
DVDD33
In 16-bit CCD Raw mode, it is input CCD5.
In 16-bit YCbCr mode, it is input Y5. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and
CR5 of the lower 8-bit channel. (4)
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Table 2-19. VPFE Terminal Functions (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
This pin is multiplexed between the VPFE(CCDC) and GPIO.
YI4(CCD4)/
GP[40]
D14
C18
I/O/Z
IPD
DVDD33
This pin is CCDC input YI4 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD4.
In 16-bit YCbCr mode, it is input Y4. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and
CR4 of the lower 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI3(CCD3)/
GP[39]
B14
A16
I/O/Z
IPD
DVDD33
This pin is CCDC input YI3 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD3.
In 16-bit YCbCr mode, it is input Y3. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and
CR3 of the lower 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI2(CCD2)/
GP[38]
C14
B17
I/O/Z
IPD
DVDD33
This pin is CCDC input YI2 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD2.
In 16-bit YCbCr mode, it is input Y2. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and
CR2 of the lower 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI1(CCD1)/
GP[37]
B15
B18
I/O/Z
IPD
DVDD33
This pin is CCDC input YI1 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD1.
In 16-bit YCbCr mode, it is input Y1. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and
CR1 of the lower 8-bit channel. (4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
This pin is CCDC input YI0 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD0.
In 16-bit YCbCr mode, it is input Y0. (4)
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and
CR0 of the lower 8-bit channel. (4)
YI0(CCD0)/
GP[36]
C15
B19
I/O/Z
IPD
DVDD3
C_WE/EM_R/W/
GP[35]
D13
C17
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
In VPFE mode, it is the CCD Controller write enable input C_WE.
C_FIELD/EM_A[21]/
GP[34]
D12
C16
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
In VPFE mode, it is CCDC field identification bidirectional signal
C_FIELD.
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Digital Media Processor
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Table 2-20. VPBE Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the VPBE Horizontal Sync (I/O/Z).
DESCRIPTION
VIDEO OUT (VPBE)
HSYNC/EM_CS5/
GP[33]
F19
J22
I/O/Z
IPD
DVDD33
VSYNC/EM_CS4/
GP[32]
E19
H22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the VPBE Vertical Sync (I/O/Z).
VCLK/GP[31]
D19
G22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE and GPIO.
In VPBE mode, this pin is the VPBE Clock Output.
VPBECLK/GP[30]
G19
K22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE and GPIO.
In VPBE mode, this pin is the VPBE Clock Input.
COUT0/EM_D[0]/
GP[14]
D16
E21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT0.
COUT1/EM_D[1]/
GP[15]
D18
G20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT1.
COUT2/EM_D[2]/
GP[16]
D17
E22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT2.
COUT3/EM_D[3]/
GP[17]
E16
F20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT3.
COUT4/EM_D[4]/
GP[18]
E18
G21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT4.
COUT5/EM_D[5]/
GP[19]
E17
F22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT5.
COUT6/EM_D[6]/
GP[20]
F16
F21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE(VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT6.
COUT7/EM_D[7]/
GP[21]
F17
H20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
In VPBE mode, this pin is the video encoder (VENC) output COUT7.
YOUT0/GP[22]/
(BOOTMODE0)
F18
J20
I/O/Z
IPD
DVDD33
YOUT1/GP[23]/
(BOOTMODE1)
F15
K20
I/O/Z
IPD
DVDD33
YOUT2/GP[24]/
(BOOTMODE2)
G15
L20
I/O/Z
IPD
DVDD33
These pins are multiplexed between VPBE (VENC) and GPIO.
After reset, these are video encoder (VENC) outputs 6:0, YOUT[6:0].
YOUT3/GP[25]/
(BOOTMODE3)
G16
H21
I/O/Z
IPD
DVDD33
YOUT4/GP[26]/
(FASTBOOT)
G17
K19
I/O/Z
IPD
DVDD33
For proper DM6437 device operation, the YOUT6 pin must be pulled
down via an external resistor.
For proper DM6437 device operation, the YOUT5 pin must be pulled
up via an external resistor.
YOUT5/GP[27]
H17
L19
I/O/Z
IPU
DVDD33
YOUT6/
GP[28]
H16
J21
I/O/Z
IPD
DVDD33
YOUT7/
GP[29]
H15
K21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE (VENC) and GPIO.
In VPBE mode, this pin is the VENC output 7, YOUT7.
LCD_OE/EM_CS3/
GP[13]
C18
D22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, it is the LCD output enable LCD_OE (O/Z).
G0/EM_CS2/
GP[12]
C19
C22
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Green output data bit 0,
G0.
B0/LCD_FIELD/
EM_A[3]/GP[11]
B18
D21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Blue output data bit 0, B0
or LCD interlaced LCD_FIELD (I/O/Z).
(1)
(2)
(3)
54
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-20. VPBE Terminal Functions (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
R0/EM_A[4]/
GP[10]/
(AEAW2/PLLMS2)
A17
B21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Red output data bit 0, R0.
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Green output data bit 1,
G1.
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
A20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Blue output data bit 1,
B1.
R1/EM_A[0]/
GP[7]/(AEM2)
B17
C21
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Red output data bit 1, R1.
R2/EM_BA[0]/
GP[6]/(AEM1)
C17
E20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Red output data bit 2, R2.
B2/EM_BA[1]/
GP[5]/(AEM0)
C16
C20
I/O/Z
IPD
DVDD33
This pin is multiplexed between VPBE, EMIFA, and GPIO.
In VPBE mode, this pin is the RGB666/888 Blue output data bit 2,
B2.
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Digital Media Processor
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Table 2-21. DAC [Part of VPBE] Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
DAC[A:D]
Reference voltage input (0.5 V)
DAC_VREF
N19
V22
AI
(3)
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be tied directly to VSS.
Output of DAC A
DAC_IOUT_A
P19
V21
AO
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be left unconnected.
Output of DAC B
DAC_IOUT_B
P18
U22
AO
DAC_IOUT_C
N18
T21
AO
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be left unconnected.
Output of DAC C
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be left unconnected.
Output of DAC D
DAC_IOUT_D
N17
T22
AO
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be left unconnected.
1.8 V Analog I/O power
VDDA_1P8V
P17
V20
S
(3)
GND
(3)
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be tied directly to VSS.
Analog I/O ground
VSSA_1P8V
P16
U20
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be tied directly to VSS.
1.20 V Analog core supply voltage
(-7/-6/-5/-4/-L/-Q6/-Q5/-Q4 devices)
VDDA_1P1V
N15
T20
S
(3)
1.05 V Analog core supply voltage
(-7/-6/-5/-4/-L/-Q5 devices)
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be tied directly to VSS.
Analog core ground
VSSA_1P1V
P15
T19
GND
(3)
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be tied directly to VSS.
External resistor connection for current bias configuration.
This must be connected via a 4 kΩ resistor to VSSA_1P8V.
DAC_RBIAS
N16
U21
AI
(3)
Note: If the DAC peripheral is not being used, for proper device
operation, this pin must be tied directly to VSS.
(1)
(2)
(3)
56
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
Specifies the operating I/O supply voltage for each signal
For more information, see the Recommended Operating Conditions table
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Table 2-22. I2C Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
I2C
(1)
(2)
(3)
SCL
M2
N2
I/O/Z
DVDD33
For I2C, this pin is I2C clock. In I2C master mode, this pin is an
output. In I2C slave mode, this pin is an input.
When the I2C module is used, for proper device operation, this pin
must be pulled up via an external resistor.
SDA
M3
P2
I/O/Z
DVDD33
For I2C, this pin is the I2C bi-directional data signal.
When the I2C module is used, for proper device operation, this pin
must be pulled up via an external resistor.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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TMS320DM6437
Digital Media Processor
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Table 2-23. Multichannel Buffered Serial Port 0 and Multichannel Buffered Serial Port 1 (McBSP0 and
McBSP1) Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
Multichannel Buffered Serial Port 0 (McBSP0)
For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations.
CLKS0/TOUT0L/
GP[97]
J4
L3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McBSP0, Timer0, and GPIO.
For McBSP0, it is McBSP0 external clock source (I).
ACLKR0/CLKX0/
GP[99]
H1
J1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z).
AHCLKR0/CLKR0/
GP[101]
J2
K1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z).
AXR0[2]/FSX0/
GP[103]
H3
J2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit frame synchronization FSX0
(I/O/Z).
AXR0[3]/FSR0/
GP[102]
G4
J3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive frame synchronization FSR0
(I/O/Z).
AXR0[1]/DX0/
GP[104]
J3
K2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data transmit output DX0 (O/Z).
AFSR0/DR0/
GP[100]
H4
K3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data receive input DR0 (I).
Multichannel Buffered Serial Port 1 (McBSP1)
For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations.
CLKS1/TINP0L/
GP[98]
K2
L2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McBSP1, Timer0, and GPIO.
For McBSP1, it is McBSP1 external clock source (I).
ACLKX0/CLKX1/
GP[106]
F1
G1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 transmit clock CLKX1 (I/O/Z).
AHCLKX0/CLKR1/
GP[108]
G1
H1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 receive clock CLKR1 (I/O/Z).
AMUTEIN0/FSX1/
GP[109]
F2
G3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 transmit frame synchronization FSX1
(I/O/Z).
AXR0[0]/FSR1/
GP[105]
H2
H2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 receive frame synchronization FSR1
(I/O/Z).
AFSX0/DX1/
GP[107]
G2
G2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 data transmit output DX1 (O/Z).
AMUTE0/DR1/
GP[110]
G3
H3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 data receive input DR1 (I).
(1)
(2)
(3)
58
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-24. Multichannel Audio Serial Port (McASP0) Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 mute input AMUTEIN0 (I).
DESCRIPTION
McASP0
AMUTEIN0/FSX1/
GP[109]
F2
G3
I/O/Z
IPD
DVDD33
AMUTE0/DR1/
GP[110]
G3
H3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 mute output AMUTE0 (O/Z).
ACLKR0/CLKX0/
GP[99]
H1
J1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive bit clock ACLKR0 (I/O/Z).
AHCLKR0/CLKR0/
GP[101]
J2
K1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive high-frequency master clock
AHCLKR0 (I/O/Z).
ACLKX0/CLKX1/
GP[106]
F1
G1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit bit clock ACLKX0 (I/O/Z).
AHCLKX0/CLKR1/
GP[108]
G1
H1
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit high-frequency master clock
AHCLKX0 (I/O/Z).
AFSR0/DR0/
GP[100]
H4
K3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive frame synchronization AFSR0
(I/O/Z).
AFSX0/DX1/
GP[107]
G2
G2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit frame synchronization AFSX0
(I/O/Z).
AXR0[3]/FSR0/
GP[102]
G4
J3
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 3
AXR0[3] (I/O/Z).
AXR0[2]/FSX0/
GP[103]
H3
J2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 2
AXR0[2] (I/O/Z).
AXR0[1]/DX0/
GP[104]
J3
K2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 1
AXR0[1] (I/O/Z).
AXR0[0]/FSR1/
GP[105]
H2
H2
I/O/Z
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 0
AXR0[0] (I/O/Z).
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-25. High-End Controller Area Network (HECC)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
HECC
(1)
(2)
(3)
60
HECC_RX/
TINP1L/
URXD1/
GP[56]
L4
P3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HECC, Timer 1, UART1, and GPIO.
For HECC, this pin is HECC receive serial data HECC_RX (I).
HECC_TX/
TOUT1L/
UTXD1/
GP[55]
K4
N3
I/O/Z
IPU
DVDD33
This pin is multiplexed between HECC, Timer 1, UART1, and GPIO.
For HECC, this pin is HECC transmit serial data HECC_TX (O/Z).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-26. UART0 and UART1 Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
UART1
HECC_RX/
TINP1L/
URXD1/
GP[56]
L4
P3
I/O/Z
IPU
DVDD33
This pin is multiplexed between the HECC, Timer 1, UART1 (Data),
and GPIO.
Fo UART1 this pin is the receive data input URXD1.
HECC_TX/
TOUT1L/
UTXD1/
GP[55]
K4
N3
I/O/Z
IPU
DVDD33
This pin is multiplexed between the HECC, Timer 1, UART1 (Data),
and GPIO.
Fo UART1 this pin is the transmit data output UTXD1.
UART0
(1)
(2)
(3)
URXD0/
GP[85]
L2
M2
I/O/Z
IPU
DVDD33
This pin is multiplexed between UART0 (Data) and GPIO.
When used by UART0 this pin is the receive data input URXD0.
UTXD0/
GP[86]
K3
N1
I/O/Z
IPU
DVDD33
This pin is multiplexed between UART0 (Data) and GPIO.
In UART0 mode, this pin is the transmit data output UTXD0.
UCTS0
GP[87]
L1
P1
I/O/Z
IPU
DVDD33
This pin is multiplexed between the UART0 (Flow Control) and GPIO.
In UART0 mode, this pin is the clear to send input UCTS0.
URTS0
PWM0
GP[88]
L3
M3
I/O/Z
IPU
DVDD33
This pin is multiplexed between the UART0 (Flow Control), PWM0,
and GPIO.
In UART0 mode, this pin is the ready to send output URTS0.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-27. PWM0, PWM1, and PWM2 Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
PWM2
CLKOUT0/PWM2/
GP[84]
M1
R1
I/O/Z
IPD
DVDD33
I/O/Z
IPD
DVDD33
This pin is multiplexed between the System Clock generator (PLL1),
PWM2, and GPIO.
For PWM2, this pin is output PWM2.
PWM1
GP[4]/PWM1
F3
F3
This pin is multiplexed between GPIO and PWM1.
For PWM1, this pin is output PWM1.
PWM0
URTS0/PWM0/
GP[88]
(1)
(2)
(3)
62
L3
M3
I/O/Z
IPU
DVDD33
This pin is multiplexed between the UART0 (Flow Control), PWM0,
and GPIO.
For PWM0, this pin is output PWM0.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-28. Timer 0, Timer 1, and Timer 2 Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
Timer 2
No external pins. The Timer 2 (watchdog) peripheral pins are not pinned out as external pins.
Timer 1
HECC_RX/
TINP1L/
URXD1/
GP[56]
L4
P3
I/O/Z
IPU
DVDD33
This pin is multiplexed between the HECC, Timer 1, UART1 (Data),
and GPIO.
For Timer 1, this pin is the timer 1 input pin for the lower 32-bit
counter
HECC_TX/
TOUT1L/
UTXD1/
GP[55]
K4
N3
I/O/Z
IPU
DVDD33
This pin is multiplexed between the HECC, Timer 1, UART1, and
GPIO.
For Timer 1, this pin is the timer 1 output pin for the lower 32-bit
counter
Timer 0
(1)
(2)
(3)
CLKS1/
TINP0L/
GP[98]
K2
L2
I/O/Z
IPD
DVDD33
This pin is multiplexed between the McBSP1, Timer 0, and GPIO.
For Timer 0, this pin is the timer 0 input pin for the lower 32-bit
counter
CLKS0/
TOUT0L/
GP[97]
J4
L3
I/O/Z
IPD
DVDD33
This pin is multiplexed between the McBSP0, Timer 0, and GPIO.
For Timer 0, this pin is the timer 0 output pin for the lower 32-bit
counter
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-29. GPIO Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE (1)
OTHER (2) (3)
DESCRIPTION
GPIO
The 111 GPIO pins on the DM6437 device are multiplexed with other peripherals pin functions (e.g., VPBE, VPFE, PCI, HPI, VLYNQ,
EMAC/MDIO, McASP0, McBSP0, McBSP1, Timer 0, Timer 1, UART0, UART1, PWM0, PWM1, PWM2, EMIFA, and the CLKOUT0 pin), see
the peripheral-specific Terminal Functions tables for the GPIO multiplexing.
(1)
(2)
(3)
64
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-30. Reserved Terminal Functions
SIGNAL
TYPE (1)
OTHER (2) (3)
DESCRIPTION
NAME
ZWT
NO.
ZDU
NO.
RSV1
E5
D4
Reserved. (Leave unconnected, do not connect to power or ground)
RSV2
K5
L4
Reserved. (Leave unconnected, do not connect to power or ground)
RESERVED
(1)
(2)
(3)
RSV3
L5
M4
RSV4
L15
P19
AO
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
RSV5
R13
W16
AO
Reserved. (Leave unconnected, do not connect to power or ground)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
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Table 2-31. Supply Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
A1
A2
A2
A21
TYPE (1)
OTHER
DESCRIPTION
SUPPLY VOLTAGE PINS
DVDD33
A18
B1
E6
D6
E8
D8
F5
D10
F7
D16
F9
D18
F11
E3
F13
E5
G6
E7
G8
E9
G10
E11
G12
E13
G14
E15
H5
E17
H18
E19
J1
F4
J6
F18
J14
G5
J16
G19
K15
H4
K17
H18
L6
J5
M5
J19
M15
K4
N6
K18
P1
L1
S
3.3 V I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
L5
L21
M18
M20
N5
N19
P4
P18
P20
P22
R5
T4
(1)
66
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-31. Supply Terminal Functions (continued)
SIGNAL
NAME
DVDDR2
ZWT
NO.
ZDU
NO.
L14
U5
P5
V1
P7
V4
P9
V6
P11
V8
P13
V10
R4
V12
R6
V14
R8
V16
R10
V18
R12
W7
R14
W9
R16
W11
T5
W17
V1
W19
W18
AA1
W19
AB21
TYPE (1)
OTHER
DESCRIPTION
S
1.8 V DDR2 I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
S
1.20 V supply voltage (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4 devices)
1.05 V core supply voltage (-7/-6/-5/-4/-L/-Q5 devices)
(see the Power-Supply Decoupling section of this data manual)
AB22
CVDD
H7
J10
H9
J11
H11
J12
H13
J13
J8
K9
J10
K14
J12
L9
K7
L13
K9
L14
K11
M9
K13
M10
L8
M14
L10
N9
L12
N14
M7
P10
M9
P11
M11
P12
M13
P13
N8
N10
N12
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Table 2-32. Ground Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
A19
A1
B1
A22
B19
B22
E7
D5
E9
D7
TYPE (1)
OTHER
DESCRIPTION
GROUND PINS
VSS
(1)
68
E13
D9
F4
D11
F6
D15
F8
D17
F10
E4
F12
E6
F14
E8
G5
E10
G7
E12
G9
E14
G11
E16
G13
E18
G18
F5
H6
F19
H8
G4
H10
G18
H12
H5
H14
H19
H19
J4
J5
J9
J7
J14
J9
J18
J11
K5
J13
K10
J15
K11
J17
K12
J18
K13
K1
L10
K6
L11
K8
L12
K10
L18
K12
L22
K14
M1
K16
M5
GND
Ground pins
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-32. Ground Terminal Functions (continued)
SIGNAL
NAME
VSS
ZWT
NO.
ZDU
NO.
L7
M11
L9
M12
L11
M13
L13
M19
L17
N4
L19
N10
M6
N11
M8
N12
M10
N13
M12
N18
M14
P5
M16
P9
M17
P14
M18
P21
M19
R4
N5
R18
N7
R19
N9
R20
N11
R21
N13
R22
N14
T5
P6
T18
P8
U4
P10
U18
P12
U19
P14
V5
R1
V7
R5
V9
R7
V11
R9
V13
R11
V15
R15
V17
R17
V19
R18
W1
R19
W6
V19
W8
W1
W10
W2
W20
TYPE (1)
GND
OTHER
DESCRIPTION
Ground pins
W21
W22
AA22
AB1
AB2
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2.7 Device Support
2.7.1
Development Support
TI offers an extensive line of development tools for the TMS320DM643x DMP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320DM643x DMP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any SoC application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports TMS320DM643x DMP multiprocessor
system debug) EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320DM643x DMP platform, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator
(URL). For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
2.8 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320DM6437ZWTQ6). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
70
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "6" indicates [600-MHz]).
Figure 2-10 provides a legend for reading the complete device name for any TMS320DM643x DMP
platform member.
TMS
PREFIX
TMX = Experimental device
TMS = Qualified device
DEVICE FAMILY
320 = TMS320™ DSP Family
DEVICE
C64x+™ DSP:
DM6437
DM6435
DM6433
DM6431
320
DM6437 ( ) ZWT
( )
( )
DEVICE SPEED RANGE
4 = 400 MHz
5 = 500 MHz
6 = 600 MHz(D)
7 = 700 MHz
L = Low Power Device
TEMPERATURE RANGE (JUNCTION)
Blank
= 0° C to 90° C, Commercial Grade
Q
= -40°C to 125°C, Automotive Grade
R
= 0° C to 90° C, Commercial Grade (Tape and Reel)
S
= -40°C to 125°C, Automotive Grade (Tape and Reel)
PACKAGE TYPE(A)
ZWT = 361-pin plastic BGA, with Pb-Free soldered balls
ZDU = 376-pin plastic BGA, with Pb-Free soldered balls [Green]
SILICON REVISION:
Blank = Revision 1.3
A.
B.
C.
D.
BGA = Ball Grid Array
For “TMX” initial devices, the device number is DM6437.
Not all combinations are available. For more information, see the Orderable Devices table in the Packing Information section.
The maximum CPU frequency for the -Q6 device is 660 MHz. See the PLL1 and PLL2 section for maximum operating
frequencies of the PLL1 controller.
E. The device speed range symbolization indicates the maximum CPU frequency when the core voltage (CVDD) is set to 1.2 V.
To determine the maximum CPU frequency the core voltage is set to 1.05V, refer to the PLL1 and PLL2 section.
Figure 2-10. Device Nomenclature
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2.9 Documentation Support
2.9.1
Related Documentation From Texas Instruments
The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
The current documentation that describes the DM643x DMP, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
72
SPRU978
TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM643x Digital Media Processor (DMP).
SPRU983
TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320DM643x Digital Media Processor
(DMP).
SPRAA84
TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in
the devices that is identical is not included.
SPRU732
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
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3 Device Configurations
3.1 System Module Registers
The system module includes status and control registers required for configuration of the device. Brief
descriptions of the various registers are shown in Table 3-1. System Module registers required for device
configurations are discussed in the following sections.
Table 3-1. System Module Register Memory Map
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C4 0000
PINMUX0
Pin Multiplexing Control 0 (see Section 3.7.2.1, PINMUX0 Register
Description).
0x01C4 0004
PINMUX1
Pin Multiplexing Control 1 (see Section 3.7.2.2, PINMUX1 Register
Description).
0x01C4 0008
DSPBOOTADDR
DSP Boot Address (see Section 3.4.2.3, DSPBOOTADDR Register).
0x01C4 000C
BOOTCMPLT
Boot Complete (see Section 3.4.2.2, BOOTCMPLT Register).
0x01C4 0010
–
Reserved
0x01C4 0014
BOOTCFG
Device Boot Configuration (see Section 3.4.2.1, BOOTCFG Register).
0x01C4 0018 - 0x01C4 0027
–
Reserved
0x01C4 0028
JTAGID
JTAG ID (see Section 6.24.1, JTAG ID (JTAGID) Register
Description(s)).
0x01C4 002C
–
Reserved
0x01C4 0030
HPICTL
HPI Control (see Section 3.6.2.1, HPI Control Register).
0x01C4 0034
–
Reserved
0x01C4 0038
–
Reserved
0x01C4 003C
MSTPRI0
Bus Master Priority Control 0 (see Section 3.6.1, Switch Central
Resource (SCR) Bus Priorities).
0x01C4 0040
MSTPRI1
Bus Master Priority Control 1 (see Section 3.6.1, Switch Central
Resource (SCR) Bus Priorities).
0x01C4 0044
VPSS_CLKCTL
VPSS Clock Control (see Section 3.3.2, VPSS Clocks).
0x01C4 0048
VDD3P3V_PWDN
VDD 3.3-V I/O Powerdown Control (see Section 3.2, Power
Considerations).
0x01C4 004C
DDRVTPER
DDR2 VTP Enable Register (see Section 6.9.4, DDR2 Memory
Controller).
0x01C4 0050 - 0x01C4 0080
–
Reserved
0x01C4 0084
TIMERCTL
Timer Control (see Section 3.6.2.2, Timer Control Register).
0x01C4 0088
EDMATCCFG
EDMA Transfer Controller Default Burst Size Configuration (see
Section 3.6.2.3, EDMA TC Configuration Register).
0x01C4 008C
–
Reserved
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3.2 Power Considerations
The DM6437 provides several means of managing power consumption.
As described in the Section 6.3.4, DM6437 Power and Clock Domains, the DM6437 has one single power
domain—the “Always On” power domain. Within this power domain, the DM6437 utilizes local clock gating
via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see
Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320DM643x DMP DSP Subsystem
Reference Guide (literature number SPRU978).
Some of the DM6437 peripherals support additional power saving features. For more details on power
saving features supported, see the peripheral-specific reference guides [listed/linked in the
TMS320DM643x DMP Peripherals Overview Reference Guide (literature number SPRU983).
Most DM6437 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN
register in the System Module (see Figure 3-1) is used to selectively power down unused 3.3-V I/O pins.
For independent control, the 3.3-V I/Os are separated into functional groups—most of which are named
according to the pin multiplexing groups (see Table 3-2). For these I/O groups, only the I/O buffers needed
for Host/EMIFA Boot or Power-Up Operations are powered up by default (CLKOUT Block, EMIFA/VPSS
Block, Host Block, PCI Data Block, and GPIO Block).
Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user
must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers.
For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see
Section 3.7.3.1, Multiplexed Pins on DM6437.
Note: The VDD3P3V_PWDN register only controls the power to the I/O buffers. The Power and Sleep
Controller (PSC) determines the clock/power state of the peripheral.
31
16
RESERVED
R-0000 0000 0000 0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PCIDAT
EMBK3
UR0FC
UR0DAT
TIMER1
TIMER0
SP
PWM1
GPIO
HOST
EMBK2
EMBK1
EMBK0
CLKOUT
R-00
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-1. VDD3P3V_PWDN Register— 0x01C4 0048
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Table 3-2. VDD3P3V_PWDN Register Descriptions (1)
BIT
NAME
31:14
RESERVED
DESCRIPTION
Reserved. Read-only, writes have no effect.
PCI Data Block I/O Power Down Control.
Controls the power of the 3 I/O pins in the PCI Data Block.
13
PCIDAT
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
EMIFA/VPSS Sub-Block 3 I/O Power Down Control.
Controls the power of the 8 I/O pins in the EMIFA/VPSS Sub-Block 3.
12
EMBK3
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
UART0 Flow Control Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the UART0 Flow Control Block.
11
UR0FC
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
UART0 Data Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the UART0 Data Block.
10
UR0DAT
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
Timer1 Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the Timer1 Block.
9
TIMER1
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
Timer0 Block I/O Power Down Control.
Controls the power of the 2 I/O pins in the Timer0 Block.
8
TIMER0
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
7
SP
Serial Port Block I/O Power Down Control.
Controls the power of the 12 I/O pins in the Serial Port Block (Serial Port Sub-Block 0 and
Serial Port Sub-Block 1).
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
PWM1 Block I/O Power Down Control.
Contros thel power of the 1 I/O pin in the PWM1 Block.
6
PWM1
0 = I/O pins powered up.
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].
GPIO Block I/O Power Down Control.
Controls the power of the 4 I/O pins in the GPIO Block.
5
GPIO
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
Host Block I/O Power Down Control.
Controls the power of the 27 I/O pins in the Host Block.
4
HOST
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
EMIFA/VPSS Sub-Block 2 I/O Power Down Control.
Controls the power of the 3 I/O pins in the EMIFA/VPSS Sub-Block 2.
3
EMBK2
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
(1)
For more details on I/O pins belonging to each pin mux block, see Section 3.7, Multiplexed Pin Configurations.
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Table 3-2. VDD3P3V_PWDN Register Descriptions (continued)
BIT
NAME
DESCRIPTION
EMIFA/VPSS Sub-Block 1 I/O Power Down Control.
Controls the power of the 29 I/O pins in the EMIFA/VPSS Sub-Block 1.
2
EMBK1
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
EMIFA/VPSS Sub-Block 0 I/O Power Down Control.
Controls the power of the 21 I/O pins in the EMIFA/VPSS Sub-Block 0.
1
EMBK0
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
CLKOUT Block I/O Power Down Control.
Controls the power of the 1 I/O pin in the CLKOUT Block.
0
CLKOUT
0 = I/O pins powered up [default].
1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z).
76
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3.3 Clock Considerations
Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and
the Power and Sleep Controller (PSC). In addition, the System Module VPSS_CLKCTL register configures
the clock source to the Video Processing Subsystem (VPSS).
3.3.1
Clock Configurations after Device Reset
After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and
the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the
desired peripheral clock state (clock gating or not).
For additional power savings, some of the DM6437 peripherals support clock gating within the peripheral
boundary. For more details on clock gating and power saving features supported by a specific peripheral,
see the peripheral-specific reference guides [listed/linked in the TMS320DM643x DMP Peripherals
Overview Reference Guide (literature number SPRU983)].
3.3.1.1 Device Clock Frequency
The DM6437 defaults to PLL bypass mode. To bring the device up to the desired clock frequency, the
user should program PLLC1 and PLLC2 after device reset.
DM6437 supports a FASTBOOT option, where upon exit from device reset the internal bootloader code
automatically programs the PLLC1 into PLL mode with a specific PLL multiplier and divider to speed up
device boot. While the FASTBOOT option is beneficial for faster boot, the PLL multiplier and divider
selected for boot may not be the exact frequency desired for the run-time application. It is the user's
responsibility to reconfigure PLLC1 after fastboot to bring the device into the desired clock frequency.
Section 3.4.1, Boot Modes discusses the different fast boot modes in more detail.
The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2:
• Fixed frequency ratio requirements between CLKDIV1, CLKDIV3, and CLKDIV6 clock domains. For
more details on the frequency ratio requirements, see Section 6.3.4, DM6437 Power and Clock
Domains.
• PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see
Section 6.7.1, PLL1 and PLL2.
3.3.1.2 Module Clock State
The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC).
Table 3-3 shows the default state of each module after a device-level global reset. The DM6437 device
has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on
the definitions of the module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep
Controller (PSC) and the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number
SPRU978).
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Table 3-3. DM6437 Default Module States
LPSC #
DEFAULT MODULE STATE
[PSC Register MDSTATn.STATE]
MODULE NAME
0
VPSS (Master)
SwRstDisable
1
VPSS (Slave)
SwRstDisable
2
EDMACC
SwRstDisable
3
EDMATC0
SwRstDisable
4
EDMATC1
SwRstDisable
5
EDMATC2
SwRstDisable
6
EMAC Memory Controller
SwRstDisable
7
MDIO
SwRstDisable
8
EMAC
SwRstDisable
9
McASP0
SwRstDisable
11
VLYNQ
SwRstDisable
12
HPI
SwRstDisable
13
DDR2 Memory Contoller
SwRstDisable
14
EMIFA
SwRstDisable, if configuration pins AEM[2:0] = 000b
Enable, if configuration pins AEM[2:0] = Others [001b, 011b, 100b, and 101b]
78
15
PCI
SwRstDisable
16
McBSP0
SwRstDisable
17
McBSP1
SwRstDisable
18
I2C
SwRstDisable
19
UART0
SwRstDisable
20
UART1
SwRstDisable
22
HECC
SwRstDisable
23
PWM0
SwRstDisable
24
PWM1
SwRstDisable
25
PWM2
SwRstDisable
26
GPIO
SwRstDisable
27
TIMER0
SwRstDisable
28
TIMER1
SwRstDisable
39
C64x+ CPU
Enable
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3.3.2
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VPSS Clocks
The Video Processing SubSystem (VPSS) clocks are controlled via the VPSS_CLKCTL register. The
VPSS_CLKCTL register format is shown in Figure 3-2 and the bit field descriptions are given in Table 3-4.
31
16
RESERVED
R-0000 0000 0000 0000
15
5
4
3
2
1
0
RESERVED
DAC
CLKEN
VEN
CLKEN
PCLK
INV
MUXSEL
R-0000 0000 000
R/W-0
R/W-0
R/W-0
R/W-00
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-2. VPSS_CLKCTL Register— 0x01C4 0044
Table 3-4. VPSS_CLKCTL Register Description
BIT
NAME
31:5
RESERVED
DESCRIPTION
Reserved. Read-only, writes have no effect.
4
DACCLKEN
Video DAC clock enable.
0 = DAC clock disabled [default].
1 = DAC clock enabled.
3
VENCLKEN
Video Encoder clock enable.
0 = VENC clock disabled [default].
1 = VENC clock enabled.
2
PCLKINV
PCLK polarity
0 = VPSS receives normal PCLK [default].
1 = VPSS receives inverted PCLK.
VPBE (Video Encoder and DAC) clock selection
1:0
MUXSEL (1) (2)
SETTING
VENC CLK
DAC CLK
00 [default]
27 MHz(a)
27 MHz(a)
(b)
54 MHz(b)
01
54 MHz
10
VPBECLK Input
VPBECLK Input
11
PCLK (or Inverted PCLK)
OFF
(a) The 27-MHz clock comes from PLLC1 SYSCLKBP.
(b) The 54-MHz clock comes from PLLC2 PLL2_SYSCLK2.
(1)
(2)
MUXSEL = 00 selects PLLC1 SYSCLKBP as the clock source to the VPBE. The PLLC1 SYSCLKBP is a 27-MHz clock if the following
settings are true:
a. MXI/CLKIN clock source is 27 MHz.
b. PLLC1 Bypass Divider Register (BPDIV) is left at the default setting of divide-by-1.
MUXSEL = 01 selects PLLC2 PLL2_SYSCLK2 as the clock source to the VPBE. The PLLC2 PLL2_SYSCLK2 is a 54-MHz clock if the
following settings are true:
a. MXI/CLKIN clock source is 27 MHz.
b. PLLC2 is in PLL Mode with multiplier x20 to generate a PLL output clock of 27 MHz x 20 = 540 MHz.
c. PLLDIV2.RATIO is left at the default setting of divide-by-10 to generate SYSCLK2 = 54 MHz.
For more details on the different methods and software sequence to clock (gate) the VPBE components,
see the TMS320DM643x DMP Video Processing Back End (VPBE) User’s Guide (literature number
SPRU952).
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3.4 Boot Sequence
The boot sequence is a process by which the device's memory is loaded with program and data sections,
and by which some of the device's internal registers are programmed with predetermined values. The boot
sequence is started automatically after each device-level global reset. For more details on device-level
global resets, see Section 6.5, Reset.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset. For more
information on the bootmode selections, see Section 3.4.1, Boot Modes.
The device is booted through multiple means—primary bootloaders within internal ROM or EMIFA, and
secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and
register configurations required for booting the device, are described in the following subsections.
3.4.1
Boot Modes
The DM6437 boot modes are determined by these device boot and configuration pins. For information on
how these pins are sampled at device reset, see Section 6.5.1.2, Latching Boot and Configuration Pins.
• BOOTMODE[3:0]
• PCIEN
• FASTBOOT
• AEM[2:0]
• PLLMS[2:0]
Note: The PLLMS[2:0] configuration pins are actually multiplexed with the AEAW[2:0] configuration pins.
For more details on the multiplexed AEAW[2:0]/PLLMS[2:0] configuration pins and control, see
Section 3.5.1.2, EMIFA Address Width Selects (AEAW[2:0]) and FASTBOOT PLL Multiplier Selects
(PLLMS[2:0]).
BOOTMODE[3:0] and PCIEN determine the type of boot (e.g., I2C Boot, EMIFA Boot, HPI Boot, or PCI
Boot, etc.). FASTBOOT determines if the PLL is enabled during boot to speed up the boot process.
The combination of AEM[2:0] and PLLMS[2:0] is used by bootloader code to determine the PLL multiplier
used during fastboot modes (FASTBOOT = 1).
The DM6437 boot modes are grouped into three categories—Non-Fastboot Modes, Fixed-Multiplier
Fastboot Modes, and User-Select Multiplier Fastboot Modes.
•
•
•
Non-Fastboot Modes (FASTBOOT = 0): The device operates in default PLL bypass mode during
boot. The Non-Fastboot bootmodes available on the DM6437 are shown in Table 3-5.
Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b): The bootloader code speeds
up the device during boot according to the fixed PLL multipliers. The Fixed-Multiplier Fastboot
bootmodes available on the DM6437 are shown in Table 3-6.
Note: The PLLMS[2:0] configurations have no effect on the Fixed-Multiplier Fastboot Modes, as these
pins function as AEAW[2:0] to select the EMIFA address width when AEM[2:0] = 001b.
User-Select Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 000b,011b,100b,101b): The
bootloader code speeds up the device during boot. The PLL multiplier is selected by the user via the
PLLMS[2:0] pins. The User-Select Multiplier Fastboot bootmodes available on the DM6437 are shown
in Table 3-7.
All other modes not shown in these tables are reserved and invalid settings.
For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching Boot
and Configuration Pins.
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Table 3-5. Non-Fastboot Modes (FASTBOOT = 0)
DEVICE BOOT AND
CONFIGURATION PINS
PLLC1 CLOCK SETTING AT BOOT
BOOT DESCRIPTION (1)
DM6437 DMP
(Master/Slave)
PLL
MODE (2)
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
DEVICE
FREQUENCY
(SYSCLK1)
DSPBOOTADDR
(DEFAULT) (1)
BOOTMODE[3:0]
PCIEN
0000
0 or 1
No Boot (Emulation Boot)
Master
Bypass
/1
CLKIN
0001
0 or 1
Reserved
–
–
–
–
–
0
HPI Boot
Slave
Bypass
/1
CLKIN
0x0010 0000
0010
1
Reserved
–
–
–
–
–
0 or 1
Reserved
–
–
–
–
–
0100
0 or 1
EMIFA ROM Direct Boot
[PLL Bypass Mode]
Master
Bypass
/1
CLKIN
0x4200 000
0101
0 or 1
I2C Boot
[STANDARD MODE] (3)
Master
Bypass
/1
CLKIN
0x0010 0000
0110
0 or 1
16-bit SPI Boot
[McBSP0]
Master
Bypass
/1
CLKIN
0x0010 0000
0111
0 or 1
NAND Flash Boot
Master
Bypass
/1
CLKIN
0x0010 0000
1000
0 or 1
UART Boot without
Hardware Flow Control
[UART0]
Master
Bypass
/1
CLKIN
0x0010 0000
1001
0 or 1
Reserved
1010
0 or 1
VLYNQ Boot
1011
0 or 1
1100
1101
0011
(1)
(2)
(3)
0x0010 0000
–
–
–
–
–
Slave
Bypass
/1
CLKIN
0x0010 0000
Reserved
–
–
–
–
–
0 or 1
Reserved
–
–
–
–
–
0 or 1
Reserved
–
–
–
–
–
1110
0 or 1
UART Boot with
Hardware Flow Control
[UART0]
Master
Bypass
/1
CLKIN
0x0010 0000
1111
0 or 1
24-bit SPI Boot
(McBSP0 + GP[97])
Master
Bypass
/1
CLKIN
0x0010 0000
For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,
BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the
bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application code must explicitly enable the
cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader Application Report (literature number
SPRAAG0).
The PLL MODE for Non-Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no effect on
the PLL MODE.
I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not
available for MXI/CLKIN frequencies less than 21 MHz.
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Table 3-6. Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b)
DEVICE BOOT AND
CONFIGURATION PINS
DM6437 DMP
(Master/Slave)
No Boot (Emulation Boot)
0
HPI Boot with PLL
Multiplier x27 at boot
1
Reserved
0
HPI Boot with PLL
Multiplier x20 at boot
1
Reserved
0
HPI Boot with PLL
Multiplier x15 at boot
1
Reserved
BOOTMODE[3:0]
PCIEN
0000
0 or 1
0001
0010
0011
(1)
(2)
(3)
82
PLLC1 CLOCK SETTING AT BOOT
BOOT DESCRIPTION (1)
DSPBOOTADDR
(DEFAULT) (1)
PLL
MODE (2)
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
DEVICE
FREQUENCY
(SYSCLK1)
Master
Bypass
/1
CLKIN
0x0010 0000
Slave
x27
/2
CLKIN x27 / 2
0x0010 0000
–
–
–
–
–
Slave
x20
/2
CLKIN x20 / 2
0x0010 0000
–
–
–
–
–
Slave
x15
/2
CLKIN x15 / 2
0x0010 0000
–
–
–
–
–
Master
x20
/2
CLKIN x20 / 2
0x0010 000
0100
0 or 1
EMIFA ROM FASTBOOT
with Application Image
Script (AIS)
0101
0 or 1
I2C Boot
[FAST MODE] (3)
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
0110
0 or 1
16-bit SPI Boot
[McBSP0]
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
0111
0 or 1
NAND Flash Boot
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
1000
0 or 1
UART Boot without
Hardware Flow Control
[UART0]
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
1001
0 or 1
EMIFA ROM FASTBOOT
without AIS
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
1010
0 or 1
VLYNQ Boot
Slave
x20
/2
CLKIN x20 / 2
0x0010 0000
1011
0 or 1
Reserved
–
–
–
–
–
1100
0 or 1
Reserved
–
–
–
–
–
1101
0 or 1
Reserved
–
–
–
–
–
1110
0 or 1
UART Boot with
Hardware Flow Control
[UART0]
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
1111
0 or 1
24-bit SPI Boot
(McBSP0 + GP[97])
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)
so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application
code must explicitly enable the cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader
Application Report (literature number SPRAAG0).
The PLL MODE for Fixed-Multiplier Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no
effect on the PLL MODE.
I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not
available for MXI/CLKIN frequencies less than 21 MHz.
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Table 3-7. User-Select Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 000b, 011b, 100b, or 101b)
DEVICE BOOT AND
CONFIGURATION PINS
BOOTMODE[3:0]
PCIEN
0000
0 or 1
0001
0010
0011
(1)
(2)
(3)
PLLC1 CLOCK SETTING AT BOOT
BOOT DESCRIPTION (1)
DM6437 DMP
(Master/Slave)
No Boot (Emulation Boot)
DSPBOOTADDR
(DEFAULT) (1)
PLL
MODE (2)
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
DEVICE
FREQUENCY
(SYSCLK1)
Master
Bypass
/1
CLKIN
0x0010 0000
–
–
–
–
–
0
Reserved
1
PCI Boot without Auto
Initialization
Slave
Table 3-8
/2
Table 3-8
0x0010 0000
0
HPI Boot
Slave
Table 3-8
/2
Table 3-8
0x0010 0000
1
PCI Boot with Auto
Initialization
Slave
Table 3-8
/2
Table 3-8
0x0010 0000
0 or 1
Reserved
–
–
–
–
–
0100
0 or 1
EMIFA ROM FASTBOOT
with AIS
Master
Table 3-8
/2
Table 3-8
0x0010 0000
0101
0 or 1
I2C Boot
[FAST MODE] (3)
Master
Table 3-8
/2
Table 3-8
0x0010 0000
0110
0 or 1
16-bit SPI Boot
[McBSP0]
Master
Table 3-8
/2
Table 3-8
0x0010 0000
0111
0 or 1
NAND Flash Boot
Master
Table 3-8
/2
Table 3-8
0x0010 0000
1000
0 or 1
UART Boot without
Hardware Flow Control
[UART0]
Master
Table 3-8
/2
Table 3-8
0x0010 0000
1001
0 or 1
EMIFA ROM FASTBOOT
without AIS
Master
Table 3-8
/2
Table 3-8
–
1010
0 or 1
VLYNQ Boot
Slave
x20
/2
CLKIN x20 / 2
0x0010 0000
1011
0 or 1
Reserved
–
–
–
–
–
1100
0 or 1
Reserved
–
–
–
–
–
1101
0 or 1
Reserved
–
–
–
–
–
1110
0 or 1
UART Boot with
Hardware Flow Control
[UART0]
Master
Table 3-8
/2
Table 3-8
0x0010 0000
1111
0 or 1
24-bit SPI Boot
(McBSP0 + GP[97])
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)
so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application
code must explicitly enable the cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader
Application Report (literature number SPRAAG0).
Any supported PLL MODE is available. [See Table 3-8 for supported DM6437 PLL MODE options].
I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not
available for MXI/CLKIN frequencies less than 21 MHz.
Table 3-8. PLL Multiplier Selection (PLLMS[2:0]) in User-Select Multiplier Fastboot Modes
(FASTBOOT = 1; AEM[2:0] = 000b, 011b, 100b, or 101b)
DEVICE BOOT AND
CONFIGURATION PINS
PLLC1 CLOCK SETTING AT BOOT
PLLMS[2:0]
PLL MODE
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
DEVICE FREQUENCY (SYSCLK1)
000
x20
/2
CLKIN x20 / 2
001
x15
/2
CLKIN x15 / 2
010
x16
/2
CLKIN x16 / 2
011
x18
/2
CLKIN x18 / 2
100
x22
/2
CLKIN x22 / 2
101
x25
/2
CLKIN x25 / 2
110
x27
/2
CLKIN x27 / 2
111
x30
/2
CLKIN x30 / 2
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As shown in Table 3-5, Table 3-6, and Table 3-7, at device reset the Boot Controller defaults the
DSPBOOTADDR to one of two values based on the boot mode selected. In all boot modes, the C64x+ is
immediately released from reset and begins executing from address location indicated in
DSPBOOTADDR.
• Internal Bootloader ROM (0x0010 0000): For most boot modes, the DSPBOOTADDR defaults to the
internal Bootloader ROM so that the DSP can immediately execute the bootloader code in the internal
ROM. The bootloader code decodes the captured BOOTMODE, FASTBOOT, PCIEN, default AEM
(DAEM), and PLLMS information (in the BOOTCFG register) to determine the proper boot operation.
Note: For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code
disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the bootloader code, all C64x+
memories are configured as all RAM. If cache use is required, the application code must explicitly
enable the cache. For more information on boot modes, see Section 3.4.1, Boot Modes. For more
information on the bootloader, see the Using the TMS320DM643x Bootloader Application Report
(literature number SPRAAG0).
• EMIFA Chip Select Space 2 (0x4200 0000): The EMIFA ROM Direct Boot in PLL Bypass Mode
(BOOTCFG settings BOOTMODE[3:0] = 0100b, FASTBOOT = 0) is the only exception where the
DSPBOOTADDR defaults to the EMIFA Chip Select Space 2. The DSP begins execution directly from
the external ROM at this EMIFA space.
For more information how the bootloader code handles each boot mode, see Using the TMS320DM643x
Bootloader Application Report (literature number SPRAAG0).
3.4.1.1 FASTBOOT
When DM6437 exits pin reset (RESET or POR released), the PLL Controllers (PLLC1 and PLLC2) default
to PLL Bypass Mode. This means the PLLs are disabled, and the MXI/CLKIN clock input is driving the
chip. All the clock domain divider ratios discussed in Section 6.3.4, DM6437 Power and Clock Domains,
still apply. For example, assume an MXI/CLKIN frequency of 27 MHz—meaning the internal clock source
for EMIFA is at CLKDIV3 domain = 27 MHz/3 = 9 MHz, a very slow clock. In addition, the EMIFA registers
are reset to the slowest configuration which translates to very slow peripheral operation/boot.
To optimize boot time, the user should reprogram clock settings via the PLLC as early as possible during
the boot process. The FASTBOOT pin facilitates this operation by allowing the device to boot at a faster
clock rate.
Except for the EMIFA ROM Direct Boot in PLL Bypass Mode (BOOTCFG settings BOOTMODE[3:0] =
0100b, FASTBOOT = 0), all other boot modes default to executing from the Internal Bootloader ROM. The
first action that the bootloader code takes is to decode the boot mode. If the FASTBOOT option is
selected (BOOTCFG.FASTBOOT = 1), the bootloader software begins by programming the PLLC1
(System PLLC) to PLL Mode to give the device a slightly faster operation before fetching code from
external devices. The exact PLL multiplier that the bootloader uses is determined by the AEM[2:0] and
PLLMS[2:0] settings, as shown in Table 3-6 and Table 3-7.
Some boot modes must be accompanied with FASTBOOT = 1 so that the corresponding peripheral can
run at a reasonable rate to communicate to the external device(s). This includes PCI boot.
Note: PLLC2 still stays in PLL Bypass Mode, the bootloader does not reconfigure it.
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3.4.1.2 Selecting FASTBOOT PLL Multiplier
Table 3-6, Table 3-7, and Table 3-8 show the PLL multipliers used by the bootloader code during fastboot
(FASTBOOT = 1) and the resulting device frequency. The user is responsible for selecting the bootmode
with the appropriate PLL multiplier for their MXI/CLKIN clock source so that the device speed and PLL
frequency range requirements are met. For the PLLC1 Clock Frequency Ranges, see Table 6-15, PLLC1
Clock Frequency Ranges in Section 6.7.1, PLL1 and PLL2.
The following are guidelines for PLL output frequency and device speed (frequency):
• PLL Output Frequency: (PLLOUT = CLKIN frequency * boot PLL Multiplier) must stay within the
PLLOUT frequency range in Table 6-15, PLLC1 Clock Frequency Ranges.
• Device Frequency: (SYSCLK1) calculated from Table 3-6 and Table 3-7 must not exceed the
SYSCLK1 maximum frequency in Table 6-15, PLLC1 Clock Frequency Ranges.
For example, for a 600-MHz device with a CLKIN = 27 MHz, in order to stay within the PLLOUT
frequency range and SYSCLK1 maximum frequency from Table 6-15, PLLC1 Clock Frequency
Ranges, the user must select a boot mode with a PLL1 multiplier between x15 and x22.
3.4.1.3 EMIFA Boot Modes
As shown in Table 3-5, Table 3-6, and Table 3-7, there are different types of EMIFA Boot Modes. This
subsection summarizes these types of EMIFA boot modes. For further detailed information, see the Using
the TMS320DM643x Bootloader Application Report (literature number SPRAAG0).
• EMIFA ROM Direct Boot in PLL Bypass Mode (FASTBOOT = 0, BOOTMODE[3:0] = 0100b)
– The C64x+ fetches the code directly from EMIFA Chip Select 2 Space [EM_CS2] (address
0x4200 0000)
– The PLL is in Bypass Mode
– EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable
Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].
AEM[2:0] must be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1] or 011b [8-bit EMIFA
(Async) Pinout Mode 3].
• EMIFA ROM Fastboot with AIS (FASTBOOT = 1, BOOTMODE[3:0] = 0100b)
– The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.
– The bootloader code programs PLLC1 to PLL Mode to speed up the boot process. The PLL
multiplier value is determined by the AEM[2:0] and PLLMS[2:0] configurations as shown in
Table 3-6 and Table 3-7.
– The bootloader code reads code from the EMIFA EM_CS2 space using the application image script
(AIS) format.
– EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable
Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].
AEM[2:0] must be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1] or 011b [8-bit EMIFA
(Async) Pinout Mode 3].
• EMIFA ROM Fastboot without AIS: (FASTBOOT = 1, BOOTMODE[3:0] = 1001b)
– The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.
– The bootloader code programs PLLC1 to PLL Mode to speed up the boot process. The PLL
multiplier value is determined by the AEM[2:0] and PLLMS[2:0] configurations as shown in
Table 3-6 and Table 3-7.
– The bootloader code then jumps to the EMIFA EM_CS2 space, at which point the C64x+ fetches
the code directly from address 0x4200 0000.
– EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable
Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].
AEM[2:0] must be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1] or 011b [8-bit EMIFA
(Async) Pinout Mode 3].
• NAND Flash Boot: (FASTBOOT = 0 or 1, BOOTMODE[3:0] = 0111b)
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– The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.
– Depending on the FASTBOOT, AEM[2:0], and PLLMS[2:0] settings, the bootloader code may
program the PLLC1 to PLL Mode to speed up the boot process. See Table 3-5, Table 3-6, and
Table 3-7.
– The bootloader code reads the code from EMIFA (NAND) EM_CS2 (address 0x4200 0000) using
AIS format.
– EMIFA is configured in NAND mode. The user is responsible for ensuring the desirable
Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].
AEM[2:0] can be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1], 011b [8-bit EMIFA
(Async) Pinout Mode 3], 100b [8-bit EMIFA (NAND) Pinout Mode 4], or 101b [8-bit EMIFA (NAND)
Pinout Mode 5].
3.4.1.4 Serial Boot Modes (I2C, UART[UART0], SPI[McBSP0])
This subsection discusses how the bootloader configures the clock dividers for the serial boot modes—I2C
boot, UART boot, and SPI boot.
3.4.1.4.1 I2C Boot
If FASTBOOT = 0, then I2C Boot (BOOTMODE = 0101) is performed in Standard-Mode (up-to 100 kbps).
If FASTBOOT = 1, then I2C Boot is performed in Fast-Mode (up-to 400 kbps). The actual I2C data
transfer rate is dependent on the MXI/CLKIN frequency.
This is how the bootloader programs the I2C:
• I2C Boot in Fast-Mode (BOOTMODE[3:0] = 0101b, FASTBOOT = 1)
– I2C register settings: ICPSC.IPSC = 210, ICCLKL.ICCL = 810, ICCKH.ICCH = 810
– Resulting in the following I2C prescaled module clock frequency (internal I2C clock):
• (CLKIN frequency in MHz) / 3
– Resulting in the following I2C serial clock (SCL):
• SCL frequency (in kHz) = (CLKIN frequency in MHz) / 78 * 1000
• SCL low pulse duration (in µs) = 39 / (CLKIN frequency in MHz)
• SCL high pulse duration (in µs) = 39 / (CLKIN frequency in MHz)
• I2C Boot in Standard-Mode (BOOTMODE[3:0] = 0101b, FASTBOOT = 0)
– I2C register settings: ICPSC.IPSC = 210, ICCLKL.ICCL = 4510, ICCKH.ICCH = 4510
– Resulting in the following I2C prescaled module clock frequency (internal I2C clock):
• (CLKIN frequency in MHz) / 3
– Resulting in the following I2C serial clock (SCL):
• SCL frequency (in kHz) = (CLKIN frequency in MHz) / 300 * 1000
• SCL low pulse duration (in µs) = 150 / (CLKIN frequency in MHz)
• SCL high pulse duration (in µs) = 150 / (CLKIN frequency in MHz)
Note: The I2C peripheral requires that the prescaled module clock frequency must be between 7 MHz
and 12 MHz. Therefore, the I2C boot is only available for MXI/CLKIN frequency between 21 MHz and
30 MHz.
For more details on the I2C periperhal configurations and clock requirements, see the TMS320DM643x
DMP Inter-Integrated Circuit (I2C) Peripheral User’s Guide (literature number SPRU991).
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3.4.1.4.2 UART Boot
For UART Boot (BOOTMODE[3:0] = 1000b or 1110b), the bootloader programs the UART0 peripheral as
follows:
• UART0 divisor is set to 1510
• Resulting in this UART0 baud rate in kilobit per second (kbps):
– (CLKIN frequency in MHz) * 1000 / (15 * 16)
The user is responsible for ensuring the resulting baud rate is appropriate for the system. The UART0
divisor (/15) is optimized for CLKIN frequency between 27 to 29 MHz to stay within 5% of the 115200-bps
baud rate.
For more details on the UART peripheral configurations and clock generation, see the TMS320DM643x
DMP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (literature number SPRU997).
3.4.1.4.3 SPI Boot
Both 16-bit address SPI Boot (BOOTMODE = 0110) and 24-bit address SPI boot are performed through
the McBSP0 peripheral. The bootloader programs the McBSP0 peripheral as follows:
• McBSP0 register settings: SRGR.CLKGDV = 210
• Resulting in this SPI serial clock frequency:
– (SYSCLK3 frequency in MHz) / 3
SYSCLK3 frequency = SYSCLK1 frequency / 6. SYSCLK1 frequency during boot can be found in
Table 3-5, Table 3-6, Table 3-7, and/or Table 3-8 based on the boot mode selection.
For example, if BOOTMODE[3:0] = 0110b, FASTBOOT = 1, the MXI/CLKIN frequency = 27 MHz,
AEM[2:0] = 000b, PLLMS[2:0] = 100b, the combination of Table 3-7 and Table 3-8 indicates that the
device frequency (SYSCLK1) is CLKIN x 22 / 2 = 297 MHz. This means SYSCLK3 frequency is
297 / 6 = 49.5 MHz, resulting in SPI serial clock frequency of 49.5 / 3 = 16.5 MHz.
3.4.1.5 Host Boot Modes
The DM6437 supports two types of host boots—PCI Boot or HPI Boot.
The PCI Boot (BOOTMODE[3:0] = 0001b or 0010b, PCIEN = 1) is only available in fastboot
(FASTBOOT = 1), as shown in Table 3-6 and Table 3-7.
The HPI Boot is available in fastboot and non-fastboot, as shown in Table 3-5, Table 3-6, and Table 3-7.
Note: The HPI HSTROBE inactive pulse duration timing requirement [tw(HSTBH)] is dependent on the HPI
internal clock source (SYSCLK3) frequency (see Section 6.13.3, HPI Electrical Data/Timing). The external
host must be aware of the SYSCLK3 frequency during boot to ensure the HSTROBE pulse duration
timing requirement is met.
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Bootmode Registers
3.4.2.1 BOOTCFG Register
The Device Bootmode (see Section 3.4.1, Boot Modes) and Configuration pins (see Section 3.5.1, Device
and Peripheral Configurations at Device Reset) latched at reset are captured in the Device Boot
Configuration (BOOTCFG) register which is accessible through the System Module. This is a read-only
register. The bits show the values latched from the corresponding configuration pins sampled at device
reset. For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching
Boot and Configuration Pins. For the corresponding device boot and configuration pins, see Table 2-5,
BOOT Terminal Functions.
31
15
20
14
13
12
11
19
18
17
16
RESERVED
FASTBOOT
RSV
DPCIEN
RSV
R-0000 0000 0001
R-L
R-0
R-L
R-0
3
2
1
0
10
9
8
7
6
5
4
RSV
PLLMS
RSV
DAEM
RESERVED
BOOTMODE
R-0
R-LLL
R-0
R-LLL
R-0000
R-LLLL
LEGEND: R = Read only; L = pin state latched at reset rising edge; -n = value after reset
Figure 3-3. BOOTCFG Register—0x01C4 0014
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Table 3-9. BOOTCFG Register Description
Bit
Field Name
Description
31:20
RESERVED
Reserved. Writes have no effect.
Fastboot (see Section 3.4.1.1, FASTBOOT)
This field is used by the device bootloader code to determine if it needs to speed up the device to PLL mode
before booting.
19
FASTBOOT
0 = No Fastboot
1 = Fastboot
The default value is latched from FASTBOOT configuration pin.
18
RSV
Reserved. Writes have no effect.
PINMUX1.PCIEN Default (see Section 3.5.1.3, PCI Enable)
For more details on the PCIEN settings, see Section 3.7.2.2, PINMUX1 Register Description.
17
DPCIEN
This field affects the pin mux control by setting the default of PINMUX1.PCIEN. This field determines if the
internal pullup/pulldown resistors on the PCI capable pins are enabled/disabled. This field does not affect PCI
register setting.
The user must keep the value on the PCIEN pin constant throughout the operation.
The default value is from the PCIEN configuration pin.
16:15
RSV
Reserved. Writes have no effect.
PINMUX0.AEAW default [AEAW] and Fastboot PLL Multiplier Select [PLLMS] (see Section 3.5.1.2, EMIFA
Address Width Select [AEAW] and Fast Boot PLL Multiplier Select [PLLMS])
14:12
PLLMS
The AEAW[2:0]/PLLMS configuration pins serve two purposes:
AEAW[2:0]: 8-bit EMIFA (Async) Pinout Mode 1 Address Width
If AEM = 001, this field serves as AEAW and it indicates the 8-bit EMIFA (Async) Pinout Mode 1 Address
Width. In this case, this field affects pin mux control only by setting the default of Pin Mux Control Register
PINMUX0.AEAW[2:0]. This field does not affect EMIFA register settings.
For more details on the AEAW settings, see Section 3.7.2.1, PINMUX0 Register Description.
PLLMS: Fastboot PLL Multiplier Select
If FASTBOOT = 1 and AEM[2:0] = 000b, 011b, 100b, or 101b, this field selects the FASTBOOT PLL Multiplier.
In this case, this field does not affect the pin mux control or the EMIFA register settings. The bootloader code
uses this field to determine the PLL multiplier used for Fastboot.
11
RSV
Reserved. Writes have no effect.
PINMUX0.AEM default [DAEM] (see Section 3.5.1.1, EMIFA Pinout Mode (AEM[2:0]))
For more details on the AEM settings, see Section 3.7.2.1, PINMUX0 Register Description.
10:8
DAEM
This field affects pin mux control by setting the default of PINMUX0.AEM. This field does not affect EMIFA
Register settings.
The default value is latched from the AEM[2:0] configuration pins.
7:4
RESERVED
Reserved. Writes have no effect.
Boot Mode (see Section 3.4.1, Boot Modes)
3:0
BOOTMODE
This field is used in conjunction with FASTBOOT, PCIEN, AEM, and PLLMS to determine the device boot
mode.
The default value is latched from the BOOTMODE[3:0] configuration pins.
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3.4.2.2 BOOTCMPLT Register
If the bootloader code detects an error during boot, it records the error status in the Boot Complete
(BOOTCMPLT) register.
In addition, the BOOTCMPLT register is used for communication between the external host and the
bootloader code during a Host Boot (PCI Boot or HPI boot). Once the external host has completed boot, it
must perform the following communication with the bootloader code:
• Write the desired 32-bit CPU starting address in the DSPBOOTADDR register (see Section 3.4.2.3,
DSPBOOTADDR Register).
• Write a ‘1’ to the Boot Complete (BC) bit field in the BOOTCMPLT register to indicate that the host has
completed booting this device.
Once the bootloader code detects BC = 1, it directs the CPU to begin executing from the
DSPBOOTADDR register.
The BOOTCMPLT register is reset by any device-level global reset. For the list of device-level global
resets, see Section 6.5, Reset.
31
20
19
16
RESERVED
ERR
R/W-0000 0000 0000
R/W-0000
15
1
0
RESERVED
BC
R/W- 0000 0000 0000 000
R/W-0
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-4. BOOTCMPLT Register— 0x01C4 000C
Table 3-10. BOOTCMPLT Register Description
Bit
Field Name Description
31:20
RESERVED Reserved. For proper device operation, the user should only write "0" to these bits.
Boot Error
0000 = No Error (default).
0001 - 1111 = bootloader software detected a boot error and aborted the boot. For the error codes, see the
Using the TMS320DM643x DMP Bootloader Application Report (literature number SPRAAG0).
19:16
ERR
15:1
RESERVED Reserved. For proper device operation, the user should only write "0" to these bits.
0
90
BC
Boot Complete Flag from Host
This field is only applicable to Host Boots.
0 = Host has not completed booting this device (default).
1 = Host has completed booting this device. DSP can begin executing from the DSPBOOTADDR register
value.
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3.4.2.3 DSPBOOTADDR Register
The DSP Boot Address (DSPBOOTADDR) register contains the starting address for the C64x+ CPU.
Whenever the C64x+ is released from reset, it begins executing from the location pointed to by
DSPBOOTADDR register. For Host boots (PCI Boot or HPI boot), the DSPBOOTADDR register is also
used for communication between the Host and the bootloader code during boot.
The DSPBOOTADDR register is reset by any device-level global reset. For the list of device-level global
resets, see Section 6.5, Reset.
31
0
DSPBOOTADDR
R/W-0x0010 0000 or 0x4200 00000
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-5. DSPBOOTADDR Register— 0x01C4 0008
Table 3-11. DSPBOOTADDR Register Description
Bit
Field Name
Description
DSP Boot Address
After boot, the C64x+ CPU begins execution from this 32-bit address location. The lower 10 bits
(bits 9:0) should always be programmed to "0" as they are ignored by the C64x+. The default
value of the DSPBOOTADDR depends on the boot mode selected.
31:0
DSPBOOTADDR
The DSPBOOTADDR defaults to 0x0010 0000 when the Internal Bootloader ROM is used.
or
The DSPBOOTADDR defaults to 0x4200 0000 when EMIFA CS2 Space is used.
For the boot mode selections, see Table 3-5, Non-Fastboot Modes; Table 3-6, Fixed-Multiplier
Fastboot Modes; and Table 3-7, User-Select Multiplier Fastboot Modes.
For Non-Host Boot Modes, software can leave the DSPBOOTADDR register at default.
For Host Boots (PCI Boot or HPI boot), the DSPBOOTADDR register is also used for communication
between the Host and the bootloader code during boot. For Host Boots, the DSPBOOTADDR register
defaults to Internal Bootloader ROM, and the C64x+ CPU is immediately released from reset so that it can
begin executing the bootloader code in this internal ROM. The bootloader code waits for the Host to boot
the device. Once the Host is done booting the device, it must write a new starting address into the
DSPBOOTADDR register, and follow with writing BOOTCMPLT.BC = 1 to indicate the boot is complete.
As soon as the bootloader code detects BOOTCMPLT.BC = 1, it instructs the CPU to jump to this new
DSPBOOTADDR address. At this point, the CPU continues the rest of the code execution starting from
the new DSPBOOTADDR location and the boot is completed.
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3.5 Configurations At Reset
Some device configurations are determined at reset. The following subsections give more details.
3.5.1
Device and Peripheral Configurations at Device Reset
Table 2-5, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device
reset for configuring basic device settings for proper device operation. Table 3-12, summarizes the device
boot and configuration pins, and the device functions that they affect.
Table 3-12. Default Functions Affected by Device Boot and Configuration Pins
DEVICE BOOT AND
CONFIGURATION PINS
BOOT SELECTED
PIN MUX CONTROL
GLOBAL SETTING
PERIPHERAL SETTING
BOOTMODE[3:0]
Boot Mode
PINMUX0/PINMUX1
Registers:
Based on
BOOTMODE[3:0], the
bootloader code programs
PINMUX0 and PINMUX1
registers to select the
appropriate pin functions
required for boot.
I/O Pin Power:
Based on
BOOTMODE[3:0], the
bootloader code programs
VDD3P3V_PWDN register
to power up the I/O pins
required for boot.
PSC/Peripherals:
Based on
BOOTMODE[3:0], the
bootloader code programs
the PSC to put
boot-related peripheral(s)
in the Enable State, and
programs the peripheral(s)
for boot operation.
FASTBOOT
Fastboot
–
Sets Device Frequency:
Based on BOOTMODE,
FASTBOOT, PLLMS, and
AEM the bootloader code
programs PLLC1.
–
AEAW[2:0]/PLLMS[2:0]
If FASTBOOT = 1 and
AEM = 000b, 011b, 100b
or 101b the PLLMS[2:0]
selects the FASTBOOT
PLL Multiplier.
PINMUX0.AEAW:
AEAW[2:0] sets the
default of this field to
control the EMIFA
address bus width (only
applicable if
PINMUX0.AEM = 001b).
Sets Device Frequency:
Based on BOOTMODE,
FASTBOOT, PLLMS, and
AEM the bootloader code
programs PLLC1.
–
Sets Device Frequency:
Based on BOOTMODE,
FASTBOOT, PLLMS, and
AEM the bootloader code
programs PLLC1.
PSC/EMIFA:
The EMIFA module state
defaults to SwRstDisable
if AEM = 0; otherwise, the
EMIFA module state
defaults to Enable.
Affects the pin muxing in
EMIFA/VPSS Sub-Block
0.
AEM[2:0]
PCIEN (1)
Together with FASTBOOT
and PLLMS[2:0] ,
determines the
FASTBOOT PLL
Multiplier.
PINMUX0.AEM:
Sets the default of this
field to control the EMIFA
Pinout Mode.
Host Boot:
PCIEN selects the type of
Host Boot
(HPI Boot or PCI Boot)
PINMUX1.PCIEN:
–
sets this field to control
the PCI pin muxing in
Host Block, PCI Data
Block, GPIO Block,
EMIFA/VPSS Sub-Block 0
and Sub-Block 3.
Affects the pin muxing in
EMIFA/VPSS Sub-Block
0, 1, and 3.
(1) (2)
(1)
(2)
92
PSC/Peripheral
(Applicable to Host Boot
only):
Based on the Host Boot
type (PCI or HPI), the
bootloader code programs
the PSC to put the
corresponding peripheral
in the Enable State, and
programs the peripheral
for boot operation.
Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults, except for PINMUX1.PCIEN.
In addition to pin mux control, PCIEN also affects the internal pullup/down resistors of the PCI capable pins. When PCIEN = 0, internal
pullup/down resistors on the PCI capable pins are enabled. When PCIEN = 1, internal pullup/down resistors on the PCI capable pins are
disabled to be compliant to the PCI Local Bus Specification Revision 2.3.
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For proper device operation, external pullup/pulldown resistors may be required on these device boot and
configuration pins. For discussion situations where external pullup/pulldown resistors are required, see
Section 3.9.1, Pullup/Pulldown Resistors.
Note: Except for PCIEN, all other DM6437 configuration inputs (BOOTMODE[3:0], FASTBOOT,
AEAW[2:0]/PLLMS[2:0] and AEM[2:0]) are multiplexed with other functional pins. These pins function as
device boot and configuration pins only during device reset. The user must take care of any potential data
contention in the system. To help avoid system data contention, the DM6437 puts these configuration pins
into a high-impedance state (Hi-Z) when device reset (RESET or POR) is asserted, and continues to hold
them in a high-impedance state until the internal global reset is removed; at which point, the default
peripheral (either GPIO or EMIFA based on default of AEM[2:0]) will now control these pins.
All of the device boot and configuration pin settings are captured in the corresponding bit fields in the
BOOTCFG register (see Section 3.4.2.1).
The following subsections provide more details on the device configurations determined at device reset:
AEM, AEAW/PLLMS, and PCIEN.
3.5.1.1 EMIFA Pinout Mode (AEM[2:0])
To support different usage scenarios, the DM6437 provides intricate pin multiplexing between the EMIFA
and other peripherals. The PINMUX0.AEM register bit field in the System Module determines the EMIFA
Pinout Mode. The AEM[2:0] pins only select the default EMIFA Pinout Mode. It is latched at device reset
de-assertion (high) into the BOOTCFG.DAEM bit field. The AEM[2:0] value also sets the default of the
PINMUX0.AEM bit field. While the BOOTCFG.DAEM bit field shows the actual latched value and cannot
be modified, the PINMUX0.AEM value can be changed by software to modify the EMIFA Pinout Mode.
Note: The AEM[2:0] value does not affect the operation of the EMIFA module itself. It only affects which
EMIFA pins are brought out to the device pins. For more details on the AEM settings, see Section 3.7,
Multiplexed Pin Configurations.
In addition, for Fastboot modes (FASTBOOT = 1), the bootloader code determines the PLL1 multiplier
based on the default settings of AEM[2:0] and PLLMS[2:0]. For more details, see Section 3.4.1.1,
Fastboot, and Section 3.5.1.2, EMIFA Address Width Select (AEAW) and FASTBOOT PLL Multiplier
Select (PLLMS).
3.5.1.2 EMIFA Address Width Select (AEAW) and FASTBOOT PLL Multiplier Select (PLLMS)
The AEAW[2:0]/PLLMS[2:0] pins serve two functional purposes (AEAW or PLLMS), depending on the
FASTBOOT and AEM settings. The AEAW[2:0]/PLLMS[2:0] pins are latched at device reset de-assertion
(high) and captured in the BOOTCFG.PLLMS bit field. This value also sets the default of the
PINMUX0.AEAW field.
While the BOOTCFG.PLLMS field shows the actual latched value and cannot be modified, the
PINMUX0.AEAW value can be changed by software to modify the EMIFA pinout.
AEAW as EMIFA Address Width Select (AEAW)
If AEM[2:0] = 001b [8-bit EMIFA (Async) Pinout Mode 1], the AEAW[2:0]/PLLMS[2:0] pins serve as AEAW
to set the default of the EMIFA Address Width Selection.
When EMIFA is used in the 8-bit EMIFA (Async) Pinout Mode 1 (PINMUX0.AEM = 001b), the user has the
option to determine how many address pins are needed. The unused address pins can be used as
general-purpose input/output (GPIO) pins or extra data pins for VPFE. For more details on how the AEAW
settings control the exact pin out when AEM = 001b, see Section 3.7.3.13, EMIFA/VPSS Block Muxing.
For other EMIFA Pinout Modes (AEM not 001b), AEAW is not applicable in determining the EMIFA
address width.
Note: AEAW[2:0] value does not affect the operation of the EMIFA module itself. It only affects which of
the EMIFA address bits are brought out to the device pins.
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AEAW as Fast Boot PLL Multiplier Select (PLLMS)
If FASTBOOT = 1 and AEM[2:0] = 000b [No EMIFA], 011b [8-bit EMIFA (Async) Pinout Mode 3], 100b
[8-bit EMIFA (NAND) Pinout Mode 4], or 101b [8-bit EMIFA (NAND) Pinout Mode 5], the
AEAW[2:0]/PLLMS[2:0] pins serve as PLLMS to select PLL multiplier for Fastboot modes.
For more information on boot modes and the FASTBOOT PLL multiplier selection, see Section 3.4.1, Boot
Modes.
3.5.1.3 PCI Enable (PCIEN)
The PCIEN configuration pin determines if the PCI peripheral is used on this device. If PCIEN = 1
indicating the PCI is used, then the PCI multiplexed pins default to PCI functions, and the pins’
corresponding internal pullup/pulldown resistors are disabled. If PCIEN = 0 indicating the PCI is not used,
then the PCI muxed pins default to non-PCI functions, and the pins’ corresponding internal
pullup/pulldown resistors are enabled.
The PCIEN setting is captured and stored in the BOOTCFG.DPCIEN bit field, and also in the
PINMUX1.PCIEN bit field. These values cannot be changed by software. Furthermore, for proper device
operation, the user must hold the desired setting at the PCIEN pin throughout device operation.
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3.6 Configurations After Reset
The following sections provide details on configuring the device after reset.
Multiplexed pins are configured both at and after reset. Section 3.5.1, Device and Peripheral
Configurations at Device Reset, discusses multiplexed pin control at reset. For more details on multiplexed
pins control after reset, see Section 3.7 , Multiplexed Pin Configurations.
3.6.1
Switch Central Resource (SCR) Bus Priorities
Prioritization within the Switched Central Resource (SCR) is programmable for each master. The register
bit fields and default priority levels for DM6437 bus masters are shown in Table 3-13, DM6437 Default Bus
Master Priorities. The priority levels should be tuned to obtain the best system performance for a particular
application. Lower values indicate higher priority. For most masters, their priority values are programmed
at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1
registers are shown in Figure 3-6 and Figure 3-7. The C64x+, VPSS, and EDMA masters contain registers
that control their own priority values.
Table 3-13. DM6437 Default Bus Master Priorities
Priority Bit Field
Bus Master
Default Priority Level
VPSSP
VPSS
0 (VPSS PCR Register)
EDMATC0P
EDMATC0
0 (EDMACC QUEPRI Register)
EDMATC1P
EDMATC1
0 (EDMACC QUEPRI Register)
EDMATC2P
EDMATC2
0 (EDMACC QUEPRI Register)
C64X+_DMAP
C64X+ (DMA)
7 (C64x + MDMAARBE.PRI field)
C64X+_CFGP
C64X+ (CFG)
1 (MSTPRI0 Register)
EMACP
EMAC
4 (MSTPRI1 Register)
VLYNQP
VLYNQ
4 (MSTPRI1 Register)
HPIP
HPI
4 (MSTPRI1 Register)
PCIP
PCI
4 (MSTPRI1 Register)
31
16
RESERVED
R-0000 0000 0000 0000
15
11
10
8
7
0
RESERVED
C64X+_CFGP
RESERVED
R-0000 0
R/W-001
R-0000 0000
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-6. MSTPRI0 Register— 0x01C4 003C
Table 3-14. MSTPRI0 Register Description
Bit
Field Name
Description
31:11
RESERVED
Reserved. Read-only, writes have no effect.
C64X+_CFG master port priority in System Infrastructure.
10:8
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000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
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Table 3-14. MSTPRI0 Register Description (continued)
Bit
Field Name
Description
7:0
RESERVED
Reserved. Read-only, writes have no effect.
31
27
26
25
24
23
22
21
20
19
18
17
RESERVED
PCIP
RSV
HPIP
RSV
VLYNQP
R-0000 0
R/W-100
R-0
R/W-100
R-0
R/W-100
15
3
2
1
RESERVED
EMACP
R- 0000 0000 0000 0
R/W-100
16
0
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-7. MSTPRI1 Register— 0x01C4 0040
Table 3-15. MSTPRI1 Register Description
Bit
Field Name
Description
31:27
RESERVED
Reserved. Read-only, writes have no effect.
PCI master port priority in System Infrastructure.
26:24
23
PCIP
RSV
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Reserved. Read-only, writes have no effect.
HPI master port priority in System Infrastructure.
22:20
19
HPIP
RSV
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Reserved. Read-only, writes have no effect.
VLYNQ master port priority in System Infrastructure.
18:16
15:3
VLYNQP
RESERVED
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Reserved. Read-only, writes have no effect.
EMAC master port priority in System Infrastructure.
2:0
3.6.2
EMACP
000 = Priority 0 (Highest)
100 = Priority 4
001 = Priority 1
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
Peripheral Selection After Device Reset
After device reset, most peripheral configurations are done within the peripheral’s registers. This section
discusses some additional peripheral controls in the System Module. For information on multiplexed pin
controls that determine what peripheral pins are brought out to the pins, see Section 3.7, Multiplexed Pin
Configurations.
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3.6.2.1 HPI Control Register (HPICTL)
The HPI Control (HPICTL) register determines the Host Burst Write Time-Out value. The user should
only modify this register once during device initialization. When modifying this register, the user
must ensure the HPI FIFOs are empty and there are no on-going HPI transactions.
31
16
RESERVED
R-0000 0000 0000 0000
15
10
9
8
7
0
RESERVED
RESERVED
TIMOUT
R- 0000 00
R/W-00
R/W-1000 0000
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-8. HPICTL Register— 0x01C4 0030
Table 3-16. HPICTL Register Description
Bit
Field Name Description
31:10
RESERVED Reserved. Read-only, writes have no effect.
9:8
RESERVED Reserved. For proper device operation, the user should only write "0" to these bits (default).
7:0
TIMOUT
Host Burst Write Timeout Value
When the HPI time-out counter reaches the value programmed here, the HPI write FIFO content is flushed. For
more details on the time-out counter and its use in write bursting, see the TMS320DM643x DMP Host Port
Interface (HPI) User's Guide (literature number SPRU998).
3.6.2.2 Timer Control Register (TIMERCTL)
The Timer Control Register (TIMERCTL) provides additional control for Timer0 and Timer2. The user
should only modify this register once during device initialization, when the corresponding Timer is
not in use.
• Timer 2 Control: The TIMERCTL.WDRST bit determines if the WatchDog timer event (Timer 2) can
cause a device max reset. For more details on the description of a maximum reset, see Section 6.5.3,
Maximum Reset.
• Timer 0 Control: The TINP0SEL bit selects the clock source connected to Timer0's TIN0 input.
31
16
RESERVED
R-0000 0000 0000 0000
15
2
1
0
RESERVED
TINP0
SEL
WD
RST
R- 0000 0000 0000 00
R/W-0
R/W-1
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-9. TIMERCTL Register— 0x01C4 0084
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Table 3-17. TIMERCTL Register Description
Bit
Field Name Description
31:2
RESERVED Reserved. Read-Only, writes have no effect.
1
TINP0SEL
Timer0 External Input (TIN0) Select
0 = Timer0 external input comes directly from the TINP0L pin (default).
1 = Timer0 external input is TINP0L pin divided by 6. For example, if TINP0L = 27MHz, Timer0 input TIN0 is
27MHz / 6 = 4.5 MHz.
0
WDRST
WatchDog Reset Enable
0 = WatchDog Timer Event (WDINT from Timer2) does not cause device reset.
1 = WatchDog Timer Event (WDINT from Timer2) causes a device max reset (default).
3.6.2.3 EDMA TC Configuration Register (EDMATCCFG)
The EDMA Transfer Controller Configuration (EDMATCCFG) register configures the default burst size
(DBS) for EDMA TC0, EDMA TC1, and EDMA TC2. For more information on the correct usage of DBS,
see the TMS320DM643x DMP Enhanced Direct Memory Access (EDMA) Controller User's Guide
(literature number SPRU987). The user should only modify this register once during device
initialization and when the corresponding EDMA TC is not in use.
31
16
RESERVED
R-0000 0000 0000 0000
15
6
5
4
3
2
1
0
RESERVED
TC2DBS
TC1DBS
TC0DBS
R-0000 0000 00
R/W-10
R/W-01
R/W-00
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-10. EDMATCCFG Register— 0x01C4 0088
Table 3-18. EDMATCCFG Register Description
Bit
Field
31:6
RESERVED Reserved. Read-Only, writes have no effect.
5:4
TC2DBS
Description
EDMA TC2 Default Burst Size
00 = 16 byte
01 = 32 byte
10 = 64 byte (default)
11= reserved
EDMA TC2 is intended for PCI or miscellaneous transfers.
TC2 FIFO size is 128 bytes, regardless of Default Burst Size setting.
3:2
TC1DBS
EDMA TC1 Default Burst Size
00 = 16 byte
01 = 32 byte (default)
10 = 64 byte
11 = reserved
EDMA TC1 is intended for high throughput bulk transfers.
TC1 FIFO size is 256 bytes, regardless of Default Burst Size setting.
1:0
TC0DBS
EDMA TC0 Default Burst Size
00 = 16 byte (default)
01 = 32 byte
10 = 64 byte
11 = reserved
EDMA TC0 is intended for short burst transfers with stringent deadlines (e.g., McBSP, McASP).
TC0 FIFO size is 128 bytes, regardless of Default Burst Size setting.
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3.7 Multiplexed Pin Configurations
DM6437 makes extensive use of pin multiplexing to accommodate a large number of peripheral functions
in the smallest possible package, providing ultimate flexibility for end applications.
The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsible for controlling
all pin multiplexing functions on the DM6437. The default setting of some of the PINMUX0 and PINMUX1
bit fields are configured by configuration pins latched at reset (see Section 3.5.1, Device and Peripheral
Configurations at Device Reset). After reset, software may program the PINMUX0 and PINMUX1 registers
to switch pin functionalities.
The following peripherals have multiplexed pins: VPSS (VPFE/VPBE), EMIFA, PCI, HPI, VLYNQ, EMAC,
McASP0, McBSP0, McBSP1, PWM0, PWM1, PWM2, Timer0, Timer1, UART0, UART1, HECC, and GPIO.
The device is divided into the following Pin Multiplexed Blocks (Pin Mux Blocks):
• EMIFA/VPSS Block: VPSS (VPFE/VPBE), EMIFA, part of PCI, GPIO. This block is further subdivided
into these sub-blocks:
– Sub-Block 0: VPFE (CCDC), part of EMIFA (data, address, control), part of PCI, and GPIO
– Sub-Block 1: VPBE (VENC), part of EMIFA (data, address, control), and GPIO
– Sub-Block 2: part of EMIFA (control signals EM_WAIT/(RDY/BSY), EM_OE, and EM_WE)
– Sub-Block 3: part of EMIFA (address EM_A[12:5]), part of PCI, and GPIO
• Host Block: HPI, VLYNQ, EMAC, part of PCI, and GPIO
• PCI Data Block: part of PCI
• GPIO Block: part of PCI and GPIO
• Serial Port Block: McBSP0, McBSP1, McASP0, and GPIO. This block is further sub-divided into
sub-blocks.
– Serial Port Sub-Block 0: McBSP0, part of McASP0, and GPIO
– Serial Port Sub-Block 1: McBSP1, part of McASP0, and GPIO
• UART0 Flow Control Block: UART0 flow control, PWM0, and GPIO
• UART0 Data Block: UART0 data and GPIO
• Timer0 Block: Timer0 and McBSP's CLKS pins
• Timer1 Block: Timer1 and HECC, UART1 data
• PWM1 Block: PWM1 and GPIO
• CLKOUT Block: CLKOUT0, PWM2, and GPIO
As shown in the list above, the PCI, McBSP0, McBSP1, and UART0 peripherals span multiple Pin Mux
Blocks. To use these peripherals, they must be selected in all relevant Pin Mux Blocks. For more details,
see Section 3.7.3, Pin Multiplexing Details, and Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux
Blocks.
Note: There is no actual pin multiplexing in EMIFA/VPSS Sub-Block 2 and the PCI Data Block. However
these are still considered "pin mux blocks" because they contain part of the pins necessary for EMIFA and
PCI, respectively.
A high level view of the Pin Mux Blocks is shown in Figure 3-11. In each Pin Mux Block, the
PINMUX0/PINMUX1 default settings are underlined.
Note: Some default pin functions are determined by configuration pins (PCIEN, AEAW[2:0], AEM[2:0]);
therefore, more than one configuration setting can serve as default based on the configuration pin settings
latched at device reset.
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(A)(C)
(C)
Host Block (27 pins)
PCI (27)
PCI Data Block (3 pins)
GPIO (27)
HPI (26)
GPIO (1)
PCIEN=1
HOSTBK=000
PCIEN=0
HOSTBK=001
PCIEN=0
HOSTBK=000
VLYNQ
(10)
GPIO (17)
PCIEN=0
HOSTBK=010
(C)
PCIEN=1
PCIEN=0
HOSTBK=011
PCIEN=0
HOSTBK=100
PWM1BK=0
UR0DBK=0
UR0DBK=1
PCI (3)
Not muxed
CLKOUT Block (1 pin)
PWM1
(1)
GPIO
(1)
PWM1BK=1
CKOBK=00
CLKOUT
(1)
CKOBK=01
PWM2
(1)
CKOBK=10
UART0 Flow Control Block (2 pins)
GPIO (2)
UR0FCBK=00
UART1
Data (2)
Timer1
(2)
TIM1BK=10
TIM1BK=01
HECC
(2)
TIM1BK=11
(D)
UR0FCBK=01
(D)(E)
Timer0
(2)
TIM0BK=01
McBSP0
CLKS0 (1)
McBSP0
CLKS0 (1)
McBSP1
CLKS1 (1)
Timer0
TINPOL (1)
TIM0BK=10
TIM0BK=11
Serial Port Sub-Block 1 (6 pins)
McASP0 Receive
and 3 Serializers (6)
SPBK0=01
TIM0BK=00
UR0FCBK=10
(E)
Serial Port Sub-Block 0 (6 pins)
McBSP0
(6)
GPIO (2)
PWM0 (1)
GPIO (1)
UART0
FlowCtrl (2)
Timer0 Block (2 pins)
Timer1 Block (2 pins)
SPBK0=00
GPIO (10)
PCIEN=0
GPIO (2)
GPIO (6)
MDIO
(2)
GPIO
(1)
UART
Data (2)
TIM1BK=00
EMAC (15)
MDIO
(2)
GPIO
(4)
UART0 Data Block (2 pins)
GPIO (2)
EMAC (15)
PWM 1 Block (1 pin)
GPIO Block (4 pins)
PCI
(4)
VLYNQ
(10)
SPBK0=10
GPIO (6)
SPBK1=00
McBSP1
(6)
SPBK1=01
McASP0
Transmit and
1 Serializer (6)
SPBK1=10
McBSP1
Transmit (3)
McASP0
SPDIF (3)
SPBK1=11
(A)(B)(C)
EMIFA/VPSS Block (61 pins)
8b EMIFA
(NAND)
Pinout
Mode 5
8b EMIFA
(Async)
Pinout
Mode 1
32KB-16MB
per CE
8b EMIFA
(Async)
Pinout
Mode 3
32KB per
CE
8b EMIFA
(NAND)
Pinout
Mode 4
8b EMIFA
(NAND)
Pinout
Mode 5
PCI
PCI
8-16b
VPFE
8-16b
VPFE
8b
VPFE
8b
VPFE
8-16b
VPFE
8b
VPFE
8b
VPFE
8-24b
VPBE
8b
VPBE
8-16b
VPBE
8-16b
VPBE
8b
VPBE
8-24b
VPBE
8b
VPBE
GPIO
GPIO
Major Config
Option A
Major Config
Option B
AEM=000,
PCIEN=0
AEM=001,
PCIEN=0
GPIO
Major Config
Option C
AEM=011,
PCIEN=0
GPIO
GPIO
GPIO
GPIO
Major Config
Option D
Major Config
Option E
Major Config
Option F
Major Config
Option G
AEM=100,
PCIEN=0
AEM=101,
PCIEN=0
AEM=000,
PCIEN=1
AEM=101,
PCIEN=1
A.
Default settings for PINMUX0 and PINMUX1 registers are underlined.
B.
EMIFA/VPSS Block: shows the Major Config Options based on the AEM and PCIEN settings. Actual pin functions in
the EMIFA/VPSS Block are further determined by other PINMUX fields.
C.
PCI pins span multiple blocks (Host Block, GPIO Block, EMIFA/VPSS Block, and PCI Data Block). For PCI to be
operational, PCI pins must be selected in all of these Pin Mux Blocks. For the EMIFA/VPSS Block, PCI is only
supported if AEM = 000b or 101b.
D.
McBSP0 pins span multiple blocks (Serial Port Sub-Block0 and Timer0 Block). Serial Port Sub-Block0 contains most
of the pins needed for McBSP0 operation. Timer0 Block contains the optional external clock source input CLKS0.
E.
McBSP1 spans multiple blocks (Serial Port Sub-Block1, Timer0 Block). Serial Port Sub-Block1 contains most of the
pins needed for McBSP1 operation. Timer0 Block contains the optional external clock soruce input CLKS1.
Figure 3-11. Pin Mux Block Selection
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Pin Muxing Selection At Reset
This section summarizes pin mux selection at reset.
The configuration pins AEM[2:0], AEAW[2:0], and PCIEN latched at device reset determine default pin
muxing for the following Pin Mux Blocks:
•
•
•
•
EMIFA/VPSS Block: default pin mux determined by AEM[2:0], AEAW[2:0], and PCIEN. After reset,
software may modify settings in the PINMUX0 register to add VPBE and VPFE functionalities
into this block. However, after reset, software is not allowed to modify PINMUX1.PCIEN setting
to change PCI pinout.
– AEM[2:0] = 000b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option A is selected. This
block defaults to 61 GPIO pins.
– AEM[2:0] = 001b, AEAW[2:0] = 000b to 100b, PCIEN = 0: Major Config Option B is selected. This
block defaults to 8-bit EMIFA (Async) Pinout Mode 1, plus 24 to 32 GPIO pins.
– AEM[2:0] = 011b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option C is selected. This
block defaults to 8-bit EMIFA (Async) Pinout Mode 3, plus 33 GPIO pins.
– AEM[2:0] = 100b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option D is selected. This
block defaults to 8-bit EMIFA (NAND) Pinout Mode 4, plus 47 GPIO pins.
– AEM[2:0] = 101b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option E is selected. This
block defaults to 8-bit EMIFA (NAND) Pinout mode 5, plus 47 GPIO pins.
– AEM[2:0] = 000b, AEAW[2:0] = don't care, PCIEN = 1: Major Config Option F is selected. This
block defaults to PCI pins, plus 45 GPIO pins.
– AEM[2:0] = 101b, AEAW[2:0] = don't care, PCIEN = 1: Major Config Option G is selected. This
block defaults to 8-bit EMIFA (NAND) Pinout mode 5, PCI pins, plus 31 GPIO pins.
Host Block: default pin mux determined by PCIEN.
– PCIEN = 0: the 27 pins in Host Block default to GPIO function. Software may program
PINMUX1.HOSTBK to modify pin functions after reset.
– PCIEN = 1: the 27 pins in Host Block serve as PCI pins. Software is not allowed to modify this
setting after reset.
GPIO Block: pin function determined by PCIEN configuration pin.
– PCIEN = 0: the 4 pins in GPIO Block serve as GPIO pins. Software is not allowed to modify this
setting after reset.
– PCIEN = 1: the 4 pins in GPIO Block serve as PCI pins. Software is not allowed to modify this
setting after reset.
PCI Data Block: pin function determined by PCIEN.
– PCIEN = 0: the 3 pins in PCI Data Block have no function and should be left unconnected.
Software is not allowed to modify this setting after reset.
– PCIEN = 1: the 3 pins in PCI Data Block serve as PCI pins. Software is not allowed to modify
this setting after reset.
For a description of the PINMUX0 and PINMUX1 registers and more details on pin muxing, see
Section 3.7.2.
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3.7.2
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Pin Muxing Selection After Reset
The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions in
the Pin Mux Blocks. The pin control of some of the Pin Mux Blocks requires a combination of
PINMUX0/PINMUX1 bit fields. For more details on the combination of the PINMUX bit fields that control
each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6437.
This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed
discussion on how to program each Pin Mux Block, see Section 3.7.3, Pin Multiplexing Details.
3.7.2.1 PINMUX0 Register Description
The Pin Multiplexing 0 Register (PINMUX0) controls the pin function in the EMIFA/VPSS Block. The
PINMUX0 register format is shown in Figure 3-12 and the bit field descriptions are given in Table 3-19.
Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX
bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6437. For more
information on EMIFA/VPSS Block pin muxing, see Section 3.7.3.13, EMIFA/VPSS Block Muxing. For the
pin-by-pin muxing control of the EMIFA/VPSS Block, see Section 3.7.3.13.7, EMIFA/VPSS Block
Pin-By-Pin Multiplexing Summary.
Note: In addition to PINMUX0 bit fields, the EMIFA/VPSS Block also requires the PCIEN bit in the Pin
Multiplexing 1 Register (PINMUX1, Section 3.7.2.2) to determine the PCI settings.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RSV
CI10SEL
RSV
CI32SEL
RSV
CI54SEL
CI76SEL
CFLDSE
L
CWEN
SEL
HVDSEL
RSV
CCDCSE
L
RSV
AEAW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-LLL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VPBE
CKEN
RGBSEL
CS3SEL
CS4SEL
CS5SEL
VENCSEL
RSV
AEM
R/W-0
R/W-000
R/W-00
R/W-00
R/W-00
R/W-00
R/W-0
R/W-LLL
16
0
LEGEND: R/W = Read/Write; R = Read only; L = pin state latched at reset rising edge; -n = value after reset
(1)
For proper DM6437 device operation, always write a value of "0" to all RESERVED/RSV bits.
Figure 3-12. PINMUX0 Register— 0x01C4 0000 (1)
Table 3-19. PINMUX0 Register Descriptions
Bit
31
Field Name
RSV
Description
CI[1:0] Function Select.
30
29
(1)
102
CI10SEL
RSV
Pins Controlled
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
Sub-Block 0
0 = No CCDC CI[1:0].
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
settings (default).
CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]
1 = Selects CCDC [1:0] (as CCD8 and CCD9, respectively) to get at least a 10-bit
CCDC.
To use the 10-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1.
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
The combination of PINMUX0/1 fields AEM,
AEAW, PCIEN, and CI10SEL bits control the
pin muxing of these 2 pins. (1)
CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
For the full set of valid configurations of these pins, see Section 3.7.3.13.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary.
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Table 3-19. PINMUX0 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
CI[3:2] Function Select.
0 = No CCDC CI[3:2].
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
settings (default).
28
27
CI32SEL
RSV
Sub-Block 0
CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]
CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]
1 = Selects CCDC [3:2] (as CCD10 and CCD11, respectively) to get at least a
12-bit CCDC.
To use the 12-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1
and PINMUX0.CI10SEL = 1.
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
The combination of PINMUX0/1 fields AEM,
AEAW, PCIEN, and CI32SEL bits control the
pin muxing of these 2 pins. (1)
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
CI[5:4] Function Select.
0 = No CCDC CI[5:4].
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
settings (default).
26
CI54SEL
Sub-Block 0
CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]
CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]
1 = Selects CCDC [5:4] (as CCD12 and CCD13, respectively) to get at least a
14-bit CCDC.
To use the 14-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1,
PINMUX0.CI10SEL = 1, and PINMUX0.CI32SEL = 1.
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
The combination of PINMUX0/1 fields AEM,
AEAW, PCIEN, and CI54SEL bits control the
pin muxing of these 2 pins. (1)
CI[7:6] Function Select.
0 = No CCDC CI[7:6].
Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN
settings (default).
25
CI76SEL
CFLDSEL
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]
CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]
1 = Selects CCDC [7:6] (as CCD14 and CCD15, respectively) to get at least a
16-bit CCDC.
To use the 16-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1,
PINMUX0.CI10SEL = 1, PINMUX0.CI32SEL = 1, and PINMUX0.CI54SEL = 1.
Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.
CCDC Field Select.
24
Sub-Block 0
0 = No CCDC Field (C_FIELD).
Pin functions as EMIFA EM_A[21] or GPIO based on AEM setting (default).
1 = CCDC Field (C_FIELD).
The combination of PINMUX0/1 fields AEM,
AEAW, PCIEN, and CI76SEL bits control the
pin muxing of these 2 pins. (1)
Sub-Block 0
C_FIELD/EM_A[21]/GP[34]
The combination of PINMUX0/1 fields
CFLDSEL and AEM control the muxing of this
pin. (1)
CCDC Write Enable Select.
23
CWENSEL
0 = No CCDC Write Enable.
Pin functions as EMIFA EM_R/W or GPIO based on AEM setting (default).
1 = CCDC Write Enable (C_WE).
Pin functions as CCDC Write Enable C_WE.
Applicable only for AEM = 0 (000b), 4 (100b), or 5 (101b).
CCDC HD and VD Select.
22
HVDSEL
0 = No CCDC HD and VD.
Pins function as GPIO (GP[53] and GP[52]) (default).
1 = CCDC HD and VD.
21
RSV
Sub-Block 0
C_WE/EM_R/W/GP[35]
The combination of PINMUX0 fields CWENSEL
and AEM control the muxing of this pin. (1)
Sub-Block 0
VD/GP[53]
HD/GP[52]
The PINMUX0 field HVDSEL alone controls the
muxing of these 2 pins.
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
Sub-Block 0
CCDC Select.
This bit field determines if CCDC is supported or not.
20
CCDCSEL
0 = CCDC not supported.
Pins function as GPIO (GP[54] and GP[43:36]) (default).
1 = CCDC supported.
Pins function as CCDC PCLK, YI[7:0].
PCLK/GP[54]
YI7(CCD7)/GP[43]
YI6(CCD6)/GP[42]
YI5(CCD5)/GP[41]
YI4(CCD4)/GP[40]
YI3(CCD3)/GP[39]
YI2(CCD2)/GP[38]
YI1(CCD1)/GP[37]
YI0(CCD0)/GP[36]
The PINMUX0 field CCDCSEL alone controls
the muxing of these 9 pins.
19
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
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Table 3-19. PINMUX0 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
8-bit EMIFA (Async) Pinout Mode 1 Address Width Select or Fast Boot PLL
Multiplier Select
This field serves two purposes:
1.
If AEM = 001b, this field serves as the 8-bit EMIFA (Async) Pinout Mode 1
Address Width Select.
2.
If FASTBOOT = 1 and AEM = 0 (000b), 3 (011b), 4 (100b), or 5 (101b), this
field serves as the Fastboot PLL Multiplier Select.
Fastboot PLL Multiplier Select: For more details on the AEAW pin functions as
Fastboot PLL Multiplier Select, see Section 3.4.1, Bootmodes.
EMIFA Address Width Select:
000b = EMIFA (Async) pinout supports only EM_A[12:0] address pins.
EMIFA (Async) signals EM_A[20:13] are not pinned out. PINMUX bit fields
PCIEN, CI76SEL, CI54SEL, CI32SEL, and CI10SEL determine the function of
these 8 pins.
18:16
AEAW (2)
001b = EMIFA (Async) pinout supports only EM_A[14:0] address pins.
EMIFA (Async) signals EM_A[14:13] are pinned out. PINMUX0 bit field CI76SEL
must be programmed to 0.
EMIFA (Async) signals EM_A[20:15] are not pinned out. PINMUX0 bit fields
CI54SEL, CI32SEL, and CI10SEL determine the function of these 6 pins.
010b = EMIFA (Async) pinout supports only address pins EM_A[16:0].
EMIFA (Async) signals EM_A[16:13] are pinned out. PINMUX0 bit fields CI76SEL
and CI54SEL must be programmed to 0.
EMIFA (Async) signals EM_A[20:17] are not pinned out. PINMUX0 bit fields
CI32SEL and CI10SEL determine the function of these 4 pins.
Sub-Block 0
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]
CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]
CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]
CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]
CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]
CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]
CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]
CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]
The combination of PINMUX0/1 fields PCIEN,
AEM, AEAW, CI10SEL, CI32SEL, CI54SEL,
and CI76SEL control the muxing of these 8
pins. (1)
011b = EMIFA (Async) pinout supports only address pins EM_A[18:0].
EMIFA (Async) signals EM_A[18:13] are pinned out. PINMUX0 bit fields
CI76SEL, CI54SEL, and CI32SEL must be programmed to 0.
EMIFA (Async) signals EM_A[20:19] are not pinned out. PINMUX0 bit field
CI10SEL determines the function of these 2 pins.
100b = EMIFA (Async) pinout supports address pins EM_A[20:0].
EMIFA (Async) signals EM_A[20:13] are pinned out. PINMUX0 bit fields
CI76SEL, CI54SEL, CI32SEL, and CI10SEL must be programmed to 0.
101b through 111b = Reserved.
VPBE Clock Select.
15
VPBECKEN
0 = GPIO (default)
Pin functions as GPIO (GP[30]).
1 = VPBE Clock (VPBECLK)
Pin functions as VPBE Clock (VPBECLK).
Sub-Block 1
VPBECLK/GP[30]
The PINMUX0 field VPBECKEN alone controls
the muxing of this pin.
VENC RGB Mode and LCD_FIELD Select.
000b = No VENC RGB Mode or LCD_FIELD supported.
These pins function as GPIO and/or EMIFA based on AEM setting (default).
001b = LCD_FIELD Mode.
VENC LCD_FIELD pin function is supported. The remaining 7 pins function as
GPIO and/or EMIFA based on AEM setting.
Applicable only if AEM = 0 (000b), 4 (100b), or 5 (101b).
14:12
RGBSEL
010b = RGB666 Mode.
VENC RGB666 pins (R2, B2) are supported, along with 6 GPIO pins (GP[12:7]).
Applicable only if AEM = 0 (000b).
011b = RGB666 + LCD_FIELD Mode.
VENC RGB666 (R2, B2) and LCD_FIELD pins are supported, along with 5 GPIO
pins (GP[12] and GP[10:7]).
Applicable only if AEM = 0 (000b).
Sub-Block 1
G0/EM_CS2/GP[12]
B0/LCD_FIELD/EM_A[3]/GP[11]
R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)
G1/EM_A[1]/(ALE)/GP[9]/AEAW1/PLLMS1)
B1/EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0)
R1/EM_A[0]/GP[7]/(AEM2)
R2/EM_BA[0]/GP[6]/(AEM1)
B2/EM_BA[1]/GP[5]/(AEM0)
The combination of PINMUX0 fields RGBSEL
and AEM, control the muxing of these 8 pins. (1)
100b = RGB888 Mode.
VENC RGB888 (G0, B0, R0, G1, B1, R1, R2, B2) pins are supported.
Applicable only if AEM = 0 (000b).
101b through 111b = Reserved.
(2)
104
The AEAW default value is latched at reset from AEAW[2:0] configuration inputs. The latched values are also shown at
BOOTCFG.PLLMS (read-only).
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Table 3-19. PINMUX0 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
Chip Select 3 Select.
00 = GPIO pin (GP13) (default)
11:10
CS3SEL
01 = EMIFA Chip Select 3 (EM_CS3)
10 = VENC LCD Output Enable (LCD_OE)
Sub-Block 1
LCD_OE/EM_CS3/GP[13]
The PINMUX0 field CS3SEL alone controls the
muxing of this pin.
11 = Reserved
Chip Select 4 Select.
00 = GPIO pin (GP32) (default)
9:8
CS4SEL
01 = EMIFA Chip Select 4 (EM_CS4)
10 = VENC Vertical Sync (VSYNC)
Sub-Block 1
VSYNC/EM_CS4/GP[32]
The PINMUX0 field CS4SEL alone controls the
muxing of this pin.
11 = Reserved
Chip Select 5 Select.
00 = GPIO pin (GP33) (default)
7:6
CS5SEL
01 = EMIFA Chip Select 5 (EM_CS5)
10 = VENC Horizontal Sync (HSYNC)
Sub-Block 1
HSYNC/EM_CS5/GP[33]
The PINMUX0 field CS5SEL alone controls the
muxing of this pin.
11 = Reserved
Sub-Block 1
VENC Mode Select.
00 = No VENC supported.
9 pins function as GPIO (GP[31], GP[29:22]). The remaining 8 pins function as
GPIO/EMIFA based on AEM setting.
5:4
VENCSEL
01 = 8-bit VENC supported.
VENC VCLK, YOUT[7:0] functions are pinned out. The remaining 8 pins function
as GPIO/EMIFA based on AEM setting.
10 = 16-bit VENC supported.
These pins function as VENC VCLK, YOUT[7:0], and COUT[7:0].
Applicable only if AEM = 0 (000b), 3 (011b), 4 (100b).
11 = Reserved
VCLK/GP[31]
YOUT7/GP[29]
YOUT6/GP[28]
YOUT5/GP[27]
YOUT4/GP[26]
YOUT3/GP[25]
YOUT2/GP[24]
YOUT1/GP[23]
YOUT0/GP[22]
The PINMUX0 field VENCSEL alone controls
the muxing of these 9 pins.
COUT7/EM_D[7]/GP[21]
COUT6/EM_D[6]/GP[20]
COUT5/EM_D[5]/GP[19]
COUT4/EM_D[4]/GP[18]
COUT3/EM_D[3]/GP[17]
COUT2/EM_D[2]/GP[16]
COUT1/EM_D[1]/GP[15]
COUT0/EM_D[0]/GP[14
The combination of PINMUX fields VENCSEL
and AEM control the muxing of these 8 pins. (1)
3
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
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Table 3-19. PINMUX0 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
Sub-Block 0
EMIFA Pinout Modes
This field does not affect the actual EMIFA operation. It only determines what
multiplexed pins in the EMIFA/VPSS Block serves as EMIFA pins.
000b = No EMIFA Mode.
None of the multiplexed pins in the EMIFA/VPSS Block serves as EMIFA pins.
001b = 8-bit EMIFA (Async) Pinout Mode 1.
(Up to 16M-Byte address reach per Chip Select Space).
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit
EMIFA (Async or NAND) + 16-bit CCDC (VPFE) + 8-bit VENC (VPBE)
010b = Reserved.
2:0
AEM (3)
011b = 8-bit EMIFA (Async) Pinout Mode 3.
(32K-Byte reach per Chip Select Space).
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit
EMIFA (Async or NAND) + 8-bit CCDC (VPFE) + 16-bit VENC (VPBE)
100b = 8-bit EMIFA (NAND) Pinout Mode 4.
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit
EMIFA (NAND) + 8-bit CCDC (VPFE) + 16-bit VENC (VPBE)
101b = 8-bit EMIFA (NAND) Pinout Mode 5.
Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit
EMIFA (NAND) + 16-bit CCDC (VPFE) + 8-bit VENC (VPBE)
110b through 111b = Reserved
C_WE/EM_R/W/GP[35]
C_FIELD/EM_A[21]/GP[34]
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]
CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]
CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]
CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]
CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]
CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]
CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]
CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]
Sub-Block 1
COUT7/EM_D[7]/GP[21]
COUT6/EM_D[6]/GP[20]
COUT5/EM_D[5]/GP[19]
COUT4/EM_D[4]/GP[18]
COUT3/EM_D[3]/GP[17]
COUT2/EM_D[2]/GP[16]
COUT1/EM_D[1]/GP[15]
COUT0/EM_D[0]/GP[14]
G0/EM_CS2/GP[12]
B0/LCD_FIELD/EM_A[3]/GP[11]
R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)
G1/EM_A[1]/(ALE)/GP[9]/(AEAW1/PLLMS1)
B1/EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0)
R1/EM_A[0]/GP[7]/(AEM2)
R2/EM_BA[0]/GP[6]/(AEM1)
B2/EM_BA[1]/GP[5]/(AEM0)
Sub-Block3
EM_A[12]/PCBE3/GP[89]
EM_A[11]/AD24/GP[90]
EM_A[10]/AD23/GP[91]
EM_A[9]/PIDSEL/GP[92]
EM_A[8]/AD21/GP[93]
EM_A[7]/AD22/GP[94]
EM_A[6]/AD20/GP[95]
EM_A[5]/AD19/GP[96]
The pin mux for these pins are controlled by a
combination of AEM and other PINMUX0 fields,
including CWENSEL, CFLDSEL, AEAW,
PCIEN, CI76SEL, CI54SEL, CI32SEL,
CI10SEL, VENCSEL, and RGBSEL. (1)
(3)
106
The AEM default value is latched at reset from AEM[2:0] configuration inputs. The latched values are also shown at BOOTCFG.DAEM
(read-only).
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3.7.2.2 PINMUX1 Register Description
The Pin Multiplexing 1 Register (PINMUX1) controls the pin multiplexing of all Pin Mux Blocks. The
PINMUX1 register format is shown in Figure 3-13 and the bit field descriptions are given in Table 3-20.
Some muxed pins are controlled by more than one PINMUX bit field. For the combination of PINMUX bit
fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6437.
31
26
15
25
24
23
22
21
20
19
18
17
16
RESERVED
SPBK1
SPBK0
TIM1BK
RSV
TIM0BK
R/W-0000 00
R/W-00
R/W-00
R/W-00
R/W-00
R/W-00
14
13
12
CKOBK
RSV
PWM1B
K
R/W-01
R/W-0
R/W-0
11
10
9
8
7
6
5
4
3
2
1
0
UR0FCBK
RSV
UR0DBK
RSV
HOSTBK
RESERVED
PCIEN
R/W-00
R/W-0
R/W-0
R/W-0
R/W-000
R/W-000
R-P
LEGEND: R/W = Read/Write; R = Read only; P = specified pin state; -n = value after reset
(1)
For proper DM6437 device operation, always write a value of "0" to all RESERVED/RSV bits.
Figure 3-13. PINMUX1 Register— 0x01C4 0004 (1)
Table 3-20. PINMUX1 Register Descriptions
Bit
31:26
Field Name
RESERVED
Description
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
Pins Controlled
–
Serial Port Sub-Block 1 Pin Select.
Selects the function of the multiplexed pins in the Serial Port Sub-Block 1.
00 = GPIO Mode (default).
Pins function as GPIO (GP[110:105]).
25:24
SPBK1
01 = McBSP1 Mode.
Pins function as McBSP1: CLKX1, FSX1, DX1, CLKR1, FSR1, and DR1.
10 = McASP0 Transmit and 1 serializer.
Pins function as McASP0: AXR0[0], ACLKX0, AFSX0, AHCLKX0, AMUTEIN0,
and AMUTE0.
Serial Port Sub-Block 1:
AXR0[0]/FSR1/GP[105]
ACLKX0/CLKX1/GP[106]
AFSX0/DX1/GP[107]
AHCLKX0/CLKR1/GP[108]
AMUTEIN0/FSX1/GP[109]
AMUTE0/DR1/GP[110]
11 = McBSP1 Transmit + McASP0 SPDIF Mode.
Pins function as McBSP1 transmit (CLKX1, FSX1, DX1) and McASP0 SPDIF
(AXR0[0], AHCLKX0, AMUTE0).
Serial Port Sub-Block 0 Pin Select.
Selects the function of the multiplexed pins in the Serial Port Sub-Block 0.
00 = GPIO Mode (default).
Pins function as GPIO (GP[104:99]).
23:22
SPBK0
01 = McBSP0 Mode.
Pins function as McBSP0 CLKX0, FSX0, DX0, CLKR0, FSR0, and DR0.
10 = McASP0 Receive and 3 serializers.
Pins function as McASP0 ACLKR0, AFSR0, AHCLKR0, AXR0_3, AXR0_2, and
AXR0_1.
Serial Port Sub-Block 0:
ACLKR0/CLKX0/GP[99]
AFSR0/DR0/GP[100]
AHCLKR0/CLKR0/GP[101]
AXR0[3]/FSR0/GP[102]
AXR0[2]/FSX0/GP[103]
AXR0[1]/DX0/GP[104]
11 = Reserved
Timer1 Block Pin Select.
Selects the function of the multiplexed pins in theTimer1 Block.
00 = GPIO Mode (default).
Pins function as GPIO (GP[56:55]).
21:20
TIM1BK
01 = Timer1 Mode.
Pins function as Timer1 TINP1L and TOUT1L.
Timer1 Block:
HECC_RX/TINP1L/URXD1/GP[56]
HECC_TX/TOUT1L/UTXD1/GP[55]
10 = UART1 Data Mode.
Pins function as UART1 data pins URXD1 and UTXD1.
11 = HECC Mode.
Pins function as HECC HECC_RX and HECC_TX.
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Table 3-20. PINMUX1 Register Descriptions (continued)
Bit
19:18
Field Name
RSV
Description
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
Pins Controlled
–
Timer0 Block Pin Select.
Selects the function of the multiplexed pins in the Timer0 Block.
00 = GPIO Mode (default).
Pins function as GPIO (GP[98:97]).
17:16
TIM0BK
01 = Timer0 Mode.
Pins function as Timer0 TINP0L and TOUT0L.
10 = McBSP0 and McBSP1 External Clock Source Mode.
Pins function as McBSP0 and McBSP1 external clock source pins, CLKS0 and
CLKS1, respectively.
Timer0 Block:
CLKS1/TINP0L/GP[98]
CLKS0/TOUT0L/GP[97]
11 = McBSP0 External Clock Source + Timer0 Input Mode.
Pins function as McBSP0 external clock source CLKS0, and Timer0 input
TINP0L.
CLKOUT Block Pin Select.
Selects the function of the multiplexed pins in the CLKOUT Block.
00 = GPIO Mode.
Pin functions as GPIO (GP[84]).
15:14
CKOBK
01 = CLKOUT Mode (default).
Pin functions as device clock output CLKOUT0, sourced from PLLC1 OBSCLK.
CLKOUT Block:
CLKOUT0/PWM2/GP[84]
10 = PWM2 Mode.
Pin functions as PWM2.
11 = Reserved
13
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
–
PWM1 Block Pin Select.
Selects the function of the multiplexed pins in the PWM1 Block.
12
PWM1BK
0 = GPIO Mode (default).
Pin functions as GPIO (GP[4]).
PWM1 Block:
GP[4]/PWM1
1 = PWM1 Mode.
Pin functions as PWM1.
UART0 Flow Control Block Pin Select.
Selects the function of the multiplexed pins in the UART0 Flow Control Block.
00 = GPIO Mode (default).
Pins function as GPIO (GP[88:87]).
11:10
UR0FCBK
01 = UART0 Flow Control Mode.
Pins function as UART0 Flow Control UCTS0 and URTS0.
UART0 Flow Control Block:
UCTS0/GP[87]
URTS0/PWM0/GP[88]
10 = PWM0 + GPIO Mode.
Pins function as PWM0 and GPIO (GP[87]).
11 = Reserved
9
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
–
UART0 Data Block Pin Select.
Selects the function of the multiplexed pins in the UART0 Data Block.
8
UR0DBK
0 = GPIO Mode (default).
Pins function as GPIO (GP[86:85]).
UART0 Data Block:
URXD0/GP[85]
UTXD0/GP[86]
1 = UART0 Data Mode.
Pins function as UART0 data URXD0 and UTXD0.
108
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Table 3-20. PINMUX1 Register Descriptions (continued)
Bit
7
Field Name
RSV
Description
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
Pins Controlled
–
Host Block:
VLYNQ_CLOCK/PCICLK/GP[57]
HD0/VLYNQ_SCRUN/AD18/GP[58]
HD1/VLYNQ_RXD0/AD16/GP[59]
HD2/VLYNQ_RXD1/AD17/GP[60]
HD3/VLYNQ_RXD2/PCBE2/GP[61]
PCIEN = 0 and HOSTBK = 000: GPIO Mode (default if PCIEN = 0).
HD4/VLYNQ_RXD3/PFRAME/GP[62]
Pins function as GPIO (GP[83:57]).
HD5/VLYNQ_TXD0/PIRDY/GP[63]
HD6/VLYNQ_TXD1/PTRDY/GP[64]
PCIEN = 0 and HOSTBK = 001: HPI + 1 GPIO Mode.
HD7/VLYNQ_TXD2/PDEVSEL/GP[65]
Pins function as HPI and GPIO (GP[57]).
HD8/VLYNQ_TXD3/PPERR/GP[66]
PCIEN = 0 and HOSTBK = 010: VLYNQ + 17 GPIO Mode.
HD9/MCOL/PSTOP/GP[67]
Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], HD10/MCRS/PSERR/GP[68]
VLYNQ_TXD[3:0]), and GP[83:67].
HD11/MTXD3/PCBE1/GP[69]
HD12/MTXD2/PPAR/GP[70]
PCIEN = 0 and HOSTBK = 011: VLYNQ + MII + MDIO Mode.
HD13/MTXD1/AD14/GP[71]
Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], HD14/MTXD0/AD15/GP[72]
VLYNQ_TXD[3:0]), MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,
HD15/MTXCLK/AD12/GP[73]
RXCLK, RXD[3:0]), and MDIO (MDIO, MDC).
HHWIL/MRXDV/AD13/GP[74]
HCNTL1/MTXEN/AD11/GP[75]
PCIEN = 0 and HOSTBK = 100: MII + MDIO +10 GPIO Mode.
HCNTL0/MRXER/AD10/GP[76]
Pins function as MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,
HR/W/MRXCLK/AD8/GP[77]
RXCLK, RXD[3:0]), MDIO (MDIO, MDC), and GP[66:57].
HDS2/MRXD0/AD9/GP[78]
HDS1/MRXD1/AD7/GP[79]
PCIEN = 1 and HOSTBK = 000: PCI Mode (default if PCIEN = 1).
HRDY/MRXD2/PCBE0/GP[80]
Pins function as PCI pins: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME,
HCS/MDCLK/AD5/GP[81]
PIDRDY, PTRDY, PDEVSEL, PPER, PSTOP, PSERR, PPAR, AD[18:5], and
HINT/MRXD3/AD6/GP[82]
AD03.
HAS/MDIO/AD3/GP[83]
All other PCIEN and HOSTBK combinations reserved.
The combination of PINMUX1 fields PCIEN and
HOSTBK select the function of these 27 pins.
Host Block Pin Select.
If EMAC opertaion is desired, EMAC must be placed in reset before
programminng PINMUX1 HOSTBK to select EMAC pins.
6:4
HOSTBK
3:1
RESERVED
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
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Table 3-20. PINMUX1 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
Host Block:
See list of 27 pins in HOSTBK bit field
description
PCI Data Block:
AD26
AD28
AD30
0
110
PCIEN
GPIO Block:
AD0/GP[0]
AD1/GP[1]
PCI Enable.
AD2/GP[2]
The PINMUX1.PCIEN reflects the state of the PCIEN pin. PINMUX1.PCIEN is AD4/GP[3]
read only and cannot be modified by software. For proper device
EMIFA/VPSS Sub-Block 0*:
operation, the user must hold the desired setting at the PCIEN pin
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]
throughout device operation.
CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]
PCIEN = 0: No PCI supported. Internal pullup/pulldown (IPU/IPD) on these pins CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]
CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]
are enabled.
CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]
For PCI multiplexed pins in the GPIO Block, when PCIEN = 0, the pins function CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]
as GPIO (GP[3:0]).
CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]
For PCI multiplexed pins in the Host Block, refer to PINMUX1.HOSTBK field for CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]
the actual pin functions.
EMIFA/VPSS Sub-Block 3*:
For PCI multiplexed pins in the EMIFA/VPSS Block, refer to PINMUX0.AEM,
EM_A[12]/PCBE3/GP[89]
AEAW, CI76SEL, CI54SEL, CI32SEL, and CI10SEL fields for the actual pin
EM_A[11]/AD24/GP[90]
functions.
For PCI pins in the PCI Data Block, when PCIEN = 0, the pins have no function EM_A[10]/AD23/GP[91]
EM_A[9]/PIDSEL/GP[92]
and should be left unconnected.
EM_A[8]/AD21/GP[93]
PCIEN = 1: PCI supported. Internal pullup/pulldown (IPU/IPD) on all PCI pins
EM_A[7]/AD22/GP[94]
are disabled.
EM_A[6]/AD20/GP[95]
EM_A[5]/AD19/GP[96]
All pins function as PCI pins.
Applicable only for PINMUX0.AEM = 000b or 101b.
The pin mux for the EMIFA/VPSS Sub-Block 0
and EMIFA/VPSS Sub-Block 3 pins are
controlled by a combination of PCIEN and other
PINMUX0/1 fields, including HOSTBK, AEM,
AEAW, CI76SEL, CI54SEL, CI32SEL, and
CI10SEL. See Section 3.7.3.13.7, EMIFA/VPSS
Block Pin-By-Pin Multiplexing Summary, for the
full set of valid configurations of EMIFA/VPSS
Block pins.
For the full set of valid configurations of Host
Block pins, see Section 3.7.3.3, Host Block
Muxing.
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3.7.3
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Pin Multiplexing Details
This section discusses how to program each Pin Mux Block to select the desired peripheral functions.
The following steps can be used to determine pin muxing suitable for the application:
1. Understand the major configuration choices available for the specific application.
a. Device Major Configuration Choices: Figure 3-11 shown in Section 3.7, Multiplexed Pin
Configurations, provides a high-level view of the device pin muxing and can be used to determine
the possible mix of peripheral options for a specific application.
b. EMIFA/VPSS Block Major Configuration Choices: The EMIFA/VPSS block features extensive pin
multiplexing to accommodate a variety of applications. In addition to Figure 3-11, Section 3.7.3.13,
EMIFA/VPSS Block Muxing, provides more details on the Major Configuration choices for this
block.
2. See Section 3.7.3.1, Multiplexed Pins on DM6437, for a summary of all the multiplexed pins on this
device and the pin mux group they belong to.
3. Refer to the individual pin mux sections (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.13,
EMIFA/VPSS Block Muxing) for pin muxing details for a specific pin mux block.
a. For peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that
peripheral in all relevant pin mux blocks. For more details, see Section 3.7.3.2, Peripherals
Spanning Multiple Pin Mux Blocks.
For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2.
3.7.3.1 Multiplexed Pins on DM6437
Table 3-21 summarizes all of the multiplexed pins on DM6437, the pin mux group for each pin, and the
PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section
(Section 3.7.3.3, Host Block Muxing to Section 3.7.3.13, EMIFA/VPSS Block Muxing). For a description of
the PINMUX register fields, see Section 3.7.2.
Table 3-21. Multiplexed Pins on DM6437
SIGNAL
PINMUX DESCRIPTION
ZWT
NO.
ZDU
NO.
PINMUX GROUP
PCLK/GP[54]
A14
A18
EMIFA/VPSS Sub-Block 0
CCDCSEL
VD/GP[53]
A13
A17
EMIFA/VPSS Sub-Block 0
HVDSEL
HD/GP[52]
A15
A19
EMIFA/VPSS Sub-Block 0
HVDSEL
CI7(CCD15)/EM_A[13]/AD25/
EM_D[0]/GP[51]
B10
A12
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI76SEL
CI6(CCD14)/EM_A[14]/AD27/
EM_D[1]/GP[50]
A10
A13
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI76SEL
CI5(CCD13)/EM_A[15]/AD29/
EM_D[2]/GP[49]
B11
C13
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI54SEL
CI4(CCD12)/EM_A[16]/PGNT/
EM_D[3]/GP[48]
C11
B13
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI54SEL
CI3(CCD11)/EM_A[17]/AD31/
EM_D[4]/GP[47]
A11
B14
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI32SEL
CI2(CCD10)/EM_A[18]/PRST/
EM_D[5]/GP[46]
D11
A14
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI32SEL
CI1(CCD9)/EM_A[19]/PREQ/
EM_D[6]/GP[45]
B12
C14
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI10SEL
CI0(CCD8)/EM_A[20]/PINTA/
EM_D[7]/GP[44]
C12
C15
EMIFA/VPSS Sub-Block 0
PCIEN, AEM, AEAW, CI10SEL
YI7(CCD7)/GP[43]
A12
A15
EMIFA/VPSS Sub-Block 0
CCDCSEL
YI6(CCD6)/GP[42]
B13
B15
EMIFA/VPSS Sub-Block 0
CCDCSEL
YI5(CCD5)/GP[41]
C13
B16
EMIFA/VPSS Sub-Block 0
CCDCSEL
NAME
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Table 3-21. Multiplexed Pins on DM6437 (continued)
SIGNAL
PINMUX DESCRIPTION
ZWT
NO.
ZDU
NO.
PINMUX GROUP
YI4(CCD4)/GP[40]
D14
C18
EMIFA/VPSS Sub-Block 0
CCDCSEL
YI3(CCD3)/GP[39]
B14
A16
EMIFA/VPSS Sub-Block 0
CCDCSEL
YI2(CCD2)/GP[38]
C14
B17
EMIFA/VPSS Sub-Block 0
CCDCSEL
YI1(CCD1)/GP[37]
B15
B18
EMIFA/VPSS Sub-Block 0
CCDCSEL
YI0(CCD0)/GP[36]
C15
B19
EMIFA/VPSS Sub-Block 0
CCDCSEL
C_WE/EM_R/W/GP[35]
D13
C17
EMIFA/VPSS Sub-Block 0
AEM, CWENSEL
C_FIELD/EM_A[21]/GP[34]
D12
C16
EMIFA/VPSS Sub-Block 0
AEM, CFLDSEL
NAME
CONTROLLED BY PINMUX BIT FIELDS
HSYNC/EM_CS5/GP[33]
F19
J22
EMIFA/VPSS Sub-Block 1
CS5SEL
VSYNC/EM_CS4/GP[32]
E19
H22
EMIFA/VPSS Sub-Block 1
CS4SEL
VCLK/GP[31]
D19
G22
EMIFA/VPSS Sub-Block 1
VENCSEL
VPBECLK/GP[30]
G19
K22
EMIFA/VPSS Sub-Block 1
VPBECKEN
YOUT7/GP[29]
H15
K21
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT6/GP[28]
H16
J21
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT5/GP[27]
H17
L19
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT4/GP[26]/(FASTBOOT)
G17
K19
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT3/GP[25]/(BOOTMODE3)
G16
H21
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT2/GP[24]/(BOOTMODE2)
G15
L20
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT1/GP[23]/(BOOTMODE1)
F15
K20
EMIFA/VPSS Sub-Block 1
VENCSEL
YOUT0/GP[22]/(BOOTMODE0)
F18
J20
EMIFA/VPSS Sub-Block 1
VENCSEL
COUT7/EM_D[7]/GP[21]
F17
H20
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT6/EM_D[6]/GP[20]
F16
F21
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT5/EM_D[5]/GP[19]
E17
F22
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT4/EM_D[4]/GP[18]
E18
G21
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT3/EM_D[3]/GP[17]
E16
F20
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT2/EM_D[2]/GP[16]
D17
E22
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT1/EM_D[1]/GP[15]
D18
G20
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
COUT0/EM_D[0]/GP[14]
D16
E21
EMIFA/VPSS Sub-Block 1
AEM, VENCSEL
LCD_OE/EM_CS3/GP[13]
C18
D22
EMIFA/VPSS Sub-Block 1
CS3SEL
G0/EM_CS2/GP[12]
C19
C22
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
B0/LCD_FIELD/EM_A[3]/GP[11]
B18
D21
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)
A17
B21
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
G1/EM_A[1]/(ALE)/GP[9]/
(AEAW1/PLLMS1)
A16
B20
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
B1/EM_A[2]/(CLE)/GP[8]/
(AEAW0/PLLMS0)
B16
A20
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
R1/EM_A[0]/GP[7]/(AEM2)
B17
C21
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
R2/EM_BA[0]/GP[6]/(AEM1)
C17
E20
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
B2/EM_BA[1]/GP[5]/(AEM0)
C16
C20
EMIFA/VPSS Sub-Block 1
AEM, RGBSEL
EM_A[12]/PCBE3/GP[89]
D10
B12
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[11]/AD24/GP[90]
C10
C12
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[10]/AD23/GP[91]
A9
B11
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[9]/PIDSEL/GP[92]
D9
C11
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[8]/AD21/GP[93]
B9
A11
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[7]/AD22/GP[94]
C9
C10
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[6]/AD20/GP[95]
D8
B10
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
EM_A[5]/AD19/GP[96]
B8
A10
EMIFA/VPSS Sub-Block 3
PCIEN, AEM
112
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Table 3-21. Multiplexed Pins on DM6437 (continued)
SIGNAL
PINMUX DESCRIPTION
ZWT
NO.
ZDU
NO.
PINMUX GROUP
VLYNQ_CLOCK/PCICLK/GP[57]
A7
A8
Host Block
PCIEN, HOSTBK
HD0/VLYNQ_SCRUN/AD18/GP[58]
C8
B9
Host Block
PCIEN, HOSTBK
HD1/VLYNQ_RXD0/AD16/GP[59]
D7
C9
Host Block
PCIEN, HOSTBK
HD2/VLYNQ_RXD1/AD17/GP[60]
A8
A9
Host Block
PCIEN, HOSTBK
HD3/VLYNQ_RXD2/PCBE2/GP[61]
B7
B8
Host Block
PCIEN, HOSTBK
HD4/VLYNQ_RXD3/PFRAME/GP[62]
C7
C8
Host Block
PCIEN, HOSTBK
HD5/VLYNQ_TXD0/PIRDY/GP[63]
A6
A7
Host Block
PCIEN, HOSTBK
HD6/VLYNQ_TXD1/PTRDY/GP[64]
D6
C7
Host Block
PCIEN, HOSTBK
HD7/VLYNQ_TXD2/PDEVSEL/GP[65]
B6
B7
Host Block
PCIEN, HOSTBK
HD8/VLYNQ_TXD3/PPERR/GP[66]
A5
A6
Host Block
PCIEN, HOSTBK
HD9/MCOL/PSTOP/GP[67]
C6
C6
Host Block
PCIEN, HOSTBK
HD10/MCRS/PSERR/GP[68]
B5
B6
Host Block
PCIEN, HOSTBK
HD11/MTXD3/PCBE1/GP[69]
C5
A5
Host Block
PCIEN, HOSTBK
HD12/MTXD2/PPAR/GP[70]
D5
C5
Host Block
PCIEN, HOSTBK
HD13/MTXD1/AD14/GP[71]
B4
B4
Host Block
PCIEN, HOSTBK
HD14/MTXD0/AD15/GP[72]
D4
B5
Host Block
PCIEN, HOSTBK
HD15/MTXCLK/AD12/GP[73]
A4
A4
Host Block
PCIEN, HOSTBK
HHWIL/MRXDV/AD13/GP[74]
C4
D3
Host Block
PCIEN, HOSTBK
HCNTL1/MTXEN/AD11/GP[75]
D3
C4
Host Block
PCIEN, HOSTBK
HCNTL0/MRXER/AD10/GP[76]
B3
B2
Host Block
PCIEN, HOSTBK
NAME
CONTROLLED BY PINMUX BIT FIELDS
HR/W/MRXCLK/AD8/GP[77]
A3
A3
Host Block
PCIEN, HOSTBK
HDS2/MRXD0/AD9/GP[78]
C3
C2
Host Block
PCIEN, HOSTBK
HDS1/MRXD1/AD7/GP[79]
B2
B3
Host Block
PCIEN, HOSTBK
HRDY/MRXD2/PCBE0/GP[80]
D2
C3
Host Block
PCIEN, HOSTBK
HCS/MDCLK/AD5/GP[81]
C1
D1
Host Block
PCIEN, HOSTBK
HINT/MRXD3/AD6/GP[82]
C2
D2
Host Block
PCIEN, HOSTBK
HAS/MDIO/AD3/GP[83]
D1
C1
Host Block
PCIEN, HOSTBK
AD0/GP[0]
E1
E1
GPIO Block
PCIEN
AD1/GP[1]
E2
E2
GPIO Block
PCIEN
AD2/GP[2]
E3
F1
GPIO Block
PCIEN
AD4/GP[3]
E4
F2
GPIO Block
PCIEN
GP[4]/PWM1
F3
F3
PWM1Block
PWM1BK
ACLKR0/CLKX0/GP[99]
H1
J1
Serial Port Sub-Block 0
SPBK0
AFSR0/DR0/GP[100]
H4
K3
Serial Port Sub-Block 0
SPBK0
AHCLKR0/CLKR0/GP[101]
J2
K1
Serial Port Sub-Block 0
SPBK0
AXR0[3]/FSR0/GP[102]
G4
J3
Serial Port Sub-Block 0
SPBK0
AXR0[2]/FSX0/GP[103]
H3
J2
Serial Port Sub-Block 0
SPBK0
AXR0[1]/DX0/GP[104]
J3
K2
Serial Port Sub-Block 0
SPBK0
AXR0[0]/FSR1/GP[105]
H2
H2
Serial Port Sub-Block 1
SPBK1
ACLKX0/CLKX1/GP[106]
F1
G1
Serial Port Sub-Block 1
SPBK1
AFSX0/DX1/GP[107]
G2
G2
Serial Port Sub-Block 1
SPBK1
AHCLKX0/CLKR1/GP[108]
G1
H1
Serial Port Sub-Block 1
SPBK1
AMUTEIN0/FSX1/GP[109]
F2
G3
Serial Port Sub-Block 1
SPBK1
AMUTE0/DR1/GP[110]
G3
H3
Serial Port Sub-Block 1
SPBK1
HECC_RX/TINP1L/URXD1/GP[56]
L4
P3
Timer 1 Block
TIM1BK
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Table 3-21. Multiplexed Pins on DM6437 (continued)
SIGNAL
PINMUX DESCRIPTION
ZWT
NO.
ZDU
NO.
PINMUX GROUP
HECC_TX/TOUT1L/UTXD1/GP[55]
K4
N3
Timer 1 Block
TIM1BK
CLKS1/TINP0L/GP[98]
K2
L2
Timer 0 Block
TIM0BK
CLKS0/TOUT0L/GP[97]
J4
L3
Timer 0 Block
TIM0BK
URXD0/GP[85]
L2
M2
UART0 Data Block
UR0DBK
UTXD0/GP[86]
K3
N1
UART0 Data Block
UR0DBK
UCTS0/GP[87]
L1
P1
UART0 Flow Control Block
UR0FCBK
URTS0/PWM0/GP[88]
L3
M3
UART0 Flow Control Block
UR0FCBK
CLKOUT0/PWM2/GP[84]
M1
R1
CLKOUT Block
NAME
CONTROLLED BY PINMUX BIT FIELDS
CKOBK
Note: PINMUX groups EMIFA/VPSS Sub-Block 2 and PCI Data Block are not shown in the above table
because there is no actual pin multiplexing in those blocks. But these two blocks are still considered "pin
mux blocks" because they contain some of the pins necessary for EMIFA and PCI, respectively. The pins
in these blocks are as follows:
• EMIFA/VPSS Sub-Block 2
– EM_WAIT/(RDY/BSY)
– EM_OE
– EM_WE
• PCI Data Block
– AD30
– AD28
– AD26
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3.7.3.2 Peripherals Spanning Multiple Pin Mux Blocks
Some peripherals span multiple Pin Mux Blocks. To use these peripherals, they must be selected in all of
the relevant Pin Mux Blocks. The following is the list of peripherals that span multiple Pin Mux Blocks:
• PCI: PCI pins span across the Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI
Data Block, and GPIO Block. To select PCI pins, program PINMUX registers as follows:
– Host Block: PCIEN = 1, HOSTBK = 000
– EMIFA/VPSS Block: Select either Major Configuration Option F or G. For more details on the
PINMUX settings associated with Major Configuration Options F or G, see Section 3.7.3.13,
EMIFA/VPSS BLock Muxing.
– PCI Data Block: PCIEN = 1
– GPIO Block: PCIEN = 1
• McBSP0: Six McBSP0 pins are located in the Serial Port Sub-Block 0, but the CLKS0 pin is muxed in
the Timer0 Block. To select McBSP0 pins, program PINMUX registers as follows:
– Serial Port Sub-Block 0: SPBK0 = 01
– Timer0 Block: If CLKS0 pin is desired, program TIM0BK = 10 or 11.
• McBSP1: Six McBSP1 pins are located in the Serial Port Sub-Block 1, but the CLKS1 pin is muxed in
the Timer0 Block. To select McBSP1 pins, program PINMUX registers as follows:
– Serial Port Sub-Block 1: SPBK1 = 01 (if both McBSP1 transmit and receive pins are needed) or
11 (if only McBSP1 transmit pins are needed)
– Timer0 Block: If CLKS1 pin is desired, program TIM0BK = 10.
• UART0: The two UART0 data pins are located in the UART0 Data Block, but the two UART0 flow
control pins are located in the UART0 Flow Control Block. To select UART0, program PINMUX
registers as follows:
– UART0 Data Block: UR0BK = 1
– UART0 Flow Control Block: If flow control pins are desired, program UR0FCBK = 01.
3.7.3.3 Host Block Muxing
This block of 27 pins consists of PCI, HPI, VLYNQ, EMAC, MDIO, and GPIO muxed pins. The following
register fields select the pin functions in the Host Block:
• PINMUX1.PCIEN
• PINMUX1.HOSTBK
Table 3-22 summarizes the 27 pins in the Host Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
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Table 3-22. Host Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL NAME
HPI
FUNCTION
VLYNQ_CLOCK/PCICLK/GP[57]
–
EMAC/MDIO
SELECT
–
FUNCTION
VLYNQ
SELECT
FUNCTION
–
–
VLYNQ_CLOCK
PCI
SELECT
FUNCTION
GPIO
SELECT
FUNCTION
SELECT
PCICLK
GP[57]
PCIEN = 0,
and
HOSTBK = 000
or
HOSTBK = 001
or
HOSTBK = 100
AD18
GP[58]
AD16
GP[59]
AD17
GP[60]
PCBE2
GP[61]
HD0/VLYNQ_SCRUN/AD18/GP[58]
HD0
–
–
VLYNQ_SCRUN
HD1/VLYNQ_RXD0/AD16/GP[59]
HD1
–
–
VLYNQ_RXD0
HD2/VLYNQ_RXD1/AD17/GP[60]
HD2
–
–
VLYNQ_RXD1
HD3/VLYNQ_RXD2/PCBE2/GP[61]
HD3
–
–
VLYNQ_RXD2
HD4/VLYNQ_RXD3/PFRAME/GP[62]
HD4
–
–
VLYNQ_RXD3
PFRAME
GP[62]
HD5/VLYNQ_TXD0/PIRDY/GP[63]
HD5
–
–
VLYNQ_TXD0
PIRDY
GP[63]
HD6/VLYNQ_TXD1/PTRDY/GP[64]
HD6
–
–
VLYNQ_TXD1
PTRDY
GP[64]
HD7/VLYNQ_TXD2/PDEVSEL/GP[65]
HD7
–
–
VLYNQ_TXD2
PDEVSEL
GP[65]
HD8/VLYNQ_TXD3/PPERR/GP[66]
HD8
–
–
VLYNQ_TXD3
PPERR
GP[66]
HD9/MCOL/PSTOP/GP[67]
HD9
MCOL
–
–
PSTOP
HD10/MCRS/PSERR/GP[68]
HD10
MCRS
–
–
PSERR
HD11/MTXD3/PCBE1/GP[69]
HD11
MTXD3
–
–
PCBE1
HD12/MTXD2/PPAR/GP[70]
HD12
MTXD2
–
–
PPAR
GP[70]
HD13/MTXD1/AD14/GP[71]
HD13
MTXD1
–
–
AD14
GP[71]
HD14/MTXD0/AD15/GP[72]
HD14
MTXD0
–
–
AD15
GP[72]
HD15/MTXCLK/AD12/GP[73]
HD15
MTXCLK
–
–
AD12
GP[73]
HHWIL/MRXDV/AD13/GP[74]
HHWIL
MRXDV
–
–
AD13
GP[74]
HCNTL1/MTXEN/AD11/GP[75]
HCNTL1
MTXEN
–
–
AD11
GP[75]
HCNTL0/MRXER/AD10/GP[76]
PCIEN = 0,
and
HOSTBK = 001
PCIEN = 0,
and
HOSTBK = 011
or
HOSTBK = 100
PCIEN = 0,
and
HOSTBK = 010
or
HOSTBK = 011
GP[67]
PCIEN = 1,
and
HOSTBK = 000
GP[68]
GP[69]
HCNTL0
MRXER
–
–
AD10
GP[76]
HR/W/MRXCLK/AD8/GP[77]
HR/W
MRXCLK
–
–
AD8
GP[77]
HDS2/MRXD0/AD9/GP[78]
HDS2
MRXD0
–
–
AD9
GP[78]
HDS1/MRXD1/AD7/GP[79]
HDS1
MRXD1
–
–
AD7
GP[79]
HRDY/MRXD2/PCBE0/GP[80]
HRDY
MRXD2
–
–
PCBE0
GP[80]
HCS/MDCLK/AD5/GP[81]
HCS
MDCLK
–
–
AD5
GP[81]
HINT/MRXD3/AD6/GP[82]
HINT
MRXD3
–
–
AD6
GP[82]
HAS/MDIO/AD3/GP[83]
HAS
MDIO
–
–
AD3
GP[83]
116
Device Configurations
PCIEN = 0,
and
HOSTBK = 000
or
HOSTBK = 100
PCIEN = 0,
and
HOSTBK = 000
or
HOSTBK = 010
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As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,
and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
Table 3-23 provides a different view of the Host Block pin muxing, showing the Host Block function based
on PINMUX1 settings. The selection options are also shown pictorially in Figure 3-11.
If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to
select EMAC pins.
Table 3-23. Host Block Function Selection
PINMUX1 SETTING
BLOCK FUNCTION
PCIEN (1)
HOSTBK
1
000
PCI
(Default if PCIEN = 1)
1
001 to 111
Reserved
0
000
GPIO (27)
(Default if PCIEN = 0)
0
001
HPI + GPIO (1)
RESULTING PIN FUNCTIONS
PCI: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME, PIDRDY, PTRDY,
PDEVSEL, PSTOP, PPER, PSERR, PPAR, AD[18:05], AD[03]
Internal pullup/pulldown on all these pins are disabled.
Reserved
GPIO: GP[83:57]
HPI: HHWIL, HCNTL[1:0], HR/W, HDS2, HDS1, HRDY, HCS, HINT, HAS,
HD[15:0]
GPIO: GP[57]
0
010
VLYNQ + GPIO (17)
VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],
VLYNQ_TXD[3:0]
GPIO: GP[83:67]
VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],
VLYNQ_TXD[3:0]
0
011
VLYNQ + EMAC (MII) + MDIO
EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,
RXD[3:0]
MDIO: MDC, MDIO
If EMAC operation is desired, EMAC must be placed in reset before
programming PINMUX1.HOSTBK to select EMAC pins.
EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,
RXD[3:0]
0
100
EMAC (MII) + MDIO + GPIO (10)
MDIO: MDC, MDIO
GPIO: GP[66:57]
If EMAC operation is desired, EMAC must be placed in reset before
programming PINMUX1.HOSTBK to select EMAC pins.
0
(1)
101 to 111
Reserved
Reserved
If PCIEN = 1, the internal pullup/pulldown on all Host Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all Host
Block pins are enabled.
The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.
Based on the PCIEN configuration pin setting, the 27 pins in the Host Block defaults to either PCI or GPIO
function.
In addition, the VDD3P3V_PWDN.HOST field determines the power state of the Host Block pins. The
Host Block pins default to powered up. For more details on the VDD3P3V_PWDN.HOST field, see
Section 3.2, Power Considerations.
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PCI Data Block
This block of 3 pins consists of 3 PCI Address/Data pins—AD30, AD28, AD26. The PINMUX1.PCIEN
register field affects the pin functions in the PCI Data Block.
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,
and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
The 3 pins in the PCI Data Block are not muxed with any other peripherals. However, the
PINMUX1.PCIEN field controls the internal pullup/pulldown resistors on these pins. For PCI operation
(PCIEN = 1), the internal pullup/pulldown resistors are disabled. If the device does not support PCI
(PCIEN = 0), the internal pullup/pulldown resistors on these pins are enabled so that the user can leave
these pins unconnected on the board.
Table 3-24 shows the Host Block pin selection based on PINMUX1.PCIEN setting.
Table 3-24. PCI Data Block Pin Control
PINMUX1.PCIEN
BLOCK FUNCTION
0
No Connect Pins
(Default if PCIEN = 0)
No Connect Pins
Internal pullup/pulldown enabled. Leave these three pins unconnected on the board.
1
PCI
(Default if PCIEN = 1)
PCI: AD26, AD28, AD30
118
Device Configurations
RESULTING PIN FUNCTIONS
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3.7.3.5 GPIO Block Muxing
This block of 4 pins consists of PCI and GPIO muxed pins. The PINMUX1.PCIEN register field selects the
pin functions in the GPIO Block.
Table 3-25 summarizes the 4 pins in the GPIO Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-25. GPIO Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
(1)
PCI
NAME
FUNCTION
AD0/GP[0]
AD0
AD1/GP[1]
AD1
AD2/GP[2]
AD2
AD4/GP[3]
AD4
GPIO
SELECT
FUNCTION
SELECT
GP[0]
PCIEN = 1 (1)
GP[1]
PCIEN = 0 (1)
GP[2]
GP[3]
If PCIEN = 1, the internal pullup/pulldown on all GPIO Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all GPIO
Block pins are enabled.
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,
and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
Table 3-26 provides a different view of the GPIO Block pin muxing, showing the GPIO Block function
based on PINMUX1.PCIEN setting. The selection options are also shown pictorially in Figure 3-11.
Table 3-26. GPIO Block Function Selection
PINMUX1.PCIEN
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
0
PCI
(Default if PCIEN = 1)
PCI: AD0, AD1, AD2, AD4
1
GPIO (4)
(Default if PCIEN = 0)
GPIO: GP[3:0]
The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.
Based on the PCIEN configuration pin setting, the 4 pins in the GPIO Block defaults to either PCI or GPIO
function.
In addition, the VDD3P3V_PWDN.GPIO field determines the power state of the GPIO Block pins. The
GPIO Block pins default to powered up. For more details on the VDD3P3V_PWDN.GPIO field, see
Section 3.2, Power Considerations.
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3.7.3.6 UART0 Data Block Muxing
This block of 2 pins consists of UART0 Data and GPIO muxed pins. The PINMUX1.UR0DBK register field
select the pin functions in the UART0 Data Block.
Table 3-27 summarizes the 2 pins in the UART0 Data Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-27. UART0 Data Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
UART0
NAME
FUNCTION
URXD0/GP[85]
URXD0
UTXD0/GP[86]
UTXD0
GPIO
SELECT
FUNCTION
SELECT
GP[85]
UR0DBK = 1
UR0DBK = 0
GP[86]
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span
across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0
operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two
pins in the UART0 Flow Control Block are optional.
Table 3-28 provides a different view of the UART0 Data Block pin muxing, showing the UART0 Data Block
function based on PINMUX1.UR0DBK setting. The selection options are also shown pictorially in
Figure 3-11.
Table 3-28. UART0 Data Block Function Selection
PINMUX1.UR0DBK
BLOCK FUNCTION
0
GPIO (2) (default)
RESULTING PIN FUNCTIONS
GPIO: GP[86:85]
1
UART0 Data
UART0: URXD0, UTXD0
In addition, the VDD3P3V_PWDN.UR0DAT field determines the power state of the UART0 Data Block
pins. The UART0 Data Block pins default to powered down and not operational. To use these pins, user
must first program VDD3P3V_PWDN.UR0DAT = 0 to power up the pins. For more details on the
VDD3P3V_PWDN.UR0DAT field, see Section 3.2, Power Considerations.
The UART0 Data Block features internal pullup resistors, which matches the UART inactive polarity.
3.7.3.7 UART0 Flow Control Block
This block of 2 pins consists of UART0 Flow Control, PWM0, and GPIO muxed pins. The
PINMUX1.UR0FCBK register field selects the pin functions in the UART0 Flow Control Block.
Table 3-29 summarizes the 2 pins in the UART0 Flow Control Block, the multiplexed function on each pin,
and the PINMUX configurations to select the corresponding function.
Table 3-29. UART0 Flow Control Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
120
UART0
NAME
FUNCTION
UCTS0/
GP[87]
UCTS0
URTS0/
PWM0/
GP[88]
URTS0
PWM0
SELECT
GPIO
FUNCTION
SELECT
FUNCTION
SELECT
–
–
GP[87]
UR0FCBK = 00/10
PWM0
UR0FCBK = 10
GP[88]
UR0FCBK = 00
UR0FCBK = 01
Device Configurations
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As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span
across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0
operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two
pins in the UART0 Flow Control Block are optional.
Table 3-30 provides a different view of the UART0 Flow Control Block pin muxing, showing the UART0
Flow Control Block function based on PINMUX1.UR0FCBK setting. The selection options are also shown
pictorially in Figure 3-11.
Table 3-30. UART0 Flow Control Block Function Selection
PINMUX1.UR0FCBK
BLOCK FUNCTION
00
GPIO (2) (default)
RESULTING PIN FUNCTIONS
GPIO: GP[88:87]
01
UART0 Flow Control
UART0: UCTS0, URTS0
10
PWM0 + GPIO (1)
PWM0: PWM0
GPIO: GP[87]
11
Reserved
Reserved
In addition, the VDD3P3V_PWDN.UR0FC field determines the power state of the UART0 Flow Control
Block pins. The UART0 Flow Control Block pins default to powered down and not operational. To use
these pins, user must first program VDD3P3V_PWDN.UR0FC = 0 to power up the pins. For more details
on the VDD3P3V_PWDN.UR0FC field, see Section 3.2, Power Considerations.
The UART0 Flow Control Block features internal pullup resistors, which matches the UART inactive
polarity.
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3.7.3.8 Timer0 Block
This block of 2 pins consists of Timer0, McBSP0, McBSP1, and GPIO muxed pins. The
PINMUX1.TIM0BK register field selects the pin functions in the Timer0 Block.
Table 3-31 summarizes the 2 pins in the Timer0 Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-31. Timer0 Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
McBSP
Timer0
GPIO
NAME
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
CLKS1/
TINP0L/
GP[98]
CLKS1
TIM0BK = 10
TINP0L
TIM0BK = 01/11
GP[98]
CLKS0/
TOUT0L/
GP[97]
CLKS0
TIM0BK = 10/11
TOUT0L
TIM0BK = 01
GP[97]
SELECT
TIM0BK = 00
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span
across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the
Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the
Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an
external clock source to the McBSP0 internal sample rate generator.
Similarly, as discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP1
pins span across two Pin Mux Blocks: Serial Port Sub-Block1, and Timer0 Block. For proper McBSP1
operation, the Serial Port Sub-Block1 must be programmed to select McBSP1 function. The McBSP1
CLKS1 pin in the Timer0 Block is optional for McBSP1 operation. CLKS1 is only needed if you desire
using CLKS1 as an external clock source to the McBSP1 internal sample rate generator.
Table 3-32 provides a different view of the Timer0 Block pin muxing, showing the Timer0 Block function
based on PINMUX1.TIM0BK setting. The selection options are also shown pictorially in Figure 3-11.
Table 3-32. Timer0 Block Function Selection
PINMUX1.TIM0BK
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
00
GPIO (2) (default)
GPIO: GP[98:97]
01
Timer0
Timer0: TINP0L, TOUT0L
10
McBSP0 External Clock Source,
McBSP1 External Clock Source
McBSP0: CLKS0
McBSP1: CLKS1
11
McBSP0 External Clock Source,
Timer0 Input
McBSP0: CLKS0
Timer0: TINP0L
In addition, the VDD3P3V_PWDN.TIMER0 field determines the power state of the Timer0 Block pins. The
Timer0 Block pins default to powered down and not operational. To use these pins, user must first
program VDD3P3V_PWDN.TIMER0 = 0 to power up the pins. For more details on the
VDD3P3V_PWDN.TIMER0 field, see Section 3.2, Power Considerations.
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3.7.3.9 Timer1 Block
This block of 2 pins consists of Timer1, HECC, UART1 Data, and GPIO muxed pins. The
PINMUX1.TIM1BK register field selects the pin functions in the Timer1 Block.
Table 3-33 summarizes the 2 pins in the Timer1 Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-33. Timer1 Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
NAME
HECC
FUNCTION
HECC_RX/
TINP1L/
URXD1/
GP[56]
HECC_RX
HECC_TX/
TOUT1L/
UTXD1/
GP[55]
HECC_TX
TIMER1
SELECT
FUNCTION
UART1
SELECT
TINP1L
TIM1BK = 11
FUNCTION
GPIO
SELECT
URXD1
TIM1BK = 01
TOUT1L
FUNCTION
SELECT
GP[56]
TIM1BK = 10
UTXD1
TIM1BK = 00
GP[55]
Unlike UART0, UART1 only supports data pins but not flow control pins.
Table 3-34 provides a different view of the Timer1 Block pin muxing, showing the Timer1 Block function
based on PINMUX1.TIM1BK setting. The selection options are also shown pictorially in Figure 3-11.
Table 3-34. Timer1 Block Function Selection
PINMUX1.TIM1BK
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
00
GPIO (2) (default)
GPIO: GP[56:55]
01
Timer1
Timer1: TINP1L, TOUT1L
10
UART1 Data
UART1: URXD1, UTXD1
11
HECC
HECC: HECC_RX, HECC_TX
In addition, the VDD3P3V_PWDN.TIMER1 field determines the power state of the Timer1 Block pins. The
Timer1 Block pins default to powered down and not operational. To use these pins, user must first
program VDD3P3V_PWDN.TIMER1 = 0 to power up the pins. For more details on the
VDD3P3V_PWDN.TIMER1 field, see Section 3.2, Power Considerations.
The Timer1 Block features internal pull up resistors, which matches the UART and HECC inactive polarity.
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Serial Port Block
This block of 12 pins consists of McASP0, McBSP0, McBSP1, and GPIO muxed pins. The following
register fields select the pin functions in the Serial Port Block:
• PINMUX1.SPBK0
• PINMUX1.SPBK1
The Serial Port Block is further subdivided into these sub-blocks:
• Serial Port Sub-Block 0: McBSP0, part of McASP0, GPIO.
• Serial Port Sub-Block 1: McBSP1, part of McASP0, GPIO.
Table 3-35 summarizes the 12 pins in the Serial Port Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-35. Serial Port Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL NAME
McASP0
FUNCTION
McBSP0/1
SELECT
FUNCTION
SELECT
GPIO
FUNCTION
SELECT
Serial Port Sub-block 0
ACLKR0/CLKX0/GP[99]
AFSR0/DR0/GP[100]
AHCLKR0/CLKR0/GP[101]
ACLKR0
CLKX0
GP[99]
AFSR0
DR0
GP[100]
AHCLKR0
SPBK0 = 10
CLKR0
FSR0
SPBK0 = 01
GP[101]
AXR0[3]/FSR0/GP[102]
AXR0[3]
GP[102]
AXR0[2]/FSX0/GP[103]
AXR0[2]
FSX0
GP[103]
AXR0[1]/DX0/GP[104]
AXR0[1]
DX0
GP[104]
SPBK0 = 00
Serial Port Sub-block 1
AXR0[0]/FSR1/GP[105]
ACLKX0/CLKX1/GP[106]
AFSX0/DX1/GP[107]
AHCLKX0/CLKR1/GP[108]
AMUTEIN0/FSX1/GP[109]
AMUTE0/DR1/GP[110]
AXR0[0]
SPBK1 = 10/11
FSR1
SPBK1 = 01
GP[105]
GP[106]
ACLKX0
SPBK1 = 10
CLKX1
SPBK1 =
01/11
AFSX0
SPBK1 = 10
DX1
SPBK1 =
01/11
GP[107]
AHCLKX0
SPBK1 = 10/11
CLKR1
SPBK1 = 01
GP[108]
AMUTEIN0
SPBK1 = 10
FSX1
SPBK1 =
01/11
GP[109]
AMUTE0
SPBK1 = 10/11
DR1
SPBK1 = 01
GP[110]
SPBK1 = 00
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span
across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the
Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the
Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an
external clock source to the McBSP0 internal sample rate generator.
Similarly, as discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP1
pins span across two Pin Mux Blocks: Serial Port Sub-Block1, and Timer0 Block. For proper McBSP1
operation, the Serial Port Sub-Block1 must be programmed to select McBSP1 function. The McBSP1
CLKS1 pin in the Timer0 Block is optional for McBSP1 operation. CLKS1 is only needed if you desire
using CLKS1 as an external clock source to the McBSP1 internal sample rate generator.
Table 3-36 and Table 3-37 provide a different view of the Serial Port Block. Table 3-36 shows the Serial
Port Sub-Block 0 function based on PINMUX1.SPBK0 setting. Table 3-37 shows the Serial Port Sub-Block
1 function based on PINMUX1.SPBK1 setting. These selection options are also shown pictorially in
Figure 3-11.
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Table 3-36. Serial Port Sub-Block 0 Function Selection
PINMUX1.SPBK0
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
00
GPIO (6) (default)
GPIO: GP[104:99]
01
McBSP0
McBSP0: CLKX0, FSX0, DX0, CLKR0, FSR0, DR0
10
McASP0 Receive, 3 Serializers
McASP0: ACLKR0, AFSR0, AHCLKR0, AXR0[3],
AXR0[2], AXR0[1]
11
Reserved
Reserved
Table 3-37. Serial Port Sub-Block 1 Function Selection
(1)
PINMUX1.SPBK1
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
00
GPIO (6) (default)
GPIO: GP[110:105]
01
McBSP1
McBSP1: CLKX1, FSX1, DX1, CLKR1, FSR1, DR1
10
McASP0 Transmit with 1 Serializer and
Mute Control
McASP0: AXR0[0], ACLKX0, AFSX0, AHCLKX0,
AMUTEIN0 (1), AMUTE0
11
McBSP1 Transmit, McASP0 SPDIF
McBSP1: CLKX1, FSX1, DX1
McASP0: AXR0[0], AHCLKX0, AMUTE0
The input from the AMUTEIN0/FSX1/GP[109] pin is connected to both the McASP0 and GPIO.
In addition, the VDD3P3V_PWDN.SP field determines the power state of the Serial Port Block pins. The
Serial Port Block pins default to powered down and not operational. To use these pins, user must first
program VDD3P3V_PWDN.SP = 0 to power up the pins. For more details on the VDD3P3V_PWDN.SP
field, see Section 3.2, Power Considerations.
To facilitate McASP0 operation, the input from the AMUTEIN0/FSX1/GP[109] pin is connected to both the
McASP0 and the GPIO module. Therefore when an external mute event occurs, in addition to notifying the
McASP0, it can also cause an interrupt through the GPIO module.
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3.7.3.11 PWM1 Block
This block of 1 pin consists of PWM1 and GPIO muxed pins (GP[4]/PWM1). The PINMUX1.PWM1BK
register field selects the pin function in the PWM1 Block.
Table 3-38 summarizes the 1 pin in the PWM1 Block, its multiplexed function, and the PINMUX
configurations to select the corresponding function.
Table 3-38. PWM1 Block Muxed Pin Selection
MULTIPLEXED FUNCTIONS
SIGNAL
PWM1
GPIO
NAME
FUNCTION
SELECT
FUNCTION
SELECT
GP[4]/PWM1
PWM1
PWM1BK = 1
GP[4]
PWM1BK = 0
Table 3-39 provides a different view of the PWM1 Block pin muxing, showing the PWM1 Block function
based on PINMUX1.PWM1BK setting. The selection options are also shown pictorially in Figure 3-11.
Table 3-39. PWM1 Block Function Selection
PINMUX1.PWM1BK
BLOCK FUNCTION
0
GPIO (1) (default)
1
PWM1
RESULTING PIN FUNCTIONS
GPIO: GP[4]
PWM1: PWM1
In addition, the VDD3P3V_PWDN.PWM1 field determines the power state of the PWM1 Block pin. The
PWM1 Block pin defaults to powered down and not operational. To use this pin, user must first program
VDD3P3V_PWDN.PWM1 = 0 to power up the pin. For more details on the VDD3P3V_PWDN.PWM1 field,
see Section 3.2, Power Considerations.
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3.7.3.12 CLKOUT Block
This block of 1 pin consists of CLKOUT, PWM2, and GPIO muxed pin (CLKOUT0/PWM2/GP[84]). The
PINMUX1.CKOBK register field selects the pin function in the CLKOUT Block.
Table 3-40 summarizes the 1 pin in the CLKOUT Block, its multiplexed function, and the PINMUX
configurations to select the corresponding function.
Table 3-40. CLKOUT Block Multiplexed Pin Selection
MULTIPLEXED FUNCTIONS
SIGNAL
CLKOUT0
PWM2
GPIO
NAME
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
CLKOUT0/
PWM2/
GP[84]
CLKOUT0
CKOBK = 01
PWM2
CKOBK = 10
GP[84]
CKOBK = 00
Table 3-41 provides a different view of the CLKOUT Block pin muxing, showing the CLKOUT Block
function based on PINMUX1.CKOBK setting. The selection options are also shown pictorially in
Figure 3-11.
Table 3-41. CLKOUT Block Function Selection
PINMUX1.CKOBK
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
00
GPIO (1)
GPIO: GP[84]
01
CLKOUT (default)
Device Clock-Out: CLKOUT0
10
PWM2
PWM2: PWM2
11
Reserved
Reserved
This block defaults to CLKOUT0 pin function.
In addition, the VDD3P3V_PWDN.CLKOUT field determines the power state of the CLKOUT Block pin.
The CLKOUT Block pin defaults to powered up. For more details on the VDD3P3V_PWDN.CLKOUT field,
see Section 3.2, Power Considerations.
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3.7.3.13 EMIFA/VPSS Block Muxing
This block of 61 pins consists of VPSS, EMIFA, PCI, and GPIO muxed pins. The following register fields
affect the pin functions in the EMIFA/VPSS Block:
• All PINMUX0 register fields: AEM, VENCSEL, CS5SEL, CS4SEL, CS3SEL, RGBSEL, VPBECKEN,
AEAW, CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI76SEL, CI54SEL, CI32SEL, CI10SEL
• PINMUX1.PCIEN
The EMIFA/VPSS Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to
accommodate a wide variety of applications:
• Sub-Block 0: multiplexed between VPFE, EMIFA data/address/control pins, PCI, and GPIO.
• Sub-Block 1: multiplexed between VPBE, EMIFA data/address/control pins, and GPIO.
• Sub-Block 2: no multiplexing. EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, EM_WE.
• Sub-Block 3: multiplexed between EMIFA address pins EM_A[12:6], PCI, and GPIO.
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,
and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
The EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register determine the power state
of the EMIFA/VPSS Block pins. The EMIFA/VPSS Block pins default to powered up. For more details on
the EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register, see Section 3.2, Power
Considerations.
To understand pin multiplexing in the EMIFA/VPSS Block, the user should start with Section 3.7.3.13.1,
EMIFA/VPSS Block Pin Selection Procedure, which outlines the procedures to select pin functions of this
block. Section 3.7.3.13.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, provides a pin-by-pin
multiplexing summary for the EMIFA/VPSS Block. For more information on the PINMUX0 and PINMUX1
registers, see Section 3.7.2, Pin Muxing Selection After Device Reset.
3.7.3.13.1 EMIFA/VPSS Block Pin Selection Procedure
Follow the steps below to perform pin selection for the EMIFA/VPSS Block and its sub-blocks.
1. Major Configuration Options: start with Table 3-42, EMIFA/VPSS Block Major Configuration Choices.
Based on the peripheral needs, the user should select from the major configuration options in this
block: Major Config Options A, B, C, D, E, F, G.
2. Sub-Block 2 and Sub-Block 3 Selection: After selecting the major configuration option from
Table 3-42, EMIFA/VPSS Block Major Configuration Choices, the pin selection for Sub-Block 2 and
Sub-Block 3 is complete.
3. Sub-Block 0 Selection: Use Table 3-43 through Table 3-49, EMIFA/VPSS Sub-Block 0 Configuration
Choices, to refine Sub-Block 0 pin selections.
a. Go to the table with the Major Configuration Option chosen in Step 1.
b. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
c. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by
selecting the settings of PINMUX0 fields CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI10SEL,
CI32SEL, CI54SEL, and CI76SEL.
d. The Selection Fields columns show the settings needed to program the PINMUX0 register and
PINMUX1.PCIEN field.
4. Sub-Block 1 Selection: Use Table 3-50 through Table 3-54, EMIFA/VPSS Sub-Block 1 Configuration
Choices, to refine Sub-Block 1 pin selection.
a. Go to the table with the Major Configuration Option chosen in Step 1.
b. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
c. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by
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selecting the settings of PINMUX0 fields VENCSEL, RGBSEL, CS3SEL, CS4SEL, and CS5SEL.
d. The Selection Fields columns shows the settings needed to program the PINMUX0 register.
After following the procedure in this section to determine pin functions for the EMIFA/VPSS Block, the
user should refer to Section 3.7.3.13.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, for
pin-multiplexing information on a pin-by-pin basis.
3.7.3.13.2 EMIFA/VPSS Block Major Configuration Choices
Table 3-42 shows the major configuration choices in the EMIFA/VPSS Block. For instructions on how to
use the EMIFA/VPSS Block Major Configuration Choices table for the EMIFA/VPSS Block and
Sub-Blocks, see Section 3.7.3.13.1.
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Table 3-42. EMIFA/VPSS Block Major Configuration Choices
MAJOR
CONFIG.
OPTION
PINMUX SELECTION FIELDS (1)
PCIEN
AEM
VENCSEL
RESULTING PERIPHERALS/PINS
CCDCSEL
PCI
(2)
VPBE AND # GP PINS
(FROM GP[33:5])
EMIFA
VENCSEL
A
B
C
D
E
F
G
(1)
(2)
(3)
130
0
0
0
0
0
1
1
000
001 (3)
011 (3)
100
101
000
101
00, 01, 10
00, 01
00, 10
00, 01, 10
00, 01
00, 01, 10
00, 01
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
-
-
-
-
-
PCI
PCI
-
8-bit EMIFA (ASYNC)
Pinout Mode 1 with address
pins to support 32KB to 16MB
per CS.
8-bit EMIFA (ASYNC)
Pinout Mode 3 with address
pins to support up to 32KB per
CS.
8-bit EMIFA (NAND)
Pinout Mode 4
00
01
8-bit VENC
8-to-29-GP pins
10
CCDCSEL
VPFE & # GP Pins
0
No CCDC
21 GP pins
16-to-24-bit VENC
0-to-12 GP pins
1
8-to-16-bit CCDC
0-to-12 GP pins
00
No VENC
9-to-13 GP pins
0
No CCDC
11-to-19 GP pins
01 (3)
8-bit VENC (3)
0-to-4 GP pins
1 (3)
00
10 (3)
No VENC
17-to-21 GP pins
16-bit VENC (3)
0-to-4 GP pins
00
No VENC
22-to-26 GP pins
01
8-bit VENC
12-to-17 GP pins
10
0
1 (3)
8-to-16-bit CCDC (3)
0-to-10 GP pins
No CCDC
12 GP pins
8-bit CCDC (3)
0-to-3 GP pins
0
No CCDC
13 GP pins
16-to-18-bit VENC
2-to-9 GP pins
1
8-bit CCDC
0-to-4 GP pins
00
No VENC
14-to-18 GP pins
0
No CCDC
21 GP pins
01
8- bit VENC
4-to-9 GP pins
1
8-to-16-bit CCDC
0-to-12 GP pins
00
No VENC
29 GP pins
0
8-bit VENC
8-to-29 GP pins
No CCDC
13 GP pins
01
10
16-to-24-bit VENC
0-to-12 GP pins
1
8-bit CCDC
0-to-4 GP pins
00
No VENC
14-to-18 GP pins
0
No CCDC
13 GP pins
01
8-bit VENC
4-to-9 GP pins
1
8-bit CCDC
0-to-4 GP pins
8-bit EMIFA (NAND)
Pinout Mode 5
-
VPBE & # GP Pins
No VENC
29 GP pins
VPFE AND # GP PINS
(FROM GP[54:34])
8-bit EMIFA (NAND)
Pinout Mode 5
For additional pin mux details for each Sub-Block, see Table 3-43 through Table 3-49, EMIFA/VPSS Sub-Block 0 Configuration Choices, and Table 3-50 through Table 3-54,
EMIFA/VPSS Sub-Block 1 Configuration Choices.
PCI pins span across multiple Pin Mux Blocks (Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks). This table only refers to the PCI pins in the EMIFA/VPSS Block.
If PINMUX0.AEM = 001 or 011, it is not possible to get LCD_FIELD pin for VPBE, nor C_WE pin for VPFE.
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As shown in Table 3-42, the major configuration choices of the EMIFA/VPSS Block are determined by the
following PINMUX register fields:
• PINMUX1 register field PCIEN
• PINMUX0 register fields AEM, VENCSEL, CCDCSEL
Based on the peripheral needs, select from the major configuration options in this block: Major
Configuration Options A, B, C, D, E, F, and G.
The following is an example on how to read Table 3-42. For example, the "PINMUX Selection Fields"
columns indicate that Major Configuration Choice B is selected through setting PINMUX1.PCIEN = 0,
PINMUX0.AEM = 1, VENCSEL = 0 or 1 (based on the system's VPBE requirement), and CCDCSEL = 0
or 1 (based on the system's VPFE requirement). The "Resulting Peripherals/Pins" columns indicate that
Major Configuration Option B can support the following combination of pin functions:
• No PCI pins
• Pins for 8-bit EMIFA (Async or NAND) function. The number of address pins supported provide
32KByte to 16MByte address reach per EMIFA Chip Select (CS) space.
• Pins for up to 8-bit VPBE. If 8-bit VPBE (VENCSEL = 1) is selected, the user may have 0 to 4 GPIO
pins. Exact detail on number of GPIO pins and VPBE control pins is further determined by other
PINMUX0 settings discussed in the EMIFA/VPSS Sub-Block 1 Configuration Choices.
• Pins for up to 16-bit VPFE. If 8 to 16-bit VPFE (CCDCSEL = 1) is selected, the user may have 0 to 10
GPIO pins. Exact detail on number of GPIO pins and VPFE control pins is furthered determined by
other PINMUX0 settings discussed in the EMIFA/VPSS Sub-Block 0 Configuration Choices.
After using Table 3-42 to select the Major Configuration Option for the EMIFA/VPSS Block, proceed to
select the detailed pin choices in the EMIFA/VPSS Sub-Blocks.
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3.7.3.13.3 EMIFA/VPSS Sub-Block 0 Configuration Choices
Table 3-43 through Table 3-49 show the configuration choices in the EMIFA/VPSS Sub-Block 0. For
instructions on how to use the different configuration choices tables for the EMIFA/VPSS Block and
Sub-Blocks, see Section 3.7.3.13.1. Note: Italics in these tables indicate mandatory settings for a given
Minor Configuration option.
Before using Table 3-43 through Table 3-49 to configure the details of the EMIFA/VPSS Sub-Block 0, the
user should first select a Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.13.2).
After determining the Major Configuration Option (A, B, C, D, E, F, or G), the user can now use Table 3-43
through Table 3-49 to refine Sub-Block 0 pin selections:
1. Go to the table with the Major Configuration Option chosen from Table 3-42.
2. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
3. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by selecting
the settings of PINMUX0 fields CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI10SEL, CI32SEL,
CI54SEL, and CI76SEL.
4. The PINMUX Selection Fields columns show the settings needed to program the PINMUX0 register
and PINMUX1.PCIEN field.
Table 3-43. EMIFA/VPSS Sub-Block 0 Configuration Choice A (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
A1
PINMUX SELECTION FIELDS
PCIEN
0
AEM
000
AEAW
000
RESULTING PERIPHERALS/PINS
OTHERS
PCI
EMIFA
VPFE
Cfg Summary
No PCI
No EMIFA
No CCDC
CCDCSEL = 0
HVDSEL = 0
0 = GP[53:52]
CWENSEL = 0
0 = GP[35]
CFLDSEL = 0
-
-
-
0
000
000
0 = GP[45:44]
CI32SEL = 0
0 = GP[47:46]
CI54SEL = 0
0 = GP[49:48]
0 = GP[51:50]
No PCI
132
No EMIFA
8-to-16-bit
CCDC
0-to-12 GP
pins
CCDCSEL = 1
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0,1
1 = C_WE
0 = GP[35]
CFLDSEL = 0,1
(1)
0 = GP[34]
CI10SEL = 0
Cfg Summary
A2
21 GP pins
0 = GP[54,
43:36]
CI76SEL = 0
A
# GPIO PINS
1 = C_FIELD
0 = GP[34]
CI10SEL = 0,1
1 = CI[1:0]
0 = GP[45:44]
CI31SEL = 0,1
1 = CI[3:2]
0 = GP[47:46]
CI54SEL = 0,1
1 = CI[5:4]
0 = GP[49:48]
CI76SEL = 0,1
1 = CI[7:6]
0 = GP[51:50]
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
Device Configurations
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Table 3-44. EMIFA/VPSS Sub-Block 0 Configuration Choice B (1)
MAJOR
CONFIG
OPTION
B
B
B
(1)
MINOR
CONFIG
OPTION
B1
B2
B3
PINMUX SELECTION FIELDS
PCIEN
0
0
0
AEM
001
001
001
AEAW
100
000
001
RESULTING PERIPHERALS/PINS
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
Config Summary
No PCI
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[21:0]
No CCDC
11 GP pins
CCDCSEL = 0
-
0 = GP[54,
43:36]
HVDSEL = 0
-
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
CFLDSEL = 0
0 = EM_A21
-
CI10SEL = 0
0=
EM_A[19:20]
-
-
-
CI32SEL = 0
0=
EM_A[17:18]
-
CI54SEL = 0
0=
EM_A[15:16]
-
CI76SEL = 0
0=
EM_A[13:14]
-
Config Summary
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[12:0]
only
No PCI
8-to-16-bit
CCDC
0-to-10 GP
pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
-
CFLDSEL = 0,1
0 = EM_A21
(not used)
1 = C_FIELD
-
CI10SEL = 0,1
-
1 = CI[1:0]
0 = GP[45:44]
CI32SEL = 0,1
-
1 = CI[3:2]
0 = GP[47:46]
CI54SEL = 0,1
-
1 = CI[5:4]
0 = GP[49:48]
CI76SEL = 0,1
-
1 = CI[7:6]
0 = GP[51:50]
Config Summary
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[14:0]
only
-
No PCI
8-to-14-bit
CCDC
0-to-8 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
-
CFLDSEL = 0,1
0 = EM_A21
(not used)
1 = C_FIELD
-
CI10SEL = 0,1
-
1 = CI[1:0]
0 = GP[45:44]
CI32SEL = 0,1
-
1 = CI[3:2]
0 = GP[47:46]
CI54SEL = 0,1
-
1 = CI[5:4]
0 = GP[49:48]
CI76SEL = 0
0=
EM_A[13:14]
-
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
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Table 3-44. EMIFA/VPSS Sub-Block 0 Configuration Choice B (continued)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
PINMUX SELECTION FIELDS
PCIEN
AEM
AEAW
OTHERS
Config Summary
B
B4
0
001
010
B5
0
001
Device Configurations
EMIFA
VPFE
# GPIO PINS
No PCI
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[16:0]
only
8-to-12-bit
CCDC
0-to-6 GP pins
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
-
CFLDSEL = 0,1
0 = EM_A21
(not used)
1 = C_FIELD
-
-
-
1 = CI[1:0]
0 = GP[45:44]
CI32SEL = 0,1
-
1 = CI[3:2]
0 = GP[47:46]
CI54SEL = 0
0=
EM_A[15:16]
-
-
CI76SEL = 0
0=
EM_A[13:14]
-
-
Config Summary
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[18:0]
only
No PCI
8-to-10-bit
CCDC
0-to-4 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
-
CFLDSEL = 0,1
0 = EM_A21
(not used)
1 = C_FIELD
-
-
1 = CI[1:0]
0 = GP[45:44]
CI32SEL = 0
0=
EM_A[17:18]
-
-
CI54SEL = 0
0=
EM_A[15:16]
-
-
CI76SEL = 0
0=
EM_A[13:14]
-
-
011
CI10SEL = 0,1
134
PCI
CCDCSEL = 1
CI10SEL = 0,1
B
RESULTING PERIPHERALS/PINS
-
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 3-44. EMIFA/VPSS Sub-Block 0 Configuration Choice B (continued)
MAJOR
CONFIG
OPTION
B
MINOR
CONFIG
OPTION
B6
PINMUX SELECTION FIELDS
PCIEN
0
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AEM
001
AEAW
100
RESULTING PERIPHERALS/PINS
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
Config Summary
No PCI
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[21:0]
8-bit CCDC
0-to-2 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
-
CFLDSEL = 0,1
0 = EM_A21
1 = C_FIELD
-
CI10SEL = 0
0=
EM_A[19:20]
-
-
CI32SEL = 0
0=
EM_A[17:18]
-
-
CI54SEL = 0
0=
EM_A[15:16]
-
-
CI76SEL = 0
0=
EM_A[13:14]
-
-
-
Device Configurations
135
TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 3-45. EMIFA/VPSS Sub-Block 0 Configuration Choice C (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
C1
PINMUX SELECTION FIELDS
PCIEN
0
AEM
011
AEAW
000
RESULTING PERIPHERALS/PINS
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
Config Summary
No PCI
8-bit EMIFA
(Async) Pinout
mode 3
No CCDC
12 GP pins
CCDCSEL = 0
-
0 = GP[54,
43:36]
HVDSEL = 0
-
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
CFLDSEL = 0
C
C2
(1)
136
0
011
000
-
-
-
0 = GP[34]
CI10SEL = 0
0 = EM_D[6:7]
-
CI32SEL = 0
0 = EM_D[4:5]
-
CI54SEL = 0
0 = EM_D[2:3]
-
CI76SEL = 0
0 = EM_D[0:1]
-
Config Summary
8-bit EMIFA
(Async) Pinout
mode 3
No PCI
8-bit CCDC
0-to-3 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0
0 = EM_R/W
-
-
CFLDSEL = 0
-
1 = C_FIELD
0 = GP[34]
CI10SEL = 0
0 = EM_D[6:7]
-
-
CI31SEL = 0
0 = EM_D[4:5]
-
-
CI54SEL = 0
0 = EM_D[2:3]
-
-
CI76SEL = 0
0 = EM_D[0:1]
-
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
Device Configurations
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Table 3-46. EMIFA/VPSS Sub-Block 0 Configuration Choice D (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
D1
PINMUX SELECTION FIELDS
PCIEN
0
AEM
100
AEAW
000
RESULTING PERIPHERALS/PINS
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
Cfg Summary
No PCI
8-bit EMIFA
(NAND) Pinout
mode 4
No CCDC
13 GP pins
CCDCSEL = 0
-
0 = GP[54,
43:36]
HVDSEL = 0
-
0 = GP[53:52]
CWENSEL = 0
-
0 = GP[35]
CFLDSEL = 0
D
(1)
0
100
000
-
-
0 = GP[34]
0 = EM_D[6:7]
-
CI32SEL = 0
0 = EM_D[4:5]
-
CI54SEL = 0
0 = EM_D[2:3]
-
CI76SEL = 0
0 = EM_D[0:1]
-
Cfg Summary
D2
-
CI10SEL = 0
No PCI
8-bit EMIFA
(NAND) Pinout
mode 4
8-bit CCDC
0-to-4 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0,1
-
1 = C_WE
0 = GP[35]
CFLDSEL = 0,1
-
1 = C_FIELD
0 = GP[34]
CI10SEL = 0
0 = EM_D[6:7]
-
-
CI31SEL = 0
0 = EM_D[4:5]
-
-
CI54SEL = 0
0 = EM_D[2:3]
-
-
CI76SEL = 0
0 = EM_D[0:1]
-
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
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TMS320DM6437
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Table 3-47. EMIFA/VPSS Sub-Block 0 Configuration Choice E (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
E1
PINMUX SELECTION FIELDS
PCIEN
0
AEM
101
AEA
W
000
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
Cfg Summary
No PCI
8-bit EMIFA
(NAND) Pinout
mode 5
No CCDC
21 GP pins
CCDCSEL = 0
0 = GP[54, 43:36]
HVDSEL = 0
0 = GP[53:52]
CWENSEL = 0
0 = GP[35]
CFLDSEL = 0
CI10SEL = 0
-
-
E2
0
101
000
0 = GP[34]
0 = GP[45:44]
CI32SEL= 0
0 = GP[47:46]
CI54SEL = 0
0 = GP[49:48]
Cfg Summary
0 = GP[51:50]
No PCI
8-bit EMIFA
(NAND) Pinout
mode 5
8-to-16-bit
CCDC
0-to-12 GP pins
CCDCSEL = 1
1 = PCLK, YI[7:0] -
HVDSEL = 0,1
1= VD, HD
0 = GP[53:52]
CWENSEL = 0,1
1 = C_WE
0 = GP[35]
1 = C_FIELD
0 = GP[34]
1 = CI[1:0]
0 = GP[45:44]
CI31SEL = 0,1
1 = CI[3:2]
0 = GP[47:46]
CI54SEL = 0,1
1 = CI[5:4]
0 = GP[49:48]
CI76SEL = 0,1
1 = CI[7:6]
0 = GP[51:50]
CFLDSEL = 0,1
CI10SEL = 0,1
138
-
CI76SEL = 0
E
(1)
RESULTING PERIPHERALS/PINS
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
Device Configurations
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Table 3-48. EMIFA/VPSS Sub-Block 0 Configuration Choice F (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
F1
PINMUX SELECTION FIELDS
PCIEN
1
AEM
000
AEAW
000
F
OTHERS
PCI
EMIFA
VPFE
Cfg Summary
PCI
No EMIFA
No CCDC
1
000
000
# GPIO PINS
13 GP pins
CCDCSEL = 0
-
0 = GP[54,
43:36]
HVDSEL = 0
-
0 = GP[53:52]
CWENSEL = 0
-
0 = GP[35]
CFLDSEL = 0
-
0 = GP[34]
CI10SEL = 0
0 = PREQ,
PINTA
CI32SEL = 0
0 = AD31,
PRST
-
CI54SEL =0
0 = AD29,
PGNT
-
CI76SEL = 0
0 = AD25,
AD27
-
Cfg Summary
F2
(1)
RESULTING PERIPHERALS/PINS
PCI
-
-
No EMIFA
-
8-bit CCDC
0-to-4 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0,1
-
1 = C_WE
0 = GP[35]
CFLDSEL = 0,1
-
1 = C_FIELD
0 = GP[34]
CI10SEL = 0
0 = PREQ,
PINTA
-
-
CI31SEL = 0
0 = AD31,
PRST
-
-
CI54SEL = 0
0 = AD29,
PGNT
-
-
CI76SEL = 0
0 = AD25,
AD27
-
-
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
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Device Configurations
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TMS320DM6437
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 3-49. EMIFA/VPSS Sub-Block 0 Configuration Choice G (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
G1
PINMUX SELECTION FIELDS
PCIEN
1
AEM
101
AEAW
000
RESULTING PERIPHERALS/PINS
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
Cfg Summary
PCI
8-bit EMIFA
(NAND)
Pinout mode
5
No CCDC
13 GP pins
CCDCSEL = 0
-
0 = GP[54,
43:36]
HVDSEL = 0
-
0 = GP[53:52]
CWENSEL = 0
-
0 = GP[35]
CFLDSEL = 0
-
0 = GP[34]
CI10SEL = 0
0 = PREQ,
PINTA
CI32SEL = 0
0 = AD31,
PRST
-
CI54SEL = 0
0 = AD29,
PGNT
-
CI76SEL = 0
0 = AD25,
AD27
-
G
Cfg Summary
G2
(1)
1
101
000
PCI
-
-
8-bit EMIFA
(NAND)
Pinout mode
5
-
8-bit CCDC
0-to-4 GP pins
CCDCSEL = 1
-
1 = PCLK,
YI[7:0]
-
HVDSEL = 0,1
-
1 = VD, HD
0 = GP[53:52]
CWENSEL = 0,1
-
1 = C_WE
0 = GP[35]
CFLDSEL = 0,1
-
1 = C_FIELD
0 = GP[34]
CI10SEL = 0
0 = PREQ,
PINTA
-
-
CI31SEL = 0
0 = AD31,
PRST
-
-
CI54SEL = 0
0 = AD29,
PGNT
-
-
CI76SEL = 0
0 = AD25,
AD27
-
-
-
Italics indicate mandatory settings for a given Minor Configuration option.
As shown in Table 3-43 through Table 3-49, the configuration choices of the EMIFA/VPSS Sub-Block 0
are determined by the following PINMUX register fields:
• PINMUX1 register field PCIEN
• PINMUX0 register fields AEM, AEAW, CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI10SEL,
CI32SEL, CI54SEL, and CI76SEL.
140
Device Configurations
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The following is an example of how to read Table 3-43 through Table 3-49 using Sub-Block 0 Minor
Configuration B6 as an example:
• The PINMUX Selection Fields columns indicate that Sub-Block 0 Minor Configuration Option B6 is
selected through setting PINMUX1.PCIEN = 0, PINMUX0.AEM = 1, PINMUX0.AEAW = 4, CCDCSEL
= 1, HVDSEL = 0 or 1 (based on the system’s need for VPFE control signals VD and HD), CWENSEL
= 0 (mandatory setting), CFLDSEL = 0 or 1 (based on the system’s need for VPFE control signal
C_FIELD), CI10SEL = 0 (mandatory), CI32SEL = 0 (mandatory), CI54SEL = 0 (mandatory), and
CI76SEL = 0 (mandatory).
• The Resulting Peripherals/Pins columns show the functional pins resulting from the PINMUX setting.
For example, PINMUX0.CCDCSEL = 1 gives the user the PCLK and YI[7:0] pins for the VPFE.
PINMUX0.HVDSEL = 1 gives the user VD and HD pins for VPFE, while HVDSEL = 0 gives the user 2
GP pins.
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Device Configurations
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3.7.3.13.4 EMIFA/VPSS Sub-Block 1 Configuration Choices
Table 3-50 through Table 3-54 show the configuration choices in the EMIFA/VPSS Sub-Block 1. For
instructions on how to use the different configuration choices tables for the EMIFA/VPSS Block and
Sub-Blocks, see Section 3.7.3.13.1, EMIFA/VPSS Block Pin Selection Procedure.
Before using Table 3-50 through Table 3-54 to configure the details of the EMIFA/VPSS Sub-Block 1, the
user should first select the Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.13.2,
EMIFA/VPSS Block Major Configuration Choices). After determining the Major Configuration Option (A, B,
C, D, E, F, or G), the user can now use Table 3-50 through Table 3-54 to refine the Sub-Block 1 pin
selections.
1. Go to the table with the Major Configuration Option chosen from Table 3-42.
2. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
3. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by selecting
the settings of PINMUX0 fields VENCSEL, RGBSEL, CS3SEL, CS4SEL, CS5SEL, and VPBECKEN.
4. The PINMUX Selection Fields columns give the user the settings needed to program the PINMUX0
register.
142
Device Configurations
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Table 3-50. EMIFA/VPSS Sub-Block 1 Configuration Choices A and F (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
A1, F1
PINMUX SELECTION FIELDS
AEM
000
RESULTING PERIPHERALS/PINS
OTHERS
EMIFA
VPBE
GPIO
Cfg Summary
No EMIFA
No VENC
0 = GP[31, 29:14]
RGBSEL = 0
0 = GP[12:5]
CS3SEL = 0
CS4SEL = 0
-
0 = GP[13]
-
0 = GP[32]
CS5SEL = 0
0 = GP[33]
VPBECKEN = 0
Cfg Summary
A2, F2
0 = GP[30]
No EMIFA
1 = GP[21:14]
RGBSEL = 0,1
0 = none
1 = LCD_FIELD
0 = GP[12:5]
1 = GP[12],
GP[10:5]
-
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,2
2 = VSYNC
0 = GP[32]
CS5SEL = 0,2
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
1 = VPBECLK
0 = GP[30]
Cfg Summary
No EMIFA
(1)
16-to-24-bit VENC
0 to 12 GP pins
2 = VCLK,
YOUT[7:0],
COUT[7:0]
-
0 = none
1 = LCD_FIELD
2 = R2, B2
3 = R2, B2,
LCD_FIELD
4 = G0, B0, R0, G1,
B1, R1, R2, B2
0 = GP[12:5]
1 = GP[12],
GP[10:5]
2 = GP[12:7]
3 = GP[12],
GP[10:7]
4 = No GP
CS3SEL = 0,2
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,2
2 = VSYNC
0 = GP[32]
CS5SEL = 0,2
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
1 = VPBECLK
0 = GP[30]
VENCSEL = 2
000
8 to 29 GP pins
VENCSEL = 1
CS3SEL = 0,2
A3, F3
8-bit VENC
1 = VCLK,
YOUT[7:0]
000
A, F
29 GP pins
VENCSEL = 0
RGBSEL = 0,1,2,3,4
-
Italics indicate mandatory settings for a given Minor Configuration option.
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TMS320DM6437
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Table 3-51. EMIFA/VPSS Sub-Block 1 Configuration Choice B (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
B1
PINMUX SELECTION FIELDS
AEM
OTHERS
EMIFA
VPBE
GPIO
Cfg Summary
8-bit EMIFA (Async)
Pinout Mode 1
No VENC
9-to-13 GP pins
VENCSEL = 0
0 = EM_D[7:0]
-
0 = GP[31, 29:22]
RGBSEL = 0
0 = EM_CS2,
EM_A[4:0],
EM_BA[1:0]
-
-
CS3SEL = 0,1
1 = EM_CS3
-
0 = GP[13]
CS4SEL = 0,1
1 = EM_CS4
-
0 = GP[32]
CS5SEL = 0,1
1 = EM_CS5
-
0 = GP[33]
-
1 = VPBECLK, can
be used by DAC
0 = GP[30]
001
VPBECKEN = 0,1
B
Cfg Summary
B2
(1)
144
001
RESULTING PERIPHERALS/PINS
8-bit EMIFA (Async)
Pinout Mode 1
8-bit VENC
0-to-4 GP pins
VENCSEL = 1
1 = EM_D[7:0]
1 = VCLK,
YOUT[7:0]
-
RGBSEL = 0
0 = EM_CS2,
EM_A[4:0],
EM_BA[1:0]
-
-
CS3SEL = 0,1,2
1 = EM_CS3
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,1,2
1 = EM_CS4
2 = VSYNC
0 = GP[32]
CS5SEL = 0,1,2
1 = EM_CS5
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
-
1 = VPBECLK
0 = GP[30]
Italics indicate mandatory setting for a given Minor Configuration option.
Device Configurations
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Table 3-52. EMIFA/VPSS Sub-Block 1 Configuration Choice C (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
C1
PINMUX SELECTION FIELDS
AEM
OTHERS
EMIFA
VPBE
GPIO
Cfg Summary
8-bit EMIFA (Async)
Pinout Mode 3
No VENC
17-to-21 GP pins
VENCSEL = 0
-
-
0 = GP[31, 29:14]
RGBSEL = 0
0 = EM_CS2,
EM_A[4:0],
EM_BA[1:0]
-
-
CS3SEL = 0,1
1 = EM_CS3
-
0 = GP[13]
CS4SEL = 0,1
1 = EM_CS4
-
0 = GP[32]
CS5SEL = 0,1
1 = EM_CS5
-
0 = GP[33]
-
1 = VPBECLK, can
be used by DAC
0 = GP[30]
011
VPBECKEN = 0,1
C
Cfg Summary
C2
(1)
011
RESULTING PERIPHERALS/PINS
8-bit EMIFA (Async)
Pinout Mode 3
16-bit VENC
0-to-4 GP pins
VENCSEL = 2
-
2 = VCLK,
YOUT[7:0],
COUT[7:0]
-
RGBSEL = 0
0 = EM_CS2,
EM_A[4:0],
EM_BA[1:0]
-
-
CS3SEL = 0,1,2
1 = EM_CS3
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,1,2
1 = EM_CS4
2 = VSYNC
0 = GP[32]
CS5SEL = 0,1,2
1 = EM_CS5
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
-
1 = VPBECLK
0 = GP[30]
Italics indicate mandatory setting for a given Minor Configuration option.
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Table 3-53. EMIFA/VPSS Sub-Block 1 Configuration Choice D (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
D1
PINMUX SELECTION FIELDS
AEM
100
RESULTING PERIPHERALS/PINS
OTHERS
EMIFA
VPBE
GPIO
Cfg Summary
8-bit EMIFA (NAND)
Pinout Mode 4
No VENC
22-to-26 GP pins
VENCSEL = 0
-
-
0 = GP[31, 29:14]
RGBSEL = 0
0 = EM_A[2:1],
EM_CS2
-
0 = GP[11:10, 7:5]
CS3SEL = 0,1
1 = EM_CS3
-
0 = GP[13]
CS4SEL = 0,1
1 = EM_CS4
-
0 = GP[32]
CS5SEL = 0,1
1 = EM_CS5
-
0 = GP[33]
-
1 = VPBECLK,
can be used by
DAC
0 = GP[30]
VPBECKEN = 0,1
8-bit EMIFA (NAND)
Pinout Mode 4
Cfg Summary
D2
100
D
(1)
146
100
12-to-17 GP pins
VENCSEL = 1
-
1 = VCLK,
YOUT[7:0]
1 = GP[21:14]
RGBSEL = 0,1
0 = EM_A[2:1],
EM_CS2
1 = EM_A[2:1],
EM_CS2
0 = none
1 = LCD_FIELD
0 = GP[11:10, 7:5]
1 = GP[10, 7:5]
CS3SEL = 0,1,2
1 = EM_CS3
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,1,2
1 = EM_CS4
2 = VSYNC
0 = GP[32]
CS5SEL = 0,1,2
1 = EM_CS5
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
-
1 = VPBECLK
0 = GP[30]
8-bit EMIFA (NAND)
Pinout Mode 4
Cfg Summary
D3
8-bit VENC
16-to-18-bit
VENC
2-to-9 GP pins
VENCSEL = 2
-
2 = VCLK,
YOUT[7:0],
COUT[7:0]
-
RGBSEL = 0,1,2,3
0 = EM_A[2:1],
EM_CS2
1 = EM_A[2:1],
EM_CS2
2 = EM_A[2:1],
EM_CS2
3 = EM_A[2:1],
EM_CS2
0 = none
1 = LCD_FIELD
2 = R2, B2
3 = R2, B2,
LCD_FIELD
0
1
2
3
CS3SEL = 0,1,2
1 = EM_CS3
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,1,2
1 = EM_CS4
2 = VSYNC
0 = GP[32]
CS5SEL = 0,1,2
1 = EM_CS5
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
-
1 = VPBECLK
0 = GP[30]
= GP[11:10, 7:5]
= GP[10, 7:5]
= GP[11:10, 7]
= GP[10, 7]
Italics indicate mandatory setting for a given Minor Configuration option.
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Table 3-54. EMIFA/VPSS Sub-Block 1 Configuration Choices E and G (1)
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
E1,G1
PINMUX SELECTION FIELDS
AEM
101
OTHERS
EMIFA
VPBE
GPIO
Cfg Summary
8-bit EMIFA (NAND)
Pinout Mode 5
No VENC
14-to-18 GP pins
VENCSEL = 0
0 = EM_D[7:0]
-
0 = GP[31, 29:22]
RGBSEL = 0
0 = EM_A[2:1],
EM_CS2
-
0 = GP[11:10, 7:5]
CS3SEL = 0,1
1 = EM_CS3
-
0 = GP[13]
CS4SEL = 0,1
1 = EM_CS4
-
0 = GP[32]
CS5SEL = 0,1
1 = EM_CS5
-
0 = GP[33]
-
1 = VPBECLK, can
0 = GP[30]
be used by DAC
VPBECKEN = 0,1
E,G
8-bit EMIFA (NAND)
Pinout Mode 5
Cfg Summary
E2,G2
(1)
RESULTING PERIPHERALS/PINS
101
8-bit VENC
4-to-9 GP pins
VENCSEL = 1
1 = EM_D[7:0]
1 = VCLK,
YOUT[7:0]
-
RGBSEL = 0,1
0 = EM_A[2:1],
EM_CS2
1 = EM_A[2:1],
EM_CS2
0 = none
1 = LCD_FIELD
0 = GP[11:10, 7:5]
1 = GP[10, 7:5]
CS3SEL = 0,1,2
1 = EM_CS3
2 = LCD_OE
0 = GP[13]
CS4SEL = 0,1,2
1 = EM_CS4
2 = VSYNC
0 = GP[32]
CS5SEL = 0,1,2
1 = EM_CS5
2 = HSYNC
0 = GP[33]
VPBECKEN = 0,1
-
1 = VPBECLK
0 = GP[30]
Italics indicate mandatory setting for a given Minor Configuration option.
The Sub-Block 1 Minor Configuration Options are independent from the Sub-Block 0 Minor Configuration
Options. The user can independently select the appropriate Minor Configuration Option for each
Sub-Block.
As shown in Table 3-50 through Table 3-54, the configuration choices of the EMIFA/VPSS Sub-Block 1
are determined by the following PINMUX register fields:
• PINMUX0 register fields AEM, VENCSEL, RGBSEL, CS3SEL, CS4SEL, CS5SEL, and VPBECKEN.
The following is an example on how to read Table 3-50 through Table 3-54 using Sub-Block 1 Minor
Configuration G2 as an example:
• The PINMUX Selection Fields columns indicate that Sub-Block 1 Minor Configuration Option G2 is
selected through setting PINMUX0 fields to AEM = 5, VENCSEL = 1, RGBSEL = 0 or 1 (based on
whether the VPBE LCD_FIELD pin is needed), CS3SEL = 0/1/2 (based on the desired pin choice),
CS4SEL = 0/1/2 (based on the desired pin choice), CS5SEL = 0/1/2 (based on the desired pin choice),
and VPBECKEN = 0/1 (based on whether VPBE VPBECLK is needed).
• The Resulting Peripherals/Pins columns show the functional pins resulting from the PINMUX setting.
For example, PINMUX0.VENCSEL = 1 gives you the VCLK and YOUT[7:0] pins for the VPBE, in
addition to EM_D[7:0] pins for the EMIFA. PINMUX0.RGBSEL = 1 gives you the LCD_FIELD pin for
the VPBE, along with EM_A[2:1] and EM_CS2 for the EMIFA, and 4 GP pins.
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3.7.3.13.5 EMIFA/VPSS Sub-Block 2 Configuration Choices
The 3 pins in the EMIFA/VPSS Sub-Block 2 are standalone (non-multiplexed) pins. They always function
as EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. No pin mux selection is necessary
for this Sub-Block.
3.7.3.13.6 EMIFA/VPSS Sub-Block 3 Configuration Choices
The 8 pins in the EMIFA/VPSS Sub-Block 3 are multiplexed between:
• EMIFA Address Pins EM_A[12:5]
• PCI pins: PCBE3, PIDSEL, AD[24:19]
• GPIO pins GP[96:89]
The pin functions in the EMIFA/VPSS Sub-Block 3 are determined by the following PINMUX register
fields:
• PINMUX1.PCIEN
• PINMUX0.AEM
Once the Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.13.2, EMIFA/VPSS
Block Major Configuration Choices) is chosen, no further actions are necessary to refine the EMIFA/VPSS
Sub-Block 3 pin selection. For instructions on configuring the EMIFA/VPSS Block, see Section 3.7.3.13.1,
EMIFA/VPSS Block Pin Selection Procedure.
Table 3-55 summarizes the pin selections in the EMIFA/VPSS Sub-Block 3 based on the PINMUX
selections.
Table 3-55. EMIFA/VPSS Sub-Block 3 Configuration Choices
MAJOR
CONFIG
OPTION
PINMUX SELECTION FIELDS
RESULTING PERIPHERALS/PINS
PCIEN
AEM
PCI
EMIFA
GPIO
A
0
000
B
0
001
-
-
GP[96:89]
-
EM_A[12:5]
C
0
-
011
-
EM_A[12:5]
-
D
E
0
100
-
-
GP[96:89]
0
101
-
-
GP[96:89]
F
1
000
PCBE3, PIDSEL, AD[24:19]
-
-
G
1
101
PCBE3, PIDSEL, AD[24:19]
-
-
The following is an example on how to read Table 3-55 using Sub-Block 3 Major Configuration C as an
example:
• The PINMUX Selection Fields columns indicate that Sub-Block 3 Major Configuration Option C is
selected through PINMUX1.PCIEN = 0 and PINMUX0.AEM = 3.
• The Resulting Peripherals/Pins columns show the functional pins resulting from the PINMUX setting. In
Major Configuration C, the user gets EMIFA address pins EM_A[12:5] from Sub-Block 3.
148
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3.7.3.13.7 EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary
This section summarizes the EMIFA/VPSS Block muxing on a pin-by-pin basis. It provides an alternative
view to pin muxing in the EMIFA/VPSS Block. This section should only be used after following the
procedures listed in Section 3.7.3.13.1 to determine the actual EMIFA/VPSS Configuration Option for the
application need.
Table 3-56 shows the pin multiplexing control for each pin in the EMIFA/VPSS Sub-Block 0. These are the
fields in the PINMUX0 and PINMUX1 registers that control the multiplexing in this sub-block:
• PINMUX0: AEM, AEAW, CWENSEL, CFLDSEL, CI10SEL, CI32SEL, CI54SEL, CI76SEL, CCDCSEL,
HVDSEL
• PINMUX1: PCIEN
Table 3-57 shows the pin multiplexing control for each pin in the EMIFA/VPSS Sub-Block 1. These are the
fields in the PINMUX0 register that control the multiplexing in this sub-block:
• PINMUX0: AEM, VENCSEL, RGBSEL, CS5SEL, CS4SEL, CS3SEL, VPBECKEN
EMIFA/VPSS Sub-Block 2 is dedicated to EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE.
There is no pin multiplexing in this block. These pins always function as EMIFA control pins.
Table 3-58 shows the pin multiplexing control for each pin in the EMIFA/VPSS Sub-Block 3. These are the
fields in the PINMUX0 and PINMUX1 registers that control the multiplexing in this sub-block:
• PINMUX0: AEM
• PINMUX1: PCIEN
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Table 3-56. EMIFA/VPSS Sub-Block 0 Pin-By-Pin Mux Control
MULTIPLEXED FUNCTIONS
SIGNAL NAME
EMIFA ADDR/CTRL
(AEM[2:0] = 1, 3)
VPFE
PCLK/GP[54]
EMIFA DATA
(AEM[2:0] = 3, 4)
PCI
GPIO
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
PCLK
CCDCSEL = 1
–
–
–
–
–
–
GP[54]
CCDCSEL = 0
YI7(CCD7)/GP[43]
YI7(CCD7)
–
–
–
–
–
–
GP[43]
YI6(CCD6)/GP[42]
YI6(CCD6)
–
–
–
–
–
–
GP[42]
YI5(CCD5)/GP[41]
YI5(CCD5)
–
–
–
–
–
–
GP[41]
YI4(CCD4)/GP[40]
YI4(CCD4)
–
–
–
–
–
–
GP[40]
YI3(CCD3)/GP[39]
YI3(CCD3)
–
–
–
–
–
–
GP[39]
YI2(CCD2)/GP[38]
YI2(CCD2)
–
–
–
–
–
–
GP[38]
YI1(CCD1)/GP[37]
YI1(CCD1)
–
–
–
–
–
–
GP[37]
YI0(CCD0)/GP[36]
YI0(CCD0)
–
–
–
–
–
–
GP[36]
–
–
–
–
–
–
GP[53]
–
–
–
–
–
–
GP[52]
VD/GP[53]
VD
HD/GP[52]
HD
CI7(CCD15)/EM_A[13]/
AD25/EM_D[0]/GP[51]
CI7(CCD15)
CI6(CCD14)/EM_A[14]/
AD27/EM_D[1]/GP[50]
CI6(CCD14)
CI5(CCD13)/EM_A[15]/
AD29/EM_D[2]/GP[49]
CI5(CCD13)
CI4(CCD12)/EM_A[16]/
PGNT/EM_D[3]/GP[48]
CI4(CCD12)
CI3(CCD11)/EM_A[17]/
AD31/EM_D[4]/GP[47]
CI3(CCD11)
CI2(CCD10)/EM_A[18]/
PRST/EM_D[5]/GP[46]
CI2(CCD10)
CI1(CCD9)/EM_A[19]/
PREQ/EM_D[6]/GP[45]
CI1(CCD9)
CI0(CCD8)/EM_A[20]/
PINTA/EM_D[7]/GP[44]
CI0(CCD8)
C_WE/EM_R/W/GP[35]
C_FIELD/EM_A[21]/GP[34]
(1)
150
HVDSEL = 1
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0,
CI76SEL = 1
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1 (1),
CI54SEL = 1
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2 (1),
CI32SEL = 1
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2/3 (1),
CI10SEL = 1
C_WE
CWENSEL = 1,
AEM = 0/4/5
C_FIELD
CFLDSEL = 1,
AEM = 0/1/3/4/5
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
PCIEN = 0,
AEM = 1,
AEAW = 1/2/3/4,
CI76SEL = 0
PCIEN = 0,
AEM = 1,
AEAW = 2/3/4,
CI54SEL = 0
PCIEN = 0,
AEM = 1,
AEAW = 3/4,
CI32SEL = 0
PCIEN = 0,
AEM = 1,
AEAW = 4,
CI10SEL = 0
EM_D[0]
EM_D[1]
EM_D[2]
EM_D[3]
EM_D[4]
EM_D[5]
EM_D[6]
EM_D[7]
EM_R/W
CWENSEL = 0,
AEM = 1/3
–
EM_A[21]
CFLDSEL = 0,
AEM = 1
–
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI76SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI54SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI32SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI10SEL = 0
–
–
AD25
AD27
AD29
PGNT
AD31
PRST
PREQ
PINTA
–
–
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI76SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI54SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI32SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI10SEL = 0
–
–
GP[51]
GP[50]
GP[49]
GP[48]
GP[47]
GP[46]
GP[45]
GP[44]
HVDSEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0,
CI76SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1 (1),
CI54SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2 (1),
CI32SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2/3 (1),
CI10SEL = 0
GP[35]
CWENSEL = 0,
AEM = 0/4/5
GP[34]
CFLDSEL = 0,
AEM = 0/3/4/5
AEAW = 1/2/3/4 is only valid if AEM[2:0] = 1.
Device Configurations
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Table 3-57. EMIFA/VPSS Sub-Block 1 Pin-By-Pin Mux Control
MULTIPLEXED FUNCTIONS
SIGNAL
NAME
HSYNC/EM_CS5/GP[33]
VSYNC/EM_CS4/GP[32]
VPBECLK/GP[30]
VCLK/GP[31]
VPBE
EXTRA FUNCTIONS
VPBE
EMIFA
GPIO
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
HSYNC
CS5SEL = 2
–
–
EM_CS5
CS5SEL = 1
GP[33]
CS5SEL = 0
VSYNC
CS4SEL = 2
–
–
EM_CS4
CS4SEL = 1
GP[32]
CS4SEL = 0
VPBECLK
VPBECKEN = 1
–
–
–
–
GP[30]
VPBECKEN = 0
VCLK
VENCSEL = 1/2
VENCSEL = 0
–
–
–
–
GP[31]
YOUT7/GP[29]
YOUT7
–
–
–
–
GP[29]
YOUT6/GP[28]
YOUT6
–
–
–
–
GP[28]
YOUT5/GP[27]
YOUT5
–
–
–
–
GP[27]
YOUT4/GP[26]/(FASTBOOT)
YOUT4
–
–
–
–
GP[26]
YOUT3/GP[25]/(BOOTMODE3)
YOUT3
–
–
–
–
GP[25]
YOUT2/GP[24]/(BOOTMODE2)
YOUT2
–
–
–
–
GP[24]
YOUT1/GP[23]/(BOOTMODE1)
YOUT1
–
–
–
–
GP[23]
YOUT0/GP[22]/(BOOTMODE0)
YOUT0
–
–
–
–
GP[22]
COUT7/EM_D[7]/GP[21]
COUT7
–
–
EM_D[7]
GP[21]
COUT6/EM_D[6]/GP[20]
COUT6
–
–
EM_D[6]
VENCSEL =
0/1,
AEM = 1/5
COUT5/EM_D[5]/GP[19]
COUT5
–
–
EM_D[5]
GP[19]
COUT4/EM_D[4]/GP[18]
COUT4
–
–
EM_D[4]
GP[18]
COUT3/EM_D[3]/GP[17]
COUT3
–
–
EM_D[3]
GP[17]
COUT2/EM_D[2]/GP[16]
COUT2
–
–
EM_D[2]
GP[16]
COUT1/EM_D[1]/GP[15]
COUT1
–
–
EM_D[1]
GP[15]
COUT0/EM_D[0]/GP[14]
COUT0
–
–
EM_D[0]
–
–
EM_CS3
LCD_OE/EM_CS3/GP[13]
VENCSEL = 2,
AEM = 0/3/4
LCD_OE
CS3SEL = 2
G0/EM_CS2/GP[12]
G0
–
–
EM_CS2
G1/EM_A[1]/(ALE)/
GP[9]/(AEAW1/PLLMS1)
G1
–
–
EM_A[1]/(ALE)
B1/EM_A[2]/(CLE)/GP[8]/
(AEAW0/PLLMS0)
B1
RGBSEL = 4,
AEM = 0
B0/LCD_FIELD/EM_A[3]/GP[11
]
B0
R0/EM_A[4]/GP[10]/
(AEAW2/PLLMS2)
R0
R1/EM_A[0]/GP[7]/(AEM2)
R1
R2/EM_BA[0]/GP[6]/(AEM1)
R2
B2/EM_BA[1]/GP[5]/(AEM0)
B2
(1)
RGBSEL =
2/3/4,
AEM = 0
GP[20]
VENCSEL =
0/1,
AEM = 0/3/4
GP[14]
CS3SEL = 1
GP[13]
CS3SEL = 0
GP[12]
RGBSEL =
0/1 (1),
AEM = 1/3/4/5
GP[9]
RGBSEL =
0/1/2/3,
AEM = 0
–
–
EM_A[2]/(CLE)
GP[8]
LCD_FIELD
RGBSEL =
1/3 (1),
AEM = 0/4/5
EM_A[3]
GP[11]
RGBSEL =
0/2 (1),
AEM = 0/4/5
–
–
EM_A[4]
GP[10]
–
–
EM_A[0]
GP[7]
RGBSEL =
0/1/2/3 (1),
AEM = 0/4/5
–
–
EM_BA[0]
GP[6]
–
–
EM_BA[1]
GP[5]
RGBSEL = 0,
AEM = 1/3
RGBSEL = 0/1,
AEM = 0/4/5
Valid RGBSEL settings depend on AEM mode:
• RGBSEL = 0 is valid for AEM[2:0] = 0/1/3/4/5
• RGBSEL = 1 is only valid if AEM[2:0] = 0/4/5
• RGBSEL = 2/3/4 is only valid if AEM[2:0] = 0
Table 3-58. EMIFA/VPSS Sub-Block 3 Pin-By-Pin Mux Control
MULTIPLEXED FUNCTIONS
SIGNAL
NAME
EMIFA
FUNCTION
PCI
SELECT
FUNCTION
GPIO
SELECT
FUNCTION
EM_A[12]/PCBE3/GP[89]
EM_A[12]
PCBE3
GP[89]
EM_A[11]/AD24/GP[90]
EM_A[11]
AD24
GP[90]
EM_A[10]/AD23/GP[91]
EM_A[10]
AD23
EM_A[9]/PIDSEL/GP[92]
EM_A[9]
EM_A[8]/AD21/GP[93]
EM_A[8]
EM_A[7]/AD22/GP[94]
EM_A[7]
AD22
GP[94]
EM_A[6]/AD20/GP[95]
EM_A[6]
AD20
GP[95]
EM_A[5]/AD19/GP[96]
EM_A[5]
AD19
GP[96]
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PCIEN = 0,
AEM = 1/3
PIDSEL
AD21
SELECT
GP[91]
PCIEN = 1,
AEM = 0/5
GP[92]
GP[93]
PCIEN = 0,
AEM = 0/4/5
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3.8 Device Initialization Sequence After Reset
Software should follow this initialization sequence after coming out of device reset.
1. Complete the boot sequence as needed. For more details on the boot sequence, see the Using the
TMS320DM643x Bootloader Application Report (literature number SPRAAG0).
2. If the device is not already at the desired operating frequency, program the PLL Controllers (PLLC1
and PLLC2) to configure the device frequency. For details on how to program the PLLC, see the
TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978).
3. Program PINMUX0 and PINMUX1 registers to select device pin functions. For more details on
programming the PINMUX0 and PINMUX1 registers to select device pin functions, see Section 3.7,
Multiplexed Pin Configurations.
Note: If EMAC operation is desired, the EMAC must be placed in reset before programming
PINMUX1.HOSTBK to select EMAC pins.
4. Program the VDD3P3V_PWDN register to power up the necessary I/O pins. For more details on
programming the VDD3P3V_PWDN register, see Section 3.2, Power Considerations.
5. As needed by the application, program the following System Module registers when there are no active
transactions on the respective peripherals:
a. HPICTL (Section 3.6.2.1, HPI Control Register): applicable for HPI only if a different host burst
write timeout value from default is desired.
b. TIMERCTL (Section 3.6.2.2, Timer Control Register): applicable for Timer0 and Watchdog Timer2
only.
c. EDMATCCFG (Section 3.6.2.3, EDMA TC Configuration Register): applicable for EDMA only. The
recommendation is to leave the EDMATCCFG register at its default.
d. VPSS_CLKCTL (Section 3.3.2, VPSS Clocks): applicable for VPSS only.
6. Program the Power and Sleep Controller (PSC) to enable the desired peripherals. For details on how
to program the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature
number SPRU978).
7. Program the Switched Central Resource (SCR) bus priorities for the master peripherals
(Section 3.6.1). This must be configured when there are no active transactions on the respective
peripherals:
a. Program the MSTPRI0 and MSTPRI1 registers in the System Module. These registers can be
programmed before or after the respective peripheral is enabled by the PSC in step 6.
b. Program the EDMACC QUEPRI register, the C64x+ MDMAARBE.PRI field, and the VPSS PCR
register. These registers can only be programmed after the respective peripheral is enabled by the
PSC in step 6.
8. Configure the C64x+ Megamodule and the peripherals.
a. For details on C64x+ Megamodule configuration, see the TMS320C64x+ DSP Megamodule
Reference Guide (literature number SPRU871).
Special considerations: Bootloader disables C64x+ cache—For all boot modes that default to
DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,
BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2,
L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured as
all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and L1DCFG.L1DMODE = 0h). If cache
use is required, the application code must explicitly enable the cache. For more information on boot
modes, see Section 3.4.1, Boot Modes. For more information on the bootloader, see the Using the
TMS320DM643x Bootloader Application Report (literature number SPRAAG0).
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b. Peripherals configuration: see the respective peripheral user’s guide.
Special considerations: DDR2 memory controller—the Peripheral Bus Burst Priority Register
(PBBPR) should be programmed to ensure good DDR2 throughput and to prevent command
starvation (prevention of certain commands from being processed by the DDR2 memory controller).
For more details, see the TMS320DM643x DMP DDR2 Memory Controller User’s Guide (literature
number SPRU986). A hex value of 0x20 is recommended for the PBBPR PR_OLD_COUNT field to
provide a good DSP performance and still allow good utilization by other modules.
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3.9 Debugging Considerations
3.9.1
Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the DM643x DMP device always be at a valid logic
level and not floating. This may be achieved via pullup/pulldown resistors. The DM643x DMP features
internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless
otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired
value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
• EMIFA Chip Select Outputs: On DM6437, the EMIFA chip select pins (EM_CS2, EM_CS3, EM_CS4,
and EM_CS5) feature an internal pulldown (IPD) resistor. If these pins are connected and used as an
EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to
ensure the EM_CSx function defaults to an inactive (high) state.
For the boot and configuration pins (listed in Table 2-5, Boot Terminal Functions), if they are both routed
out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be
implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the
desired configuration value, providing external connectivity can help ensure that valid logic levels are
latched on these device boot and configuration pins. In addition, applying external pullup/pulldown
resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in
switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.
Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration
pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for
the DM643x DMP, see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply
Voltage and Operating Temperature.
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For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
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4 System Interconnect
On the DM6437 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system
peripherals are interconnected through a switch fabric architecture (see Figure 4-1). The switch fabric is
composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs establish
low-latency connectivity between master peripherals and slave peripherals. Additionally, the SCRs provide
priority-based arbitration and facilitate concurrent data movement between master and slave peripherals.
Through an SCR, the DSP subsystem can send data to the DDR2 Memory Controller without affecting a
data transfer between the EMAC and L2 memory. Bridges are mainly used to perform bus-width
conversion as well as bus operating frequency conversion. For example, in Figure 4-1, Bridge 6 performs
a frequency conversion between a bus operating at DSP/3 clock rate and a bus operating at DSP/6 clock
rate. Furthermore, Bridge 5 performs a bus-width conversion between a 64-bit bus and a 32-bit bus.
The C64x+ Megamodule, the EDMA3 transfer controllers (EDMA3TC[2:0]), and the various system
peripherals can be classified into two categories: master peripherals and slave peripherals. Master
peripherals are typically capable of initiating read and write transfers in the system and do not rely on the
EDMA3 or on the CPU to perform transfers to and from them. The system master peripherals include the
C64x+ Megamodule, the EDMA3 transfer controllers, VLYNQ, EMAC, HPI, PCI, and VPSS. Not all master
peripherals may connect to all slave peripherals. The supported connections are designated by "Y" in
Table 4-1.
Table 4-1. System Connection Matrix
SLAVE PERIPHERALS/MODULES
MASTER
PERIPHERALS/MODULES
C64x+
SDMA
DDR2
MEMORY
CONTROLLER
PCI
(MASTER BACK-END I/F)
SCR4 (1)
SCR2, SCR6,
SCR7, SCR8 (1)
C64x+ MDMA
–
Y
Y
–
Y
VPSS
–
Y
–
–
–
PCI (SLAVE BACK-END I/F)
Y
Y
–
Y
Y
VLYNQ
Y
Y
–
Y
Y
EMAC
Y
Y
–
Y
Y
HPI
Y
Y
–
Y
Y
EDMA3TC's
(EDMA3TC2/TC1/TC0)
Y
Y
Y
Y
Y
C64x+ CFG
–
–
–
Y
Y
(1)
All the peripherals/modules that support a connection to SCR2, SCR4, SCR6, SCR7, and SCR8 have access to all peripherals/modules
connected to those respective SCRs.
4.1 System Interconnect Block Diagram
•
•
•
•
•
156
Figure 4-1 displays the DM6437 system interconnect block diagram. The following is a list that helps in
the interpretation of this diagram:
The direction of the arrows indicates either a bus master or bus slave.
The arrow originates at a bus master and terminates at a bus slave.
The direction of the arrows does not indicate the direction of data flow. Data flow is typically
bi-directional for each of the documented bus paths.
The pattern of each arrow's line indicates the clock rate at which it is operating— i.e., either DSP/3,
DSP/6, or MXI/CLKIN clock rate.
A peripheral may have multiple instances shown in Figure 4-1 for the following reason:
– The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register
access, data access, and/or memory access. Examples of these peripherals are C64x+
Megamodule, EDMA3, VPSS, VLYNQ, HPI, EMAC, and PCI.
System Interconnect
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32
32
EMAC
SCR 5
32
Bridge 8
UART0
UART1
32
64
32
32
Bridge 2 64
32
HPI
32
DDR2 Memory
Controller
(Memory/Register)
64
SDMA
VLYNQ
MXI/CLKIN Clock Rate
32
DSP/6 Clock Rate
DSP/6 Clock Rate
HPI
32
VPSS Reg
32
HECC
32
64x+
L2/L1
I2C
32
Bridge 1 64
64
Bridge 7
32
PCI
(DSP Master I/F)
32
64
VPSS
32
SCR 6
Read
EDMA3TC0
EDMA3TC1
EDMA3TC2
32
EMAC Reg
PCI
(DSP Slave I/F) 32
64
64
Write
64
Read
64
Write
Read
64
64
Write
64
32
EMAC Control
Module Reg
EMAC Control
Module RAM
32
Bridge 5
MDIO
SCR 1
32
32
GPIO
64
Bridge 4
32
32
System Reg
PWM0
SCR 2
32
PWM1
32
PWM2
32
Timer0
32
32
Timer1
Timer2
32
32
64
Bridge 3
Bridge 6
PSC
32
32
32
32
SCR 3
32
PCI Reg
L2 Cache
PLLC1
PLLC2
32
MDMA
SCR 4
32
64
EMIFA
SCR 7
32
EDMA3CC
VLYNQ
64x+
32
CFG
32
32
EDMA3TC0
EDMA3TC1
EDMA3TC2
32
McBSP0
32
McBSP1
SCR 8
32
McASP0
DSP/3 Clock Rate
DSP/3 Clock Rate
DSP/6 Clock Rate
MXI/CLKIN Clock Rate
Figure 4-1. System Interconnect Block Diagram
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise
Noted) (1)
Supply voltage ranges:
Core (CVDD, VDDA_1P1V (2)) (3)
I/O, 3.3V (DVDD33)
–0.5 V to 1.5 V
(3)
–0.5 V to 4.2 V
I/O, 1.8V (DVDDR2, DDR_VDDDLL, PLLPWR18, VDDA_1P8V, MXVDD) (3)
Input voltage ranges:
VI I/O, 3.3-V pins (except PCI-capable pins)
VI I/O, 3.3-V pins PCI-capable pins
VI I/O, 1.8 V
Output voltage ranges:
VO I/O, 3.3-V pins (except PCI-capable pins)
VO I/O, 3.3-V pins PCI-capable pins
VO I/O, 1.8 V
–0.5 to 2.5 V
–0.5 V to 4.2 V
–0.5 V to DVDD33 + 0.5 V
–0.5 V to 2.5 V
–0.5 V to 4.2 V
–0.5 V to DVDD33 + 0.5 V
–0.5 V to 2.5 V
Operating Junction temperature
ranges, TJ:
Commercial
Automotive (Q or S suffix)
–40°C to 125°C
Storage temperature range, Tstg
(default)
–65°C to 150°C
(1)
(2)
(3)
158
0°C to 90°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Based on JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of
Microelectronic Components) testing the TMS320DM643xZDU device’s charged-device model (CDM) sensitivity classification is Class II
(200 to region1 > region2 > region3.
Interface to conventional Bayer pattern. Each region can accumulate either 3 or 4 colors.
32, 64, 128, or 256 bins per color per region.
32, 64, or 128 bins per color for 2 regions.
32 or 64 bins per color for 3 or 4 regions.
Automatic clear of histogram RAM after an ARM read.
Saturation of the pixel count if the count exceeds the maximum value (each memory location is 20-bit
wide).
Downshift ranging from 0 to 7 bits (maximum bin range 128).
The last bin (highest range of values) will accumulate any value that is higher than the lower bound.
The Histogram register memory mapping is shown in Table 6-34.
Table 6-34. Histogram Register Descriptions
HEX ADDRESS RANGE
218
REGISTER ACRONYM
DESCRIPTION
0x01C7 1000
PID
Peripheral Revision and Class Information Register
0x01C7 1004
PCR
Peripheral Control Register
0x01C7 1008
HIST_CNT
Histogram Control Bits Register
0x01C7 100C
WB_GAIN
White/Channel Balance Settings Register
0x01C7 1010
R0_HORZ
Region 0 Horizontal Information Register
0x01C7 1014
R0_VERT
Region 0 Vertical Information Register
0x01C7 1018
R1_HORZ
Region 1 Horizontal Information Register
0x01C7 101C
R1_VERT
Region 1 Vertical Information Register
0x01C7 1020
R2_HORZ
Region 2 Horizontal Information Register
0x01C7 1024
R2_VERT
Region 2 Vertical Information Register
0x01C7 1028
R3_HORZ
Region 3 Horizontal Information Register
0x01C7 102C
R3_VERT
Region 3 Vertical Information Register
0x01C7 1030
HIST_ADDR
Histogram Address for Data to be Read Register
0x01C7 1034
HIST_DATA
Histogram Data That is Read From the Memory Register
0x01C7 1038
RADD
Read Address From DDR2 Memory Register
0x01C7 103C
RADD_OFF
Read Address Offset for Each Line in the DDR2 Memory Register
0x01C7 1040
H_V_INFO
Horizontal/Vertical Information Register (Horizontal/Vertical Number of
Pixels When Data is Read From DDR2 Memory Information Register)
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6.10.1.6 VPFE Electrical Data/Timing
Table 6-35. Timing Requirements for VPFE PCLK Master/Slave Mode (1) (see Figure 6-19)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
UNIT
MIN
(1)
(2)
MAX
10.204 or 13.33 (2)
ns
Pulse duration, PCLK high
0.4P
ns
tw(PCLKL)
Pulse duration, PCLK low
0.4P
ns
tt(PCLK)
Transition time, PCLK
1
tc(PCLK)
Cycle time, PCLK
2
tw(PCLKH)
3
4
7
ns
P = PCLK period in ns.
When PCLK sources the clock for both the VPFE and VPBE, the minimum cycle time of 13.33 ns (specified in Table 6-42, Timing
Requirements for VPBE CLK Inputs for VPBE) must be met. When PCLK sources the clock for only the VPFE, a minimum cycle time of
10.2 ns may be used.
2
3
1
PCLK
4
4
Figure 6-19. VPFE PCLK Timing
Table 6-36. Timing Requirements for VPFE (CCD) Slave Mode (1) (see Figure 6-20)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
(1)
5
tsu(CCDV-PCLK)
Setup time, CCD valid before PCLK edge
6
th(PCLK-CCDV)
Hold time, CCD valid after PCLK edge
7
tsu(HDV-PCLK)
Setup time, HD valid before PCLK edge
8
th(PCLK-HDV)
Hold time, HD valid after PCLK edge
9
tsu(VDV-PCLK)
Setup time, VD valid before PCLK edge
10
th(PCLK-VDV)
Hold time, VD valid after PCLK edge
11
tsu(C_WEV-PCLK)
Setup time, C_WE valid before PCLK edge
12
th(PCLK-C_WEV)
Hold time, C_WE valid after PCLK edge
13
tsu(C_FIELDV-PCLK)
Setup time, C_FIELD valid before PCLK edge
14
th(PCLK-C_FIELDV)
Hold time, C_FIELD valid after PCLK edge
UNIT
MAX
4.5
ns
1
ns
4.5
ns
1
ns
4.5
ns
1
ns
4.5
ns
1
ns
4.5
ns
1
ns
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
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PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
8, 10
7, 9
HD/VD
11, 13
12, 14
C_WE/C_FIELD
5
6
CCD[15:0]
Figure 6-20. VPFE (CCD) Slave Mode Input Data Timing
Table 6-37. Timing Requirements for VPFE (CCD) Master Mode (1) (see Figure 6-21)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
15
tsu(CCDV-PCLK)
Setup time, CCD valid before PCLK edge
16
th(PCLK-CCDV)
Hold time, CCD valid after PCLK edge
23
tsu(CWEV-PCLK)
Setup time, C_WE valid before PCLK edge
24
th(PCLK-CWEV)
Hold time, C_WE valid after PCLK edge
(1)
UNIT
MAX
4.5
ns
1
ns
4.5
ns
1
ns
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
(Positive Edge Clocking)
PCLK
(Positive Edge Clocking)
15
16
CCD[15:0]
23
24
C_WE/C_FIELD
Figure 6-21. VPFE (CCD) Master Mode Input Data Timing
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Table 6-38. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode (1) (see Figure 6-22)
NO.
(1)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
UNIT
MIN
MAX
18
td(PCLK-HDV)
Delay time, PCLK edge to HD valid
2
9.5
ns
20
td(PCLK-VDV)
Delay time, PCLK edge to VD valid
2
9.5
ns
22
td(PCLK-C_FIELDV)
Delay time, PCLK edge to C_FIELD valid
2
9.5
ns
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
18
HD
20
VD
22
C_FIELD
Figure 6-22. VPFE (CCD) Master Mode Control Output Data Timing
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6.10.2 Video Processing Back-End (VPBE)
The Video Processing Back-End (VPBE) consists of the On-Screen Display (OSD) module, the Video
Encoder (VENC) including the Digital LCD (DLCD) and Analog (i.e., DAC) interfaces. The video encoder
generates analog video output. The DLCD controller generates digital RGB/YCbCr data output and timing
signals.
Note: If the DAC is not used, for proper device operation connect the DAC pins as described in
Table 2-21, DAC [Part of VPBE] Terminal Functions.
The VPBE register memory mapping is shown in Table 6-39.
Table 6-39. VPBE Register Descriptions
Address
Register
Description
0x01C7 2780
PID
Peripheral Revision and Class Information Register
0x01C7 2784
PCR
Peripheral Control Register
To ensure NTSC and PAL compliant output video, the stability of the input clock source is very important.
TI recommends a 27-MHz, 50-ppm crystal. Ceramic oscillators are not recommended. The NTSC/PAL
color sub-carrier frequency is derived from the 27-MHz clock; therefore, if the 27-MHz clock drifts, then the
color sub-carrier frequency will drift as well. Assuming no 27-MHz frequency drift, the color sub-carrier
frequency is generated as follows:
f
sc-ntsc
æ 35 ö
÷ = 3.5795454545 MHz
è 264 ø
= 27 MHz ç
æ 167 ö
÷ = 4.4332628318 MHz
è 1017 ø
f sc- pal = 27 MHz ç
To ensure the color sub-carrier frequency will not drift out of specification, the user must follow the crystal
requirements discussed in Section 6.6.1, Clock Input Option 1—Crystal. Alternatively, if the VPBE input
clock is sourced from the VPBECLK or VPFE clock inputs, these clocks must have a frequency stability of
±50 ppm to ensure NTSC and PAL compliant output video.
6.10.2.1 On-Screen Display (OSD)
The major function of the OSD module is to gather and blend video data and display/bitmap data before
feeding it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from an
external memory, typically DDR2. The OSD is programmed via control and parameter registers. The
following are the primary features that are supported by the OSD.
• Simultaneous display of two video windows and two OSD windows (VIDWIN0/VIDWIN1 and
OSDWIN0/OSDWIN1).
– Separate enable for each window
– Programmable width, height, and base starting coordinates for each window
– External memory address and offset registers for each window
– Support for x2 and x4 zoom in both the horizontal and vertical direction
– OSDWIN1 can be used as an attribute window for OSDWIN0
– Attribute window blinking intervals
– Field/frame mode for the windows (interlaced/progressive)
– Eight step blending process between the OSD and video windows
– Transparency support for the OSD and video data (when a bitmap pixel is zero, there will be no
blending for that corresponding video pixel)
– Resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows
– Reads in YCbCr data in 4:2:2 format from external memory, with the capability for swapping the
order of the CbCr component in the 32-bit word (this is relevant to the two video windows)
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– Support for a ping-pong buffer scheme that can be used for VIDWIN0 (allows for video data to be
accessed from two different locations in DDR2)
– Each OSD window (either one, but not both at the same time) is capable of reading in RGB data
(16-bit data with six bits for the green and five bits each for the red and blue colors) instead of
bitmap data in YCbCr format restricted to a maximum of 8-bits
– The OSD bitmap data width is selectable between 1, 2, 4, or 8-bits.
– Each OSD window supports 16 entries for the bitmap (to index into a 256 entry RAM/ROM CLUT
table).
– Indirect support for 24-bit RGB input data (which will be transformed into 16-bit YCbCr video
window data) via the wrapper interface in the VPBE.
Support for a rectangular cursor window and a programmable background color selection.
– Programmable color palette with the ability to select between a RAM/ROM table with support for
256 colors.
– The width, height, and color of the cursor is programmable.
– The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 >
background color
Support for attenuation of the YCbCr values for the REC601 standard.
The following restrictions exist in the OSD module.
• Both the OSD windows and VIDWIN1 should be fully contained inside VIDWIN0.
• When one of the OSD windows is set in RGB mode, it cannot overlap with VIDWIN1.
• The OSD cannot support more than 256 color entries in the CLUT RAM/ROM. Some applications
require higher number of entries, and one workaround is to use VIDWIN1 as an overlay mimicking the
OSD window. Another option is to use the RGB mode for one of the OSD windows which allows for a
total of 16-bits for the R, G, and B colors (64K colors).
• The OSD can only read YCbCr in 4:2:2 interleaved format for the video windows. Other formats, either
color separate storage or 4:4:4/4:2:0 interleaved data is not supported.
• If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window
dimension cannot be greater than 720 currently.
• It is not possible to use both of the CLUT ROMs at the same time. However, one window can use
RAM while another uses ROM.
• The 24-bit RGB input mode is only valid for one of the two video windows (programmable) and does
not apply to the OSD windows.
The OSD register memory mapping is shown in Table 6-40.
Table 6-40. OSD Register Descriptions
Address
Register
Description
0x01C7 2600
MODE
OSD Mode Register
0x01C7 2604
VIDWINMD
Video Window Mode Setup
0x01C7 2608
OSDWIN0MD
OSD Window Mode Setup
0x01C7 260C
OSDWIN1MD
OSD Window 1 Mode Setup (when used as a second OSD window)
0x01C7 260C
OSDATRMD
OSD Attribute Window Mode Setup (when used as an attribute window)
0x01C7 2610
RECTCUR
Rectangular Cursor Setup
0x01C7 2614
RSV0
Reserved
0x01C7 2618
VIDWIN0OFST
Video Window 0 Offset
0x01C7 261C
VIDWIN1OFST
Video Window 1 Offset
0x01C7 2620
OSDWIN0OFST
OSD Window 0 Offset
0x01C7 2624
OSDWIN1OFST
OSD Window 1 Offset
0x01C7 2628
RSV1
Reserved
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Table 6-40. OSD Register Descriptions (continued)
224
0x01C7 262C
VIDWIN0ADR
Video Window 0 Address
0x01C7 2630
VIDWIN1ADR
Video Window 1 Address
0x01C7 2634
RSV2
Reserved
0x01C7 2638
OSDWIN0ADR
OSD Window 0 Address
0x01C7 263C
OSDWIN1ADR
OSD Window 1 Address
0x01C7 2640
BASEPX
Base Pixel X
0x01C7 2644
BASEPY
Base Pixel Y
0x01C7 2648
VIDWIN0XP
Video Window 0 X-Position
0x01C7 264C
VIDWIN0YP
Video Window 0 Y-Position
0x01C7 2650
VIDWIN0XL
Video Window 0 X-Size
0x01C7 2654
VIDWIN0YL
Video Window 0 Y-Size
0x01C7 2658
VIDWIN1XP
Video Window 1 X-Position
0x01C7 265C
VIDWIN1YP
Video Window 1 Y-Position
0x01C7 2660
VIDWIN1XL
Video Window 1 X-Size
0x01C7 2664
VIDWIN1YL
Video Window 1 Y-Size
0x01C7 2668
OSDWIN0XP
OSD Bitmap Window 0 X-Position
0x01C7 266C
OSDWIN0YP
OSD Bitmap Window 0 Y-Position
0x01C7 2670
OSDWIN0XL
OSD Bitmap Window 0 X-Size
0x01C7 2674
OSDWIN0YL
OSD Bitmap Window 0 Y-Size
0x01C7 2678
OSDWIN1XP
OSD Bitmap Window 1 X-Position
0x01C7 267C
OSDWIN1YP
OSD Bitmap Window 1 Y-Position
0x01C7 2680
OSDWIN1XL
OSD Bitmap Window 1 X-Size
0x01C7 2684
OSDWIN1YL
OSD Bitmap Window 1 Y-Size
0x01C7 2688
CURXP
Rectangular Cursor Window X-Position
0x01C7 268C
CURYP
Rectangular Cursor Window Y-Position
0x01C7 2690
CURXL
Rectangular Cursor Window X-Size
0x01C7 2694
CURYL
Rectangular Cursor Window Y-Size
0x01C7 2698
RSV3
Reserved
0x01C7 269C
RSV4
Reserved
0x01C7 26A0
W0BMP01
Window 0 Bitmap Value to Palette Map 0/1
0x01C7 26A4
W0BMP23
Window 0 Bitmap Value to Palette Map 2/3
0x01C7 26A8
W0BMP45
Window 0 Bitmap Value to Palette Map 4/5
0x01C7 26AC
W0BMP67
Window 0 Bitmap Value to Palette Map 6/7
0x01C7 26B0
W0BMP89
Window 0 Bitmap Value to Palette Map 8/9
0x01C7 26B4
W0BMPAB
Window 0 Bitmap Value to Palette Map A/B
0x01C7 26B8
W0BMPCD
Window 0 Bitmap Value to Palette Map C/D
0x01C7 26BC
W0BMPEF
Window 0 Bitmap Value to Palette Map E/F
0x01C7 26C0
W1BMP01
Window 1 Bitmap Value to Palette Map 0/1
0x01C7 26C4
W1BMP23
Window 1 Bitmap Value to Palette Map 2/3
0x01C7 26C8
W1BMP45
Window 1 Bitmap Value to Palette Map 4/5
0x01C7 26CC
W1BMP67
Window 1 Bitmap Value to Palette Map 6/7
0x01C7 26D0
W1BMP89
Window 1 Bitmap Value to Palette Map 8/9
0x01C7 26D4
W1BMPAB
Window 1 Bitmap Value to Palette Map A/B
0x01C7 26D8
W1BMPCD
Window 1 Bitmap Value to Palette Map C/D
0x01C7 26DC
W1BMPEF
Window 1 Bitmap Value to Palette Map E/F
0x01C7 26E0
-
Reserved
0x01C7 26E4
RSV5
Reserved
0x01C7 26E8
MISCCTL
Miscellaneous Control
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Table 6-40. OSD Register Descriptions (continued)
0x01C7 26EC
CLUTRAMYCB
CLUT RAMYCB Setup
0x01C7 26F0
CLUTRAMCR
CLUT RAM Setup
0x01C7 26F4
TRANSPVAL
CLUT RAM Setup
0x01C7 26F8
RSV6
Reserved
0x01C7 26FC
PPVWIN0ADR
Ping-Pong Video Window 0 Address
6.10.2.2 Video Encoder (VENC)
Analog/DACs interface of the Video Encoder (VENC) supports the following features.
• Master Clock Input - 27MHz (x2 Upsampling)
• SDTV Support
– Composite NTSC-M, PAL-B/D/G/H/I
– S-Video (Y/C)
– Component YPbPr (SMPTE/EBU N10, Betacam, MII)
– RGB
– Non-Interlace
– CGMS/WSS
– Line 21 Closed Caption Data Encoding
– Chroma Low Pass Filter 1.5MHz/3MHz
– Programmable SC-H phase
• HDTV Support
– Progressive Output (525p/625p)
– Component YPbPr
– RGB
– CGMS/WSS
• 4 10-bit Over-Sampling D/A Converters
• Optional 7.5% Pedestal
• 16-235/0-255 Input Amplitude Selectable
• Programmable Luma Delay
• Master/Slave Operation
• Internal Color Bar Generation (100%/75%)
The Digital LCD Controller (DLCD) of the VENC supports the following features.
• Programmable DCLK
• Various Output Formats
– YCbCr 16bit
– YCbCr 8bit
– ITU-R BT. 656
– Parallel RGB 24bit
• Low Pass Filter for Digital RGB Output
• Programmable Timing Generator
• Master/Slave Operation
• Internal Color Bar Generation (100%/75%)
The VENC register memory mapping including the Digital LCD and DACs is shown in Table 6-41.
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Table 6-41. VENC (Including Digital LCD and DACs) Register Descriptions
Address
226
Register
Description
0x01C7 2400
VMOD
Video Mode
0x01C7 2404
VIDCTL
Video Interface I/O Control
0x01C7 2408
VDPRO
Video Data Processing
0x01C7 240C
SYNCCTL
Sync Control
0x01C7 2410
HSPLS
Horizontal Sync Pulse Width
0x01C7 2414
VSPLS
Vertical Sync Pulse Width
0x01C7 2418
HINT
Horizontal Interval
0x01C7 241C
HSTART
Horizontal Valid Data Start Position
0x01C7 2420
HVALID
Horizontal Data Valid Range
0x01C7 2424
VINT
Vertical Interval
0x01C7 2428
VSTART
Vertical Valid Data Start Position
0x01C7 242C
VVALID
Vertical Data Valid Range
0x01C7 2430
HSDLY
Horizontal Sync Delay
0x01C7 2434
VSDLY
Vertical Sync Delay
0x01C7 2438
YCCTL
YCbCr Control
0x01C7 243C
RGBCTL
RGB Control
0x01C7 2440
RGBCLP
RGB Level Clipping
0x01C7 2444
LINECTL
Line ID Control
0x01C7 2448
CULLLINE
Culling Line Control
0x01C7 244C
LCDOUT
LCD Output Signal Control
0x01C7 2450
BRTS
Brightness Start Position Signal Control
0x01C7 2454
BRTW
Brightness Width Signal Control
0x01C7 2458
ACCTL
LCD_AC Signal Control
0x01C7 245C
PWMP
PWM Start Position Signal Control
0x01C7 2460
PWMW
PWM Width Signal Control
0x01C7 2464
DCLKCTL
DCLK Control
0x01C7 2468
DCLKPTN0
DCLK Pattern 0
0x01C7 246C
DCLKPTN1
DCLK Pattern 1
0x01C7 2470
DCLKPTN2
DCLK Pattern 2
0x01C7 2474
DCLKPTN3
DCLK Pattern 3
0x01C7 2478
DCLKPTN0A
DCLK Auxiliary Pattern 0
0x01C7 247C
DCLKPTN1A
DCLK Auxiliary Pattern 1
0x01C7 2480
DCLKPTN2A
DCLK Auxiliary Pattern 2
0x01C7 2484
DCLKPTN3A
DCLK Auxiliary Pattern 3
0x01C7 2488
DCLKHS
Horizontal DCLK Mask Start
0x01C7 248C
DCLKHSA
Horizontal Auxiliary DCLK Mask Start
0x01C7 2490
DCLKHR
Horizontal DCLK Mask Range
0x01C7 2494
DCLKVS
Vertical DCLK Mask Start
0x01C7 2498
DCLKVR
Vertical DCLK Mask Range
0x01C7 249C
CAPCTL
Caption Control
0x01C7 24A0
CAPDO
Caption Data Odd Field
0x01C7 24A4
CAPDE
Caption Data Even Field
0x01C7 24A8
ATR0
Video Attribute Data # 0
0x01C7 24AC
ATR1
Video Attribute Data # 1
0x01C7 24B0
ATR2
Video Attribute Data # 2
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Table 6-41. VENC (Including Digital LCD and DACs) Register Descriptions (continued)
0x01C7 24B4
0x01C7 24B4
Reserved
0x01C7 24B4
0x01C7 24B4
0x01C7 24B8
VSTAT
0x01C7 24BC
Video Status
Reserved
0x01C7 24C0
0x01C7 24C4
DACTST
DAC Test
0x01C7 24C8
YCOLVL
YOUT and COUT Levels
0x01C7 24CC
SCPROG
Sub-Carrier Programming
0x01C7 24D0
0x01C7 24D4
Reserved
0x01C7 24D8
0x01C7 24DC
CVBS
Composite Mode
0x01C7 24E0
CMPNT
Component Mode
0x01C7 24E4
ETMG0
CVBS Timing Control 0
0x01C7 24E8
ETMG1
CVBS Timing Control 1
0x01C7 24EC
ETMG2
Component Timing Control 0
0x01C7 24F0
ETMG3
Component Timing Control 1
0x01C7 24F4
DACSEL
DAC Output Select
0x01C7 24F8
Reserved
0x01C7 24FC
0x01C7 2500
ARGBX0
Analog RGB Matrix 0
0x01C7 2504
ARGBX1
Analog RGB Matrix 1
0x01C7 2508
ARGBX2
Analog RGB Matrix 2
0x01C7 250C
ARGBX3
Analog RGB Matrix 3
0x01C7 2510
ARGBX4
Analog RGB Matrix 4
0x01C7 2514
DRGBX0
Digital RGB Matrix 0
0x01C7 2518
DRGBX1
Digital RGB Matrix 1
0x01C7 251C
DRGBX2
Digital RGB Matrix 2
0x01C7 2520
DRGBX3
Digital RGB Matrix 3
0x01C7 2524
DRGBX4
Digital RGB Matrix 4
0x01C7 2528
VSTARTA
Vertical Data Valid Start Position for Even Field
0x01C7 252C
OSDCLK0
OSD Clock Control 0
0x01C7 2530
OSDCLK1
OSD Clock Control 1
0x01C7 2534
HVLDCL0
Horizontal Valid Culling Control 0
0x01C7 2538
HVLDCL1
Horizontal Valid Culling Control 1
0x01C7 253C
OSDHADV
OSD Horizontal Sync Advance
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6.10.2.3 VPBE Electrical Data/Timing
Table 6-42. Timing Requirements for VPBE CLK Inputs (1) (2) (see Figure 6-23)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
(1)
(2)
UNIT
MAX
1
tc(PCLK)
Cycle time, PCLK
13.33
ns
2
tw(PCLKH)
Pulse duration, PCLK high
0.4P
ns
3
tw(PCLKL)
Pulse duration, PCLK low
0.4P
ns
4
tt(PCLK)
Transition time, PCLK
5
tc(VPBECLK)
Cycle time, VPBECLK
6
tw(VPBECLKH)
7
8
7
ns
13.33
ns
Pulse duration, VPBECLK high
0.4V
ns
tw(VPBECLKL)
Pulse duration, VPBECLK low
0.4V
tt(VPBECLK)
Transition time, VPBECLK
ns
7
ns
P = PCLK period in ns.
V = VPBECLK period in ns.
3
1
2
PCLK
4
6
5
7
4
VPBECLK
8
8
Figure 6-23. VPBE PCLK and VPBECLK Timing
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Table 6-43. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK (1) (see
Figure 6-24)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
(1)
(2)
UNIT
MAX
9
tsu(VCTLV-PCLK)
Setup time, VCTL valid before PCLK edge
3
ns
10
th(PCLK-VCTLV)
Hold time, VCTL valid after PCLK edge
1
ns
27
tsu(VCTLV-VPBECLK)
Setup time, VCTL valid before VPBECLK rising edge
3
ns
28
th(VPBECLK-VCTLV)
Hold time, VCTL valid after VPBECLK rising edge
1
ns
33
tsu(FIELD-PCLK)
Setup time, LCD_FIELD valid before PCLK edge
5P (2)
ns
34
th(PCLK-FIELD)
Hold time, LCD_FIELD valid after PCLK edge
5P (2)
ns
(2)
ns
ns
35
tsu(FIELD-VPBECLK)
Setup time, LCD_FIELD valid before VPBECLK edge
5P
36
th(VPBECLK-FIELD)
Hold time, LCD_FIELD valid after VPBECLK edge
5P (2)
PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
10
9
28
27
VCTL(A)
34
33
36
35
LCD_FIELD
A. VCTL = HSYNC and VSYNC
Figure 6-24. VPBE Input Timing With Respect to PCLK and VPBECLK
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Table 6-44. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and VPBECLK (1) (see Figure 6-25)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
11
td(PCLK-VCTLV)
Delay time, PCLK edge to VCTL valid
12
td(PCLK-VCTLIV)
Delay time, PCLK edge to VCTL invalid
13
td(PCLK-VDATAV)
Delay time, PCLK edge to VDATA valid
14
td(PCLK-VDATAIV)
Delay time, PCLK edge to VDATA invalid
29
td(VPBECLK-VCTLV)
Delay time, VPBECLK rising edge to VCTL valid
30
td(VPBECLK-VCTLIV)
Delay time, VPBECLK rising edge to VCTL invalid
31
td(VPBECLK-VDATAV)
Delay time, VPBECLK rising edge to VDATA valid
32
td(VPBECLK-VDATAIV)
Delay time, VPBECLK rising edge to VDATA invalid
(1)
UNIT
MAX
14
2.5
ns
ns
14
2.5
ns
ns
14
2.5
ns
ns
14
2.5
ns
ns
PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
11, 29
12, 30
13, 31
14, 32
VCTL(A)
VDATA(B)
A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-25. VPBE Output Timing With Respect to PCLK and VPBECLK
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Table 6-45. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK (1) (2) (3) (see Figure 6-26)
NO.
(1)
(2)
(3)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
UNIT
MIN
MAX
13.33
160
17
tc(VCLK)
Cycle time, VCLK
18
tw(VCLKH)
Pulse duration, VCLK high
0.4C
ns
19
tw(VCLKL)
Pulse duration, VCLK low
0.4C
ns
20
tt(VCLK)
Transition time, VCLK
7
ns
21
td(VCLKINH-VCLKH)
Delay time, VCLKIN high to VCLK high
1
9
ns
22
td(VCLKINL-VCLKL)
Delay time, VCLKIN low to VCLK low
1
9
ns
23
td(VCLK-VCTLV)
Delay time, VCLK edge to VCTL valid
9
ns
24
td(VCLK-VCTLIV)
Delay time, VCLK edge to VCTL invalid
25
td(VCLK-VDATAV)
Delay time, VCLK edge to VDATA valid
26
td(VCLK-VDATAIV)
Delay time, VCLK edge to VDATA invalid
0.6
ns
ns
9
0.6
ns
ns
The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
VCLKIN = PCLK or VPBECLK
C = VCLK period in ns.
VCLKIN(A)
21
VCLK
18
17
22
19
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
23
24
25
26
20
20
VCTL(B)
VDATA(C)
A. VCLKIN = PCLK or VPBECLK
B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-26. VPBE Control and Data Output Timing With Respect to VCLK
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6.10.2.4 DAC Electrical Data/Timing
Table 6-46. Switching Characteristics Over Recommended Operating Conditions for DAC Static
Specifications
NO.
PARAMETER
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
TEST CONDITIONS
MIN
DC Accuracy
Integral Non-Linearity (INL)
Differential Non-Linearity (DNL)
Analog Output
Offset Error
Gain Error
Full-Scale Output Voltage
TYP
-1.0
-0.5
RLOAD = 500 Ω
Output Capacitance
Reference
Reference Voltage Range (VREF)
Full-Scale Current Adjust Resistor (RBIAS)
0.475
3.3
UNIT
MAX
1.0
0.5
LSB
LSB
0.5
5
500
LSB
%FS
mVPP
200
pF
0.5
4.0
0.525
4.4
V
kΩ
Table 6-47. Switching Characteristics Over Recommended Operating Conditions for DAC Dynamic
Specifications
NO.
PARAMETER
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
TEST CONDITIONS
MIN
Output Update Rate (FCLK)
Signal Bandwidth
FCLK = 27 MHz
SFDR to Nyquist
FOUT = 2.0 MHz
FCLK = 60 MHz
FOUT = 2.0 MHz
FCLK = 27 MHz
SFDR within Bandwidth
FOUT = 2.0 MHz
FCLK = 60 MHz
FOUT = 2.0 MHz
PSRR Over Temp vs Power Supply
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UNIT
TYP
MAX
27
60
MHz
6
MHz
60
dB
60
dB
60
db
60
dB
dB
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The DM6437's analog video DAC outputs are designed to drive a 500-Ω load. Figure 6-27 describes a
typical circuit that will permit connecting the analog video output from the DM6437 device to standard
75-Ω impedance video systems. Another solution is to use a Video Amplifier, such as the Texas
Instruments' OPA361, which provides a complete solution to the typical output circuit shown in
Figure 6-27.
DAC
IOUT
Low-Pass Filter
fc = 6.5 MHz
~RLOAD = 500 Ω
Amplifier
Gain = 5.6 V/V
75 Ω
75 Ω
Figure 6-27. Typical Output Circuit for NTSC/PAL Video From DACs
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6.11 Universal Asynchronous Receiver/Transmitter (UART)
DM6437 has 2 UART peripherals. Each UART has the following features:
• 16-byte storage space for both the transmitter and receiver FIFOs
• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• Programmable auto-rts and auto-cts for autoflow control
• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
• Prioritized interrupts
• Programmable serial data formats
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity bit generation and detection
– 1, 1.5, or 2 stop bit generation
• False start bit detection
• Line break generation and detection
• Internal diagnostic capabilities
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Modem control functions (CTS, RTS) on UART0 only.
The UART0/1 registers are listed in Table 6-48 and Table 6-49 .
6.11.1 UART Peripheral Register Description(s)
Table 6-48. UART0 Register Descriptions
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01C2 0000
RBR
UART0 Receiver Buffer Register (Read Only)
0x01C2 0000
THR
UART0 Transmitter Holding Register (Write Only)
0x01C2 0004
IER
UART0 Interrupt Enable Register
0x01C2 0008
IIR
UART0 Interrupt Identification Register (Read Only)
0x01C2 0008
FCR
UART0 FIFO Control Register (Write Only)
0x01C2 000C
LCR
UART0 Line Control Register
0x01C2 0010
MCR
UART0 Modem Control Register
0x01C2 0014
LSR
UART0 Line Status Register
0x01C2 0018
-
Reserved
0x01C2 001C
-
Reserved
0x01C2 0020
DLL
UART0 Divisor Latch (LSB)
0x01C2 0024
DLH
UART0 Divisor Latch (MSB)
0x01C2 0028
PID1
Peripheral Identification Register 1
0x01C2 002C
PID2
Peripheral Identification Register 2
0x01C2 0030
PWREMU_MGMT
UART0 Power and Emulation Management Register
0x01C2 0034 - 0x01C2 03FF
-
Reserved
Table 6-49. UART1 Register Descriptions
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01C2 0400
RBR
UART1 Receiver Buffer Register (Read Only)
0x01C2 0400
THR
UART1 Transmitter Holding Register (Write Only)
0x01C2 0404
IER
UART1 Interrupt Enable Register
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Table 6-49. UART1 Register Descriptions (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01C2 0408
IIR
UART1 Interrupt Identification Register (Read Only)
0x01C2 0408
FCR
UART1 FIFO Control Register (Write Only)
0x01C2 040C
LCR
UART1 Line Control Register
0x01C2 0410
MCR
UART1 Modem Control Register
0x01C2 0414
LSR
UART1 Line Status Register
0x01C2 0418
-
Reserved
0x01C2 041C
-
Reserved
0x01C2 0420
DLL
UART1 Divisor Latch (LSB)
0x01C2 0424
DLH
UART1 Divisor Latch (MSB)
0x01C2 0428
PID1
Peripheral Identification Register 1
0x01C2 042C
PID2
Peripheral Identification Register 2
0x01C2 0430
PWREMU_MGMT
UART1 Power and Emulation Management Register
0x01C2 0434 - 0x01C2 07FF
-
Reserved
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6.11.2 UART Electrical Data/Timing
Table 6-50. Timing Requirements for UARTx Receive (1) (see Figure 6-28)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
(1)
UNIT
MIN
MAX
4
tw(URXDB)
Pulse duration, receive data bit (URXDx) [15/30/100 pF]
0.96U
1.05U
ns
5
tw(URXSB)
Pulse duration, receive start bit [15/30/100 pF]
0.96U
1.05U
ns
U = UART baud time = 1/programmed baud rate.
Table 6-51. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1)
(see Figure 6-28)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
(1)
UNIT
MAX
1
f(baud)
Maximum programmable baud rate
2
tw(UTXDB)
Pulse duration, transmit data bit (UTXDx) [15/30/100 pF]
U-2
U+2
128
kHz
ns
3
tw(UTXSB)
Pulse duration, transmit start bit [15/30/100 pF]
U-2
U+2
ns
U = UART baud time = 1/programmed baud rate.
3
2
UTXDx
Start
Bit
Data Bits
5
4
URXDx
Start
Bit
Data Bits
Figure 6-28. UART Transmit/Receive Timing
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6.12 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between DM6437 and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise Filter to Remove Noise 50 ns or less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
• Events: DMA, Interrupt, or Polling
• Slew-Rate Limited Open-Drain Output Buffers
I2C Module
Clock
Prescale
Peripheral Clock
(DSP/18)
ICPSC
Control
Bit Clock
Generator
SCL
Noise
Filter
I2C Clock
ICCLKH
ICOAR
Own
Address
ICSAR
Slave
Address
ICMDR
Mode
ICCNT
Data
Count
ICCLKL
Transmit
ICXSR
Transmit
Shift
ICDXR
Transmit
Buffer
ICEMDR
Extended
Mode
SDA
I2C Data
Interrupt/DMA
Noise
Filter
Receive
ICDRR
Receive
Buffer
ICRSR
Receive
Shift
ICIMR
Interrupt
Mask/Status
ICSTR
Interrupt
Status
ICIVR
Interrupt
Vector
Shading denotes control/status registers.
Figure 6-29. I2C Module Block Diagram
For more detailed information on the I2C peripheral, see Section 2.9, Documentation Support section of
this document for the TMS320DM643x DMP Peripherals Overview Reference Guide (literature number
SPRU983).
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I2C Peripheral Register Description(s)
Table 6-52. I2C Registers
238
HEX ADDRESS RANGE
ACRONYM
0x1C2 1000
ICOAR
I2C Own Address Register
REGISTER NAME
0x1C2 1004
ICIMR
I2C Interrupt Mask Register
0x1C2 1008
ICSTR
I2C Interrupt Status Register
0x1C2 100C
ICCLKL
I2C Clock Divider Low Register
0x1C2 1010
ICCLKH
I2C Clock Divider High Register
0x1C2 1014
ICCNT
I2C Data Count Register
0x1C2 1018
ICDRR
I2C Data Receive Register
0x1C2 101C
ICSAR
I2C Slave Address Register
0x1C2 1020
ICDXR
I2C Data Transmit Register
0x1C2 1024
ICMDR
I2C Mode Register
0x1C2 1028
ICIVR
I2C Interrupt Vector Register
0x1C2 102C
ICEMDR
I2C Extended Mode Register
0x1C2 1030
ICPSC
I2C Prescaler Register
0x1C2 1034
ICPID1
I2C Peripheral Identification Register 1
0x1C2 1038
ICPID2
I2C Peripheral Identification Register 2
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I2C Electrical Data/Timing
6.12.2.1
Inter-Integrated Circuits (I2C) Timing
Table 6-53. Timing Requirements for I2C Timings (1) (see Figure 6-30)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
STANDARD
MODE
MIN
1
(1)
(2)
(3)
(4)
(5)
UNIT
FAST MODE
MAX
MIN
MAX
tc(SCL)
Cycle time, SCL
10
2.5
µs
2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
µs
3
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
µs
4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100 (2)
7
th(SDA-SCLL)
Hold time, SDA valid after SCL low
0 (3)
0 (3)
8
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
(5)
ns
0.9 (4)
µs
µs
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
300
ns
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb (5)
300
ns
(5)
300
ns
300
11
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
12
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb (5)
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
14
tw(SP)
Pulse duration, spike (must be suppressed)
15
Cb (5)
Capacitive load for each bus line
4
0.6
ns
µs
0
400
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-30. I2C Receive Timings
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Table 6-54. Switching Characteristics for I2C Timings (1) (see Figure 6-31)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
PARAMETER
STANDARD
MODE
MIN
UNIT
FAST MODE
MAX
MIN
MAX
16
tc(SCL)
Cycle time, SCL
10
2.5
µs
17
td(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START
condition)
4.7
0.6
µs
18
td(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
4
0.6
µs
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
td(SDAV-SCLH)
Delay time, SDA valid to SCL high
250
100
ns
22
tv(SCLL-SDAV)
Valid time, SDA valid after SCL low
0
0
23
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
24
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb (1)
300
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb (1)
300
ns
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb (1)
300
ns
27
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb (1)
300
ns
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
29
Cp
Capacitance for each I2C pin
10
pF
(1)
4
0.9
µs
0.6
10
µs
µs
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-31. I2C Transmit Timings
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6.13 Host-Port Interface (HPI) Peripheral
6.13.1 HPI Device-Specific Information
The DM6437 device includes a user-configurable 16-bit Host-port interface (HPI16).
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the
DM6437.
The DM6437 HPI does not support the HAS feature. For proper device operation, the HAS pin must be
pulled up via an external resistor.
6.13.2 HPI Peripheral Register Description(s)
Table 6-55. HPI Control Registers
(1)
HEX ADDRESS RANGE
ACRONYM
01C6 7800
PID
REGISTER NAME
01C6 7804
PWREMU_MGMT
01C6 7808 - 01C6 7824
-
Reserved
01C6 7828
-
Reserved
01C6 782C
-
Reserved
01C6 7830
HPIC
HPI control register
01C6 7834
HPIA
(HPIAW) (1)
HPI address register
(Write)
01C6 7838
HPIA
(HPIAR) (1)
HPI address register
(Read)
01C6 780C - 01C6 7FFF
-
COMMENTS
Peripheral Identification Register
HPI power and emulation management register
The CPU has read/write
access to the
PWREMU_MGMT register.
The Host and the CPU both
have read/write access to the
HPIC register.
The Host has read/write
access to the HPIA registers.
The CPU has only read
access to the HPIA registers.
Reserved
There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently. For more details about the HPIA registers and their
modes, see the TMS320DM643x DMP Host Port Interface (HPI) User's Guide (literature number SPRU998).
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6.13.3 HPI Electrical Data/Timing
Table 6-56. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Figure 6-32 and Figure 6-33)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
1
tsu(SELV-HSTBL)
Setup time, select signals (3) valid before HSTROBE low
5
ns
2
th(HSTBL-SELV)
Hold time, select signals (3) valid after HSTROBE low
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE active low
15
ns
4
tw(HSTBH)
Pulse duration, HSTROBE inactive high between consecutive accesses
2M
ns
11
tsu(HDV-HSTBH)
Setup time, host data valid before HSTROBE high
5
ns
12
th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
0
ns
th(HRDYL-HSTBL)
Hold time, HSTROBE high after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
0
ns
13
(1)
(2)
(3)
242
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
M = SYSCLK3 period = (CPU clock frequency)/6 in ns. For example, when running parts at 600 MHz, use M = 10 ns.
Select signals include: HCNTL[1:0], HR/W and HHWIL.
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Table 6-57. Switching Characteristics for Host-Port Interface Cycles (1) (2) (3)
(see Figure 6-32 and Figure 6-33)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
UNIT
MAX
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full
or flushing (can be either first or
second half-word)
Case 4: HPIA write and Write FIFO not
empty
5
td(HSTBL-HRDYV)
Delay time, HSTROBE low to
HRDY valid
6
ten(HSTBL-HD)
Enable time, HD driven from HSTROBE low
7
td(HRDYL-HDV)
Delay time, HRDY low to HD valid
8
toh(HSTBH-HDV)
Output hold time, HD valid after HSTROBE high
14
tdis(HSTBH-HDV)
Disable time, HD high-impedance from HSTROBE high
15
18
(1)
(2)
(3)
For HPI Read, HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with
auto-increment) and data not in Read
FIFO (can only happen to first
half-word of HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without
auto-increment and data is already in
Read FIFO (always applies to second
half-word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
td(HSTBL-HDV)
td(HSTBH-HRDYV)
12
2
ns
ns
0
1.5
ns
ns
12
ns
Delay time, HSTROBE low to
HD valid
For HPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is
already in Read FIFO
Case 3: Second half-word of HPID
read with or without auto-increment
15
ns
Delay time, HSTROBE high to
HRDY valid
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: HPID write when Write FIFO is
full (can happen to either half-word)
Case 2: HPIA write (can happen to
either half-word)
Case 3: HPID write without
auto-increment (only happens to
second half-word)
12
ns
M = SYSCLK3 period = (CPU clock frequency)/6 in ns. For example, when running parts at 600 MHz, use M = 10 ns.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
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HCS
HAS(D)
2
2
1
1
HCNTL[1:0]
2
1
2
1
HR/W
2
2
1
1
HHWIL
4
3
3
HSTROBE(A)(C)
15
15
14
14
6
8
HD[15:0]
(output)
5
13
7
8
6
1st Half-Word
2nd Half-Word
HRDY(B)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User’s Guide
(literature number SPRU998).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are
reflected by parameters for HSTROBE.
D For proper HPI operation, HAS must be pulled up via an external resistor.
Figure 6-32. HPI16 Read Timing (HAS Not Used, Tied High)
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HCS
HAS(D)
1
1
2
2
HCNTL[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
3
3
4
HSTROBE(A)(C)
11
HD[15:0]
(input)
11
12
12
1st Half-Word
5
13
2nd Half-Word
18
13
18
5
HRDY(B)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User’s Guide (literature number
SPRU998).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by
parameters for HSTROBE.
D For proper HPI operation, HAS must be pulled up via an external resistor.
Figure 6-33. HPI16 Write Timing (HAS Not Used, Tied High)
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6.14 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must
always be set to a value of 1 or greater.
For more detailed information on the McBSP peripheral, see the TMS320DM643x DMP Multichannel
Buffered Serial Port (McBSP) User's Guide (literature number SPRU943).
6.14.1 McBSP Peripheral Register Description(s)
Table 6-58. McBSP 0 Registers
HEX ADDRESS RANGE
01D0 0000
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA3
controller can only read
this register; they cannot
write to it.
DRR0
McBSP0 Data Receive Register
01D0 0004
DXR0
McBSP0 Data Transmit Register
01D0 0008
SPCR0
01D0 000C
RCR0
McBSP0 Receive Control Register
01D0 0010
XCR0
McBSP0 Transmit Control Register
01D0 0014
SRGR0
01D0 0018
MCR0
01D0 001C
RCERE00
McBSP0 Enhanced Receive Channel Enable Register
0 Partition A/B
01D0 0020
XCERE00
McBSP0 Enhanced Transmit Channel Enable Register
0 Partition A/B
01D0 0024
PCR0
01D0 0028
RCERE10
McBSP0 Enhanced Receive Channel Enable Register
1 Partition C/D
01D0 002C
XCERE10
McBSP0 Enhanced Transmit Channel Enable Register
1 Partition C/D
01D0 0030
RCERE20
McBSP0 Enhanced Receive Channel Enable Register
2 Partition E/F
01D0 0034
XCERE20
McBSP0 Enhanced Transmit Channel Enable Register
2 Partition E/F
01D0 0038
RCERE30
McBSP0 Enhanced Receive Channel Enable Register
3 Partition G/H
01D0003C
XCERE30
McBSP0 Enhanced Transmit Channel Enable Register
3 Partition G/H
01D0 0040 - 01D0 07FF
-
McBSP0 Serial Port Control Register
McBSP0 Sample Rate Generator register
McBSP0 Multichannel Control Register
McBSP0 Pin Control Register
Reserved
Table 6-59. McBSP 1 Registers
246
HEX ADDRESS RANGE
ACRONYM
01D0 0800
DRR1
REGISTER NAME
McBSP1 Data Receive Register
Peripheral Information and Electrical Specifications
COMMENTS
The CPU and EDMA
controller can only read
this register; they cannot
write to it.
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Table 6-59. McBSP 1 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
01D0 0804
DXR1
01D0 0808
SPCR1
McBSP1 serial port control register
01D0 080C
RCR1
McBSP1 Receive Control Register
01D0 0810
XCR1
McBSP1 Transmit Control Register
01D0 0814
SRGR1
01D0 0818
MCR1
01D0 081C
RCERE01
McBSP1 Enhanced Receive Channel Enable Register
0 Partition A/B
01D0 0820
XCERE01
McBSP1 Enhanced Transmit Channel Enable Register
0 Partition A/B
01D0 0824
PCR1
01D0 0828
RCERE11
McBSP1 Enhanced Receive Channel Enable Register
1 Partition C/D
01D0 082C
XCERE11
McBSP1 Enhanced Transmit Channel Enable Register
1 Partition C/D
01D0 0830
RCERE21
McBSP1 Enhanced Receive Channel Enable Register
2 Partition E/F
01D0 0834
XCERE21
McBSP1 Enhanced Transmit Channel Enable Register
2 Partition E/F
01D0 0838
RCERE31
McBSP1 Enhanced Receive Channel Enable Register
3 Partition G/H
01D0 083C
XCERE31
McBSP1 Enhanced Transmit Channel Enable Register
3 Partition G/H
01D0 0840 - 01D0 0FFF
-
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REGISTER NAME
COMMENTS
McBSP1 Data Transmit Register
McBSP1 sample rate generator register
McBSP1 multichannel control register
McBSP1 Pin Control Register
Reserved
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6.14.2 McBSP Electrical Data/Timing
6.14.2.1
Multichannel Buffered Serial Port (McBSP) Timing
Table 6-60. Timing Requirements for McBSP (1) (see Figure 6-34)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P (2) (3)
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P - 1 (4)
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
(1)
(2)
(3)
(4)
248
CLKR int
14
CLKR ext
4
CLKR int
6
CLKR ext
4
CLKR int
14
CLKR ext
4
CLKR int
3
CLKR ext
3.5
CLKX int
14
CLKX ext
4
CLKX int
6
CLKX ext
3
ns
ns
ns
ns
ns
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
Peripheral Information and Electrical Specifications
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Table 6-61. Switching Characteristics Over Recommended Operating Conditions for McBSP (1) (2)
(see Figure 6-34)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input
2
tc(CKRX)
Cycle time, CLKR/X
(2)
(3)
(4)
(5)
(6)
(7)
(8)
3
CLKR/X int
2P (3) (4) (5)
(6)
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
-4
5.5
CLKX int
-4
5.5
CLKX ext
2.5
14.5
CLKX int
-5.5
7.5
CLKX ext
-2.1
16
CLKX int
-4 + D1 (7)
5.5 + D2 (7)
(7)
14.5 + D2 (7)
Delay time, CLKX high to internal FSX valid
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following
last data bit from CLKX high
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
td(FXH-DXV)
CLKX ext
2.5 + D1
C+2
ns
tw(CKRX)
td(CKXH-FXV)
ns
(6)
4
9
C-2
10
3
14
(1)
UNIT
MAX
Delay time, FSX high to DX valid
FSX int
-4 (8)
5 (8)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1 (8)
14.5 (8)
ns
ns
ns
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
Use whichever value is greater.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
DR
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
14
13 (A)
Bit(n-1)
12
DX
A.
Bit 0
13 (A)
(n-2)
(n-3)
Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Figure 6-34. McBSP Timing(B)
Table 6-62. Timing Requirements for FSR When GSYNC = 1 (see Figure 6-35)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
1
tsu(FRH-CKSH)
Setup time, FSR high before CLKS high
4
ns
2
th(CKSH-FRH)
Hold time, FSR high after CLKS high
4
ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 6-35. FSR Timing When GSYNC = 1
250
Peripheral Information and Electrical Specifications
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Table 6-63. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1) (2)
(see Figure 6-36)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MASTER
MIN
(1)
(2)
4
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
5
th(CKXL-DRV)
Hold time, DR valid after CLKX low
UNIT
SLAVE
MAX
MIN
MAX
14
2 - 3P
ns
4
5 + 6P
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
Table 6-64. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0 (1) (2) (see Figure 6-36)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
(1)
(2)
(3)
(4)
(5)
PARAMETER
MASTER (3)
(4)
1
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2
td(FXL-CKXH)
Delay time, FSX low to CLKX high (5)
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following
last data bit from CLKX low
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
8
td(FXL-DXV)
Delay time, FSX low to DX valid
UNIT
SLAVE
MIN
MAX
T-4
T + 5.5
L-4
L+4
-4
5.5
L-6
L + 7.5
MIN
MAX
ns
ns
3P + 2.8
5P + 17
ns
ns
P+3
3P + 17
ns
2P + 1.8
4P + 17
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = 2P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 6-65. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1) (2)
(see Figure 6-37)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MASTER
MIN
(1)
(2)
252
4
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
UNIT
SLAVE
MAX
MIN
MAX
14
2 - 3P
ns
4
5 + 6P
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
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Table 6-66. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0 (1) (2) (see Figure 6-37)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
(1)
(2)
(3)
(4)
(5)
PARAMETER
MASTER (3)
UNIT
SLAVE
MIN
MAX
1
th(CKXL-FXL)
Hold time, FSX low after CLKX low (4)
L-4
L + 5.5
MIN
MAX
ns
2
td(FXL-CKXH)
Delay time, FSX low to CLKX high (5)
T-4
T+4
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
-4
5.5
3P + 2.8
5P + 17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following
last data bit from CLKX low
-6
7.5
3P + 2
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
H-4
H + 5.5
2P + 2
4P + 17
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = 2P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
6
Bit 0
7
FSX
DX
3
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Table 6-67. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1) (2)
(see Figure 6-38)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MASTER
MIN
(1)
(2)
4
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
UNIT
SLAVE
MAX
MIN
MAX
14
2 - 3P
ns
4
5 + 6P
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
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Table 6-68. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1 (1) (2) (see Figure 6-38)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
(1)
(2)
PARAMETER
MASTER (3)
UNIT
SLAVE
MIN
MAX
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high (4)
T-4
T + 5.5
MIN
MAX
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low (5)
H-4
H+4
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
-4
5.5
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following
last data bit from CLKX high
H-6
H + 7.5
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
8
td(FXL-DXV)
Delay time, FSX low to DX valid
3P + 2.8
5P + 17
ns
ns
P+3
3P + 17
ns
2P + 2
4P + 17
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = 2P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
(3)
(4)
(5)
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Table 6-69. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1) (2)
(see Figure 6-39)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MASTER
MIN
(1)
(2)
254
4
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
UNIT
SLAVE
MAX
MIN
MAX
14
2 - 3P
ns
4
5+ 6P
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
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Table 6-70. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1 (1) (2) (see Figure 6-39)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
(1)
(2)
(3)
(4)
(5)
PARAMETER
MASTER (3)
UNIT
SLAVE
MIN
MAX
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high (4)
H-4
H + 5.5
MIN
MAX
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low (5)
T-4
T+4
ns
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
-4
5.5
3P + 2.8
5P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following
last data bit from CLKX high
-6
7.5
3P + 2
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
L-4
L+ 5.5
2P + 2
4P + 17
ns
P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = 2P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
6
DX
7
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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TMS320DM6437
Digital Media Processor
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6.15
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Multichannel Audio Serial Port (McASP0) Peripheral
The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel
audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated
Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).
6.15.1
McASP0 Device-Specific Information
The DM6437 device includes one multichannel audio serial port (McASP) interface peripheral (McASP0).
The McASP0 is a serial port optimized for the needs of multichannel audio applications.
The McASP0 consists of a transmit and receive section. These sections can operate completely
independently with different data formats, separate master clocks, bit clocks, and frame syncs or
alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a
pool of 16 shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM
synchronous serial format.
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive
format at a time. All transmit shift registers use the same format and all receive shift registers use the
same format. However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for
non-audio data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling,
as well as error management.
For more detailed information on and the functionality of the McASP0 peripheral, see the TMS320DM643x
DMP Multichannel Audio Serial Port (McASP) User's Guide (literature number SPRU980).
256
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6.15.1.1
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
McASP Block Diagram
Figure 6-40 illustrates the major blocks along with external signals of the TMS320DM6437 McASP0
peripheral; and shows the 4 serial data [AXR] pins.
McASP0
DIT
RAM
Transmit
Frame Sync
Generator
AFSX0
Transmit
Clock Check
(HighFrequency)
Transmit
Clock
Generator
AHCLKX0
ACLKX0
AMUTE0
AMUTEIN0
Receive
Clock Check
(HighFrequency)
Receive
Clock
Generator
Transmit
Data
Formatter
Receive
Frame Sync
Generator
INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
DMA Receive
DMS Transmit
Error
Detect
Receive
Data
Formatter
AHCLKR0
ACLKR0
AFSR0
Serializer 0
AXR0[0]
Serializer 1
AXR0[1]
Serializer 2
AXR0[2]
Serializer 3
AXR0[3]
GPIO
Control
Figure 6-40. McASP0 Configuration
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6.15.1.2
www.ti.com
McASP0 Peripheral Register Description(s)
Table 6-71. McASP0 Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
01D0 1000
PID
01D0 1004
–
Reserved
01D0 1008
–
Reserved
01D0 100C
–
Reserved
01D0 1010
PFUNC
Pin function register
01D0 1014
PDIR
Pin direction register
Peripheral Identification register [Register value: 0x0010 0101]
01D0 1018
–
Reserved
01D0 101C
–
Reserved
01D0 1020
–
Reserved
01D0 1024 – 01D0 1040
–
Reserved
01D0 1044
GBLCTL
Global control register
01D0 1048
AMUTE
Mute control register
01D0 104C
DLBCTL
Digital Loop-back control register
DIT mode control register
01D0 1050
DITCTL
01D0 1054 – 01D0 105C
–
01D0 1060
RGBLCTL
01D0 1064
RMASK
01D0 1068
RFMT
01D0 106C
AFSRCTL
Reserved
Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
Receiver format UNIT bit mask register
Receive bit stream format register
Receive frame sync control register
01D0 1070
ACLKRCTL
01D0 1074
AHCLKRCTL
01D0 1078
RTDM
01D0 107C
RINTCTL
01D0 1080
RSTAT
Status register – Receiver
01D0 1084
RSLOT
Current receive TDM slot register
01D0 1088
RCLKCHK
01D0 108C – 01D0 109C
–
01D0 10A0
XGBLCTL
01D0 10A4
XMASK
01D0 10A8
XFMT
01D0 10AC
AFSXCTL
258
Receive clock control register
High-frequency receive clock control register
Receive TDM slot 0–31 register
Receiver interrupt control register
Receiver clock check control register
Reserved
Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
Transmit format UNIT bit mask register
Transmit bit stream format register
Transmit frame sync control register
01D0 10B0
ACLKXCTL
01D0 10B4
AHCLKXCTL
Transmit clock control register
01D0 10B8
XTDM
Transmit TDM slot 0–31 register
01D0 10BC
XINTCTL
Transmit interrupt control register
High-frequency Transmit clock control register
01D0 10C0
XSTAT
Status register – Transmitter
01D0 10C4
XSLOT
Current transmit TDM slot
01D0 10C8
XCLKCHK
Transmit clock check control register
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-71. McASP0 Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
01D0 10CC – 01D0 10FC
–
REGISTER NAME
01D0 1100
DITCSRA0
Left (even TDM slot) channel status register file
01D0 1104
DITCSRA1
Left (even TDM slot) channel status register file
01D0 1108
DITCSRA2
Left (even TDM slot) channel status register file
01D0 110C
DITCSRA3
Left (even TDM slot) channel status register file
01D0 1110
DITCSRA4
Left (even TDM slot) channel status register file
01D0 1114
DITCSRA5
Left (even TDM slot) channel status register file
01D0 1118
DITCSRB0
Right (odd TDM slot) channel status register file
01D0 111C
DITCSRB1
Right (odd TDM slot) channel status register file
01D0 1120
DITCSRB2
Right (odd TDM slot) channel status register file
01D0 1124
DITCSRB3
Right (odd TDM slot) channel status register file
01D0 1128
DITCSRB4
Right (odd TDM slot) channel status register file
01D0 112C
DITCSRB5
Right (odd TDM slot) channel status register file
01D0 1130
DITUDRA0
Left (even TDM slot) user data register file
01D0 1134
DITUDRA1
Left (even TDM slot) user data register file
Reserved
01D0 1138
DITUDRA2
Left (even TDM slot) user data register file
01D0 113C
DITUDRA3
Left (even TDM slot) user data register file
01D0 1140
DITUDRA4
Left (even TDM slot) user data register file
01D0 1144
DITUDRA5
Left (even TDM slot) user data register file
01D0 1148
DITUDRB0
Right (odd TDM slot) user data register file
01D0 114C
DITUDRB1
Right (odd TDM slot) user data register file
01D0 1150
DITUDRB2
Right (odd TDM slot) user data register file
01D0 1154
DITUDRB3
Right (odd TDM slot) user data register file
01D0 1158
DITUDRB4
Right (odd TDM slot) user data register file
01D0 115C
DITUDRB5
Right (odd TDM slot) user data register file
01D0 1160 – 01D0 117C
–
01D0 1180
SRCTL0
Reserved
Serializer 0 control register
01D0 1184
SRCTL1
Serializer 1 control register
01D0 1188
SRCTL2
Serializer 2 control register
Serializer 3 control register
01D0 118C
SRCTL3
01D0 1190 – 01D0 11FC
–
01D0 1200
XBUF0
Transmit Buffer for Serializer 0
01D0 1204
XBUF1
Transmit Buffer for Serializer 1
01D0 1208
XBUF2
Transmit Buffer for Serializer 2
01D0 120C
XBUF3
Transmit Buffer for Serializer 3
Reserved
01D0 1210 – 01D0 127C
–
01D0 1280
RBUF0
Reserved
Receive Buffer for Serializer 0
01D0 1284
RBUF1
Receive Buffer for Serializer 1
01D0 1288
RBUF2
Receive Buffer for Serializer 2
01D0 128C
RBUF3
Receive Buffer for Serializer 3
01D0 1290 – 01D0 13FF
–
Reserved
Table 6-72. McASP0 Data Registers
HEX ADDRESS RANGE
01D0 1400 – 01D0 17FF
ACRONYM
RBUF/XBUF
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REGISTER NAME
McASP0 receive buffers or McASP0 transmit buffers via
the Peripheral Data Bus.
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT registers,
respectively].)
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TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
6.15.1.3
www.ti.com
McASP0 Electrical Data/Timing
6.15.1.3.1
Multichannel Audio Serial Port (McASP) Timing
Table 6-73. Timing Requirements for McASP (see Figure 6-41 and Figure 6-42) (1)
-7/-6/-5/-4
-L/-Q6/-Q5/Q4
NO.
MIN
UNIT
MAX
1
tc(AHCKRX)
Cycle time, AHCLKR/X
25
ns
2
tw(AHCKRX)
Pulse duration, AHCLKR/X high or low
10
ns
3
tc(CKRX)
Cycle time, ACLKR/X
ACLKR/X ext
25
ns
4
tw(CKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X ext
10
ns
ACLKR/X int
11
ns
ACLKR/X ext
3
ns
ACLKR/X int
0
ns
ACLKR/X ext input
4
ns
ACLKR/X ext output
6
ns
ACLKR/X int
11
ns
ACLKR/X ext
3
ns
ACLKR/X int
3
ns
ACLKR/X ext input
4
ns
ACLKR/X ext output
6
ns
5
tsu(FRX-CKRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
6
th(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
7
8
(1)
260
tsu(AXR-CKRX)
th(CKRX-AXR)
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
Peripheral Information and Electrical Specifications
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Digital Media Processor
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-74. Switching Characteristics Over Recommended Operating Conditions for McASP (1) (2)
(see Figure 6-41 and Figure 6-42) (3)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
9
tc(AHCKRX)
Cycle time, AHCLKR/X
10
tw(AHCKRX)
Pulse duration, AHCLKR/X high or low
UNIT
MAX
25
ns
AH - 2.5
ns
25
ns
ns
11
tc(CKRX)
Cycle time, ACLKR/X
ACLKR/X
int
12
tw(CKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X
int
A - 2.5
ACLKR/X
int
-2.25
5.5
ns
ACLKR/X
ext input
0
12.5
ns
ACLKR/X
ext output
0
14
ns
ACLKX int
-2.25
5.5
ns
ACLKX
ext input
0
12.5
ns
ACLKX
ext output
0
14
ns
ACLKR/X
int
-4.5
8
ns
ACLKR/X
ext
-4.5
12.5
ns
13
14
15
(1)
(2)
(3)
td(CKRX-FRX)
td(CKX-AXRV)
tdis(CKRX-AXRHZ)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKX transmit edge to AXR output valid
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
A = (ACLKR/X period)/2 in ns. For example, when ACLKR/X period is 25 ns, use A = 12.5 ns.
AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
ACLKR/X (CLKRP = CLKXP = 0)(A)
ACLKR/X (CLKRP = CLKXP = 1)(B)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0
A1
A30 A31 B0 B1
B30 B31 C0 C1
C2 C3
C31
A.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-41. McASP Input Timings
262
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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
ACLKR/X (CLKRP = CLKXP = 1)(A)
ACLKR/X (CLKRP = CLKXP = 0)(B)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
13
13
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
14
15
AXR[n] (Data Out/Transmit)
A0
A1
A30 A31 B0 B1
B30 B31 C0
C1 C2 C3
A.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
C31
Figure 6-42. McASP Output Timings
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Digital Media Processor
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6.16 High-End Controller Area Network Controller (HECC)
The DM6437 device has a High-End Controller Area Network Controllers (HECC). The HECC uses
established protocol to communicate serially with other controllers in harsh environments. The HECC is
fully compliant with the Controller Area Network (CAN) protocol, version 2.0B.
Key features of the HECC include the following:
• CAN, version 2.0B compliant
• 32 RX/TX message objects
• 32 receive identifier masks
• Programmable wake-up on bus activity
• Programmable interrupt scheme
• Automatic reply to a remote request
• Automatic re-transmission in case of error or loss of arbitration
• Protection against reception of a new message
• 32-bit time stamp
• Local network time counter
• Programmable priority register for each message
• Programmable transmission and reception time-out
• HECC/SCC mode of operation
• Standard-Extended Identifier
• Self-test mode
For more details on the HECC, see the TMS320DM643x High-End CAN Controller (HECC) User's Guide
(literature number SPRU981).
6.16.1 HECC Device-Specific Information
Software must not access "Reserved" locations of the HECC. Access to HECC "Reserved" locations may
hang the device.
264
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6.16.2
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
HECC Peripheral Register Description(s)
Table 6-75 through Table 6-78 show the High-End CAN Controller (HECC) registers. For more detailed
information, see the TMS320DM643x DMP High-End CAN Controller User’s Guide (literature number
SPRU981).
Table 6-75. HECC Control and Status Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
01C2 3000
CANME
Mailbox Enable Register
01C2 3004
CANMD
Mailbox Direction Register
01C2 3008
CANTRS
Transmission Request Set Register
01C2 300C
CANTRR
Transmission Request Reset Register
01C2 3010
CANTA
Transmission Acknowledge Register
01C2 3014
CANAA
Abort Acknowledge Register
01C2 3018
CANRMP
Receive Message Pending Register
01C2 301C
CANRML
Receive Message Lost Register
01C2 3020
CANRFP
Remote Frame Pending Register
01C2 3024
CANGAM
Global Acceptance Mask Register (SCC Mode Only)
01C2 3028
CANMC
Master Control Register
01C2 302C
CANBTC
Bit-Timing Configuration Register
01C2 3030
CANES
01C2 3034
CANTEC
Transmit Error Counter Register
Error and Status Register
01C2 3038
CANREC
Receive Error Counter Register
01C2 303C
CANGIF0
Global Interrupt Flag 0 Register
01C2 3040
CANGIM
Global Interrupt Mask Register
01C2 3044
CANGIF1
Global Interrupt Flag 1 Register
01C2 3048
CANMIM
Mailbox Interrupt Mask Register
01C2 304C
CANMIL
Mailbox Interrupt Level Register
01C2 3050
CANOPC
Overwrite Protection Control Register
01C2 3054
CANTIOC
Transmit I/O Control Register
01C2 3058
CANRIOC
Receive I/O Control Register
01C2 305C
CANLNT
Local Network Time Register (HECC Mode Only)
01C2 3060
CANTOC
Time-Out Control Register (HECC Mode Only)
01C2 3064
CANTOS
Time-Out Status Register (HECC Mode Only)
01C2 3068 – 01C2 306C
–
01C2 3070
CANETC
01C2 3074 – 01C2 307C
–
01C2 3080
SCCLAM0
01C2 3084 – 01C2 3088
–
01C2 308C
SSCLAM3
01C2 3090 – 01C2 4FFF
–
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Reserved
Error Test Control Register
Reserved
SCC Local Acceptance Mask Register 0 (SCC Mode Only)
Reserved
SCC Local Acceptance Mask Register 3 (SCC Mode Only)
Reserved
Peripheral Information and Electrical Specifications
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Table 6-76. HECC Message Object Registers (1)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
HECC Local Acceptance Mask Registers
01C2 5000
LAM0
HECC Local Acceptance Mask Register for Mailbox 0
01C2 5004
LAM1
HECC Local Acceptance Mask Register for Mailbox 1
01C2 5008
LAM2
HECC Local Acceptance Mask Register for Mailbox 2
01C2 500C
LAM3
HECC Local Acceptance Mask Register for Mailbox 3
01C2 5010
LAM4
HECC Local Acceptance Mask Register for Mailbox 4
01C2 5014
LAM5
HECC Local Acceptance Mask Register for Mailbox 5
01C2 5018
LAM6
HECC Local Acceptance Mask Register for Mailbox 6
01C2 501C
LAM7
HECC Local Acceptance Mask Register for Mailbox 7
01C2 5020
LAM8
HECC Local Acceptance Mask Register for Mailbox 8
01C2 5024
LAM9
HECC Local Acceptance Mask Register for Mailbox 9
01C2 5028
LAM10
HECC Local Acceptance Mask Register for Mailbox 10
01C2 502C
LAM11
HECC Local Acceptance Mask Register for Mailbox 11
01C2 5030
LAM12
HECC Local Acceptance Mask Register for Mailbox 12
01C2 5034
LAM13
HECC Local Acceptance Mask Register for Mailbox 13
01C2 5038
LAM14
HECC Local Acceptance Mask Register for Mailbox 14
01C2 503C
LAM15
HECC Local Acceptance Mask Register for Mailbox 15
01C2 5040
LAM16
HECC Local Acceptance Mask Register for Mailbox 16
01C2 5044
LAM17
HECC Local Acceptance Mask Register for Mailbox 17
01C2 5048
LAM18
HECC Local Acceptance Mask Register for Mailbox 18
01C2 504C
LAM19
HECC Local Acceptance Mask Register for Mailbox 19
01C2 5050
LAM20
HECC Local Acceptance Mask Register for Mailbox 20
01C2 5054
LAM21
HECC Local Acceptance Mask Register for Mailbox 21
01C2 5058
LAM22
HECC Local Acceptance Mask Register for Mailbox 22
01C2 505C
LAM23
HECC Local Acceptance Mask Register for Mailbox 23
01C2 5060
LAM24
HECC Local Acceptance Mask Register for Mailbox 24
01C2 5064
LAM25
HECC Local Acceptance Mask Register for Mailbox 25
01C2 5068
LAM26
HECC Local Acceptance Mask Register for Mailbox 26
01C2 506C
LAM27
HECC Local Acceptance Mask Register for Mailbox 27
01C2 5070
LAM28
HECC Local Acceptance Mask Register for Mailbox 28
01C2 5074
LAM29
HECC Local Acceptance Mask Register for Mailbox 29
01C2 5078
LAM30
HECC Local Acceptance Mask Register for Mailbox 30
01C2 507C
LAM31
HECC Local Acceptance Mask Register for Mailbox 31
Message Object Time-Stamp Registers
(1)
266
01C2 5080
MOTS0
Message Object Time-Stamp Register for Mailbox 0
01C2 5084
MOTS1
Message Object Time-Stamp Register for Mailbox 1
01C2 5088
MOTS2
Message Object Time-Stamp Register for Mailbox 2
01C2 508C
MOTS3
Message Object Time-Stamp Register for Mailbox 3
01C2 5090
MOTS4
Message Object Time-Stamp Register for Mailbox 4
01C2 5094
MOTS5
Message Object Time-Stamp Register for Mailbox 5
01C2 5098
MOTS6
Message Object Time-Stamp Register for Mailbox 6
01C2 509C
MOTS7
Message Object Time-Stamp Register for Mailbox 7
01C2 50A0
MOTS8
Message Object Time-Stamp Register for Mailbox 8
01C2 50A4
MOTS9
Message Object Time-Stamp Register for Mailbox 9
01C2 50A8
MOTS10
Message Object Time-Stamp Register for Mailbox 10
01C2 50AC
MOTS11
Message Object Time-Stamp Register for Mailbox 11
All registers in this table apply to HECC mode only, they do not apply to SCC mode.
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Table 6-76. HECC Message Object Registers (continued)
HEX ADDRESS RANGE
ACRONYM
01C2 50B0
MOTS12
Message Object Time-Stamp Register for Mailbox 12
REGISTER NAME
01C2 50B4
MOTS13
Message Object Time-Stamp Register for Mailbox 13
01C2 50B8
MOTS14
Message Object Time-Stamp Register for Mailbox 14
01C2 50BC
MOTS15
Message Object Time-Stamp Register for Mailbox 15
01C2 50C0
MOTS16
Message Object Time-Stamp Register for Mailbox 16
01C2 50C4
MOTS17
Message Object Time-Stamp Register for Mailbox 17
01C2 50C8
MOTS18
Message Object Time-Stamp Register for Mailbox 18
01C2 50CC
MOTS19
Message Object Time-Stamp Register for Mailbox 19
01C2 50D0
MOTS20
Message Object Time-Stamp Register for Mailbox 20
01C2 50D4
MOTS21
Message Object Time-Stamp Register for Mailbox 21
01C2 50D8
MOTS22
Message Object Time-Stamp Register for Mailbox 22
01C2 50DC
MOTS23
Message Object Time-Stamp Register for Mailbox 23
01C2 50E0
MOTS24
Message Object Time-Stamp Register for Mailbox 24
01C2 50E4
MOTS25
Message Object Time-Stamp Register for Mailbox 25
01C2 50E8
MOTS26
Message Object Time-Stamp Register for Mailbox 26
01C2 50EC
MOTS27
Message Object Time-Stamp Register for Mailbox 27
01C2 50F0
MOTS28
Message Object Time-Stamp Register for Mailbox 28
01C2 50F4
MOTS29
Message Object Time-Stamp Register for Mailbox 29
01C2 50F8
MOTS30
Message Object Time-Stamp Register for Mailbox 30
01C2 50FC
MOTS31
Message Object Time-Stamp Register for Mailbox 31
01C2 5100
MOTO0
Message Object Time-Out Register for Mailbox 0
01C2 5104
MOTO1
Message Object Time-Out Register for Mailbox 1
01C2 5108
MOTO2
Message Object Time-Out Register for Mailbox 2
01C2 510C
MOTO3
Message Object Time-Out Register for Mailbox 3
01C2 5110
MOTO4
Message Object Time-Out Register for Mailbox 4
01C2 5114
MOTO5
Message Object Time-Out Register for Mailbox 5
01C2 5118
MOTO6
Message Object Time-Out Register for Mailbox 6
01C2 511C
MOTO7
Message Object Time-Out Register for Mailbox 7
01C2 5120
MOTO8
Message Object Time-Out Register for Mailbox 8
01C2 5124
MOTO9
Message Object Time-Out Register for Mailbox 9
01C2 5128
MOTO10
Message Object Time-Out Register for Mailbox 10
01C2 512C
MOTO11
Message Object Time-Out Register for Mailbox 11
01C2 5130
MOTO12
Message Object Time-Out Register for Mailbox 12
01C2 5134
MOTO13
Message Object Time-Out Register for Mailbox 13
Message Object Time-Out Registers
01C2 5138
MOTO14
Message Object Time-Out Register for Mailbox 14
01C2 513C
MOTO15
Message Object Time-Out Register for Mailbox 15
01C2 5140
MOTO16
Message Object Time-Out Register for Mailbox 16
01C2 5144
MOTO17
Message Object Time-Out Register for Mailbox 17
01C2 5148
MOTO18
Message Object Time-Out Register for Mailbox 18
01C2 514C
MOTO19
Message Object Time-Out Register for Mailbox 19
01C2 5150
MOTO20
Message Object Time-Out Register for Mailbox 20
01C2 5154
MOTO21
Message Object Time-Out Register for Mailbox 21
01C2 5158
MOTO22
Message Object Time-Out Register for Mailbox 22
01C2 515C
MOTO23
Message Object Time-Out Register for Mailbox 23
01C2 5160
MOTO24
Message Object Time-Out Register for Mailbox 24
01C2 5164
MOTO25
Message Object Time-Out Register for Mailbox 25
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Table 6-76. HECC Message Object Registers (continued)
HEX ADDRESS RANGE
ACRONYM
01C2 5168
MOTO26
Message Object Time-Out Register for Mailbox 26
REGISTER NAME
01C2 516C
MOTO27
Message Object Time-Out Register for Mailbox 27
01C2 5170
MOTO28
Message Object Time-Out Register for Mailbox 28
01C2 5174
MOTO29
Message Object Time-Out Register for Mailbox 29
01C2 5178
MOTO30
Message Object Time-Out Register for Mailbox 30
01C2 517C
MOTO31
Message Object Time-Out Register for Mailbox 31
Table 6-77. HECC Message Mailbox RAM (1) (2)
HEX ADDRESS RANGE
DESCRIPTION
01C2 4000 – 01C2 400F
Mailbox 0 (4 32-bit Registers)
01C2 4010 – 01C2 401F
Mailbox 1 (4 32-bit Registers)
01C2 4020 – 01C2 402F
Mailbox 2 (4 32-bit Registers)
01C2 4030 – 01C2 403F
Mailbox 3 (4 32-bit Registers)
01C2 4040 – 01C2 404F
Mailbox 4 (4 32-bit Registers)
...
...
01C2 41E0 – 01C2 41EF
Mailbox 30 (4 32-bit Registers)
01C2 41F0 – 01C2 41FF
Mailbox 31 (4 32-bit Registers)
(1)
(2)
This table summarizes the address ranges for the Message Mailboxes 0 to 31. For the contents within each Message Mailbox RAM, see
Table 6-78, Message Mailbox n RAM Entries.
For SCC mode, only Mailboxes 0 to 15 are supported.
Table 6-78. HECC Message Mailbox n RAM Entries (1)
HEX ADDRESS
OFFSET (within RAM)
(1)
(2)
268
ACRONYM (2)
MAILBOX REGISTER NAME
0
MIDn
Message Identifier Register for Mailbox n
4
MCFn
Message Control Field Register for Mailbox n
8
MDLn
Message Data Low-Word Register for Mailbox n
C
MDHn
Message Data High-Word Register for Mailbox n
For the hex address range of Mailbox n, see Table 6-77, Message Mailbox RAM. For example, Message Mailbox 0 occupies hex
address range 0x01C2 4000 – 0x01C2 400F.
The suffix "n" indicates the Message Mailbox number. For example, Message Mailbox 0 has the following Message Mailbox Registers:
MID0, MCF0, MDL0, and MDH0.
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6.16.3 HECC Electrical Data/Timing
Table 6-79. Timing Requirements for HECC Receive (1) (see Figure 6-43)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
(1)
1
f(baud)
Maximum programmable baud rate
2
tw(HECC_RX)
Pulse duration, receive data bit
UNIT
MIN
MAX
H-2
H+2
1
Mbps
ns
H = HECC baud time = 1/programmed baud rate.
Table 6-80. Switching Characteristics Over Recommended Operating Conditions for HECC Transmit (1)
(see Figure 6-43)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
(1)
3
f(baud)
Maximum programmable baud rate
4
tw(HECC_TX)
Pulse duration, transmit data bit
UNIT
MAX
1
H-2
H+2
Mbps
ns
H = HECC baud time = 1/programmed baud rate.
2
HECCx_RX
4
HECCx_TX
Figure 6-43. HECC Transmit/Receive Timing
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6.17 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6437 and the
network. The DM6437 EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100
Mbps) in either half- or full-duplex mode. The EMAC module also supports hardware flow control and
quality of service (QOS) support.
The EMAC controls the flow of packet data from the DM6437 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network.
Both the EMAC and the MDIO modules interface to the DM6437 device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
For the DM6437 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Module User's Guide (literature number SPRU941) which describes the DM6437 EMAC peripheral in
detail, see Section 2.9, Documentation Support section . For a list of supported registers and register
fields, see Table 6-81 [Ethernet MAC (EMAC) Control Registers] and Table 6-82 [EMAC Statistics
Registers] in this data manual.
6.17.1
EMAC Peripheral Register Description(s)
Table 6-81. Ethernet MAC (EMAC) Control Registers
270
HEX ADDRESS RANGE
ACRONYM
01C8 0000
TXIDVER
REGISTER NAME
01C8 0004
TXCONTROL
01C8 0008
TXTEARDOWN
01C8 0010
RXIDVER
01C8 0014
RXCONTROL
01C8 0018
RXTEARDOWN
Receive Teardown Register
01C8 0080
TXINTSTATRAW
Transmit Interrupt Status (Unmasked) Register
01C8 0084
TXINTSTATMASKED
01C8 0088
TXINTMASKSET
01C8 008C
TXINTMASKCLEAR
01C8 0090
MACINVECTOR
MAC Input Vector Register
01C8 00A0
RXINTSTATRAW
Receive Interrupt Status (Unmasked) Register
01C8 00A4
RXINTSTATMASKED
01C8 00A8
RXINTMASKSET
01C8 00AC
RXINTMASKCLEAR
Receive Interrupt Mask Clear Register
01C8 00B0
MACINTSTATRAW
MAC Interrupt Status (Unmasked) Register
01C8 00B4
MACINTSTATMASKED
01C8 00B8
MACINTMASKSET
01C8 00BC
MACINTMASKCLEAR
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown Register
Receive Identification and Version Register
Receive Control Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
01C8 0100
RXMBPENABLE
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
01C8 0104
RXUNICASTSET
Receive Unicast Enable Set Register
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Table 6-81. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
01C8 0108
RXUNICASTCLEAR
01C8 010C
RXMAXLEN
REGISTER NAME
Receive Unicast Clear Register
Receive Maximum Length Register
01C8 0110
RXBUFFEROFFSET
01C8 0114
RXFILTERLOWTHRESH
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
01C8 0120
RX0FLOWTHRESH
Receive Channel 0 Flow Control Threshold Register
01C8 0124
RX1FLOWTHRESH
Receive Channel 1 Flow Control Threshold Register
01C8 0128
RX2FLOWTHRESH
Receive Channel 2 Flow Control Threshold Register
01C8 012C
RX3FLOWTHRESH
Receive Channel 3 Flow Control Threshold Register
01C8 0130
RX4FLOWTHRESH
Receive Channel 4 Flow Control Threshold Register
01C8 0134
RX5FLOWTHRESH
Receive Channel 5 Flow Control Threshold Register
01C8 0138
RX6FLOWTHRESH
Receive Channel 6 Flow Control Threshold Register
01C8 013C
RX7FLOWTHRESH
Receive Channel 7 Flow Control Threshold Register
01C8 0140
RX0FREEBUFFER
Receive Channel 0 Free Buffer Count Register
01C8 0144
RX1FREEBUFFER
Receive Channel 1 Free Buffer Count Register
01C8 0148
RX2FREEBUFFER
Receive Channel 2 Free Buffer Count Register
01C8 014C
RX3FREEBUFFER
Receive Channel 3 Free Buffer Count Register
01C8 0150
RX4FREEBUFFER
Receive Channel 4 Free Buffer Count Register
01C8 0154
RX5FREEBUFFER
Receive Channel 5 Free Buffer Count Register
01C8 0158
RX6FREEBUFFER
Receive Channel 6 Free Buffer Count Register
01C8 015C
RX7FREEBUFFER
Receive Channel 7 Free Buffer Count Register
01C8 0160
MACCONTROL
MAC Control Register
01C8 0164
MACSTATUS
MAC Status Register
Emulation Control Register
01C8 0168
EMCONTROL
01C8 016C
FIFOCONTROL
01C8 0170
MACCONFIG
MAC Configuration Register
Soft Reset Register
FIFO Control Register (Transmit and Receive)
01C8 0174
SOFTRESET
01C8 01D0
MACSRCADDRLO
MAC Source Address Low Bytes Register (Lower 32-bits)
01C8 01D4
MACSRCADDRHI
MAC Source Address High Bytes Register (Upper 16-bits)
01C8 01D8
MACHASH1
MAC Hash Address Register 1
01C8 01DC
MACHASH2
MAC Hash Address Register 2
01C8 01E0
BOFFTEST
Back Off Test Register
01C8 01E4
TPACETEST
Transmit Pacing Algorithm Test Register
01C8 01E8
RXPAUSE
Receive Pause Timer Register
01C8 01EC
TXPAUSE
Transmit Pause Timer Register
01C8 0200 - 01C8 02FC
(see Table 6-82)
01C8 0500
MACADDRLO
MAC Address Low Bytes Register
01C8 0504
MACADDRHI
MAC Address High Bytes Register
01C8 0508
MACINDEX
01C8 0600
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
01C8 0604
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer Register
01C8 0608
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer Register
01C8 060C
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer Register
01C8 0610
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer Register
01C8 0614
TX5HDP
Transmit Channel 5 DMA Head Descriptor Pointer Register
01C8 0618
TX6HDP
Transmit Channel 6 DMA Head Descriptor Pointer Register
01C8 061C
TX7HDP
Transmit Channel 7 DMA Head Descriptor Pointer Register
01C8 0620
RX0HDP
Receive Channel 0 DMA Head Descriptor Pointer Register
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EMAC Statistics Registers
MAC Index Register
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Table 6-81. Ethernet MAC (EMAC) Control Registers (continued)
272
HEX ADDRESS RANGE
ACRONYM
01C8 0624
RX1HDP
REGISTER NAME
Receive Channel 1 DMA Head Descriptor Pointer Register
01C8 0628
RX2HDP
Receive Channel 2 DMA Head Descriptor Pointer Register
01C8 062C
RX3HDP
Receive Channel 3 DMA Head Descriptor Pointer Register
01C8 0630
RX4HDP
Receive Channel 4 DMA Head Descriptor Pointer Register
01C8 0634
RX5HDP
Receive Channel 5 DMA Head Descriptor Pointer Register
01C8 0638
RX6HDP
Receive Channel 6 DMA Head Descriptor Pointer Register
01C8 063C
RX7HDP
Receive Channel 7 DMA Head Descriptor Pointer Register
01C8 0640
TX0CP
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0644
TX1CP
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0648
TX2CP
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
01C8 064C
TX3CP
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0650
TX4CP
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0654
TX5CP
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0658
TX6CP
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
01C8 065C
TX7CP
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0660
RX0CP
Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0664
RX1CP
Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0668
RX2CP
Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
01C8 066C
RX3CP
Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0670
RX4CP
Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0674
RX5CP
Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0678
RX6CP
Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
01C8 067C
RX7CP
Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
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Table 6-82. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
01C8 0200
RXGOODFRAMES
REGISTER NAME
Good Receive Frames Register
01C8 0204
RXBCASTFRAMES
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
01C8 0208
RXMCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
01C8 020C
RXPAUSEFRAMES
Pause Receive Frames Register
01C8 0210
RXCRCERRORS
01C8 0214
RXALIGNCODEERRORS
01C8 0218
RXOVERSIZED
01C8 021C
RXJABBER
01C8 0220
RXUNDERSIZED
Receive Undersized Frames Register
(Total number of undersized frames received)
01C8 0224
RXFRAGMENTS
Receive Frame Fragments Register
01C8 0228
RXFILTERED
01C8 022C
RXQOSFILTERED
01C8 0230
RXOCTETS
01C8 0234
TXGOODFRAMES
Good Transmit Frames Register
(Total number of good frames transmitted)
Receive CRC Errors Register (Total number of frames received with
CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
Filtered Receive Frames Register
Received QOS Filtered Frames Register
Receive Octet Frames Register
(Total number of received bytes in good frames)
01C8 0238
TXBCASTFRAMES
Broadcast Transmit Frames Register
01C8 023C
TXMCASTFRAMES
Multicast Transmit Frames Register
01C8 0240
TXPAUSEFRAMES
Pause Transmit Frames Register
01C8 0244
TXDEFERRED
Deferred Transmit Frames Register
01C8 0248
TXCOLLISION
Transmit Collision Frames Register
01C8 024C
TXSINGLECOLL
01C8 0250
TXMULTICOLL
01C8 0254
TXEXCESSIVECOLL
01C8 0258
TXLATECOLL
01C8 025C
TXUNDERRUN
01C8 0260
TXCARRIERSENSE
01C8 0264
TXOCTETS
01C8 0268
FRAME64
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
Transmit and Receive 64 Octet Frames Register
01C8 026C
FRAME65T127
Transmit and Receive 65 to 127 Octet Frames Register
01C8 0270
FRAME128T255
Transmit and Receive 128 to 255 Octet Frames Register
01C8 0274
FRAME256T511
Transmit and Receive 256 to 511 Octet Frames Register
01C8 0278
FRAME512T1023
Transmit and Receive 512 to 1023 Octet Frames Register
01C8 027C
FRAME1024TUP
Transmit and Receive 1024 to 1518 Octet Frames Register
01C8 0280
NETOCTETS
01C8 0284
RXSOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
01C8 0288
RXMOFOVERRUNS
Receive FIFO or DMA Middle of Frame Overruns Register
01C8 028C
RXDMAOVERRUNS
Receive DMA Start of Frame and Middle of Frame Overruns
Register
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Table 6-83. EMAC Control Module Registers
HEX ADDRESS RANGE
ACRONYM
0x01C8 1004
EWCTL
0x01C8 1008
EWINTTCNT
REGISTER NAME
Interrupt control register
Interrupt timer count
Table 6-84. EMAC Control Module RAM
HEX ADDRESS RANGE
ACRONYM
0x01C8 2000 - 0x01C8 3FFF
274
Peripheral Information and Electrical Specifications
REGISTER NAME
EMAC Control Module Descriptor Memory
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6.17.2
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
EMAC Electrical Data/Timing
Table 6-85. Timing Requirements for MRCLK (see Figure 6-44)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
10 Mbps
100 Mbps
MIN MAX
MIN MAX
UNIT
1
tc(MRCLK)
Cycle time, MRCLK
400
40
ns
2
tw(MRCLKH)
Pulse duration, MRCLK high
140
14
ns
3
tw(MRCLKL)
Pulse duration, MRCLK low
140
14
ns
1
2
3
MRCLK
Figure 6-44. MRCLK Timing (EMAC - Receive)
Table 6-86. Timing Requirements for MTCLK (see Figure 6-44)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
10 Mbps
100 Mbps
MIN MAX
MIN MAX
UNIT
1
tc(MTCLK)
Cycle time, MTCLK
400
40
ns
2
tw(MTCLKH)
Pulse duration, MTCLK high
140
14
ns
3
tw(MTCLKL)
Pulse duration, MTCLK low
140
14
ns
1
2
3
MTCLK
Figure 6-45. MTCLK Timing (EMAC - Transmit)
Table 6-87. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (1) (see Figure 6-46)
-7/-6/-5/-4
-L/-Q6/-Q5/Q4
NO.
MIN
(1)
UNIT
MAX
1
tsu(MRXD-MRCLKH)
Setup time, receive selected signals valid before MRCLK high
8
ns
2
th(MRCLKH-MRXD)
Hold time, receive selected signals valid after MRCLK high
8
ns
Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
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1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 6-46. EMAC Receive Interface Timing
Table 6-88. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s (1) (see Figure 6-47)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
1
(1)
td(MTCLKH-MTXD)
Delay time, MTCLK high to transmit selected signals valid
MIN
MAX
2
25
UNIT
ns
Transmit selected signals include: MTXD3-MTXD0, and MTXEN.
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 6-47. EMAC Transmit Interface Timing
276
Peripheral Information and Electrical Specifications
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6.18
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
For more detailed information on the MDIO peripheral, see the Documentation Support section for the
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module Reference
Guide. For a list of supported registers and register fields, see Table 6-89 [MDIO Registers] in this data
manual.
6.18.1
Peripheral Register Description(s)
Table 6-89. MDIO Registers
HEX ADDRESS RANGE
ACRONYM
0x01C8 4000
–
0x01C8 4004
CONTROL
REGISTER NAME
Reserved
MDIO Control Register
0x01C8 4008
ALIVE
MDIO PHY Alive Status Register
0x01C8 400C
LINK
MDIO PHY Link Status Register
0x01C8 4010
LINKINTRAW
0x01C8 4014
LINKINTMASKED
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
0x01C8 4018
–
0x01C8 4020
USERINTRAW
Reserved
0x01C8 4024
USERINTMASKED
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
MDIO User Command Complete Interrupt (Unmasked) Register
0x01C8 4028
USERINTMASKSET
0x01C8 402C
USERINTMASKCLEAR
0x01C8 4030 - 0x01C8 407C
–
0x01C8 4080
USERACCESS0
MDIO User Access Register 0
0x01C8 4084
USERPHYSEL0
MDIO User PHY Select Register 0
0x01C8 4088
USERACCESS1
MDIO User Access Register 1
0x01C8 408C
USERPHYSEL1
MDIO User PHY Select Register 1
0x01C8 4090 - 0x01C8 47FF
–
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MDIO User Command Complete Interrupt Mask Clear Register
Reserved
Reserved
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6.18.2
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Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-90. Timing Requirements for MDIO Input (see Figure 6-48 and Figure 6-49)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
1
tc(MDCLK)
Cycle time, MDCLK
400
2
tw(MDCLK)
Pulse duration, MDCLK high/low
180
ns
3
tt(MDCLK)
Transition time, MDCLK
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
10
ns
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
ns
ns
5
ns
1
3
3
MDCLK
4
5
MDIO
(input)
Figure 6-48. MDIO Input Timing
Table 6-91. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-49)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
UNIT
MAX
100
ns
1
MDCLK
7
MDIO
(output)
Figure 6-49. MDIO Output Timing
6.19 Timers
The DM6437 device has 3 64-bit general-purpose timers which have the following features:
• 64-bit count-up counter
• Timer modes:
– 64-bit general-purpose timer mode (Timer 0 and 1)
– Dual 32-bit general-purpose timer mode (Timer 0 and 1)
– Watchdog timer mode (Timer 2)
• 2 possible clock sources:
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•
•
•
•
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– Internal clock
– External clock input via timer input pin TINPL (Timer 0 and 1 only)
2 operation modes:
– One-time operation (timer runs for one period then stops)
– Continuous operation (timer automatically resets after each period)
Generates interrupts to the DSP
Generates sync event to EDMA
Causes device global reset upon watchdog timer timeout (Timer 2 only)
For more detailed information, see Section 2.9, Documentation Support for the TMS320DM643x DMP
64-Bit Timer User's Guide (literature number SPRU989).
6.19.1
Timer Peripheral Register Description(s)
Table 6-92. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
0x01C2 1400
-
DESCRIPTION
0x01C2 1404
EMUMGT_CLKSPD
0x01C2 1410
TIM12
Timer 0 Counter Register 12
0x01C2 1414
TIM34
Timer 0 Counter Register 34
Reserved
Timer 0 Emulation Management/Clock Speed Register
0x01C2 1418
PRD12
Timer 0 Period Register 12
0x01C2 141C
PRD34
Timer 0 Period Register 34
0x01C2 1420
TCR
0x01C2 1424
TGCR
0x01C2 1428 - 0x01C2 17FF
-
Timer 0 Control Register
Timer 0 Global Control Register
Reserved
Table 6-93. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
0x01C2 1800
-
0x01C2 1804
EMUMGT_CLKSPD
0x01C2 1810
TIM12
Timer 1 Counter Register 12
0x01C2 1814
TIM34
Timer 1 Counter Register 34
0x01C2 1818
PRD12
Timer 1 Period Register 12
0x01C2 181C
PRD34
Timer 1 Period Register 34
0x01C2 1820
TCR
0x01C2 1824
TGCR
0x01C2 1828 - 0x01C2 1BFF
-
DESCRIPTION
Reserved
Timer 1 Emulation Management/Clock Speed Register
Timer 1 Control Register
Timer 1 Global Control Register
Reserved
Table 6-94. Timer 2 (Watchdog) Registers
HEX ADDRESS RANGE
ACRONYM
0x01C2 1C00
-
DESCRIPTION
0x01C2 1C04
EMUMGT_CLKSPD
0x01C2 1C10
TIM12
Timer 2 Counter Register 12
0x01C2 1C14
TIM34
Timer 2 Counter Register 34
Reserved
Timer 2 Emulation Management/Clock Speed Register
0x01C2 1C18
PRD12
Timer 2 Period Register 12
0x01C2 1C1C
PRD34
Timer 2 Period Register 34
0x01C2 1C20
TCR
0x01C2 1C24
TGCR
0x01C2 1C28
WDTCR
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Timer 2 Control Register
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
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Table 6-94. Timer 2 (Watchdog) Registers (continued)
HEX ADDRESS RANGE
ACRONYM
0x01C2 1C2C - 0x01C2 1FFF
-
6.19.2
DESCRIPTION
Reserved
Timer Electrical Data/Timing
Table 6-95. Timing Requirements for Timer Input (1) (2) (3) (see Figure 6-50)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
1
tw(TINPH)
2
tw(TINPL)
Pulse duration, TINPxL high
Pulse duration, TINPxL low
TINP0L, if TIMERCTL.TINP0SEL = 0
[default]
2P
ns
TINP0L, if TIMERCTL.TINP0SEL = 1
0.33P
ns
TINP1L
2P
ns
TINP0L, if TIMERCTL.TINP0SEL = 0
[default]
2P
ns
TINP0L, if TIMERCTL.TINP0SEL = 1
0.33P
ns
2P
ns
TINP1L
(1)
(2)
UNIT
MAX
P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns.
The TIMERCTL.TINP0SEL field in the System Module determines if the TINP0L input directly goes to Timer 0
(TIMERCTL.TINP0SEL=0), or if the TINP0L input is first divided down by 6 before going to Timer 0 (TIMERCTL.TINP0SEL=1).
TINP1L input goes directly to Timer 1.
(3)
Table 6-96. Switching Characteristics Over Recommended Operating Conditions for Timer Output (1) (see
Figure 6-50)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
3
tw(TOUTH)
Pulse duration, TOUTxL high
P
ns
4
tw(TOUTL)
Pulse duration, TOUTxL low
P
ns
(1)
P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns.
1
2
TINPxL
3
4
TOUTxL
Figure 6-50. Timer Timing
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6.20 Peripheral Component Interconnect (PCI)
The DM6437 DMP supports connections to PCI-compliant devices via the integrated PCI master/slave bus
interface. The PCI port interfaces to DSP internal resources via the data switched central resource. The
data switched central resource is described in more detail in Section 4, System Interconnect.
For more detailed information on the PCI port peripheral module, see the TMS320DM643x DMP
Peripheral Component Interconnect (PCI) User's Guide (literature number SPRU985).
6.20.1 PCI Device-Specific Information
The PCI peripheral can act both as a PCI bus master and as a target. It supports PCI bus operation of
speeds up to 33 MHz and uses a 32-bit data/address bus.
On the DM6437 device, the pins of the PCI peripheral are multiplexed with the pins of the VPSS, EMIFA,
GPIO, HPI, VLYNQ, and EMAC peripherals. For more detailed information on how to select PCI, see
Section 3, Device Configurations.
The DM6437 device provides an initialization mechanism through which the default values for some of the
PCI configuration registers can be read from an I2C EEPROM. Table 6-97 shows the registers which can
be initialized through the PCI auto-initialization. The default value of these registers when PCI
auto-initialization is not used is also shown in Table 6-97. PCI auto-initialization is enabled by selecting
PCI boot with auto-initialization. For information on how to select PCI boot with auto-initialization, see
Section 3.4.1, Boot Modes. For more information on PCI auto-initialization, see the TMS320DM643x DMP
Peripheral Component Interconnect (PCI) User's Guide (literature number SPRU985) and the Using the
TMS320DM643x Bootloader Application Report (literature number SPRAAG0).
The PCI peripheral is a master peripheral within the DM6437 DMP.
Table 6-97. Default Values for PCI Configuration Registers
REGISTER
DEFAULT VALUE (HEX)
Vendor ID
104C
Device ID
B001
Class Code
11 8000
Revision ID
01
System Vendor ID
0000
Subsystem ID
0000
Max Latency
00
Min Grant
00
Interrupt Pin
00
Interrupt Line
00
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6.20.2 PCI Peripheral Register Description(s)
Table 6-98. PCI Memory-Mapped Registers
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
01C1 A000 - 01C1 A00F
-
Reserved
01C1 A010
PCISTATSET
PCI Status Set Register
01C1 A014
PCISTATCLR
PCI Status Clear Register
01C1 A018 - 01C1 A01F
-
01C1 A020
PCIHINTSET
PCI Host Interrupt Enable Set Register
PCI Host Interrupt Enable Clear Register
Reserved
01C1 A024
PCIHINTCLR
01C1 A028 - 01C1 A02F
-
01C1 A030
PCIDINTSET
PCI DSP Interrupt Enable Set Register
01C1 A034
PCIDINTCLR
PCI DSP Interrupt Enable Clear Register
01C1 A038 - 01C1 A0FF
-
01C1 A100
282
DSP ACCESS REGISTER NAME
Reserved
Reserved
PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register
01C1 A104
PCICSRMIR
01C1 A108
PCICLREVMIR
PCI Class Code/Revision ID Mirror Register
01C1 A10C
PCICLINEMIR
PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register
01C1 A110
PCIBAR0MSK
PCI Base Address Mask Register 0
01C1 A114
PCIBAR1MSK
PCI Base Address Mask Register 1
01C1 A118
PCIBAR2MSK
PCI Base Address Mask Register 2
01C1 A11C
PCIBAR3MSK
PCI Base Address Mask Register 3
01C1 A120
PCIBAR4MSK
PCI Base Address Mask Register 4
01C1 A124
PCIBAR5MSK
PCI Base Address Mask Register 5
01C1 A128 - 01C1 A12B
-
01C1 A12C
PCISUBIDMIR
01C1 A130
-
01C1 A134
PCICPBPTRMIR
01C1 A138 - 01C1 A13B
-
01C1 A13C
PCILGINTMIR
01C1 A140 - 01C1 A17F
-
01C1 A180
PCISLVCNTL
PCI Command/Status Mirror Register
Reserved
PCI Subsystem Vendor ID/Subsystem ID Mirror Register
Reserved
PCI Capabilities Pointer Mirror Register
Reserved
PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register
Reserved
PCI Slave Control Register
01C1 A184 - 01C1 A1BF
-
01C1 A1C0
PCIBAR0TRL
Reserved
PCI Slave Base Address 0 Translation Register
01C1 A1C4
PCIBAR1TRL
PCI Slave Base Address 1 Translation Register
01C1 A1C8
PCIBAR2TRL
PCI Slave Base Address 2 Translation Register
01C1 A1CC
PCIBAR3TRL
PCI Slave Base Address 3 Translation Register
01C1 A1D0
PCIBAR4TRL
PCI Slave Base Address 4 Translation Register
01C1 A1D4
PCIBAR5TRL
PCI Slave Base Address 5 Translation Register
01C1 A1D8 - 01C1 A1DF
-
01C1 A1E0
PCIBAR0MIR
Reserved
PCI Base Address Register 0 Mirror Register
01C1 A1E4
PCIBAR1MIR
PCI Base Address Register 1 Mirror Register
01C1 A1E8
PCIBAR2MIR
PCI Base Address Register 2 Mirror Register
01C1 A1EC
PCIBAR3MIR
PCI Base Address Register 3 Mirror Register
01C1 A1F0
PCIBAR4MIR
PCI Base Address Register 4 Mirror Register
PCI Base Address Register 5 Mirror Register
01C1 A1F4
PCIBAR5MIR
01C1 A1F8 - 01C1 A2FF
-
01C1 A300
PCIMCFGDAT
Peripheral Information and Electrical Specifications
Reserved
PCI Master Configuration/IO Access Data Register
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Table 6-98. PCI Memory-Mapped Registers (continued)
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
01C1 A304
PCIMCFGADR
PCI Master Configuration/IO Access Address Register
PCI Master Configuration/IO Access Command Register
DSP ACCESS REGISTER NAME
01C1 A308
PCIMCFGCMD
01C1 A30C - 01C1 A30F
-
01C1 A310
PCIMSTCFG
PCI Master Configuration Register
01C1 A314
PCIADDSUB0
PCI Address Substitution 0 Register
01C1 A318
PCIADDSUB1
PCI Address Substitution 1 Register
01C1 A31C
PCIADDSUB2
PCI Address Substitution 2 Register
01C1 A320
PCIADDSUB3
PCI Address Substitution 3 Register
01C1 A324
PCIADDSUB4
PCI Address Substitution 4 Register
01C1 A328
PCIADDSUB5
PCI Address Substitution 5 Register
01C1 A32C
PCIADDSUB6
PCI Address Substitution 6 Register
01C1 A330
PCIADDSUB7
PCI Address Substitution 7 Register
01C1 A334
PCIADDSUB8
PCI Address Substitution 8 Register
01C1 A338
PCIADDSUB9
PCI Address Substitution 9 Register
01C1 A33C
PCIADDSUB10
PCI Address Substitution 10 Register
01C1 A340
PCIADDSUB11
PCI Address Substitution 11 Register
01C1 A344
PCIADDSUB12
PCI Address Substitution 12 Register
01C1 A348
PCIADDSUB13
PCI Address Substitution 13 Register
01C1 A34C
PCIADDSUB14
PCI Address Substitution 14 Register
01C1 A350
PCIADDSUB15
PCI Address Substitution 15 Register
01C1 A354
PCIADDSUB16
PCI Address Substitution 16 Register
Reserved
01C1 A358
PCIADDSUB17
PCI Address Substitution 17 Register
01C1 A35C
PCIADDSUB18
PCI Address Substitution 18 Register
01C1 A360
PCIADDSUB19
PCI Address Substitution 19 Register
01C1 A364
PCIADDSUB20
PCI Address Substitution 20 Register
01C1 A368
PCIADDSUB21
PCI Address Substitution 21 Register
01C1 A36C
PCIADDSUB22
PCI Address Substitution 22 Register
01C1 A370
PCIADDSUB23
PCI Address Substitution 23 Register
01C1 A374
PCIADDSUB24
PCI Address Substitution 24 Register
01C1 A378
PCIADDSUB25
PCI Address Substitution 25 Register
01C1 A37C
PCIADDSUB26
PCI Address Substitution 26 Register
01C1 A380
PCIADDSUB27
PCI Address Substitution 27 Register
01C1 A384
PCIADDSUB28
PCI Address Substitution 28 Register
01C1 A388
PCIADDSUB29
PCI Address Substitution 29 Register
01C1 A38C
PCIADDSUB30
PCI Address Substitution 30 Register
01C1 A390
PCIADDSUB31
PCI Address Substitution 31 Register
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Table 6-99. PCI Hook Configuration Registers
284
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
01C1 A394
PCIVENDEVPRG
01C1 A398
–
01C1 A39C
PCICLREVPRG
PCI Class Code and Revision ID Program Register
01C1 A3A0
PCISUBIDPRG
PCI Subsystem Vendor ID and Subsystem ID Program Register
01C1 A3A4
PCIMAXLGPRG
PCI Max Latency and Min Grant Program Register
01C1 A3A8
–
01C1 A3AC
PCICFGDONE
01C1 A3B0 - 01C1 A7FF
–
DSP ACCESS REGISTER NAME
PCI Vendor ID and Device ID Program Register
Reserved
Reserved
PCI Configuration Done Register
Reserved
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Table 6-100. PCI External Memory Space
HEX ADDRESS RANGE
ACRONYM
3000 0000 - 307F FFFF
-
PCI Master Window 0
PCI MASTER WINDOW
3080 0000 - 30FF FFFF
-
PCI Master Window 1
3100 0000 - 317F FFFF
-
PCI Master Window 2
3180 0000 - 31FF FFFF
-
PCI Master Window 3
3200 0000 - 327F FFFF
-
PCI Master Window 4
3280 0000 - 32FF FFFF
-
PCI Master Window 5
3300 0000 - 337F FFFF
-
PCI Master Window 6
3380 0000 - 33FF FFFF
-
PCI Master Window 7
3400 0000 - 347F FFFF
-
PCI Master Window 8
3480 0000 - 34FF FFFF
-
PCI Master Window 9
3500 0000 - 357F FFFF
-
PCI Master Window 10
3580 0000 - 35FF FFFF
-
PCI Master Window 11
3600 0000 - 367F FFFF
-
PCI Master Window 12
3680 0000 - 36FF FFFF
-
PCI Master Window 13
3700 0000 - 377F FFFF
-
PCI Master Window 14
3780 0000 - 37FF FFFF
-
PCI Master Window 15
3800 0000 - 387F FFFF
-
PCI Master Window 16
3880 0000 - 38FF FFFF
-
PCI Master Window 17
3900 0000 - 397F FFFF
-
PCI Master Window 18
3980 0000 - 39FF FFFF
-
PCI Master Window 19
3A00 0000 - 3A7F FFFF
-
PCI Master Window 20
3A80 0000 - 3AFF FFFF
-
PCI Master Window 21
3B00 0000 - 3B7F FFFF
-
PCI Master Window 22
3B80 0000 - 3BFF FFFF
-
PCI Master Window 23
3C00 0000 - 3C7F FFFF
-
PCI Master Window 24
3C80 0000 - 3CFF FFFF
-
PCI Master Window 25
3D00 0000 - 3D7F FFFF
-
PCI Master Window 26
3D80 0000 - 3DFF FFFF
-
PCI Master Window 27
3E00 0000 - 3E7F FFFF
-
PCI Master Window 28
3E80 0000 - 3EFF FFFF
-
PCI Master Window 29
3F00 0000 - 3F7F FFFF
-
PCI Master Window 30
3F80 0000 - 3FFF FFFF
-
PCI Master Window 31
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6.20.3 PCI Electrical Data/Timing
Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI
peripheral meets all AC timing specifications as required by the PCI Local Bus Specification Revision 2.3.
Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing
specifications, see Section 4.2.3, Timing Specification (33-MHz timing) of the PCI Local Bus Specification
Revision 2.3. Note: The DM6437 PCI peripheral only supports 3.3-V signaling and 33-MHz operation.
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6.21 Pulse Width Modulator (PWM)
The 3 DM6437 Pulse Width Modulator (PWM) peripherals support the following features:
• Period counter
• First-phase duration counter
• Repeat count for one-shot operation
• Configurable to operate in either one-shot or continuous mode
• Buffered period and first-phase duration registers
• One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or
high-to-low).
• One-shot operation generates N+1 periods of waveform, N being the repeat count register value
• Emulation support
The register memory maps for PWM0/1/2 are shown in Table 6-101, Table 6-102, and Table 6-103.
Table 6-101. PWM0 Register Memory Map
HEX ADDRESS RANGE
ACRONYM
0x01C2 2000
REGISTER NAME
Reserved
0x01C2 2004
PCR
PWM0 Peripheral Control Register
0x01C2 2008
CFG
PWM0 Configuration Register
0x01C2 200C
START
PWM0 Start Register
0x01C2 2010
RPT
PWM0 Repeat Count Register
0x01C2 2014
PER
PWM0 Period Register
0x01C2 2018
PH1D
PWM0 First-Phase Duration Register
0x01C2 201C - 0x01C2 23FF
-
Reserved
Table 6-102. PWM1 Register Memory Map
HEX ADDRESS RANGE
ACRONYM
0x01C2 2400
REGISTER NAME
Reserved
0x01C2 2404
PCR
PWM1 Peripheral Control Register
0x01C2 2408
CFG
PWM1 Configuration Register
0x01C2 240C
START
PWM1 Start Register
0x01C2 2410
RPT
PWM1 Repeat Count Register
0x01C2 2414
PER
PWM1 Period Register
0x01C2 2418
PH1D
PWM1 First-Phase Duration Register
0x01C2 241C -0x01C2 27FF
-
Reserved
Table 6-103. PWM2 Register Memory Map
HEX ADDRESS RANGE
ACRONYM
0x01C2 2800
REGISTER NAME
Reserved
0x01C2 2804
PCR
PWM2 Peripheral Control Register
0x01C2 2808
CFG
PWM2 Configuration Register
0x01C2 280C
START
PWM2 Start Register
0x01C2 2810
RPT
PWM2 Repeat Count Register
0x01C2 2814
PER
PWM2 Period Register
0x01C2 2818
PH1D
PWM2 First-Phase Duration Register
0x01C2 281C - 0x01C2 2BFF
-
Reserved
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6.21.1 PWM0/1/2 Electrical Data/Timing
Table 6-104. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2 Outputs
(see Figure 6-51 and Figure 6-52)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
UNIT
MAX
1
tw(PWMH)
Pulse duration, PWMx high
37
ns
2
tw(PWML)
Pulse duration, PWMx low
37
ns
3
tt(PWM)
Transition time, PWMx
4
td(CCDC-PWMV)
Delay time, CCDC(VD) trigger event to PWMx valid
2
5
ns
10
ns
1
2
PWM0/1/2
3
3
Figure 6-51. PWM Output Timing
VD(CCDC)
4
PWM0
INVALID
VALID
4
PWM1
INVALID
VALID
4
PWM2
INVALID
VALID
Figure 6-52. PWM Output Delay Timing
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6.22 VLYNQ
The DM6437 VLYNQ peripheral provides a high speed serial communications interface with the following
features.
• Low Pin Count
• Scalable Performance / Support
• Simple Packet Based Transfer Protocol for Memory Mapped Access
– Write Request / Data Packet
– Read Request Packet
– Read Response Data Packet
– Interrupt Request Packet
• Supports both Symmetric and Asymmetric Operation
– Tx pins on first device connect to Rx pins on second device and vice versa
– Data pin widths are automatically detected after reset
– Request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins
– Supports both Host/Peripheral and Peer to Peer communication
• Simple Block Code Packet Formatting (8b/10b)
• In Band Flow Control
– No extra pins needed
– Allows receiver to momentarily throttle back transmitter when overflow is about to occur
– Uses built in special code capability of block code to seamlessly interleave flow control information
with user data
– Allows system designer to balance cost of data buffering versus performance
• Multiple outstanding transactions
• Automatic packet formatting optimizations
• Internal loop-back mode
6.22.1 VLYNQ Peripheral Register Description(s)
Table 6-105. VLYNQ Registers
HEX ADDRESS RANGE
ACRONYM
0x01E0 1000
-
REGISTER NAME
0x01E0 1004
CTRL
VLYNQ Local Control Register
0x01E0 1008
STAT
VLYNQ Local Status Register
Reserved
0x01E0 100C
INTPRI
0x01E0 1010
INTSTATCLR
VLYNQ Local Interrupt Priority Vector Status/Clear Register
VLYNQ Local Unmasked Interrupt Status/Clear Register
0x01E0 1014
INTPENDSET
VLYNQ Local Interrupt Pending/Set Register
0x01E0 1018
INTPTR
0x01E0 101C
XAM
0x01E0 1020
RAMS1
VLYNQ Local Receive Address Map Size 1 Register
0x01E0 1024
RAMO1
VLYNQ Local Receive Address Map Offset 1 Register
0x01E0 1028
RAMS2
VLYNQ Local Receive Address Map Size 2 Register
0x01E0 102C
RAMO2
VLYNQ Local Receive Address Map Offset 2 Register
0x01E0 1030
RAMS3
VLYNQ Local Receive Address Map Size 3 Register
0x01E0 1034
RAMO3
VLYNQ Local Receive Address Map Offset 3 Register
0x01E0 1038
RAMS4
VLYNQ Local Receive Address Map Size 4 Register
0x01E0 103C
RAMO4
VLYNQ Local Receive Address Map Offset 4 Register
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VLYNQ Local Interrupt Pointer Register
VLYNQ Local Transmit Address Map Register
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Table 6-105. VLYNQ Registers (continued)
290
HEX ADDRESS RANGE
ACRONYM
0x01E0 1040
CHIPVER
VLYNQ Local Chip Version Register
REGISTER NAME
0x01E0 1044
AUTNGO
VLYNQ Local Auto Negotiation Register
0x01E0 1048
-
Reserved
0x01E0 104C
-
Reserved
0x01E0 1050 - 0x01E0 105C
-
Reserved
0x01E0 1060
-
Reserved
01E0 10C00 0064
-
Reserved
0x01E0 1068 - 0x01E0 107C
-
Reserved for future use
0x01E0 1080
RREVID
VLYNQ Remote Revision Register
0x01E0 1084
RCTRL
VLYNQ Remote Control Register
0x01E0 1088
RSTAT
VLYNQ Remote Status Register
0x01E0 108C
RINTPRI
VLYNQ Remote Interrupt Priority Vector Status/Clear Register
0x01E0 1090
RINTSTATCLR
VLYNQ Remote Unmasked Interrupt Status/Clear Register
0x01E0 1094
RINTPENDSET
VLYNQ Remote Interrupt Pending/Set Register
0x01E0 1098
RINTPTR
VLYNQ Remote Interrupt Pointer Register
0x01E0 109C
RXAM
0x01E0 10A0
RRAMS1
VLYNQ Remote Transmit Address Map Register
VLYNQ Remote Receive Address Map Size 1 Register
0x01E0 10A4
RRAMO1
VLYNQ Remote Receive Address Map Offset 1 Register
0x01E0 10A8
RRAMS2
VLYNQ Remote Receive Address Map Size 2 Register
0x01E0 10AC
RRAMO2
VLYNQ Remote Receive Address Map Offset 2 Register
0x01E0 10B0
RRAMS3
VLYNQ Remote Receive Address Map Size 3 Register
0x01E0 10B4
RRAMO3
VLYNQ Remote Receive Address Map Offset 3 Register
0x01E0 10B8
RRAMS4
VLYNQ Remote Receive Address Map Size 4 Register
0x01E0 10BC
RRAMO4
VLYNQ Remote Receive Address Map Offset 4 Register
0x01E0 10C0
RCHIPVER
VLYNQ Remote Chip Version Register (values on the device_id and
device_rev pins of remote VLYNQ)
0x01E0 10C4
RAUTNGO
VLYNQ Remote Auto Negotiation Register
0x01E0 10C8
RMANNGO
VLYNQ Remote Manual Negotiation Register
0x01E0 10CC
RNGOSTAT
VLYNQ Remote Negotiation Status Register
0x01E0 10D0 - 0x01E0 10DC
-
0x01E0 10E0
RINTVEC0
VLYNQ Remote Interrupt Vectors 3 - 0 (sourced from vlynq_int_i[3:0] port of
remote VLYNQ)
0x01E0 10E4
RINTVEC1
VLYNQ Remote Interrupt Vectors 7 - 4 (sourced from vlynq_int_i[7:4] port of
remote VLYNQ)
0x01E0 10E8 - 0x01E0 10FC
-
Reserved for future use
0x01E0 1100 - 0x01E0 1FFF
-
Reserved
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6.22.2 VLYNQ Electrical Data/Timing
Table 6-106. Timing Requirements for VLYNQ_CLK Input (see Figure 6-53)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
1
tc(VCLK)
Cycle time, VLYNQ_CLK
10
ns
2
tw(VCLKH)
Pulse duration, VLYNQ_CLK high
3
ns
3
tw(VCLKL)
Pulse duration, VLYNQ_CLK low
3
ns
Table 6-107. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLK
Output (see Figure 6-53)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
UNIT
MAX
1
tc(VCLK)
Cycle time, VLYNQ_CLK
10
ns
2
tw(VCLKH)
Pulse duration, VLYNQ_CLK high
4
ns
3
tw(VCLKL)
Pulse duration, VLYNQ_CLK low
4
ns
1
2
VLYNQ_CLK
3
Figure 6-53. VLYNQ_CLK Timing for VLYNQ
Table 6-108. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for
the VLYNQ Module (see Figure 6-54)
NO.
PARAMETER
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN
1
td(VCLKH-
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid
UNIT
MAX
2.25
ns
TXDI)
2
td(VCLKH-
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] valid
12
ns
TXDV)
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Table 6-109. Timing Requirements for Receive Data for the VLYNQ Module (1) (see Figure 6-54)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
3
4
(1)
tsu(RXDV-VCLKH)
th(VCLKH-RXDV)
UNIT
MAX
Setup time, VLYNQ_RXD[3:0] valid before RTM disabled, RTM sample = 3
VLYNQ_CLK high
RTM enabled
1.75
ns
(1)
ns
RTM disabled, RTM sample = 3
3
ns
(1)
ns
Hold time, VLYNQ_RXD[3:0] valid after
VLYNQ_CLK high
RTM enabled
The VLYNQ receive timing manager (RTM) is a serial receive logic designed to eliminate setup and hold violations that could occur in
traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see Table 6-110). When
RTM logic is disabled, the setup and hold timing from the default data flop (3) is used.
Table 6-110. RTM RX Data Flop Hold/Setup Timing
Constraints (Typical Values)
RX Data Flop
HOLD (Y)
SETUP (X)
0
1.3
0.9
1
1.4
0.7
2
1.5
-0.4
3
1.6
-0.6
4
1.8
-0.8
5
2.0
-1.0
6
2.2
-1.1
7
2.4
-1.2
1
VLYNQ_CLK
2
Data
VLYNQ_TXD[3:0]
4
3
VLYNQ_RXD[3:0]
Data
Figure 6-54. VLYNQ Transmit/Receive Timing
292
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6.23 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GP[0:15]).
The DM6437 GPIO peripheral supports the following:
• Up to 111 3.3-V GPIO pins, GP[0:110]
• Interrupts:
– Up to 8 unique GP[0:7] interrupts from Bank 0
– 7 GPIO bank (aggregated) interrupt signals from each of the 7 banks of GPIOs
– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
• DMA events:
– Up to 8 unique GPIO DMA events from Bank 0
– 7 GPIO bank (aggregated) DMA event signals from each of the 7 banks of GPIOs
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-111. For more detailed information on
GPIOs, see the TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (literature
number SPRU988).
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GPIO Peripheral Register Description(s)
Table 6-111. GPIO Registers
HEX ADDRESS RANGE
ACRONYM
0x01C6 7000
PID
0x01C6 7004
-
0x01C6 7008
BINTEN
REGISTER NAME
Peripheral Identification Register
Reserved
GPIO interrupt per-bank enable
GPIO Banks 0 and 1
0x01C6 700C
-
0x01C6 7010
DIR01
Reserved
0x01C6 7014
OUT_DATA01
GPIO Banks 0 and 1 Output Data Register (GP[0:31])
0x01C6 7018
SET_DATA01
GPIO Banks 0 and 1 Set Data Register (GP[0:31])
0x01C6 701C
CLR_DATA01
GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GP[0:31])
GPIO Banks 0 and 1 Direction Register (GP[0:31])
0x01C6 7020
IN_DATA01
0x01C6 7024
SET_RIS_TRIG01
GPIO Banks 0 and 1 Input Data Register (GP[0:31])
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GP[0:31])
0x01C6 7028
CLR_RIS_TRIG01
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GP[0:31])
0x01C6 702C
SET_FAL_TRIG01
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GP[0:31])
0x01C6 7030
CLR_FAL_TRIG01
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GP[0:31])
0x01C6 7034
INSTAT01
GPIO Banks 0 and 1 Interrupt Status Register (GP[0:31])
GPIO Banks 2 and 3
0x01C6 7038
DIR23
0x01C6 703C
OUT_DATA23
GPIO Banks 2 and 3 Direction Register (GP[32:63])
GPIO Banks 2 and 3 Output Data Register (GP[32:63])
0x01C6 7040
SET_DATA23
GPIO Banks 2 and 3 Set Data Register (GP[32:63])
0x01C6 7044
CLR_DATA23
GPIO Banks 2 and 3 Clear Data Register (GP[32:63])
0x01C6 7048
IN_DATA23
GPIO Banks 2 and 3 Input Data Register (GP[32:63])
0x01C6 704C
SET_RIS_TRIG23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (GP[32:63])
0x01C6 7050
CLR_RIS_TRIG23
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (GP[32:63])
0x01C6 7054
SET_FAL_TRIG23
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (GP[32:63])
0x01C6 7058
CLR_FAL_TRIG23
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (GP[32:63])
0x01C6 705C
INSTAT23
0x01C6 7060
DIR45
0x01C6 7064
OUT_DATA45
GPIO Bank 4 and 5 Output Data Register (GP[64:95])
GPIO Banks 2 and 3 Interrupt Status Register (GP[32:63])
GPIO Bank 4 and 5
GPIO Bank 4 and 5 Direction Register (GP[64:95])
0x01C6 7068
SET_DATA45
GPIO Bank 4 and 5 Set Data Register (GP[64:95])
0x01C6 706C
CLR_DATA45
GPIO Bank 4 and 5 Clear Data Register (GP[64:95])
0x01C6 7070
IN_DATA45
GPIO Bank 4 and 5 Input Data Register (GP[64:95])
0x01C6 7074
SET_RIS_TRIG45
GPIO Bank 4 and 5 Set Rising Edge Interrupt Register (GP[64:95])
0x01C6 7078
CLR_RIS_TRIG45
GPIO Bank 4 and 5 Clear Rising Edge Interrupt Register (GP[64:95])
0x01C6 707C
SET_FAL_TRIG45
GPIO Bank 4 and 5 Set Falling Edge Interrupt Register (GP[64:95])
0x01C6 7080
CLR_FAL_TRIG45
GPIO Bank 4 and 5 Clear Falling Edge Interrupt Register (GP[64:95])
0x01C6 7084
INSTAT45
0x01C6 7088
DIR6
0x01C6 708C
OUT_DATA6
GPIO Bank 6 Output Data Register (GP[96:110])
0x01C6 7090
SET_DATA6
GPIO Bank 6 Set Data Register (GP[96:110])
0x01C6 7094
CLR_DATA6
GPIO Bank 6 Clear Data Register (GP[96:110])
GPIO Bank 6 Input Data Register (GP[96:110])
GPIO Bank 4 and 5 Interrupt Status Register (GP[64:95])
GPIO Bank 6
294
GPIO Bank 6 Direction Register (GP[96:110])
0x01C6 7098
IN_DATA6
0x01C6 709C
SET_RIS_TRIG6
GPIO Bank 6 Set Rising Edge Interrupt Register (GP[96:110])
0x01C6 70A0
CLR_RIS_TRIG6
GPIO Bank 6 Clear Rising Edge Interrupt Register (GP[96:110])
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Table 6-111. GPIO Registers (continued)
HEX ADDRESS RANGE
ACRONYM
0x01C6 70A4
SET_FAL_TRIG6
GPIO Bank 6 Set Falling Edge Interrupt Register (GP[96:110])
0x01C6 70A8
CLR_FAL_TRIG6
GPIO Bank 6 Clear Falling Edge Interrupt Register (GP[96:110])
0x01C6 70AC
INSTAT6
0x01C6 70B0 - 0x01C6 7FFF
-
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REGISTER NAME
GPIO Bank 6 Interrupt Status Register (GP[96:110])
Reserved
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GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-112. Timing Requirements for GPIO Inputs (1) (see Figure 6-55)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
1
tw(GPIH)
Pulse duration, GP[x] input high
2C (2)
ns
2
tw(GPIL)
Pulse duration, GP[x] input low
2C (2)
ns
(1)
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have DM6437 recognize
the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow DM6437
enough time to access the GPIO register through the internal bus.
C = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use C = 10 ns.
(2)
Table 6-113. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-55)
NO.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
MIN
(1)
(2)
UNIT
MAX
3
tw(GPOH)
Pulse duration, GP[x] output high
2C (1) (2)
ns
4
tw(GPOL)
Pulse duration, GP[x] output low
2C (1) (2)
ns
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
C = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use C = 10 ns.
2
GP[x]
Input
1
4
3
GP[x]
Output
Figure 6-55. GPIO Port Timing
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6.24 IEEE 1149.1 JTAG
The JTAG (3) interface is used for BSDL testing and emulation of the DM6437 device.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
For maximum reliability, DM6437 includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.24.1
(3)
JTAG ID (JTAGID) Register Description(s)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Table 6-114. JTAG ID (JTAGID) Register
HEX ADDRESS RANGE
ACRONYM
0x01C4 0028
JTAGID
REGISTER NAME
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
JTAG Identification Register
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM6437 device, the JTAG ID register resides at address location 0x01C4 0028. For the actual register bit
names and their associated bit field descriptions, see Figure 6-56 and Table 6-115.
31-28
27-12
11-1
0
VARIANT (4-Bit)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-n
R-1011 0111 0010 0001
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-56. JTAG ID (JTAGID) Register—0x01C4 0028
Table 6-115. JTAG ID (JTAGID) Register Selection Bit Descriptions
BIT
NAME
31:28
VARIANT
Variant (4-Bit) value. A read from this field always returns 0b0000.
27:12
PART NUMBER
Part Number (16-Bit) value. DM6437 value: 1011 0111 0010 0001.
11-1
MANUFACTURER
0
LSB
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DESCRIPTION
Manufacturer (11-Bit) value. DM6437 value: 0000 0010 111.
LSB. This bit is read as a "1" for DM6437.
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6.24.2 JTAG Electrical Data/Timing
Table 6-116. Timing Requirements for JTAG Test Port (see Figure 6-57)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MIN
UNIT
MAX
1
tc(TCK)
Cycle time, TCK
33
ns
3
tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
2.5
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
16.5
ns
Table 6-117. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-57)
NO.
2
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
PARAMETER
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
UNIT
MIN
MAX
0
14
ns
1
TCK
2
2
TDO
4
3
TDI/TMS/TRST
Figure 6-57. JTAG Test-Port Timing
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7 Mechanical Data
The following table(s) show the thermal resistance characteristics for the PBGA–ZWT and ZDU
mechanical package(s). For more details, see the Thermal Considerations for TMS320DM64xx,
TMS320DM64x, and TMS320C6000 Devices Application Report (literature number SPRAAL9).
7.1 Thermal Data for ZWT
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZWT]
NO.
N/A
RΘJC
Junction-to-case
5.4
2
RΘJB
Junction-to-board
16.0
N/A
26.6
0.00
4
21.9
1.0
5
20.4
2.00
7
0.0
0.00
8
RΘJA
PsiJT
Junction-to-free air
Junction-to-package top
9
11
12
PsiJB
Junction-to-board
13
(2)
AIR FLOW (m/s) (2)
1
3
(1)
°C/W (1)
0.1
1.0
0.2
2.00
15.9
0.00
15.8
1.0
15.3
2.00
The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC
defined 1S2P system and will change based on environment as well as application.
For more information, see these three EIA/JEDEC standards:
• EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
.
m/s = meters per second
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7.1.1 Thermal Data for ZDU
Table 7-2. Thermal Resistance Characteristics (PBGA Package) [ZDU]
NO.
°C/W (1)
AIR FLOW (m/s) (2)
1
RΘJC
Junction-to-case
7.7
N/A
2
RΘJB
Junction-to-board
10.5
N/A
19.7
0.00
RΘJA
Junction-to-free air
3
4
15.5
1.0
5
14.3
2.00
7
4.9
0.00
8
5.1
1.0
9
5.2
2.00
11
10.4
0.00
12
PsiJT
PsiJB
Junction-to-package top
Junction-to-board
13
(1)
(2)
9.8
1.0
9.6
2.00
The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC
defined 1S2P system and will change based on environment as well as application.
For more information, see these three EIA/JEDEC standards:
• EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
m/s = meters per second
7.1.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
300
Mechanical Data
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
TMS320DM6437ZDU4
ACTIVE
BGA
ZDU
376
60
RoHS & Green
Call TI
Level-3-260C-168 HR
0 to 90
L2
DM6437ZDU
TMS320
4
TMS320DM6437ZDU6
ACTIVE
BGA
ZDU
376
60
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 90
DM6437ZDU6
TMS320DM6437ZDUQ6
ACTIVE
BGA
ZDU
376
60
RoHS & Green
SNAGCU
Level-3-260C-168 HR
TMS320DM6437ZWT4
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 90
L2
DM6437ZWT
TMS320
4
TMS320DM6437ZWT5
NRND
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 90
L2
DM6437ZWT
TMS320
5
TMS320DM6437ZWT6
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 90
L2
DM6437ZWT
TMS320
TMS320DM6437ZWT7
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 90
L2
DM6437ZWT
TMS320
7
TMS320DM6437ZWTQ4
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
L1
DM6437ZWTQ
TMS320
4
TMS320DM6437ZWTQ5
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
L1
DM6437ZWTQ
TMS320
5
TMS320DM6437ZWTQ6
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Addendum-Page 1
L1
DM6437ZDUQ
TMS320
6
L1
DM6437ZWTQ
TMS320
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
13-May-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
6
TNETV1644ZDU6
ACTIVE
BGA
ZDU
376
60
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 90
DM6437ZDU6
TNETV6437INZWTQ5
ACTIVE
NFBGA
ZWT
361
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
L1
DM6437ZWTQ
TMS320
5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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