TMS320DM6441ZWT

TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 TMS320DM6441 Digital Media System-on-Chip Check for Samples: TMS320DM6441 1 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • High-Performance Digital Media SoC – C64x+™ DSP Clock Rate • 405-MHz (Max) at 1.05 V or 513-MHz (Max) at 1.2 V – ARM926EJ-S™ Clock Rate • 202.5-MHz (Max) at 1.05 V or 256-MHz (Max) at 1.2 V – Eight 32-Bit C64x+ Instructions/Cycle – 4752 C64x+ MIPS – Fully Software-Compatible With C64x / ARM9™ • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core – Eight Highly Independent Functional Units • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle – Load-Store Architecture With Non-Aligned Support – 64 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional – Additional C64x+™ Enhancements • Protected Mode Operation • Exceptions Support for Error Detection and Program Redirection • Hardware Support for Modulo Loop Operation • C64x+ Instruction Set Features – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions – Additional Instructions to Support Complex Multiplies • C64x+ L1/L2 Memory Architecture – 32K-Byte L1P Program RAM/Cache (Direct Mapped) – 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) – 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) • ARM926EJ-S Core – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – DSP Instruction Extensions and Single Cycle MAC – ARM® Jazelle® Technology – Embedded ICE-RT™ Logic for Real-Time Debug • ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache – 16K-Byte RAM – 8K-Byte ROM • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug • Endianness: Little Endian for ARM and DSP • Video Imaging Co-Processor (VICP) • Video Processing Subsystem – Front End Provides: • CCD and CMOS Imager Interface • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface • Preview Engine for Real-Time Image Processing • Glueless Interface to Common Video Decoders • Histogram Module • Auto-Exposure, Auto-White Balance, and Auto-Focus Module • Resize Engine – Resize Images From 1/4x to 4x – Separate Horizontal/Vertical Control 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2010, Texas Instruments Incorporated TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 • Video Processing Subsystem (Continued) – Back End Provides: • Hardware On-Screen Display (OSD) • Four 54-MHz DACs for a Combination of – Composite NTSC/PAL Video – Luma/Chroma Separate Video (S-video) – Component (YPbPr or RGB) Video (Progressive) • Digital Output – 8-/16-bit YUV or up to 24-Bit RGB – HD Resolution – Up to Two Video Windows • External Memory Interfaces (EMIFs) – 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) – Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach • Flash Memory Interfaces – NOR (8-/16-Bit-Wide Data) – NAND (8-/16-Bit-Wide Data) • Flash Card Interfaces – Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) – CompactFlash Controller With True IDE Mode – SmartMedia – Memory Stick® and Memory Stick PRO™ • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) • One 64-Bit Watch Dog Timer • Three UARTs (One with RTS and CTS Flow Control) 2 www.ti.com • One Serial Port Interface (SPI) With Two Chip-Selects • Master/Slave Inter-Integrated Circuit (I2C Bus™) • Audio Serial Port (ASP) – I2S – AC97 Audio Codec Interface – Standard Voice Codec Interface (AIC12) • 10/100 Mb/s Ethernet MAC (EMAC) – IEEE 802.3 Compliant – Media Independent Interface (MII) • VLYNQ™ Interface (FPGA Interface) • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data • USB Port With Integrated 2.0 PHY – USB 2.0 High-/Full-Speed Client – USB 2.0 High-/Full-/Low-Speed Host • Three Pulse Width Modulator (PWM) Outputs • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART • ATA/ATAPI I/F (ATA/ATAPI-5 Specification) • Individual Power-Saving Modes for ARM/DSP • Flexible PLL Clock Generators • IEEE-1149.1 (JTAG) BoundaryScan-Compatible • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch • 0.09-µm/6-Level Cu Metal Process (CMOS) • 3.3-V and 1.8-V I/O, 1.05-V or 1.2-V internal • Applications: – Digital Media – Networked Media Encode/Decode – Video Imaging – Portable Media Players Digital Media System-on-Chip (DMSoC) Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 1.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Description The TMS320DM6441 (also referenced as DM6441) leverages TI’s DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6441 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the DM6441 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates: • A coprocessor 15 (CP15) and protection module • Data and program memory management units (MMUs) with table look-aside buffers. • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4104 million instructions per second (MIPS) at a clock rate of 513 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2052 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4104 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6441 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6441 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; an inter-integrated circuit (I2C) bus interface; one audio serial port (ASP); two 64-bit general-purpose timers each configurable as two independent 32-bit timers; one 64-bit watchdog timer; up to 71 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UARTs with hardware handshaking support on one UART; three pulse width modulator (PWM) peripherals; and two external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. Digital Media System-on-Chip (DMSoC) Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 3 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com The DM6441 device includes a video processing subsystem (VPSS) with two configurable video/imaging peripherals: one video processing front-end (VPFE) input used for video capture, one video processing back-end (VPBE) output with imaging coprocessor (VICP) used for display. The video processing front-end (VPFE) consists of a CCD controller (CCDC), a preview engine (previewer), histogram module, auto-exposure/white balance/focus module (H3A), and resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and charge coupled devices (CCDs). The previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer pattern to YUV4:2:2. The histogram and H3A modules provide statistical information on the raw color data for use by the DM6441. The resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The video processing back-end (VPBE) consists of an on-screen display engine (OSD) and a video encoder (VENC). The OSD engine is capable of handling two separate video windows and two separate OSD windows. Other configurations include two video windows, one OSD window, and one attribute window allowing up to eight levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs. VFocus (part of the VPBE functionality and operationally (e.g., 16-bit multiplexed address/data) is also provided. The Ethernet media access controller (EMAC) provides an efficient interface between the DM6441 and the network. The DM6441 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses. The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6441 to easily control peripheral devices and/or communicate with host processors. The DM6441 also provides Memory Stick/Memory Stick PRO card support, MMC/SD with SDIO support, and a universal serial bus (USB). The DM6441 also includes a video/imaging coprocessor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments. The DM6441 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. 4 Digital Media System-on-Chip (DMSoC) Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 1.3 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Functional Block Diagram Figure 1-1 shows the functional block diagram of the device. Video-Imaging Coprocessor (VICP) JTAG Interface Input Clock(s) System Control ARM Subsystem DSP Subsystem PLLs/Clock Generator ARM926EJ-S CPU C64x+ t DSP CPU Power/Sleep Controller 16 KB I-Cache 8 KB D-Cache 16 KB RAM Pin Multiplexing 64 KB L2 RAM 32 KB L1 Pgm 80 KB L1 Data 8 KB ROM BT.656, Y/C, Raw (Bayer) Video Processing Subsystem (VPSS) Front End Back End Resizer CCD Controller Histogram/ 3A Video Preview Interface 8b BT.656, Y/C, 24b RGB On-Screen Video 10b DAC Display Encoder 10b DAC (OSD) (VENC) 10b DAC 10b DAC NTSC/ PAL, S-Video, RGB, YPbPr Switched Central Resource (SCR) Peripherals Serial Interfaces EDMA3 Audio Serial Port I2 C SPI System UART VLYNQ EMAC With MDIO Watchdog Timer PWM Program/Data Storage Connectivity USB 2.0 PHY GeneralPurpose Timer HPI DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA/ Compact Flash MMC/ SD/ SDIO MS/ MS PRO Figure 1-1. TMS320DM6441 Functional Block Diagram Digital Media System-on-Chip (DMSoC) Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 5 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 1 www.ti.com Digital Media System-on-Chip (DMSoC) ............ 1 1.1 Features .............................................. 1 ........................................... 3 1.3 Functional Block Diagram ............................ 5 Revision History .............................................. 7 2 Device Overview ....................................... 10 2.1 Device Characteristics .............................. 10 2.2 Device Compatibility ................................ 11 2.3 ARM Subsystem .................................... 11 2.4 DSP Subsystem .................................... 16 2.5 Memory Map Summary ............................. 20 2.6 Pin Assignments .................................... 24 2.7 Terminal Functions ................................. 28 2.8 Device Support ..................................... 58 3 Device Configurations ................................ 63 3.1 System Module Registers .......................... 63 3.2 Power Considerations .............................. 63 3.3 Bootmode ........................................... 65 3.4 Configurations at Reset ............................ 68 3.5 Configurations After Reset ......................... 72 3.6 Emulation Control ................................... 86 4 System Interconnect .................................. 88 4.1 System Interconnect Block Diagram ............... 89 5 Device Operating Conditions ....................... 90 1.2 5.1 5.2 5.3 6 6 Description Peripheral and Electrical Specifications .......... 93 Parameter Information .............................. 93 Recommended Clock and Control Signal Transition Behavior ............................................ 94 6.3 Power Supplies 6.4 Reset 6.5 6.6 6.7 6.8 6.9 Enhanced Direct Memory Access (EDMA3) Controller .......................................... 125 ................ ............................................ MMC/SD/SDIO .................................... External Memory Interface (EMIF) 137 6.11 ATA/CF 145 6.12 6.13 Video Processing Sub-System (VPSS) Overview 158 ..................................................... USB 2.0 ........................................... 161 ......................... ...................... Audio Serial Port (ASP) ........................... Ethernet Media Access Controller (EMAC) ....... Management Data Input/Output (MDIO) .......... Timer .............................................. Pulse Width Modulator (PWM) .................... VLYNQ ............................................ Memory Stick/Memory Stick PRO ................. Host-Port Interface (HPI) .......................... IEEE 1149.1 JTAG ................................ 185 Universal Asynchronous Receiver/Transmitter (UART) ............................................ 194 6.16 Serial Port Interface (SPI) 197 6.17 Inter-Integrated Circuit (I2C) 201 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 7 ..................................... 94 .............................................. 103 External Clock Input From MXI/CLKIN Pin ........ 106 Clock PLLs ........................................ 109 Interrupts .......................................... 115 General-Purpose Input/Output (GPIO) ............ 122 6.10 6.14 6.15 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) .... 90 Recommended Operating Conditions .............. 91 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) ............ 92 6.1 6.2 204 208 214 216 218 220 224 227 230 Mechanical Packaging and Orderable Information ............................................ 232 7.1 Thermal Data for ZWT 7.2 Packaging Information Contents ............................ ............................ 232 232 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS359D device-specific data manual to make it an SPRS359E revision. Scope: Added information/data on silicon revision 2.3. Applicable updates to the DM644x device family, specifically relating to the TMS320DM6441 device, have been incorporated. TMS320DM6441 Revision History SEE Global ADDITIONS/MODIFICATIONS/DELETIONS • • • Added information/data on silicon revision 2.3 Updated/changed all applicable EDMA instances to "EDMA3" [Cleared Documentation Feedback Issue] Updated the document to reflect the following: – "ARM can boot from internal ROM SPI" Section 1.1 Features • Section 1.3 Functional Block Diagram Figure 1-1, TMS320DM6441 Functional Block Diagram: • Updated/changed the ARM Subsystem Block to "8 KB ROM" [Cleared Documentation Feedback Issue] Section 2.1 Device Characteristics Table 2-1, Characteristics of the Processor: • Added "VICP" row • Updated/changed "C64x+ Megamodule Revision" for silicon revision 2.3 • Updated/changed "JTAG BSDL_ID" for silicon revision 2.3 • Added "ball finish SnAgCu" to the BGA Package HARDWARE FEATURES row [Cleared Documentation Feedback Issue] Section 2.3.14 Power Management • Section 2.7 Terminal Functions Table 2-28, Reserved Terminal Functions: • Added the RSV24, M3 row • Updated/changed the description for the RSV1–4, RSV6, and RSV7 signals Section 2.8.2 Device and Development-Support Tool Nomenclature Figure 2-6, Device Nomenclature: • Added "B = Silicon 2.3" under SILICON REVISION Added "Video Imaging Co-Processor (VICP)" bullet Added "DM6441 gives the programmer full flexibility to use ..." paragraph Section 2.8.3.1 • Related Documentation From Texas Instruments Updated/changed list of reference documents Section 3.3.1.1 BOOTCFG Register Description • Updated/changed the location of the BOOTCFG register from "0x01C4 000A" to "0x01C4 0014" [Cleared Documentation Feedback Issue] Section 3.3.2 ARM Boot • "The DM6441 ARM can boot from EMIFA ..." paragraph: – Updated/changed "The DM6441 ARM can boot from EMIFA, internal ROM (NAND) or UART0 as determined by ..." to "The DM6441 ARM can boot from EMIFA, internal ROM (NAND, SPI), UART0, or HPI, as determined by ..." Updated/changed this section to reflect "ARM can boot from internal ROM SPI" • Section 3.3.3.1 Host-Boot Mode • Added "In host boot mode, the ARM is the master and controls the reset and boot of the C64x+ ..." paragraph Contents Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 7 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com TMS320DM6441 Revision History (continued) SEE Section 3.5.1 Switched Central Resource (SCR) Bus Priorities ADDITIONS/MODIFICATIONS/DELETIONS Table 3-12, DM6441 Default Bus Master Priorities: • Added, for clarity, ", DMA_PRI bit fields" to the VPSSP Default Priority Level description [Cleared Documentation Feedback Issue] • Added "[For more detailed information ..." statement to the VPSSP, EDMATC0P, EDMATC1P, and C64X+_DMAP rows • Added "(MSTPRI1 Register)" to the HPIP row • Removed VICPP row with Default Priority Level of 4 Figure 3-6, MSTPRI1 Register: • Updated/changed the bit field of bits 22:20 from "RESERVED" to "HPIP" • Updated/changed the default value of bits 22:20 from "R-100" to "R/W-100" Section 3.5.4 PINMUX0 Register Description • "The PINMUX0 pin multiplexing register controls which peripheral is given ownership ..." paragraph: – Updated/changed "... ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, and GPIO peripherals" to "... ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals" Figure 3-7, PINMUX0 Register: • Bits 4–0: Updated/changed "R/W-LLLL" to "R/W-LLLLL" • Updated/changed footnote from "For proper DM6441 device operation, always write a value of '0' to RSV bits 30 and 29" to "For proper DM6441 device operation, always write a value of '0' to RSV bit 30" Table 3-14, PINMUX0 Register Field Descriptions: • Updated/changed the description of Bit 29 (HPIEN) [Cleared Documentation Feedback Issue] 8 Section 3.5.5 PINMUX1 Register Description Figure 3-8, PINMUX1 Register: • Removed "For proper DM6441 device operation, always write a value of '0' to RSV bit 9" footnote Section 3.6 Emulation Control Figure 3-9, Emulation Suspend Source Register (SUSPSRC): • Bits 15–13: Updated/changed "R-0000 00" to "R-000" Section 5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature • Section 6.3.1.3 DM6441 Power and Clock Domains Figure 6-6, PLL1 and PLL2 Clock Domain Block Diagram: • PLL Controller 2: Updated/changed "PLLDIV1 (/1)" to "PLLDIV1 (/10)" • Updated/changed "EDMA" to "EDMA3" Section 6.3.1.4 Power and Sleep Controller (PSC) Module Table 6-6, PSC Register Memory Map [Cleared Documentation Feedback Issue]: • Updated/changed address range "0x01C4 1004 through 0x01C4 1014 to "Reserved" • Updated/changed address range "0x01C4 1100 through 0x01C4 111F to "Reserved" • Updated/changed address range "0x01C4 1308 through 0x01C4 17FF to "Reserved" Section 6.4.1 Reset Electrical Data/Timing Figure 6-9, Reset Timing: • Updated/changed the pins specified in the Z Group [Cleared Documentation Feedback Issue] Section 6.6.3 Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 6-19, Switching Characteristics Over Recommended Operating Conditions for CLK_OUT1: • Parameter 1 (tC): Added "ns" in UNIT column Section 6.10.1.2 EMIFA Electrical Data/Timing Table 6-35, Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module: • Parameter 24 [tw(EMWEL)]: Added "ns" in UNIT column "Measured under the following conditions:" footnote: – Added "For more details on core and I/O activity, as well as information relevant to board power supply design, see the TMS320DM6441 Power Consumption Summary application report (literature number SPRAAU3)." Contents Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 TMS320DM6441 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 6.12 MMC/SD/SDIO • Section 6.12.1 MMC/SD/SDIO Peripheral Description(s) Table 6-43, MMC/SD/SDIO Register Descriptions: • Updated/changed 0x01E1 0064 from "SDIO" to "SDIOCTL (SDIO Control Register)" • Updated/changed 0x01E1 0068 from "SDIO" to "SDIOST0 (SDIO Status Register 0)" • Updated/changed 0x01E1 006C from "SDIO" to "SDIOIEN (SDIO Interrupt Enable Register)" • Updated/changed 0x01E1 0070 from "Reserved" to "SDIOIST (SDIO Interrupt Status Register)" Section 6.13.1.6 VPFE Electrical Data/Timing Table 6-53, Timing Requirements for VPFE PCLK Master/Slave Mode: • Parameter 1 [tc(PCLK)]: Removed MAX value of 160 ns [Cleared Documentation Feedback Issue] Section 6.13.2.3 VPBE Electrical Data/Timing Table 6-63, Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK: • Updated/changed PARAMETER NO. 22 to "Delay time, VCLKIN low to VCLK low" [Cleared Documentation Feedback Issue] Section 6.13.2.4 DAC Electrical Data/Timing • Section 6.14.3 USB2.0 Electrical Data/Timing Table 6-68, Switching Characteristics Over Recommended Operating Conditions for USB2.0: • Parameter 5 [tjr(source)NT], HIGH SPEED 480 Mbps: – MAX column: Added footnote reference Section 6.25.1 Host-Port Interface (HPI) Electrical Data/Timing Table 6-116, Timing Requirements for Host-Port Interface Cycles: • Updated/changed the P = 1/CPU clock frequency in ... footnote from "P = 1.48" to "P = 2.47" ns [Cleared Documentation Feedback Issue] Section 6.26 IEEE 1149.1 JTAG • • Removed "TRST is synchronous and must be clocked by TCK ..." NOTE Added Note about the sequencing of all the JTAG signals [Cleared Documentation Feedback Issue] Section 6.26.1 JTAG Peripheral Register Description(s) – JTAG ID Register • Updated/changed "The JTAG ID register is a read-only register ..." paragraph Added "SDIO is only supported for WLAN operation through TI third parties ..." paragraph Updated/changed "The DM6441's analog video DAC outputs are designed to drive ..." paragraph Figure 6-83, JTAG ID Register Description - DM6441 Register Value - 0xXB70 002F: • Updated/changed footnote Table 6-119, JTAG ID Register Selection Bit Descriptions: • Updated/changed DESCRIPTION of Bits 31:28 (VARIANT) Contents Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 9 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the TMS320DM6441 SoC. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count. Table 2-1. Characteristics of the Processor HARDWARE FEATURES DM6441 DDR2 Memory Controller DDR2 (16/32-bit bus width) Asynchronous EMIF (EMIFA) Asynchronous (8/16-bit bus width) RAM, Flash (NOR, NAND) Flash Cards Compact Flash MMC/SD with secure data input/output (SDIO) SmartMedia/xD Memory Stick/Memory Stick PRO EDMA3 64 independent channels 8 QDMA channels Timers 2 64-bit general purpose (each configurable as 2 separate 32-bit timers) 64-bit watch dog Peripherals UART Not all peripherals pins SPI are available at the I2C same time. (For more details, see Section 3, Audio Serial Port [ASP] Device Configurations.) 10/100 Ethernet MAC with Management Data Input/Output 3 (one with RTS and CTS flow control) 1 (supports 2 slave devices) 1 (master/slave) 1 1 VLYNQ 1 HPI 1 (16-bit multiplexed address/data) General-Purpose Input/Output Port Up to 71 PWM 3 outputs ATA/CF 1 (ATA/ATAPI-5) Configurable Video Ports 1 input (VPFE) 1 output (VPBE) USB 2.0 High speed client VICP 1 Size (Bytes) On-Chip Memory 160KB RAM, 8KB ROM DSP • 32KB L1 program (L1P)/cache (up to 32KB) • 80KB L1 data (L1D)/cache (up to 32KB) • 64KB unified mapped RAM/cache (L2) Organization ARM • 16KB I-cache • 8KB D-cache • 16KB RAM • 8KB ROM CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) C64x+ Megamodule Revision Revision ID Register (MM_REVID[15:0]) (address location: 0x0181 2000) 0x0000 (Silicon Revision 1.3 and earlier) 0x0003 (Silicon Revision 2.1 and later) JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) 0x0B70 002F (Silicon Revision 1.3 and earlier) 0x1B70 002F (Silicon Revision 2.1 and later) CPU Frequency MHz 10 0x1000 DSP 405 MHz , ARM 202.5 MHz at 1.05 V DSP 513 MHz, ARM 256 MHz at 1.2 V Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-1. Characteristics of the Processor (continued) HARDWARE FEATURES Cycle Time Voltage ns DSP 1.9 ns, ARM 3.9 ns at 1.2V Core (V) 1.05 V, 1.2 V I/O (V) 1.8 V, 3.3 V PLL Options CLKIN frequency multiplier (27 MHz reference) BGA Package 16 x 16 mm ball finish SnAgCu Process Technology µm Product Status (1) Product Preview (PP), Advance Information (AI), Production Data (PD) (1) 2.2 DM6441 DSP 2.47 ns, ARM 4.94 ns at 1.05 V x1 (bypass), x15 (1.05 V), x19 (1.2 V) 361-pin BGA (ZWT) 0.09 µm PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the C64x DSP family. 2.3 ARM Subsystem The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the VPSS subsystem, and a majority of the peripherals and external memories. The ARM subsystem includes the following features: • ARM926EJ-S RISC processor • ARMv5TEJ (32/16-bit) instruction set • Little endian • Coprocessor 15 (CP15) • MMU • 16KB instruction cache • 8KB data cache • Write buffer • 16KB internal RAM (32-bit-wide access) • 8KB internal ROM (ARM bootloader for non-EMIFA boot options) • Embedded trace module and embedded trace buffer (ETM/ETB) • ARM interrupt controller • PLL controller • Power and sleep controller (PSC) • System module Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 11 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2.3.1 www.ti.com ARM926EJ-S RISC CPU The ARM subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: • ARM926EJ -S integer core • CP15 system control coprocessor • Memory management unit (MMU) • Separate instruction and data caches • Write buffer • Separate instruction and data tightly-coupled memories (TCMs) [internal RAM] interfaces • Separate instruction and data AHB bus interfaces • Embedded trace module and embedded trace buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com. 2.3.2 CP15 The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, tightly-coupled memories (TCMs), memory management unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. 2.3.3 MMU The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux™, WindowCE®, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified translation lookaside buffer (TLB) to cache the information held in the page tables. The MMU features are: • Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme. • Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages) • Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) • Hardware page table walks • Invalidate entire TLB, using CP15 register 8 • Invalidate TLB entry, selected by MVA, using CP15 register 8 • Lockdown of TLB entries, using CP15 register 10 12 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 2.3.4 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Caches and Write Buffer The size of the instruction cache is 16KB, data cache is 8KB. Additionally, the caches have the following features: • Virtual index, virtual tag, and addressed using the modified virtual address (MVA) • Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache • Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables. • Critical-word first cache refilling • Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption • Dcache stores the physical address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the virtual address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address. • Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry. 2.3.5 Tightly Coupled Memory (TCM) ARM internal RAM is provided for storing real-time and performance-critical code/data and the interrupt vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA3 or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers. Instruction and data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction region at 0x0000 and data region at 0x8000 map to the same physical 16K-byte TCM RAM. Placing the instruction region at 0x0000 is necessary to allow the ARM interrupt vector table to be placed at 0x0000, as required by the ARM architecture. The internal 16K-byte RAM is split into two physical banks of 8KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks. 2.3.6 Advanced High-performance Bus (AHB) The ARM subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the config bus and the external memories bus. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 13 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2.3.7 www.ti.com Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an embedded trace macrocell (ETM). The ARM926ES-J subsystem in the DM6441 also includes the embedded trace buffer (ETB). The ETM consists of two parts: • Trace port provides real-time trace capability for the ARM9. • Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. The DM6441 trace port is not pinned out and is instead only connected to the embedded trace buffer. The ETB has a 4K-byte buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. 2.3.8 ARM Memory Mapping The ARM memory map is shown in Section 2.5, Memory Map Summary, of this document. The ARM has access to memories shown in the following sections. 2.3.8.1 ARM Internal Memories The ARM has access to the following ARM internal memories: • 16KB ARM internal RAM on TCM interface, logically separated into two 8-KB pages to allow simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions. • 8KB ARM internal ROM 2.3.8.2 External Memories The ARM has access to the following external memories: • DDR2 synchronous DRAM • Asynchronous EMIF / NOR flash / NAND flash • ATA/CF • Flash card devices: – MMC/SD with SDIO – Memory Stick/Memory Stick PRO – xD – SmartMedia 2.3.8.3 DSP Memories The ARM has access to the following DSP memories: • L2 RAM • L1P RAM • L1D RAM 2.3.8.4 VICP Registers and Memories The ARM has access to the registers and memories of the video/imaging coprocessor (VICP) subsystem. 14 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 2.3.8.5 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 ARM-DSP Integration DM6441 ARM and DSP integration features are as follows: • DSP visibility from ARM’s memory map, see Section 2.5, Memory Map Summary, for details • Boot modes for DSP - see Device Configurations section, Section 3.3.3, DSP Boot, for details • ARM control of DSP boot / reset - see Device Configurations section, Section 3.3.2, ARM Boot, for details • ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for details • ARM & DSP Interrupts - see Section 6.7.1, ARM CPU Interrupts, and Section 6.7.2, DSP Interrupts, for details 2.3.9 Peripherals The ARM9 has access to all of the peripherals on the DM6441 device with the exception of the VICP. 2.3.10 PLL Controller (PLLC) The ARM subsystem includes the PLL controller. The PLL controller contains a set of registers for configuring DM6441’s two internal PLLs (PLL1 and PLL2). The PLL controller provides the following configuration and control: • PLL bypass mode • Set PLL multiplier parameters • Set PLL divider parameters • PLL power down • Oscillator power down The PLLs are briefly described in this document in Section 6.6, Clock PLLs. For more detailed information on the PLLs and PLL Controller register descriptions, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). 2.3.11 Power and Sleep Controller (PSC) The ARM subsystem includes the power and sleep controller (PSC). Through register settings accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power domain shut-off. Brief details on the PSC are given in Section 6.3, Power Supplies. For more detailed information and complete register descriptions for the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). 2.3.12 ARM Interrupt Controller (AINTC) The ARM interrupt controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ (interrupt request) or FIQ (fast interrupt request). The ARM interrupt controller is briefly described in this document in the Interrupts section. For detailed information on the ARM interrupt controller, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). 2.3.13 System Module The ARM subsystem includes the system module. The system module consists of a set of registers for configuring and controlling a variety of system functions. For details and register descriptions for the system module, see Section 3, Device Configurations, and see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 15 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 2.3.14 Power Management DM6441 has several means of managing power consumption. There is extensive use of clock gating, which reduces the power used by global device clocks and individual peripheral clocks. Clock management can be utilized to reduce clock frequencies in order to reduce switching power. For more details on power management techniques, see Section 3, Device Configurations, Section 6, Peripheral and Electrical Specifications, and see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). DM6441 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to customize an optimal power management strategy. Several typical power management scenarios are described in the following sections. 2.4 DSP Subsystem The DSP subsystem includes the following features: • C64x+ DSP CPU • 32KB L1 program (L1P)/cache (up to 32KB) • 80KB L1 data (L1D)/cache (up to 32KB) • 64KB unified mapped RAM/cache (L2) • Little endian 2.4.1 C64x+ DSP CPU Description The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining eight or 32 MSBs in the next upper register (which is always an odd-numbered register). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. 16 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. • Compact instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. • Instruction set enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. • Exceptions handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). • Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. • Time-stamp counter - Primarily targeted for real-time operating system (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: • TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732) • TMS320C64x Technical Overview (literature number SPRU395) Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 17 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Á ÁÁ Á Á Á ÁÁ Á ÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á www.ti.com src1 Odd register file A (A1, A3, A5...A31) src2 .L1 odd dst Even register file A (A0, A2, A4...A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src 8 8 even dst odd dst .S1 src1 Data path A (D) src2 LD1b LD1a 32 LSB DA2 32 32 src2 32 MSB DA1 LD2a LD2b Á Á Á Á Á Á .M1 dst2 dst1 src1 (A) (B) (C) dst .D1 src1 src2 2x 1x Odd register file B (B1, B3, B5...B31) src2 .D2 32 LSB 32 MSB src1 dst src2 .M2 Even register file B (B0, B2, B4...B30) (C) src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst even dst long src Data path B ST2a ST2b 32 MSB 32 LSB long src even dst .L2 (D) 8 8 (D) odd dst src2 src1 Control Register A. B. C. D. On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths 18 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 2.4.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DSP Memory Mapping The DSP memory map is shown in Table 2-3. Configuration of the control registers for DDR2, EMIFA, and ARM internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections. 2.4.2.1 ARM Internal Memories The DSP has access to the 16KB ARM internal RAM on the ARM D-TCM interface (i.e., data only). 2.4.2.2 External Memories The DSP has access to the following external memories: • DDR2 synchronous DRAM • Asynchronous EMIF / NOR Flash 2.4.2.3 DSP Internal Memories The DSP has access to the following DSP memories: • L2 RAM • L1P RAM • L1D RAM 2.4.2.4 C64x+ CPU The C64x+ core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is 32 KB direct mapped cache and the Level 1 data cache (L1D) is 80 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device. Table 2-2. C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 0000 L2CFG 0x0184 0020 L1PCFG 0x0184 0024 L1PCC 0x0184 0040 L1DCFG 0x0184 0044 L1DCC 0x0184 0048 - 0x0184 0FFC - 0x0184 1000 EDMAWEIGHT DESCRIPTION L2 cache configuration register L1P size cache configuration register L1P freeze mode cache configuration register L1D size cache configuration register L1D freeze mode cache configuration register Reserved L2 EDMA3 access control register 0x0184 1004 - 0x0184 1FFC - 0x0184 2000 L2ALLOC0 Reserved L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register Reserved 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 19 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-2. C64x+ Cache Registers (continued) HEX ADDRESS RANGE REGISTER ACRONYM 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register DESCRIPTION 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - 0x0184 4040 L1DWBAR L1D block writeback 0x0184 4044 L1DWWC L1D block writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register Reserved 0x0184 4050 - 0x0184 4FFF - 0x0184 5000 L2WB Reserved 0x0184 5004 L2WBINV 0x0184 5008 L2INV 0x0184 500C - 0x0184 5027 - 0x0184 5028 L1PINV 0x0184 502C - 0x0184 5039 - L2 writeback all register L2 writeback invalidate all register L2 global invalidate without writeback Reserved L1P global invalidate Reserved 0x0184 5040 L1DWB 0x0184 5044 L1DWBINV L1D global writeback 0x0184 5048 L1DINV L1D global invalidate without writeback 0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF 0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory attribute registers for EMIFA 0x0200 0000 - 0x09FF FFFF 0x0184 8028 - 0x0184 802C MAR10 - MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF 0x0184 8030 - 0x0184 803C MAR12 - MAR15 Memory attribute registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF 0x0184 8040 - 0x0184 8104 MAR16 - MAR65 Reserved 0x1000 0000 - 0x41FF FFFF 0x0184 8108 - 0x0184 813C MAR66 - MAR79 Memory attribute registers for EMIFA/VLYNQ shadow 0x4200 0000 0x4FFF FFFF L1D global writeback with invalidate 0x0184 8140- 0x0184 81FC MAR80 - MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF 0x0184 8200 - 0x0184 823C MAR128 - MAR143 Memory attribute registers for DDR2 0x8000 0000 - 0x8FFF FFFF 0x0184 8240 - 0x0184 83FC MAR144 - MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF 2.4.3 Peripherals The DSP has controllability for the following peripherals: • VICP • EDMA3 • ASP • Two Timers (Timer 0 and Timer1) that can each be configured as one 64-bit or two 32-bit timers 2.4.4 DSP Interrupt Controller The DSP interrupt controller accepts device interrupts and appropriately maps them to available DSP interrupts. The DSP interrupt controller is briefly described in this document in the Interrupts section. For more detailed on the DSP interrupt controller, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). 2.5 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the configuration space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. 20 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-3. Memory Map Summary START ADDRESS END ADDRESS SIZE (Bytes) ARM EDMA3/ PERIPHERAL C64x+ HPI VPSS 0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction) 0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction) 0x0000 4000 0x0000 5FFF 8K ARM ROM (Instruction) 0x0000 6000 0x0000 7FFF 8K Reserved 0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) 0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) 0x0000 C000 0x0000 DFFF 8K ARM ROM (Data) 0x0000 E000 0x0000 FFFF 8K 0x0001 0000 0x000F FFFF 960K 0x0010 0000 0x001F FFFF 1M VICP 0x0020 0000 0x007F FFFF 6M Reserved 0x0080 0000 0x0080 FFFF 64K L2 RAM/Cache 0x0081 0000 0x00E0 7FFF 6112K 0x00E0 8000 0x00E0 FFFF 32K L1P Cache 0x00E1 0000 0x00F0 3FFF 976K Reserved 0x00F0 4000 0x00F0 FFFF 48K L1D RAM 0x00F1 0000 0x00F1 7FFF 32K L1D Cache 0x00F1 8000 0x017F FFFF 9120K Reserved 0x0180 0000 0x01BB FFFF 3840K 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals 0x0200 0000 0x09FF FFFF 128M EMIFA (Code and Data) EMIFA (Data) EMIFA (Data) 0x0A00 0000 0x0BFF FFFF 32M Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) 0x1000 0000 0x1000 7FFF 32K 0x1000 8000 0x1000 9FFF 8K ARM RAM0 ARM RAM0 0x1000 A000 0x1000 BFFF 8K ARM RAM1 ARM RAM1 0x1000 C000 0x1000 DFFF 8K ARM ROM ARM ROM 0x1000 E000 0x1000 FFFF 8K Reserved Reserved 0x1001 0000 0x110F FFFF 17344K 0x1110 0000 0x111F FFFF 1M VICP VICP VICP 0x1120 0000 0x117F FFFF 6M Reserved Reserved Reserved 0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache 0x1181 0000 0x11E0 7FFF 6112K Reserved Reserved Reserved 0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache 0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved 0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM 0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache 0x11F1 8000 0x1FFF FFFF 241M-32K Reserved Reserved Reserved 0x2000 0000 0x2000 7FFF 32K DDR2 Control Regs DDR2 Control Regs DDR2 Control Regs DDR2 Control Regs 0x2000 8000 0x41FF FFFF 544M-32k Reserved Reserved Reserved Reserved 0x4200 0000 (1) 0x4FFF FFFF 224M Reserved EMIFA/VLYNQ Shadow EMIFA/VLYNQ Shadow 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved Reserved Reserved Reserved ARM RAM0 ARM RAM0 ARM RAM1 ARM RAM1 ARM ROM ARM ROM Reserved Reserved Reserved CFG Space Reserved Reserved Reserved Reserved VLYNQ (Remote) Reserved Reserved (1) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000 through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be used by C64x+ for both code execution and data accesses. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 21 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-4. Configuration Memory Map Summary START ADDRESS END ADDRESS SIZE (Bytes) 0x0180 0000 0x0180 FFFF 64K C64x+ interrupt controller 0x0181 0000 0x0181 0FFF 4K C64x+ powerdown controller 0x0181 1000 0x0181 1FFF 4K C64x+ security ID 0x0181 2000 0x0181 2FFF 4K C64x+ revision ID 0x0182 0000 0x0182 FFFF 64K 0x0183 0000 0x0183 FFFF 64K Reserved 0x0184 0000 0x0184 FFFF 64K C64x+ memory system 0x0185 0000 0x0187 FFFF 192K Reserved 0x0188 0000 0x01BB FFFF 3328K Reserved 0x01BC 0000 0x01BC 00FF 256 0x01BC 0100 0x01BC 01FF 256 0x01BC 0200 0x01BC 0FFF 3.5K 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA3 CC EDMA3 CC 0x01C1 0000 0x01C1 03FF 1K EDMA3 TC0 EDMA3 TC0 0x01C1 0400 0x01C1 07FF 1K EDMA3 TC1 EDMA3 TC1 0x01C1 8800 0x01C1 9FFF 6K 0x01C1 A000 0x01C1 FFFF 24K 0x01C2 0000 0x01C2 03FF 1K UART0 0x01C2 0400 0x01C2 07FF 1K UART1 0x01C2 0800 0x01C2 0BFF 1K UART2 0x01C2 0C00 0x01C2 0FFF 1K Reserved 0x01C2 1000 0x01C2 13FF 1K I2C 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2 (WatchDog) 0x01C2 2000 0x01C2 23FF 1K PWM0 0x01C2 2400 0x01C2 27FF 1K PWM1 0x01C2 2800 0x01C2 2BFF 1K PWM2 0x01C2 2C00 0x01C3 FFFF 117K Reserved 0x01C4 0000 0x01C4 07FF 2K System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2 0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller Power and sleep controller 0x01C4 2000 0x01C4 202F 48 Reserved Reserved 0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP reg 0x01C4 2034 0x01C4 23FF 1K - 52 0x01C4 2400 0x01C4 7FFF 23K 0x01C4 8000 0x01C4 83FF 1K 0x01C4 8400 0x01C5 FFFF 95K 0x01C6 0000 0x01C6 3FFF 16K 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Regs / RAM 0x01C6 6000 0x01C6 67FF 2K ATA/CF 0x01C6 6800 0x01C6 6FFF 2K SPI 0x01C6 7000 0x01C6 77FF 2K GPIO 22 ARM/EDMA3 Reserved C64x+ C64x+ EMC Reserved ARM ETB Memory Pin manager and trace Reserved Reserved Reserved Reserved System module Reserved Reserved ARM interrupt controller Reserved Reserved Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-4. Configuration Memory Map Summary (continued) START ADDRESS END ADDRESS SIZE (Bytes) ARM/EDMA3 C64x+ 0x01C6 7800 0x01C6 7FFF 2K HPI HPI 0x01C6 8000 0x01C6 FFFF 32K Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Regs 0x01C7 4000 0x01C7 FFFF 48K Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Regs 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Regs 0x01C8 2000 0x01C8 3FFF 8K EMAC Control Module RAM 0x01C8 4000 0x01C8 47FF 2K MDIO Control Regs 0x01C8 4800 0x01C8 4FFF 2K 0x01C8 5000 0x01CB FFFF 236K 0x01CC 0000 0x01CD FFFF 128K 0x01CE 0000 0x01CF FFFF 128K 0x01D0 0000 0x01DF FFFF 1M 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control 0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Regs 0x01E0 2000 0x01E0 3FFF 8K ASP 0x01E0 4000 0x01E0 FFFF 48K Reserved 0x01E1 0000 0x01E1 FFFF 64K MMC/SD/SDIO 0x01E2 0000 0x01E3 FFFF 128K Memory Stick/Memory Stick PRO 0x01E4 0000 0x01FF FFFF 1792K Reserved 0x0200 0000 0x03FF FFFF 32M EMIFA Data/Code (CS2) EMIFA data (CS2) 0x0400 0000 0x05FF FFFF 32M EMIFA Data/Code (CS3) EMIFA data (CS3) 0x0600 0000 0x07FF FFFF 32M EMIFA Data/Code (CS4) EMIFA data (CS4) 0x0800 0000 0x09FF FFFF 32M EMIFA Data/Code (CS5) EMIFA data (CS5) 0x0A00 0000 0x0BFF FFFF 32M Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved Reserved VICP VICP Reserved Reserved ASP Reserved Reserved Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 23 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2.6 www.ti.com Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 3.5.2, Multiplexed Pin Configurations, of this document. 2.6.1 Pin Map (Bottom View) Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A, B, C, and D). 1 2 3 4 5 6 7 8 9 10 W RSV3 DDR_D[4] DDR_D[7] DDR_D[9] DDR_D[12] DDR_D[14] DDR_CLK0 DDR_CLK0 DDR_A[12] DDR_A[11] W V DDR_D[2] DDR_D[3] DDR_D[6] DDR_D[8] DDR_D[11] DDR_D[13] DDR_D[15] DDR_CKE DDR_BS[1] DDR_A[8] V U DDR_D[0] DDR_D[1] DDR_D[5] DDR_DQS[0] DDR_D[10] DDR_DQS[1] DDR_RAS DDR_BS[0] DDR_BS[2] DDR_A[10] U T EM_CS5/ GPIO8/ VLYNQ_ CLOCK EM_CS4/ GPIO9/ VLYNQ_ SCRUN EM_A[21]/ GPIO10/ VLYNQ_TXD0 DDR_ DQM[0] DVDDR2 DDR_ DQM[1] DDR_CAS DDR_WE DDR_CS DDR_VDDDLL T R EM_A[12]/ GPIO19 VSS VSS RSV7 DVDDR2 VSS R P EM_A[10]/ GPIO21 EM_A[11]/ GPIO20 DVDDR2 VSS DVDDR2 VSS DVDDR2 P N EM_A[6]/ GPIO25 EM_A[7]/ GPIO24 EM_A[8]/ GPIO23 EM_A[13]/ GPIO18 DVDD18 VSS DVDDR2 VSS DVDDR2 VSS N M MXO PLLVDD18 RSV24 EM_A[9]/ GPIO22 VSS DVDD18 VSS CVDD VSS CVDD M L MXI/CLKIN MXV SS RSV6 RESET MXV DD VSS DVDD18 CVDD CVDD CVDD L K CLK_OUT0/ GPIO48 EM_A[3]/ GPIO28 EM_A[5]/ GPIO26 EM_A[4]/ GPIO27 VSS VSS CVDDDSP CVDDDSP CVDD K 1 2 3 4 5 7 8 9 10 EM_A[16]/ EM_A[17]/ EM_A[19]/ EM_A[20]/ GPIO15/ GPIO14/ GPIO12/ GPIO11/ VLYNQ_TXD2 VLYNQ_RXD0 VLYNQ_TXD1 VLYNQ_RXD2 EM_A[14]/ EM_A[18]/ EM_A[15]/ GPIO17/ GPIO13/ GPIO16/ VLYNQ_TXD3 VLYNQ_RXD3 VLYNQ_RXD1 DVDD18 6 Figure 2-2. Pin Map [Quadrant A] 24 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 11 12 13 14 15 16 17 18 19 W DDR_A[6] DDR_A[5] DDR_A[0] DDR_D[16] DDR_D[18] DDR_D[21] DDR_D[27] DDR_D[29] RSV4 W V DDR_A[7] DDR_A[4] DDR_A[2] DDR_D[17] DDR_D[19] DDR_D[22] DDR_D[24] DDR_D[28] DDR_D[30] V U DDR_A[9] DDR_A[3] DDR_A[1] DDR_DQS[2] DDR_D[20] DDR_DQS[3] DDR_D[25] DDR_D[26] DDR_D[31] U T DDR_ VSSDLL DDR_ZN DDR_ZP DDR_DQM[2] DDR_VREF DDR_DQM[3] DDR_D[23] VSSA_1P1V DAC_IOUT_D T R DVDDR2 VSS DVDDR2 VSS DVDDR2 DAC_RBIAS DAC_VREF VDDA_1P8V DAC_IOUT_C R P VSS DVDDR2 VSS DVDDR2 VSS VDDA_1P1V VSSA_1P8V DAC_IOUT_B DAC_IOUT_A P N DVDDR2 VSS DVDDR2 VSS CI3/CCD11 CI4/CCD12/ UART_RTS2 CI5/CCD13/ UART_CTS2 CI6/CCD14/ UART_TXD2 CI7/CCD15/ UART_RXD2 N M VSS CVDD VSS DVDD18 CI0/CCD8 CI1/CCD9 CI2/CCD10 HD PCLK M L CVDD VSS DVDD18 VSS YI4/CCD4 YI5/CCD5 YI6/CCD6 YI7/CCD7 VD L K CVDDDSP CVDD VSS DVDD18 VSS YI0/CCD0 YI1/CCD1 YI2/CCD2 YI3/CCD3 K 11 12 13 14 15 16 17 18 19 Figure 2-3. Pin Map [Quadrant B] Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 25 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 11 12 13 14 15 16 17 18 19 J CVDDDSP VSS CVDDDSP VSS DVDD18 USB_ID USB_VBUS USB_ VSSA3P3 USB_ VDDA3P3 J H CVDDDSP CVDDDSP VSS DVDD18 VSS USB_V SS1P8 USB_V DD1P8 USB_R1 USB_DM H G VSS VSS VSS VSS DVDD18 USB_ VSSREF USB_ VSSA1P2LD0 USB_ VDDA1P2LD0 USB_DP G F DVDD33 DVDD33 DVDD33 DVDD18 CVDD M24VDD M24VSS M24XI M24XO F E GPIOV33_10/ RXD3 GPIOV33_7/ RXD0 GPIO1/ C_WE GPIO5/G1 YOUT4/R4/ AEAW4 YOUT5/R5 YOUT6/R6 YOUT7/R7 CLK_OUT1/ TIM_IN/ GPIO49 E D GPIOV33_12/ RXDV GPIOV33_4/ TXD1 GPIO2/G0 GPIO38/R1 YOUT0/G5/ AEAW0 YOUT1/G6/ AEAW1 YOUT2/G7/ AEAW2 YOUT3/R3/ AEAW3 VCLK D C GPIOV33_8/ RXD1 GPIOV33_6/ TXD3 GPIO0/ LCD_OE GPIO3/B0/ LCD_FIELD PWM0/ GPIO45 COUT7/G4 HSYNC VSYNC VPBECLK C B GPIOV33_9/ RXD2 GPIOV33_3/ TXD0 GPIOV33_0/ TXEN GPIO4/R0/ C_FIELD PWM1/R2/ GPIO46 COUT1/B4/ BTSEL1 COUT3/B6/ DSP_BT COUT5/G2 COUT6/G3 B A GPIOV33_5/ TXD2 GPIOV33_2/ COL GPIOV33_1/ TXCLK GPIO6/B1 PWM2/ B2/GPIO47 COUT0/B3/ BTSEL0 COUT2/B5/ EM_WIDTH COUT4/B7 RSV2 A 11 12 13 14 15 16 17 18 19 Figure 2-4. Pin Map [Quadrant C] 26 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 1 2 3 4 5 6 7 8 9 10 J EM_A[2]/ (CLE)/ HCNTL0 EM_A[1]/ (ALE)/ HHWIL EM_BA[0]/ DA0/ HINT EM_A[0]/ DA2/ HCNTL1/ GPIO53 GPIO50/ ATA_CS0 VSS DVDD18 VSS CVDDDSP CVDDDSP H GPIO51/ ATA_CS1 EM_BA[1]/ DA1/ GPIO52 DMACK/ UART_TXD1 EM_OE/(RE)/ (IORD)/DIOR/ HDS1 EM_D14/ DD14/ HD14 DVDD18 VSS CVDDDSP VSS CVDDDSP H G DMARQ/ UART_RXD1 EM_WE/(WE)/ (IOWR)/DIOW/ HDS2 EM_R/W/ INTRQ/ HR/W EM_D11/ DD11/ HD11 EM_D10/ DD10/ HD10 VSS DVDD18 VSS DVDD18 VSS G F EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY EM_D13/ DD13/ HD13 EM_D8/ DD8/ HD8 EM_D6/ DD6/ HD6 EM_D2/ DD2/ HD2 DVDD18 VSS DVDD18 VSS DVDD33 F E EM_D15/ DD15/ HD15 EM_D9/ DD9/ HD9 EM_D3/ DD3/ HD3 EM_D4/ DD4/ HD4 EM_D0/ DD0/ HD0 TMS DVDD18 VSS SD_DATA1 GPIOV33_15/ MDIO E D EM_D12/ DD12/ HD12 EM_D5/ DD5/ HD5 EM_D1/ DD1/ HD1 RSV5 UART_RXD0/ GPIO35 EMU0 TRST SD_DATA0 SD_DATA2 GPIOV33_13/ D RXER C EM_D7/ DD7/ HD7 EM_CS2/ HCS GPIO7 UART_TXD0/ GPIO36 EMU1 FSR/ GPIO32 FSX/ GPIO31 SD_DATA3 GPIOV33_14/ C CRS B EM_CS3 SPI_EN1/ HDDIR/ GPIO42 SPI_DI/ GPIO40 SDA/GPIO44 TDO RTCK DX/ GPIO33 A RSV1 SPI_DO/ GPIO41 SPI_CLK/ GPIO39 SPI_EN0/ GPIO37 TDI TCK DR/ GPIO34 1 2 3 4 5 6 7 SCL/ GPIO43 J CLKX/ GPIO29 SD_CMD GPIOV33_16/ MDCLK B CLKR/ GPIO30 SD_CLK GPIOV33_11/ RXCLK A 8 9 10 Figure 2-5. Pin Map [Quadrant D] Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 27 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2.7 www.ti.com Terminal Functions The terminal functions tables (Table 2-5 through Table 2-30) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see Section 3, Device Configurations, of this data manual. Table 2-5. BOOT Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION (3) BOOT COUT0/ B3/ BTSEL0 COUT1/ B4/ BTSEL1 COUT2/ B5/ EM_WIDTH (1) (2) (3) 28 A16 B16 A17 I/O/Z I/O/Z I/O/Z IPD DVDD18 IPD DVDD18 These pins are multiplexed between ARM boot mode and the VPBE. At reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to determine the ARM boot configuration. See below for the boot modes set by these inputs. See Section 3.3, Bootmode, for more details. After reset, these are video encoder outputs COUT0 and COUT1, or RGB666/888 Blue output data bits 3 and 4 B3/B4. BTSEL1 BTSEL0 0 0 ARM ROM boot (NAND, SPI) [default] ARM Boot Mode 0 1 ARM EMIFA boot (NOR) 1 0 ARM ROM boot (HPI) 1 1 ARM ROM boot (UART0) IPD DVDD18 This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit-wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data bus, EM_WIDTH = 1. After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5 B5. This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1. After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output B6. COUT3/ B6/ DSP_BT B17 I/O/Z IPD DVDD18 YOUT0/ G5/ AEAW0 D15 I/O/Z IPD DVDD18 YOUT1/ G6/ AEAW1 D16 I/O/Z IPD DVDD18 YOUT2/ G7/ AEAW2 D17 I/O/Z IPD DVDD18 YOUT3/ R3/ AEAW3 D18 I/O/Z IPD DVDD18 YOUT4/ R4/ AEAW4 E15 I/O/Z IPD DVDD18 These pins are multiplexed between EMIFA and the VPBE. At reset, the input states of AEAW[4:0] are sampled to set the EMIFA address bus width. See Section 3.4.2, Peripheral Selection at Device Reset, for details. After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-6. Oscillator/PLL Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION OSCILLATOR, PLL (1) (2) (3) (4) MXI/CLKIN L1 I DVDD18 Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz). If a crystal input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input. MXO M1 O DVDD18 Crystal output for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXO should be left as a No Connect. MXVDD L5 S MXVSS L2 GND (3) M24XI F18 I DVDD18 Crystal input for M24 oscillator (24 MHz for USB). If a crystal input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input. When the USB peripheral is not used, M24XI should be left as a No Connect. M24XO F19 O DVDD18 Crystal output for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24XO should be left as a No Connect. When the USB peripheral is not used, M24XO should be left as a No Connect. M24VDD F16 S (3) 1.8-V power supply for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24VDD should still be connected to the 1.8-V power supply. When the USB peripheral is not used, M24VDD should be connected to the 1.8-V power supply. M24VSS F17 GND PLLVDD18 M2 S 1.8-V power supply for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXVDD should still be connected to the 1.8-V power supply. (3) Ground for MX oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, MXVSS should still be connected to ground. (4) Ground for M24 oscillator. If a crystal input is not used, but instead a physical clock-in source is supplied, M24VSS should still be connected to ground. When the USB peripheral is not used, M24VSS should be connected to ground. (4) 1.8-V power supply for PLLs (system). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information, see Section 5.2, Recommended Operating Conditions. For more information, see Section 5.2, Recommended Operating Conditions. Table 2-7. Clock Generator Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION CLOCK GENERATOR (1) (2) CLK_OUT0/ GPIO48 K1 I/O/Z DVDD18 This pin is multiplexed between the PLL1 clock generator and GPIO. For the PLL1 clock generator, it is clock output CLK_OUT0. This is configurable for 13.5 MHz or 27 MHz clock outputs. CLK_OUT1/ TIM_IN/ GPIO49 E19 I/O/Z DVDD18 This pin is multiplexed between the USB clock generator, timer, and GPIO. For the USB clock generator, it is clock output CLK_OUT1. This is configurable for 12 MHz or 24 MHz clock outputs. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 29 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-8. RESET and JTAG Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION RESET RESET L4 I IPU DVDD18 This is the active low global reset input. JTAG (1) (2) (3) TMS E6 I IPU DVDD18 JTAG test-port mode select input TDO B5 O/Z – DVDD18 JTAG test-port data output TDI A5 I IPU DVDD18 JTAG test-port data input TCK A6 I IPU DVDD18 JTAG test-port clock input RTCK B6 O/Z – DVDD18 JTAG test-port return clock output TRST D7 I IPD DVDD18 JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data manual (Section 6.26, IEEE 1149.1 JTAG). EMU1 C6 I/O/Z IPU DVDD18 Emulation pin 1 EMU0 D6 I/O/Z IPU DVDD18 Emulation pin 0 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Table 2-9. EMIFA Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA BOOT CONFIGURATION COUT2/ B5/ EM_WIDTH (1) (2) (3) 30 A17 I/O/Z IPD DVDD18 This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit-wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data bus, EM_WIDTH = 1. After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5 B5. This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1. After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output B6. COUT3/ B6/ DSP_BT B17 I/O/Z IPD DVDD18 YOUT0/ G5/ AEAW0 D15 I/O/Z IPD DVDD18 YOUT1/ G6/ AEAW1 D16 I/O/Z IPD DVDD18 YOUT2/ G7/ AEAW2 D17 I/O/Z IPD DVDD18 YOUT3/ R3/ AEAW3 D18 I/O/Z IPD DVDD18 YOUT4/ R4/ AEAW4 E15 I/O/Z IPD DVDD18 These pins are multiplexed between EMIFA and the VPBE. At reset, the input states of AEAW[4:0] are sampled to set the EMIFA address bus width. See Section 3.4.2, Peripheral Selection at Device Reset, for details. After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA FUNCTIONAL PINS: ASYNC / NOR EM_CS2/ HCS C2 I/O/Z DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot and ROM boot modes. EM_CS3 B1 I/O/Z DVDD18 For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_CS4/ GPIO9/ VLYNQ_SCRUN T2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_CS5/ GPIO8/ VLYNQ_CLOCK T1 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_R/W/ INTRQ/ HR/W G3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, it is read/write output EM_R/W. EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY F1 I/O/Z IPU DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is wait state extension input EM_WAIT. EM_OE/ (RE)/ (IORD)/ DIOR/ HDS1 H4 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is output enable output EM_OE. EM_WE (WE) (IOWR)/ DIOW/ HDS2 G2 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE. IPD DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, this is the Bank Address 0 output (EM_BA[0]). When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. When connected to a 16-bit asynchronous memory, this pin has the same function as EMIF address pin 22 (EM_A[22]). EM_BA[0]/ DA0/ HINT J3 I/O/Z EM_BA[1]/ DA1/ GPIO52 H2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is the Bank Address 1 output EM_BA[1]. When connected to a 16 bit asynchronous memory this pin is the lowest order bit of the 16-bit word address. When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address. EM_A[21]/ GPIO10/ VLYNQ_TXD0 T3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 21 output EM_A[21]. EM_A[20]/ GPIO11/ VLYNQ_RXD0 R3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 20 output EM_A[20]. EM_A[19]/ GPIO12/ VLYNQ_TXD1 R4 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 19 output EM_A[19]. EM_A[18]/ GPIO13/ VLYNQ_RXD1 P5 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 18 output EM_A[18]. EM_A[17]/ GPIO14/ VLYNQ_TXD2 R2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 17 output EM_A[17]. EM_A[16]/ GPIO15/ VLYNQ_RXD2 R5 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 16 output EM_A[16]. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 31 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. EM_A[15]/ GPIO16/ VLYNQ_TXD3 P3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 15 output EM_A[15]. EM_A[14]/ GPIO17/ VLYNQ_RXD3 P4 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is address bit 14 output EM_A[14]. EM_A[13]/ GPIO18 N4 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 13 output EM_A[13]. EM_A[12]/ GPIO19 R1 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 12 output EM_A[12]. EM_A[11]/ GPIO20 P2 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 11 output EM_A[11]. EM_A[10]/ GPIO21 P1 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 10 output EM_A[10]. EM_A[9]/ GPIO22 M4 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 9 output EM_A[9]. EM_A[8]/ GPIO23 N3 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 8 output EM_A[8]. EM_A[7]/ GPIO24 N2 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 7 output EM_A[7]. EM_A[6]/ GPIO25 N1 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 6 output EM_A[6]. EM_A[5]/ GPIO26 K3 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 5 output EM_A[5]. EM_A[4]/ GPIO27 K4 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 4 output EM_A[4]. EM_A[3]/ GPIO28 K2 I/O/Z DVDD18 This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 3 output EM_A[3]. EM_A[2]/ (CLE)/ HCNTL0 J1 I/O/Z DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is the EM_A[2] address line. EM_A[1]/ (ALE)/ HHWIL J2 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia.xD) and HPI. DVDD18 This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. For EMIFA, this is Address output EM_A[0], which is the least significant bit on a 32-bit word address. When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. EM_A[0]/ DA2/ HCNTL1/ GPIO53 32 J4 I/O/Z Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) NAME NO. EM_D0/ DD0/ HD0 E5 I/O/Z DVDD18 EM_D1/ DD1/ HD1 D3 I/O/Z DVDD18 EM_D2/ DD2/ HD2 F5 I/O/Z DVDD18 EM_D3/ DD3/ HD3 E3 I/O/Z DVDD18 EM_D4/ DD4/ HD4 E4 I/O/Z DVDD18 EM_D5/ DD5/ HD5 D2 I/O/Z DVDD18 EM_D6/ DD6/ HD6 F4 I/O/Z DVDD18 EM_D7/ DD7/ HD7 C1 I/O/Z DVDD18 EM_D8/ DD8/ HD8 F3 I/O/Z DVDD18 EM_D9/ DD9/ HD9 E2 I/O/Z DVDD18 EM_D10/ DD10/ HD10 G5 I/O/Z DVDD18 EM_D11/ DD11/ HD11 G4 I/O/Z DVDD18 EM_D12/ DD12/ HD12 D1 I/O/Z DVDD18 EM_D13/ DD13/ HD13 F2 I/O/Z DVDD18 EM_D14/ DD14/ HD14 H5 I/O/Z DVDD18 EM_D15/ DD15/ HD15 E1 I/O/Z DVDD18 (3) DESCRIPTION These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 33 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-9. EMIFA Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD EM_A[1]/ (ALE)/ HHWIL J2 I/O/Z DVDD18 This pin is multiplexed between EMIFA and HPI. For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE). EM_A[2]/ (CLE)/ HCNTL0 J1 I/O/Z DVDD18 This pin is multiplexed between EMIFA and HPI. For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE). EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY F1 I/O/Z IPU DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY). EM_OE/ ( RE )/ ( IORD )/ DIOR/ HDS1 H4 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is read enable output (RE). EM_WE (WE) (IOWR)/ DIOW/ HDS2 G2 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For NAND/SmartMedia/xD, it is write enable output (WE). EM_CS2/ HCS C2 I/O/Z DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot and ROM boot modes. EM_CS3 B1 I/O/Z DVDD18 For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous memories (i.e. NOR flash) or NAND flash. EM_CS4/ GPIO9/ VLYNQ_SCRUN T2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or NAND flash. EM_CS5/ GPIO8/ VLYNQ_CLOCK T1 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or NAND flash. 34 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) NAME NO. EM_D0/ DD0/ HD0 E5 I/O/Z DVDD18 EM_D1/ DD1/ HD1 D3 I/O/Z DVDD18 EM_D2/ DD2/ HD2 F5 I/O/Z DVDD18 EM_D3/ DD3/ HD3 E3 I/O/Z DVDD18 EM_D4/ DD4/ HD4 E4 I/O/Z DVDD18 EM_D5/ DD5/ HD5 D2 I/O/Z DVDD18 EM_D6/ DD6/ HD6 F4 I/O/Z DVDD18 EM_D7/ DD7/ HD7 C1 I/O/Z DVDD18 EM_D8/ DD8/ HD8 F3 I/O/Z DVDD18 EM_D9/ DD9/ HD9 E2 I/O/Z DVDD18 EM_D10/ DD10/ HD10 G5 I/O/Z DVDD18 EM_D11/ DD11/ HD11 G4 I/O/Z DVDD18 EM_D12/ DD12/ HD12 D1 I/O/Z DVDD18 EM_D13/ DD13/ HD13 F2 I/O/Z DVDD18 EM_D14/ DD14/ HD14 H5 I/O/Z DVDD18 EM_D15/ DD15/ HD15 E1 I/O/Z DVDD18 (3) DESCRIPTION These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 35 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-10. DDR2 Memory Controller Terminal Functions SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. DDR_CLK0 W7 I/O/Z DVDDR2 DDR2 clock DDR_CLK0 W8 I/O/Z DVDDR2 DDR2 differential clock DDR_CKE V8 I/O/Z DVDDR2 DDR2 clock enable DDR2 Memory Controller (1) (2) (3) 36 DDR_CS T9 I/O/Z DVDDR2 DDR2 active low chip select DDR_WE T8 I/O/Z DVDDR2 DDR2 active low write enable DDR_DQM[3] T16 I/O/Z DVDDR2 DDR_DQM[2] T14 I/O/Z DVDDR2 DDR_DQM[1] T6 I/O/Z DVDDR2 DDR_DQM[0] T4 I/O/Z DVDDR2 DDR2 data mask outputs DQM3: For upper byte data bus DDR_D[31:24] DQM2: For DDR_D[23:16] DQM1: For DDR_D[15:8] DQM0: For lower byte DDR_D[7:0] DDR_RAS U7 I/O/Z DVDDR2 DDR2 row access signal output DDR_CAS T7 I/O/Z DVDDR2 DDR2 column access signal output DDR_DQS[0] U4 I/O/Z DVDDR2 DDR_DQS[1] U6 I/O/Z DVDDR2 DDR_DQS[2] U14 I/O/Z DVDDR2 DDR_DQS[3] U16 I/O/Z DVDDR2 Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR2 memory when writing and inputs when reading. They are used to synchronize the data transfers. DQS3 : For upper byte DDR_D[31:24] DQS2: For DDR_D[23:16] DQS1: For DDR_D[15:8] DQS0: For bottom byte DDR_D[7:0] DDR_BS[0] U8 DDR_BS[1] V9 I/O/Z DVDDR2 Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories. I/O/Z DVDDR2 DDR2 address bus DDR_BS[2] U9 DDR_A[12] W9 DDR_A[11] W10 DDR_A[10] U10 DDR_A[9] U11 DDR_A[8] V10 DDR_A[7] V11 DDR_A[6] W11 DDR_A[5] W12 DDR_A[4] V12 DDR_A[3] U12 DDR_A[2] V13 DDR_A[1] U13 DDR_A[0] W13 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information, see Section 5.2, Recommended Operating Conditions. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-10. DDR2 Memory Controller Terminal Functions (continued) SIGNAL NAME NO. DDR_D[31] U19 DDR_D[30] V19 DDR_D[29] W18 DDR_D[28] V18 DDR_D[27] W17 DDR_D[26] U18 DDR_D[25] U17 DDR_D[24] V17 DDR_D[23] T17 DDR_D[22] V16 DDR_D[21] W16 DDR_D[20] U15 DDR_D[19] V15 DDR_D[18] W15 DDR_D[17] V14 DDR_D[16] W14 DDR_D[15] V7 DDR_D[14] W6 DDR_D[13] V6 DDR_D[12] W5 DDR_D[11] V5 DDR_D[10] U5 DDR_D[9] W4 DDR_D[8] V4 DDR_D[7] W3 DDR_D[6] V3 DDR_D[5] U3 DDR_D[4] W2 DDR_D[3] V2 DDR_D[2] V1 DDR_D[1] U2 DDR_D[0] U1 DDR_VREF T15 TYPE (1) I/O/Z OTHER (2) (3) DVDDR2 DESCRIPTION DDR2 data bus can be configured as 32-bits wide or 16-bits wide. I (4) Reference voltage input for the SSTL_18 IO buffers. Ground for the DDR2 digital locked loop. DDR_VSSDLL T11 GND (4) DDR_VDDDLL T10 S (4) Power (1.8 Volts) for the DDR2 digital locked loop. DDR_ZN T12 O/Z (4) Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor to DVDDR2. DDR_ZP T13 O/Z (4) Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor to VSS. (4) For more information, see Section 5.2, Recommended Operating Conditions. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 37 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-11. I2C Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION I2C (1) (2) SCL/ GPIO43 C4 I/O/Z DVDD18 This pin is multiplexed between I2C and GPIO. For I2C, it is clock output SCL. SDA/ GPIO44 B4 I/O/Z DVDD18 This pin is multiplexed between I2C and GPIO. For I2C, it is bidirectional data signal SDA. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-12. Audio Serial Port (ASP) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION Audio Serial Port (ASP) (1) (2) CLKX/ GPIO29 B8 I/O/Z DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is transmit clock IO CLKX. CLKR/ GPIO30 A8 I/O/Z DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is receive clock IO CLKR. FSX/ GPIO31 C8 I/O/Z DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is transmit frame synchronization IO FSX. FSR/ GPIO32 C7 I/O/Z DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is receive frame synchronization IO FSR. DX/ GPIO33 B7 I/O/Z DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is data transmit output DX. DR/ GPIO34 A7 I/O/Z DVDD18 This pin is multiplexed between ASP and GPIO. For ASP, it is data receive input DR. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-13. SPI Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION Serial Port Interface (SPI) (1) (2) 38 SPI_EN0/ GPIO37 A4 I/O/Z DVDD18 This pin is multiplexed between SPI and GPIO. When used by SPI, it is SPI slave device 0 enable output SPI_EN0. SPI_EN1/ HDDIR/ GPIO42 B2 I/O/Z DVDD18 This pin is multiplexed between SPI, ATA, and GPIO. When used by SPI, it is SPI slave device 1 enable output SPI_EN1. SPI_CLK/ GPIO39 A3 I/O/Z DVDD18 This pin is multiplexed between SPI and GPIO. For SPI, it is clock output SPI_CLK. SPI_DI/ GPIO40 B3 I/O/Z DVDD18 This pin is multiplexed between SPI and GPIO. For SPI, it is data input SPI_DI. SPI_DO/ GPIO41 A2 I/O/Z DVDD18 This pin is multiplexed between SPI and GPIO. For SPI it is data output SPI_DO. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-14. EMAC and MDIO Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION EMAC GPIOV33_0/ TXEN B13 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is transmit enable output TXEN. GPIOV33_1/ TXCLK A13 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is transmit clock output TXCLK. GPIOV33_2/ COL A12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is collision detect input COL. GPIOV33_6/ TXD3 C12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is transmit data 3 output TXD3. GPIOV33_5/ TXD2 A11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is transmit data 2 output TXD2. GPIOV33_4/ TXD1 D12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is transmit data 1 output TXD1. GPIOV33_3/ TXD0 B12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is transmit data 0 output TXD0. GPIOV33_11/ RXCLK A10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive clock input RXCLK. GPIOV33_12/ RXDV D11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive data valid input RXDV. GPIOV33_13/ RXER D10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive error input RXER. GPIOV33_14/ CRS C10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is carrier sense input CRS. GPIOV33_10/ RXD3 E11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive data 3 input RXD3. GPIOV33_9/ RXD2 B11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive data 2 input RXD2. GPIOV33_8/ RXD1 C11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive data 1 input RXD1. GPIOV33_7/ RXD0 E12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is receive data 0 input RXD0. MDIO (1) (2) GPIOV33_16/ MDCLK B10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is management data clock output MDCLK. GPIOV33_15/ MDIO E10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In Ethernet MAC mode, it is management data IO MDIO. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 39 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-15. GPIOV33 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION GPIOV33 (1) (2) GPIOV33_16/ MDCLK B10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_16. GPIOV33_15/ MDIO E10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_15. GPIOV33_14/ CRS C10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_14. GPIOV33_13/ RXER D10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_13. GPIOV33_12/ RXDV D11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_12. GPIOV33_11/ RXCLK A10 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_11. GPIOV33_10/ RXD3 E11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_10. GPIOV33_9/ RXD2 B11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_9. GPIOV33_8/ RXD1 C11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_8. GPIOV33_7/ RXD0 E12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_7. GPIOV33_6/ TXD3 C12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_6. GPIOV33_5/ TXD2 A11 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_5. GPIOV33_4/ TXD1 D12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_4. GPIOV33_3/ TXD0 B12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_3. GPIOV33_2/ COL A12 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_2. GPIOV33_1/ TXCLK A13 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is 3.3V GPIO GPIOV33_1. GPIOV33_0/ TXEN B13 I/O/Z DVDD33 This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, this pin is 3.3V GPIO pin GPIOV33_0. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-16. Standalone GPIOV18 Terminal Functions SIGNAL NAME NO. GPIO7 C3 TYPE (1) OTHER (2) I/O/Z DVDD18 DESCRIPTION Standalone GPIOV18 (1) (2) 40 This pin is standalone and functions as GPIO7. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-17. USB Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION USB 2.0 Crystal input for M24 oscillator (24 MHz for USB). M24XI F18 I DVDD18 If a crystal input is not used, but instead a physical clock-in source is supplied, this is the external oscillator clock input. When the USB peripheral is not used, M24XI should be left as a No Connect. Crystal output for M24 oscillator. M24XO F19 O DVDD18 If a crystal input is not used, but instead a physical clock-in source is supplied, M24XO should be left as a No Connect. When the USB peripheral is not used, M24XO should be left as a No Connect. 1.8-V power supply for M24 oscillator. M24VDD F16 S (3) If a crystal input is not used, but instead a physical clock-in source is supplied, M24VDD should still be connected to the 1.8-V power supply. When the USB peripheral is not used, M24VDD should be connected to the 1.8-V power supply. Ground for M24 oscillator. M24VSS F17 GND (3) If a crystal input is not used, but instead a physical clock-in source is supplied, M24VSS should still be connected to ground. When the USB peripheral is not used, M24VSS should be connected to ground. 5-V input that signifies that VBUS is connected. USB_VBUS USB_ID J17 J16 A I/O (3) When the USB peripheral is not used, the USB_VBUS signal should be either pulled down or pulled up via a 10-kΩ resistor. USB operating mode identification pin. For Host mode operation, pull down this pin to ground (VSS) via an external 1.5-kΩ resistor. For Device mode operation, pull up this pin to DVDD33 rail via an external 1.5-kΩ resistor. A I/O When the USB peripheral is not used, the USB_ID signal should be either pulled down or pulled up via a 10-kΩ resistor. USB_DP G19 A I/O USB bi-directional Data Differential signal pair [positive/negative]. USB_DM H19 A I/O When the USB peripheral is not used, the USB_DP signal should be pulled high and the USB_DM signal should be pulled down via a 10-kΩ resistor. USB_R1 H18 A I/O (3) Reference current output. This must be connected via a 10-kΩ ±1% resistor to USB_VSSREF. When the USB peripheral is not used, the USB_R1 signal should be connected via a 10-kΩ resistor to USB_VSSREF. GND (3) USB_VSSREF G16 USB_VDDA3P3 J19 S (3) USB_VSSA3P3 J18 GND (3) USB_VDD1P8 H17 S (3) USB_VSS1P8 H16 GND (3) Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_VSSREF signal should be connected to VSS. Analog 3.3 V power supply for USB phy. When the USB peripheral is not used, the USB_VDDA3P3 signal should be connected to DVDD33. Analog ground for USB phy. When the USB peripheral is not used, the USB_VSSA3P3 signal should be connected to VSS. 1.8-V I/O power supply for USB phy. When the USB peripheral is not used, the USB_VDD1P8 signal should be connected to DVDD18. I/O Ground for USB phy. (1) (2) (3) When the USB peripheral is not used, the USB_VSS1P8 signal should be connected to VSS. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information, see Section 5.2, Recommended Operating Conditions. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 41 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-17. USB Terminal Functions (continued) SIGNAL NAME USB_VDDA1P2LDO USB_VSSA1P2LDO NO. G18 TYPE (1) S OTHER (2) (3) DESCRIPTION Core Power supply LDO output for USB phy. This must be connected via a 1-mF capacitor to VSS. (3) When the USB peripheral is not used, the USB_VDDA1P2LDO signal should still be connected via a 1-mF capacitor to VSS. G17 GND Core Ground for USB phy. This is the ground for the LDO and must be connected to VSS. (3) When the USB peripheral is not used, the USB_VSSA1P2LDO signal should still be connected to VSS. Table 2-18. VLYNQ Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION VLYNQ EM_CS5/ GPIO8/ VLYNQ_CLOCK T1 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is the clock (VLYNQ_CLOCK). EM_CS4/ GPIO9/ VLYNQ_SCRUN T2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is the serial clock run request (VLYNQ_SCRUN). EM_A[15]/ GPIO16/ VLYNQ_TXD3 P3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3. EM_A[17]/ GPIO14/ VLYNQ_TXD2 R2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2. EM_A[19]/ GPIO12/ VLYNQ_TXD1 R4 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1. EM_A[21]/ GPIO10/ VLYNQ_TXD0 T3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is bit 0 of the transmit bus (VLYNQ_TXD0). EM_A[14]/ GPIO17/ VLYNQ_RXD3 P4 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3. EM_A[16]/ GPIO15/ VLYNQ_RXD2 R5 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2. EM_A[18]/ GPIO13/ VLYNQ_RXD1 P5 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1. EM_A[20]/ GPIO11/ VLYNQ_RXD0 R3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0. (1) (2) 42 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-19. VPFE Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION VIDEO/IMAGE IN (VPFE) PCLK M19 I – DVDD18 VD L19 I/O/Z – DVDD18 Vertical synchronization signal that can be either an input (slave mode) or an output (master mode), which signals the start of a new frame to the CCDC. HD M18 I/O/Z – DVDD18 Horizontal synchronization signal that can be either an input (slave mode) or an output (master mode), which signals the start of a new line to the CCDC. IPD DVDD18 This pin is multiplexed between the CCDC and UART2. When used by the CCDC as input CI7, it supports several modes. In 16-bit CCD analog-front-end (AFE) mode, it is input CCD15. In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the upper 8-bit channel. IPD DVDD18 This pin is multiplexed between the CCDC and UART2. When used by the CCDC as input CI6, it supports several modes. In 16-bit CCD AFE mode, it is input CCD14. In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the upper 8-bit channel. IPD DVDD18 This pin is multiplexed between the CCDC and UART2. When used by the CCDC as input CI5, it supports several modes. In 16-bit CCD AFE mode, it is input CCD13. In 16-bit YCbCr mode, it is time multiplexed between CB5 and CR5 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the upper 8-bit channel. I/O/Z IPD DVDD18 This pin is multiplexed between the CCDC and UART2. When used by the CCDC as input CI4, it supports several modes. In 16-bit CCD AFE mode, it is input CCD12. In 16-bit YCbCr mode, it is time multiplexed between CB4 and CR4 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the upper 8-bit channel. I IPD DVDD18 This pin is CCDC input CI3 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD11. In 16-bit YCbCr mode, it is time multiplexed between CB3 and CR3 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the upper 8-bit channel. I IPD DVDD18 This pin is CCDC input CI2 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD10. In 16-bit YCbCr mode, it is time multiplexed between CB2 and CR2 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the upper 8-bit channel. I IPD DVDD18 This pin is CCDC input CI1 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD9. In 16-bit YCbCr mode, it is time multiplexed between CB1 and CR1 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the upper 8-bit channel. I IPD DVDD18 This pin is CCDC input CI0 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD8. In 16-bit YCbCr mode, it is time multiplexed between CB0 and CR0 inputs. In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the upper 8-bit channel. I IPD DVDD18 This pin is CCDC input YI7 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD7. In 16-bit YCbCr mode, it is input Y7. In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the lower 8-bit channel. CI7/ CCD15/ UART_RXD2 CI6/ CCD14/ UART_TXD2 CI5/ CCD13/ UART_CTS2 CI4/ CCD12/ UART_RTS2 CI3/ CCD11 CI2/ CCD10 CI1/ CCD9 CI0/ CCD8 YI7/ CCD7 (1) (2) (3) N19 N18 N17 N16 N15 M17 M16 M15 L18 I/O/Z I/O/Z I/O/Z Pixel clock input used to load image data into the CCD controller (CCDC) on pins CI[7:0] and YI[7:0]. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 43 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-19. VPFE Terminal Functions (continued) SIGNAL NAME YI6/ CCD6 YI5/ CCD5 YI4/ CCD4 YI3/ CCD3 YI2/ CCD2 YI1/ CCD1 44 NO. L17 L16 L15 K19 K18 K17 TYPE (1) OTHER (2) (3) DESCRIPTION I IPD DVDD18 This pin is CCDC input YI6 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD6. In 16-bit YCbCr mode, it is input Y6. In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the lower 8-bit channel. I IPD DVDD18 This pin is CCDC input YI5 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD5. In 16-bit YCbCr mode, it is input Y5. In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the lower 8-bit channel. I IPD DVDD18 This pin is CCDC input YI4 and it supports several modes. In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD4. In 16-bit YCbCr mode, it is input Y4. In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the lower 8-bit channel. I IPD DVDD18 This pin is CCDC input YI3 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD3. In 16-bit YCbCr mode, it is input Y3. In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the lower 8-bit channel. I IPD DVDD18 This pin is CCDC input YI2 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD2. In 16-bit YCbCr mode, it is input Y2. In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the lower 8-bit channel. I IPD DVDD18 This pin is CCDC input YI1 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD1. In 16-bit YCbCr mode, it is input Y1. In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the lower 8-bit channel. This pin is CCDC input YI0 and it supports several modes. In 16-bit CCD AFE mode, it is input CCD0. In 16-bit YCbCr mode, it is input Y0. In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the lower 8-bit channel. YI0/ CCD0 K16 I IPD DVDD18 GPIO1/ C_WE E13 I/O/Z DVDD18 This pin is multiplexed between GPIO and the VPFE. In VPFE mode, it is the CCD controller write enable input C_WE. GPIO4/ R0/ C_FIELD B14 I/O/Z DVDD18 This pin is multiplexed between GPIO, the VPFE, and the VPBE. In VPFE mode, it is CCDC field identification bidirectional signal C_FIELD. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-20. VPBE Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION (3) VIDEO OUT (VPBE) (1) (2) (3) HSYNC C17 I/O/Z IPD DVDD18 VSYNC C18 I/O/Z IPD DVDD18 VPBE vertical sync output VCLK D19 I/O/Z DVDD18 VPBE clock output VPBE clock input VPBE horizontal sync output VPBECLK C19 I/O/Z IPD DVDD18 COUT0/ B3/ BTSEL0 A16 I/O/Z IPD DVDD18 This pin is multiplexed between ARM boot mode and the VPBE. After reset, this pin is either video encoder outputs COUT0, or RGB666/888 Blue output data bits 3, B3. COUT1/ B4/ BTSEL1 B16 I/O/Z IPD DVDD18 This pin is multiplexed between ARM boot mode and the VPBE. After reset, this pin is either video encoder outputs COUT1, or RGB666/888 Blue output data bits 4, B4. COUT2/ B5/ EM_WIDTH A17 I/O/Z IPD DVDD18 This pin is multiplexed between EMIFA and the VPBE. After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5 B5. COUT3/ B6/ DSP_BT B17 I/O/Z IPD DVDD18 This pin is multiplexed between DSP boot and the VPBE. After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output B6. COUT4/ B7 A18 O DVDD18 Video encoder output COUT4 or RGB666/888 Blue data bit 7 output B7. COUT5/ G2 B18 O DVDD18 Video encoder output COUT5 or RGB666/888 Green data bit 2 output G2. COUT6/ G3 B19 O DVDD18 Video encoder output COUT6 or RGB666/888 Green data bit 3 output G3. COUT7/ G4 C16 O DVDD18 Video encoder output COUT7 or RGB666/888 Green data bit 4 output G4. YOUT0/ G5/ AEAW0 D15 I/O/Z IPD DVDD18 YOUT1/ G6/ AEAW1 D16 I/O/Z IPD DVDD18 YOUT2/ G7/ AEAW2 D17 I/O/Z IPD DVDD18 YOUT3/ R3/ AEAW3 D18 I/O/Z IPD DVDD18 YOUT4/ R4/ AEAW4 E15 I/O/Z IPD DVDD18 YOUT5/ R5 E16 O DVDD18 Video encoder output YOUT5 or RGB666/888 Red data bit 5 output R5. YOUT6/ R6 E17 O DVDD18 Video encoder output YOUT6 or RGB666/888 Red data bit 6 output R6. YOUT7/ R7 E18 O DVDD18 Video encoder output YOUT7 or RGB666/888 Red data bit 7 output R7. GPIO0/ LCD_OE C13 I/O/Z DVDD18 This pin is multiplexed between GPIO and the VPBE. In VPBE mode, it is the LCD output enable LCD_OE. GPIO2/ G0 D13 I/O/Z DVDD18 This pin is multiplexed between GPIO and the VPBE. In VPBE mode, it is RGB888 Green data bit 0 output G0. These pins are multiplexed between EMIFA and the VPBE. After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 45 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-20. VPBE Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) DESCRIPTION (3) NAME NO. GPIO3/ B0/ LCD_FIELD C14 I/O/Z DVDD18 This pin is multiplexed between GPIO, and the VPBE. In VPBE mode, it is RGB888 Blue data bit 0 output B0. or LCD interlaced output LCD_FIELD. GPIO4/ R0/ C_FIELD B14 I/O/Z DVDD18 This pin is multiplexed between GPIO, the VPFE, and the VPBE. In VPBE mode, it is RGB888 Red data bit 0 output R0. GPIO5/ G1 E14 I/O/Z DVDD18 This pin is multiplexed between GPIO and the VPBE. In VPBE mode, it is RGB888 Green data bit 1 output G1. GPIO6/ B1 A14 I/O/Z DVDD18 This pin is multiplexed between GPIO and the VPBE. In VPBE mode, it is RGB888 Blue data bit 1 output B1. GPIO38/ R1 D14 I/O/Z DVDD18 This pin is multiplexed between VPBE and GPIO. In VPBE mode, it is RGB888 Red output data bit 1. PWM1/ R2/ GPIO46 B15 I/O/Z DVDD18 This pin is multiplexed between PWM1, VPBE, and GPIO. In VPBE mode, it is RGB888 Red output bit 2 (R2). PWM2/ B2/ GPIO47 A15 I/O/Z DVDD18 This pin is multiplexed between PWM2, VPBE, and GPIO. In VPBE mode, it is RGB888 Blue output bit 2 (B2). Table 2-21. DAC [Part of VPBE] Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION DAC[A:D] (1) (2) (3) 46 (3) Reference voltage input (0.5 V). When the DAC is not used, the DAC_VREF signal should be connected to VSS. DAC_VREF R17 AI DAC_IOUT_A P19 AO Output of DAC A. When the DAC is not used, the DAC_IOUT_A signal should be left as a No Connect. DAC_IOUT_B P18 AO Output of DAC B. When the DAC is not used, the DAC_IOUT_B signal should be left as a No Connect. DAC_IOUT_C R19 AO Output of DAC C. When the DAC is not used, the DAC_IOUT_C signal should be left as a No Connect. DAC_IOUT_D T19 AO Output of DAC D. When the DAC is not used, the DAC_IOUT_D signal should be left as a No Connect. VDDA_1P8V R18 S (3) 1.8-V analog I/O power. When the DAC is not used, the VDDA_1P8V signal should be connected to VSS. VSSA_1P8V P17 GND (3) Analog I/O ground. When the DAC is not used, the VSSA_1P8V signal should be connected to VSS. VDDA_1P1V P16 S (3) VSSA_1P1V T18 GND (3) DAC_RBIAS R16 AI (3) 1.05-V analog core supply voltage (-405 device) or 1.20-V analog core supply voltage (-513 device). When the DAC is not used, the VDDA_1P1V signal should be connected to VSS. Analog core ground. When the DAC is not used, the VSSA_1P1V signal should be connected to VSS. External resistor connection for current bias configuration. This pin must be connected via a 4-kΩ resistor to VSSA_1P8V. When the DAC is not used, the DAC_RBIAS signal should be connected to VSS. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal For more information, see Section 5.2, Recommended Operating Conditions. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-22. UART0, UART1, UART2 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION UART2 CI7/ CCD15/ UART_RXD2 N19 I/O/Z IPD DVDD18 This pin is multiplexed between the CCDC and UART2. When used by UART2 it is the receive data input UART_RXD2. CI6/ CCD14/ UART_TXD2 N18 I/O/Z IPD DVDD18 This pin is multiplexed between the CCDC and UART2. In UART2 mode, it is the transmit data output UART_TXD2. CI5/ CCD13/ UART_CTS2 N17 I/O/Z IPD DVDD18 This pin is multiplexed between the CCDC and UART2. In UART2 mode, it is the clear to send input UART_CTS2. CI4/ CCD12/ UART_RTS2 N16 I/O/Z IPD DVDD18 This pin is multiplexed between the CCDC and UART2. In UART2 mode, it is the ready to send output UART_RTS2. UART1 DMACK/ UART_TXD1 H3 I/O/Z DVDD18 This pin is multiplexed between ATA/CF and UART1. For UART1, it is transmit data output UART_TXD1. DMARQ/ UART_RXD1 G1 I/O/Z DVDD18 This pin is multiplexed between ATA/CF and UART1. For UART1, it is receive data input UART_RXD1. UART0 (1) (2) (3) UART_RXD0/ GPIO35 D5 I/O/Z DVDD18 This pin is multiplexed between UART0 and GPIO. For UART0, it is receive data input UART_RXD0. UART_TXD0/ GPIO36 C5 I/O/Z DVDD18 This pin is multiplexed between UART0 and GPIO. . For UART0, it is transmit data output UART_TXD0. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 47 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-23. PWM0, PWM1, PWM2 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION PWM2 PWM2/ B2/ GPIO47 A15 I/O/Z This pin is multiplexed between PWM2, VPBE, and GPIO. For PWM2, it is output PWM2. DVDD18 PWM1 PWM1/ R2/ GPIO46 B15 I/O/Z DVDD18 This pin is multiplexed between PWM1, VPBE, and GPIO. For PWM1, it is output PWM1. DVDD18 This pin is multiplexed between PWM0 and GPIO. For PWM0, it is output PWM0. PWM0 PWM0/ GPIO45 (1) (2) C15 I/O/Z I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-24. ATA/CF Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION ATA/CF (1) (2) (3) 48 SPI_EN1/ HDDIR/ GPIO42 B2 I/O/Z DVDD18 This pin is multiplexed between SPI, ATA, and GPIO. For ATA, it is buffer direction control output HDDIR. GPIO50/ ATA_CS0 J5 O DVDD18 This pin is multiplexed between GPIO and ATA/CF. In ATA mode, it is ATA/CF chip select output ATA_CS0. GPIO51/ ATA_CS1 H1 O DVDD18 This pin is multiplexed between GPIO and ATA/CF. In ATA mode, it is ATA/CF chip select output ATA_CS1. EM_R/W/ INTRQ/ H/W G3 I DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For ATA/CF, it is interrupt request input INTRQ. EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY F1 I IPU DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For ATA/CF, it is IO Ready input IORDY. EM_OE/ ( RE )/ ( IORD )/ DIOR/ HDS1 H4 O DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For CF, it is read strobe output (IORD). For ATA, it is read strobe output DIOR. EM_WE (WE) (IOWR)/ DIOW/ HDS2 G2 O DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For CF, it is write strobe output (IOWR). For ATA, it is write strobe output DIOW. DMACK/ UART_TXD1 H3 O DVDD18 This pin is multiplexed between ATA/CF and UART1. For ATA/CF, it is DMA acknowledge output DMACK. DMARQ/ UART_RXD1 G1 O IPD DVDD18 This pin is multiplexed between ATA/CF and UART1. For ATA/CF, it is DMA request DMARQ input. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-24. ATA/CF Terminal Functions (continued) SIGNAL NAME NO. EM_D15/ DD15/ HD15 E1 EM_D14/ DD14/ HD14 H5 EM_D13/ DD13/ HD13 F2 EM_D12/ DD12/ HD12 D1 EM_D11/ DD11/ HD11 G4 EM_D10/ DD10/ HD10 G5 EM_D9/ DD9/ HD9 E2 EM_D8/ DD8/ HD8 F3 EM_D7/ DD7/ HD7 C1 EM_D6/ DD6/ HD6 F4 EM_D5/ DD5/ HD5 D2 EM_D4/ DD4/ HD4 E4 EM_D3/ DD3/ HD3 E3 EM_D2/ DD2/ HD2 F5 EM_D1/ DD1/ HD1 D3 EM_D0/ DD0/ HD0 E5 EM_A[0]/ DA2/ HCNTL1/ GPIO53 TYPE (1) OTHER (2) (3) DESCRIPTION I/O/Z DVDD18 These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For ATA/CF, these are DD[15:0]. J4 I/O/Z DVDD18 This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. For ATA/CF, it is Device address bit 2 output DA2. EM_BA[1]/ DA1/ GPIO52 H2 I/O/Z DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For ATA/CF, it is Device address bit 1 output DA1. EM_BA[0]/ DA0/ HINT J3 I/O/Z DVDD18 This pin is multiplexed between EMIFA, ATA/CF, HPI. For ATA/CF, it is Device address bit 0 output DA0. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 49 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-25. MMC/SD/SDIO and Memory Stick/Memory Stick PRO Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION MMC/SD/SDIO and Memory Stick/Memory Stick PRO (1) (2) 50 SD_CLK/ MS_CLK A9 O DVDD33 This pin is multiplexed between MMC/SD/SDIO and Memory Stick/Memory Stick PRO. For MMC/SD/SDIO, this is the data clock output SD_CLK. In Memory Stick mode, this is the clock output MS_CLK. SD_CMD/ MS_BS B9 O DVDD33 This pin is multiplexed between MMC/SD/SDIO and Memory Stick/Memory Stick PRO. For MMC/SD/SDIO, this is the Command IO output SD_CMD. In Memory Stick mode, this is the Bus State output MS_BS. SD_DATA3/ MS_DATA3 C9 I/O/Z SD_DATA2/ MS_DATA2 D9 I/O/Z SD_DATA1/ MS_DATA1 DVDD33 E9 I/O/Z These pins are multiplexed between MMC/SD/SDIO and Memory Stick/Memory Stick PRO. In MMC/SD/SDIO mode, these pins are the nibble-wide bi-directional data bus SD_DATA[3:0]. In Memory Stick mode, these pins are the nibble-wide bi-directional data bus MS_DATA[3:0]. SD_DATA0/ MS_DATA0 D8 I/O/Z I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-26. HPI Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (1) (2) DESCRIPTION Host-Port Interface (HPI) EM_CS3 EM_BA[0]/ DA0/ HINT EM_A[0]/ DA2/ HCNTL1/ GPIO53 J3 J4 I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, this is the Bank Address 0 output EM_BA[0]. When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. When connected to a 16-bit asynchronous memory, this pin has the same function as EMIF address pin 22 EM_A[22]. For ATA/CF, it is Device address bit 0 output DA0. In HPI mode, it is the host interrupt output HINT. DVDD18 This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. For EMIFA, this is Address output EM_A[0], which is the least significant bit on a 32-bit word address. When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. For ATA/CF, it is Device address bit 2 output DA2. For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine if address, data, or control information is being transmitted between an external host and DM6441. In GPIO mode, it is GPIO53. EM_A[2]/ (CLE)/ HCNTL0 J1 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. For EMIFA, this pin is the EM_A[2] address line. For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE). In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0 determine if address, data, or control information is being transmitted between an external host and DM6441. EM_A[1]/ (ALE)/ HHWIL J2 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI. When used for EMIFA, it is address output EM_A[1]. For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE). In HPI mode, it is Half-word identification input HHWIL. DVDD18 This pin is multiplexed between EMIFA, ATA/CF, and HPI. For EMIFA, it is EMIF read/write output EM_R/W. For ATA/CF, it is interrupt request input INTRQ. For HPI, it is the Host Read Write input HR/W. This signal is active high for reads and low for writes. DVDD18 This pin is multiplexed between EMIFA and HPI. For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot and ROM boot modes. In HPI mode, this pin is HPI Active Low Chip Select input HCS. DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is write enable output EM_WE. For NAND/SmartMedia/xD, it is write enable output (WE). For CF, it is write strobe output (IOWR). For ATA, it is write strobe output DIOW. For HPI, it is data strobe 2 input HDS2. I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is output enable output EM_OE. For NAND/SmartMedia/xD, it is read enable output (RE). For CF, it is read strobe output (IORD). For ATA, it is read strobe output DIOR. For HPI, it is data strobe 1 input HDS1. I/O/Z IPU DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI. For EMIFA, it is wait state extension input EM_WAIT. For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY). For ATA/CF, it is IO Ready input IORDY. For HPI, it is ready output HRDY. EM_R/W/ INTRQ/ HR/W EM_CS2/ HCS EM_WE (WE) (IOWR)/ DIOW/ HDS2 EM_OE/ (RE)/ (IORD)/ DIOR/ HDS1 EM_WAIT/ (RDY/BSY)/ IORDY/ HRDY (1) (2) B1 For EMIFA, this pin is Chip Select 3 output. In HPI mode, this pin must be pulled high via an external 10-kΩ resistor. G3 C2 G2 H4 F1 I/O/Z I/O/Z I/O/Z IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 51 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-26. HPI Terminal Functions (continued) SIGNAL 52 NAME NO. EM_D15/ DD15/ HD15 E1 EM_D14/ DD14/ HD14 H5 EM_D13/ DD13/ HD13 F2 EM_D12/ DD12/ HD12 D1 EM_D11/ DD11/ HD11 G4 EM_D10/ DD10/ HD10 G5 EM_D9/ DD9/ HD9 E2 EM_D8/ DD8/ HD8 F3 EM_D7/ DD7/ HD7 C1 EM_D6/ DD6/ HD6 F4 EM_D5/ DD5/ HD5 D2 EM_D4/ DD4/ HD4 E4 EM_D3/ DD3/ HD3 E3 EM_D2/ DD2/ HD2 F5 EM_D1/ DD1/ HD1 D3 EM_D0/ DD0/ HD0 E5 TYPE (1) I/O/Z OTHER (1) DVDD18 (2) DESCRIPTION These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. For ATA/CF, these are DD[15:0]. In HPI mode, these are HD[15:0] and are multiplexed internally with the HPI address lines. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-27. Timer 0, Timer 1, and Watchdog Timer Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION Watchdog timer and Timer 1 No external pins. The Watchdog timer and Timer 1 peripheral pins are not pinned out as external pins. Timer 0 CLK_OUT1/ TIM_IN/ GPIO49 (1) (2) E19 I/O/Z This pin is multiplexed between the USB clock generator, timer, and GPIO. For Timer0, it is the timer event capture input TIM_IN. DVDD18 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Specifies the operating I/O supply voltage for each signal Table 2-28. Reserved Terminal Functions SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. RSV1 A1 Reserved. (Leave unconnected, do not connect to power or ground) RSV2 A19 Reserved. (Leave unconnected, do not connect to power or ground) RSV3 W1 Reserved. (Leave unconnected, do not connect to power or ground) RSV4 W19 RESERVED RSV5 (1) (2) (3) Reserved. (Leave unconnected, do not connect to power or ground) IPD VSS D4 I Reserved. This pin must be tied directly to VSS for normal device operation. RSV6 L3 AO Reserved. (Leave unconnected, do not connect to power or ground) RSV7 R8 A Reserved. (Leave unconnected, do not connect to power or ground) RSV24 M3 S Reserved. (Leave unconnected, do not connect to power or ground) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 53 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-29. Supply Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION SUPPLY VOLTAGE PINS F10 F11 DVDD33 F12 S 3.3 V I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) S 1.8 V I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) S 1.8 V DDR2 I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) F13 N5 G15 F14 J15 H14 K14 M14 L13 G9 DVDD18 F8 E7 G7 J7 L7 F6 H6 K6 M6 T5 P6 N7 P8 N9 R9 DVDDR2 P10 N11 R11 P12 N13 R13 P14 R15 (1) 54 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-29. Supply Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION F15 K12 M12 L11 CVDD M10 L10 S 1.05 V or 1.2 V core supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) S 1.05 V or 1.2 V DSPSS supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) K10 L9 L8 M8 J13 H12 H11 J11 K11 CVDDDSP J10 H10 J9 K9 K8 H8 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 55 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 2-30. Ground Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION GROUND PINS K5 M5 G6 J6 L6 N6 R6 F7 H7 K7 M7 P7 R7 E8 G8 J8 N8 F9 H9 VSS M9 GND Ground pins P9 G10 N10 R10 G11 M11 P11 G12 J12 N12 L12 R12 G13 H13 K13 M13 P13 G14 J14 (1) 56 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 2-30. Ground Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION L14 N14 VSS R14 H15 GND Ground pins K15 P15 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 57 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2.8 2.8.1 www.ti.com Device Support Development Support TI offers an extensive line of development tools for the SoC platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). The following products support development of SoC-based applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any SoC application. Hardware Development Tools: Extended Development System (XDS™) Emulator For a complete listing of development-support tools for the SoC platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 2.8.2 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320DM6441ZWT). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. 58 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperature range). Figure 2-6 provides a legend for reading the complete device name for any SoC platform member. TMS 320 DM6441 S ( PREFIX TMX = TMP = TMS = SMX= SMJ = SM = ) ZWT ( ) 405 DEVICE SPEED RANGE Experimental device Prototype device Qualified device Experimental device, MIL MIL-PRF-38535, QML High Rel (non-38535) 405 (405-MHz DSP, 202.5−MHz ARM9 at 1.05V) 513 (513-MHz DSP, 256-MHz ARM9 at 1.2V) TEMPERATURE RANGE (DEFAULT: 0°C TO 85°C) Blank = 0°C to 85°C PACKAGE TYPE(A) ZWT = 361-pin plastic BGA, with Pb-free soldered balls DEVICE FAMILY 320 = TMS320t DSP family SILICON REVISION 0 = Initial Silicon A = Silicon 2.1 B = Silicon 2.3 DEVICE(B) DM644x DMSoC: DM6441 DM6442 DM6443 DM6444 DM6446 DM6447 ROM SECURITY S = Secure N = Non-secure A. BGA = Ball Grid Array B. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com). Figure 2-6. Device Nomenclature Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 59 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2.8.3 www.ti.com Documentation Support 2.8.3.1 Related Documentation From Texas Instruments The following documents describe the Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. The current documentation that describes the DM6441 DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000. 60 SPRU395 TMS320C64x Technical Overview. Provides an introduction to the TMS320C64x digital signal processors (DSPs) of the TMS320C6000 DSP family. SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set. SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRUE14 TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the video processing subsystem, and a majority of the peripherals and external memories. SPRUE15 TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signal processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). SPRUE19 TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320DM644x Digital Media System-on-Chip (DMSoC). SPRUE20 TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) Reference Guide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices. SPRUE21 TMS320DM644x DMSoC ATA Controller User's Guide. Describes the ATA controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ATA controller provides a glueless interface to storage media to be used by video and audio applications for video and audio data storage. SPRUE22 TMS320DM644x DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2 memory controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. SPRUE23 TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide. Describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DMSoC. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 SPRUE24 TMS320DM644x DMSoC Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller (EMAC) and physical layer (PHY) device management data input/output (MDIO) module in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packet data from the DMSoC to the PHY. The MDIO module controls PHY configuration and status monitoring. SPRUE25 TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describes the general-purpose input/output (GPIO) peripheral in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin. SPRUE26 TMS320DM644x DMSoC 64-Bit Timer User's Guide. Describes the operation of the software-programmable 64-bit timer in the TMS320DM644x Digital Media System-on-Chip (DMSoC). Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanced direct memory access (EDMA) synchronization events. The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. SPRUE29 TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide. Describes the operation of the audio serial port (ASP) audio interface in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface. SPRUE35 TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide. Describes the universal serial bus (USB) controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices and also supports host negotiation. SPRUE37 TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide. Describes the video processing back end (VPBE) in the TMS320DM644x Digital Media System-on-Chip (DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screen display, and digital LCD controller. SPRUE97 TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide. Describes the features and operation of the host port interface (HPI) in the TMS320DM644x Digital Media System-on-Chip (DMSoC). SPRA839 Using IBIS Models for Timing Analysis. Describes how to properly use IBIS models to attain accurate timing analysis for a given system. SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. SPRAAA6 EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3. Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 61 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 62 www.ti.com SPRAAC5 Implementing DDR2 PCB Layout on the TMS320DM644x DSP. Contains implementation instructions for the DDR2 interface contained on the TMS320DM644x digital signal processor (DSP) device. SPRAAU3 TMS320DM6441 Power Consumption Summary. Discusses the power consumption of the Texas Instruments TMS320DM6441 digital media System-on-Chip (DMSoC). Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3 Device Configurations 3.1 System Module Registers The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System module registers required for device configurations are discussed in the following sections. Table 3-1. System Module Register Memory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0000 PINMUX0 Pin multiplexing control 0. See Section 3.5.4, PINMUX0 Register Description, for details. 0x01C4 0004 PINMUX1 Pin multiplexing control 1. See Section 3.5.5, PINMUX1 Register Description, for details. 0x01C4 0008 DSPBOOTADDR Boot address of DSP. See Section 3.3.1.2, DSPBOOTADDR Register Description, for details. 0x01C4 000C SUSPSRC Emulator Suspend Source. See Section 3.6, Emulation Control, for details. 0x01C4 0010 INTGEN ARM/DSP Interrupt Status and Control. See Section 6.7.3, ARM/DSP Communications Interrupts, for details. 0x01C4 0014 BOOTCFG Device boot configuration. See Section 3.3.1.1, BOOTCFG Register Description, for details. 0x01C4 0018 - 0x01C4 0027 – Reserved 0x01C4 0028 JTAGID JTAGID/Device ID number. See Section 6.26.1, JTAG Peripheral Register Description(s) – JTAG ID Register, for details. 0x01C4 002C – Reserved 0x01C4 0030 HPI_CTL HPI control. See Section 3.5.6.10, HPI and EMIFA/ATA Pin Multiplexing, for details. 0x01C4 0034 USBPHY_CTL USB PHY control. See Section 6.14.1, USBPHY_CTL Register Description, for details. 0x01C4 0038 CHP_SHRTSW Chip shorting switch control. See Section 3.2.1, Power Configurations at Reset, for details. 0x01C4 003C MSTPRI0 Bus master priority control 0. See Section 3.5.1, Switched Central Resource (SCR) Bus Priorities, for details. 0x01C4 0040 MSTPRI1 Bus master priority control 1. See Section 3.5.1, Switched Central Resource (SCR) Bus Priorities, for details. 0x01C4 0044 VPSS_CLKCTL VPSS clock control. 0x01C4 0048 VDD3P3V_PWDN VDD 3.3V I/O powerdown control. See Section 3.2.2, Power Configurations after Reset, for details. 0x01C4 004C DRRVTPER Enables access to the DDR2 VTP register. 0x01C4 0050 - 0x01C4 006F – 3.2 Reserved Power Considerations Global device power domains are controlled by the power and sleep controller, except as shown in the following sections. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 63 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.2.1 www.ti.com Power Configurations at Reset As described in Section 6.3.1.3, DM6441 Power and Clock Domains, the DM6441 has two power domains: Always On and DSP. There is a shorting switch between the two power domains that must be opened when the DSP domain is powered off and closed when the DSP domain is powered on. The CHP_SHRTSW register, shown in Figure 3-1, controls the shorting switch between the device always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain. Setting the DSPPWRON bit to a value of 1 closes (enables) the switch and enables the DSP power domain. The default switch value is determined by the DSP_BT configuration input. If DSP self boot is selected (DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of 1. For ARM boot operation (DSP_BT=0), DSPPWRON will be set to the disable value of 0 and must be set by the ARM before the DSP domain power is turned on. Figure 3-1. CHP_SHRTSW Register 31 1 0 RESERVED DSPPWRON R-0000 0000 0000 0000 0000 0000 0000 000 R/W-L LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising Table 3-2. CHP_SHRTSW Register Field Descriptions Bit Field 31 - 1 RESERVED 0 DSPPWRON 3.2.2 Value Description Reserved DSP power domain enable 0 Shorting switch open 1 Shorting switch closed Power Configurations after Reset The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD/SDIO, Memory Stick/Memory Stick PRO, and GPIOV33. The 3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and described in Table 3-3. By default, these pins are all disabled at reset. Figure 3-2. VDD3P3V_PWDN Register 31 1 0 RESERVED 2 IOPWDN1 IOPWDN0 R-0000 0000 0000 0000 0000 0000 0000 00 R/W-1 R/W-1 LEGEND: R = Read, W = Write, n = value at reset Table 3-3. VDD3P3V_PWDN Register Field Descriptions Bit Field 31 - 2 RESERVED 1 IOPWDN1 0 64 Value Description Reserved Memory Stick/Memory Stick PRO, MMC/SD/SDIO powerdown controls. 0 I/O buffers powered up 1 I/O buffers powered down IOPWDN0 GIOV33 I/O powerdown controls GIOV33[16:0] pins. 0 I/O buffers powered up 1 I/O buffers powered down Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 3.3 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Bootmode The device is booted through multiple means: pin states captured at reset, primary bootloaders within internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and register configurations required for booting the device, are described in the following sections. 3.3.1 Bootmode Registers The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status of various pins required for proper boot are stored within these registers. 3.3.1.1 BOOTCFG Register Description The BOOTCFG register (located at address 0x01C4 0014) contains the status values of the BTSEL1, BTSEL0, DSP_BT, EM_WIDTH, and AEAW[4:0] pins captured at the rising edge of RESET. The register format is shown in Figure 3-3 and bit field descriptions are shown in Table 3-4. The captured bits are software readable after reset. Figure 3-3. BOOTCFG Register 31 9 8 7 6 5 4 3 2 RESERVED DSP_BT BTSEL EM_WIDTH DAEAW R-0000 0000 0000 0000 0000 000 R-L R-LL R-L R-LLLLL 1 0 LEGEND: R = Read; W = Write; L = pin state latched at reset rising; -n = value after reset Table 3-4. BOOTCFG Register Field Descriptions Bit Field 31 - 9 RESERVED 8 DSP_BT 7-6 5 4-0 Value DSP boot mode selection pin state captured at the rising edge of RESET. 0 Sets ARM boot of C64x+. 1 Sets C64x+ self boot. BTSEL ARM boot mode selection pin states (BTSEL1, BTSEL0) captured at the rising edge of RESET. 00 Indicates ARM boots from ROM (NAND Flash/SPI Flash). 01 Indicates that ARM boots from EMIFA (NOR Flash). 10 Indicates that ARM boots from ROM (HPI). 11 Indicates that ARM boots from ROM (UART0). EM_WIDTH DAEAW Description Reserved EMIFA data bus width selection pin state captured at the rising edge of RESET. 0 Sets EMIFA to 8 bit data bus width 1 Sets EMIFA to 16 bit data bus width. EMIFA address bus width selection pin states (AEAW[4:0]) captured at the rising edge of RESET. This configures EMIFA address pins multiplexed with GPIO. See the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11). Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 65 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.3.1.2 www.ti.com DSPBOOTADDR Register Description The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register format is shown in Figure 3-4 and bit field descriptions are shown in Table 3-5. DSPBOOTADDR is readable and writable by software after reset. Figure 3-4. DSPBOOTADDR Register 31 10 9 0 BOOTADDR[21:0] RESERVED R- 0100 0010 0010 0000 0000 00 R-00 0000 0000 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-5. DSPBOOTADDR Register Field Descriptions Bit Field 31 - 10 BOOTADDR[21:0] 9-0 RESERVED 3.3.2 Value Description Upper 22 bits of the C64x+ DSP boot address. Reserved ARM Boot The DM6441 ARM can boot from EMIFA, internal ROM (NAND, SPI), UART0, or HPI, as determined by the setting of the BTSEL[1:0] pins. The BTSEL[1:0] pins are read by the ARM ROM boot loader (RBL) to further define the ROM boot mode. The ARM boot modes are summarized in Table 3-6. Table 3-6. ARM Boot Modes BTSEL1 BTSEL0 Boot Mode ARM Reset Vector Brief Description 0 0 ARM NAND, SPI RBL 0x0000 4000 Up to 14 K-bytes secondary boot loader through NAND with up to 2 K-bytes page sizes. 0 1 ARM EMIFA external Boot 0x0200 0000 EMIFA EM_CS2 external memory space. 1 0 ARM HPI RBL 0x0000 4000 Up to 14 K-btyes secondary boot loader through an external host. 1 1 ARM UART RBL 0x0000 4000 Up to 14 K-bytes secondary boot loader through UART0. When the BTSEL[1:0] pins are set to the ARM EMIFA external boot ("01"), the ARM immediately begins executing code from the EMIFA EM_CS2 memory space (0x0200 0000). When the BTSEL[1:0] pins indicate a condition other than the ARM EMIFA external boot (!01), the RBL begins execution. ARM NAND/SPI boot mode has the following features: • Loads a secondary user boot loader (UBL) from NAND/SPI flash to ARM internal RAM (AIM) and transfers control to the user software. • Support for NAND with page sizes up to 2048 bytes. • Support for error correction when loading UBL • Support for up to 14KB UBL • Optional, user selectable, support for use of DMA, I-cache, and PLL enable while loading UBL ARM UART boot mode has the following features: • Loads a secondary UBL via UART0 to AIM and transfers control to the user software. • Support for up to 14KB UBL ARM HPI boot mode has the following features: • No support for a full firmware boot. Instead, waits for external host ot load a secondary UBL via HPI to AIM and transfers control to the user software. • Support for up to 14KB UBL. 66 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 For further details on the ROM bootloader, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). 3.3.3 DSP Boot For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the ARM will be the master of C64x+ and control booting (host-boot mode). If DSP_BT is high, the C64x+ will boot itself coming out of device reset (self-boot mode). Table 3-7 shows a summary of the DSP boot modes. Table 3-7. DSP Boot Modes DSP_BT DSP Boot Mode ARM Boot Mode DSPBOOTADDR Register Value Brief Description 0 Host boot Internal boot Programmable ARM sets an internal DSP memory location in DSPBOOTADDR register where valid DSP code resides and loads code to this internal DSP memory through DMA prior to releasing DSP reset. 0 Host boot External boot Programmable ARM sets an external DSP memory location in DSPBOOTADDR register (EMIFA or DDR2) where valid DSP code resides prior to releasing DSP reset. 1 Self boot Any, except HPI 0x4220 0000 Default EMIFA base address 1 Host boot HPI Programmable ARM sets a DSP memory location in the DSPBOOTADDR register. HPI loads code into the DM6441 memory map with the entry point set to the memory location specified in the DSPBOOTADDR register. Once the HPI completes loading the code, the ARM should release the DSP from reset. 3.3.3.1 Host-Boot Mode In host boot mode, the ARM is the master and controls the reset and boot of the C64x+. The C64x+ DSP remains powered-off after device reset. The ARM is responsible for enabling power to the C64x+ and releasing it from reset (PSC MMR bits: MDCTL[39].LRST and MRSTOUT1.MRSTz[39]). Prior to releasing the C64x+ reset, the ARM must program the address from which the C64x+ will begin execution in the DSPBOOTADDR register. 3.3.3.2 Self-Boot Mode In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000) contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache enabled. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 67 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.4 www.ti.com Configurations at Reset The following sections give information on configuration settings for the device at reset. 3.4.1 Device Configuration at Device Reset Table 3-8 shows a summary of device inputs required for booting the ARM and DSP, and configuring EMIFA data and address bus widths for proper operation of the device at the rising edge of the RESET input. Table 3-8. Device Configurations (Input Pins Sampled at Reset) DEVICE SIGNALS SAMPLED AT RESET BTSEL[1:0] DEVICE SIGNAL NAME AFTER RESET COUT[1:0] DESCRIPTION ARM boot mode selection pins. ‘00’ ‘01’ ‘10’ ‘11’ DSP_BT COUT3 indicates indicates indicates indicates ARM boots from ROM (NAND/SPI Flash). that ARM boots from EMIFA (NOR Flash). that the ARM boots from the HPI (ROM) that ARM boots from ROM (UART0). DSP boot mode selection pin. ‘0’ sets ARM boot of C64x+. ‘1’ sets C64x+ self boot. EM_WIDTH COUT2 EMIFA data bus width selection pin. ‘0’ sets EMIFA to 8-bit data bus width ‘1’ sets EMIFA to 16-bit data bus width. AEAW[4:0] 3.4.2 YOUT[4:0] EMIFA address bus width selection pins for EMIFA address pins multiplexed with GPIO. See the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11) for details. Peripheral Selection at Device Reset As briefly mentioned in Table 3-8, the state of the AEAW[4:0] pins captured at reset configures the number of EMIFA address pins required for device boot. These values are stored in the AEAW field of the PINMUX0 register. At reset, this provides proper addressing for external boot. Unused address pins are available for use as GPIO. The register settings are software programmable after reset. Table 3-9, Table 3-10, and Table 3-11 show the AEAW[4:0] bit settings and the corresponding multiplexing for EMIFA address and GPIO pins. The number of EMIFA address bits enabled is configurable from 0 to 23. EM_BA[1] and EM_A[21:0] pins that are not assigned to another peripheral and not enabled as address signals become GPIO pins. The enabled address pins are always contiguous from EM_BA[1] upwards and address bits cannot be skipped. The exception to this are the EM_A[2:1] pins. EM_A[2:1] are usable as the ALE and CLE signals for the NAND Flash mode of EMIFA and are always enabled as EMIFA pins. If an address width of 0 is selected, this still allows a NAND Flash to be accessed. Also, selecting an address width of 2, 3, or 4 (AEAW[4:0] = 00010, 00011, or 00100) always results in 4 address outputs. For these and other address bit enable settings, see the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11). 68 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 3-9. GPIO and EMIFA Multiplexing (Part 1) Pin Mux Register AEAW[4:0] Bit Settings 00000 (default) 00001 00010 00011 00100 00101 00110 00111 GPIO[52] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] GPIO[53] GPIO[53] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[28] GPIO[28] GPIO[28] GPIO[28] GPIO[28] EM_A[3] EM_A[3] EM_A[3] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] EM_A[4] EM_A[4] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] EM_A[5] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 69 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 3-10. GPIO and EMIFA Multiplexing (Part 2) Pin Mux Register AEAW[4:0] Bit Settings 01000 01001 01010 01011 01100 01101 01110 01111 EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM _A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] GPIO[24] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] GPIO[23] GPIO[23] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] GPIO[22] GPIO[22] GPIO[22] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] GPIO[21] GPIO[21] GPIO[21] GPIO[21] EM_A[10] EM_A[10] EM_A[10] EM_A[10] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] EM_A[11] EM_A[11] EM_A[11] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] EM_A[12] EM_A[12] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] EM_A[13] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] 70 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 3-11. GPIO and EMIFA Multiplexing (Part 3) Pin Mux Register AEAW[4:0] Bit Settings 10000 10001 10010 10011 10100 10101 10110 Others EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] GPIO[16] EM_A[15] EM_A[15] EM_A[15] EM _A[15] EM_A[15] EM_A[15] EM_A[15] GPIO[15] GPIO[15] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] GPIO[14] GPIO[14] GPIO[14] EM_A[17] EM_A[17] EM_A[17] EM_A[17] EM_A[17] GPIO[13] GPIO[13] GPIO[13] GPIO[13] EM_A[18] EM_A[18] EM_A[18] EM_A[18] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] EM_A[19] EM_A[19] EM_A[19] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] EM_A[20] EM_A[20] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] EM_A[21] Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 71 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5 www.ti.com Configurations After Reset The following sections give the details on configuring the device after reset. 3.5.1 Switched Central Resource (SCR) Bus Priorities Prioritization within the switched central resource (SCR) is programmable for each master. The register bit fields and default priority levels for DM6441 bus masters are shown in Table 3-12. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and Figure 3-6. The C64x+, VPSS, and EDMA3 masters contain registers that control their own priority values. Table 3-12. DM6441 Default Bus Master Priorities Priority Bit Field Bus Master VPSSP VPSS 0 (VPSS PCR registerRegister, DMA_PRI bit field) [For more detailed information on the DMA_PRI bit field, see the TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (literature number SPRUE37).] Default Priority Level EDMATC0P EDMATC0 0 (EDMA3CC QUEPRI register) [For more detailed information on the QUEPRI register, see the TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).] EDMATC1P EDMATC1 0 (EDMA3CC QUEPRI register) [For more detailed information on the QUEPRI register, see the TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23).] ARM_DMAP ARM (DMA) 1 (MSTPRI0 register) ARM_CFGP ARM (CFG) 1 (MSTPRI0 register) C64X+_DMAP C64X+ (DMA) 7 (C64x+ MDMAARBE.PRI register bit field) [For more detailed information on the PRI bit field, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).] C64X+_CFGP C64X+ (CFG) 1 (MSTPRI0 register) EMACP EMAC 4 (MSTPRI1 register) USBP USB 4 (MSTPRI1 register) ATAP ATA/CF 4 (MSTPRI1 register) VLYNQP VLYNQ 4 (MSTPRI1 register) HPIP HPI 4 (MSTPRI1 register) VICPP VICP 5 (MSTPRI0 Register) Figure 3-5. MSTPRI0 Register 31 19 15 11 18 16 RESERVED VICPP (1) R-0000 0000 0000 0 R/W-101 10 8 7 6 4 3 2 0 RESERVED C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001 LEGEND: R = Read; W = Write; -n = value after reset (1) 72 The VICPP bit field is configured by the third-party software. When modifying the MSTPRI0 register a read/modify/write must be performed to preserve the configuration set by the third-party software. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Figure 3-6. MSTPRI1 Register 31 15 23 14 12 22 20 19 18 16 RESERVED HPIP RSV VLYNQP R-0000 0000 0 R/W-100 R-0 R/W-100 11 10 8 7 6 4 3 2 0 RSV ATAP RSV USBP RSV RESERVED RSV EMACP R-0 R/W-100 R-0 R/W-100 R-0 R-100 R-0 R/W-100 LEGEND: R = Read; W = Write; -n = value after reset Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 73 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.2 www.ti.com Multiplexed Pin Configurations There are numerous multiplexed pins that are shared by more than one peripheral. Some of these pins are configured by external pullup/pulldown resistors only at reset, and others are configured by software. As described in detail in Section 3.4.1, Device Configuration at Device Reset, and Section 3.4.2, Peripheral Selection at Device Reset, hardware configurable multiplexed pins are programmed by external pullup/pulldown resistors at reset to set the initial functionality of pins for use by a single peripheral. After reset, software configurable multiplexed pins are programmable through memory mapped registers (MMR) to allow the switching of pin functionalities during run-time. See Section 3.5.3, Peripheral Selection After Device Reset, for more details on the register settings. A summary of the pin multiplexing is shown in Table 3-13. The EMAC peripheral shares pins with the 3.3V GPIO pins. The VLYNQ pins overlap upper EMIFA address pins resulting in a reduced EMIFA address range as the VLYNQ width is increased. The ATA peripheral shares data lines and some control signals with EMIFA. The ATA DMA pins are multiplexed with UART1. The ASP, UART0/1/2, SPI, I2C, and PWM0/1/2 all default to GPIO pins when not enabled. The VPBE function of the VPSS requires additional pins to implement the RGB888 mode. These are multiplexed with GPIOs. Table 3-13. DM6441 Multiplexed Peripheral Pins and Multiplexing Controls MULTIPLEXED PERIPHERALS PRIMARY (DEFAULT) FUNCTION SECONDARY (1) FUNCTION SECONDARY REGISTER/PIN (3) CONTROL TERTIARY (2) FUNCTION EMIFA (NAND), HPI EMIFA: HPI: EM_A[1] (ALE), HHWIL, HCNTL0, EM_A[2] (CLE) HCS EM_CS2, EM_CS3 TERTIARY REGISTER/PIN (3) CONTROL PinMux0:HPIEN Pins:BTSEL[1:0] = 10 EMIFA, HPI, ATA (CF) EMIFA: EM_D[0:15], EM_BA[0] ATA (CF): DD[0:15], DA0 HPI: HD[0:15], HINT PinMux0:ATAEN PinMux0:HPIEN EMIFA (NAND), HPI, ATA (CF) EMIFA (NAND): R/W, EM_WAIT (RDY/BSY), EM_OE (RE), EM_WE (WE) ATA (CF): INTRQ, IORDY, DIOR(IORD) , DIOW (IOWR) HPI: HR/W, HRDY, HDS1, HDS2 PinMux0:ATAEN PinMux0:HPIEN VPBE LCD, GPIO GPIO:GPIO[0] VPBE: LCD_OE PinMux0:LOEEN VPFE CCD, GPIO GPIO:GPIO[1] VPFE: C_WE PinMux0:CWE VPBE RGB888, GPIO GPIO:GPIO[2] VPBE: RGB888 G0 PinMux0:RGB888 VPBE GPIO:GPIO[3] LCD/RGB888, GPIO VPBE: RGB888 B0 VPBE: LCD_FIELD PinMux0:RGB888 PinMux0:LFLDEN VPFE CCD, VPBE RGB888, GPIO GPIO:GPIO[4] VPBE: RGB888 R0 VPFE: CCD_FIELD PinMux0:RGB888 PinMux0:CFLDEN VPBE RGB888, GPIO GPIO: GPIO[5:6, 38] VPBE: RGB888 G1, B1, R1 EMIFA, VLYNQ, GPIO GPIO:GPIO[8] EMIFA: EM_CS5 VLYNQ: VLYNQ_CLOCK PinMux0:AECS5 PinMux0:VLYNQEN EMIFA, VLYNQ, GPIO GPIO:GPIO[9] EMIFA: EM_CS4 VLYNQ: VLYNQ_SCRUN PinMux0:AECS4 PinMux0:VLSCREN EMIFA, VLYNQ, GPIO GPIO: GPIO[10:17] EMIFA: EM_A[21:14] VLYNQ: VLYNQ_TXD[0:3], VLYNQ_RXD[0:3] PinMux0:AEAW, Pins:DAEAW[4:0] PinMux0:VLYNQEN, PinMux0:VLYNQWD[1:0] EMIFA, GPIO GPIO: GPIO[18:28] EMIFA: EM_A[13:3] (1) (2) (3) 74 PinMux0:RGB888 PinMux0:AEAW, Pins:DAEAW[4:0] When the secondary function is enabled, to avoid potential contention, ensure that the primary (if not GPIO) and tertiary functions are disabled. When the tertiary function is enabled, to avoid potential contention, ensure that the primary (if not GPIO), secondary, and other tertiary functions are disabled. Pin states are sampled at power on reset and written into the register fields. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 3-13. DM6441 Multiplexed Peripheral Pins and Multiplexing Controls (continued) MULTIPLEXED PERIPHERALS PRIMARY (DEFAULT) FUNCTION SECONDARY (1) FUNCTION SECONDARY REGISTER/PIN (3) CONTROL TERTIARY (2) FUNCTION TERTIARY REGISTER/PIN (3) CONTROL ASP, GPIO GPIO: GPIO[29:34] ASP: (all pins) (4) PinMux1:ASP UART0, GPIO GPIO: GPIO[35:36] UART0: RXD, TXD PinMux1:UART0 SPI, GPIO GPIO: GPIO[37, 39:41] SPI: SPI_EN0, SPI_CLK, SPI_DI, SPI_DO PinMux1:SPI SPI, ATA, GPIO GPIO:GPIO[42] SPI: SPI_EN1 I2C, GPIO GPIO: GPIO[43:44] I2C: SCL, SDA PinMux1:I2C PWM0, GPIO GPIO:GPIO[45] PWM0 PinMux1:PWM0 PWM1, VPBE (RGB666/RGB888), GPIO GPIO:GPIO[46] VPBE: PWM1: RGB666/RGB888 PWM1 R2 PinMux0:RGB666/ PinMux0:RGB888 PinMux1:PWM1 PWM2, VPBE (RGB666/RGB888), GPIO GPIO:GPIO[47] VPBE: PWM2: RGB666/RGB888 PWM2 B2 PinMux0:RGB666/ PinMux0:RGB888 PinMux1:PWM2 ClockOut0, GPIO PinMux1:CLK0 ATA: HDDIR PinMux1:SPI PinMux0:HDIREN GPIO:GPIO[48] CLK_OUT0 ClockOut1, TIMER0, GPIO:GPIO[49] GPIO CLK_OUT1 ATA, GPIO GPIO: GPIO[50:51] ATA: ATA_CS0, ATA_CS1 EMIFA, GPIO, ATA (CF) GPIO:GPIO[52] EMIFA: EM_BA[1] ATA (CF): DA1 PinMux0:AEAW[4:0], Pins:DAEAW[4:0] PinMux0:ATAEN EMIFA, HPI, ATA (CF), GPIO GPIO:GPIO[53] EMIFA: EM_A[0] ATA (CF): DA2 HPI: HCNTL1 PinMux0:AEAW[4:0], Pins:DAEAW[4:0] PinMux0:ATAEN, PinMux0:HPIEN, Pins:BTSEL[1:0] = 10 EMAC, GPIO3V GPIO: GPIO3V[0:13] EMAC: (all pins, except CRS) (5) PinMux0:EMACEN EMAC, MDIO, GPIO3V GPIO: GPIO3V[14:16] EMAC: CRS, MDIO: MDIO, MDCLK PinMux0:EMACEN UART1, ATA (CF) N/A ATA (CF): DMACK,DMARQ UART2, VPFE VPFE: UART2: CI[7:6]/ UART_RXD2, CCD_DATA[15:14] UART_TXD2 PinMux1:UART2 UART2, VPFE VPFE: UART2: CI[5:4]/ UART_CTS2, CCD_DATA[13:12] UART_RTS2 PinMux1:UART2, PinMux1:U2FLO Memory Stick/Memory Stick PRO, MMC/SD/SDIO MMC/SD/SDIO: CLK, CMD, DATA[3:0] PinMux1:MSTK (4) (5) TIMER0: TIM_IN PinMux1:CLK1 PinMux1:TIM_IN PinMux0:ATAEN UART1: TXD, RXD Memory Stick/Memory Stick PRO: CLK, BS, DATA[3:0] PinMux0:ATAEN PinMux1:UART1 See Section 2.7, Terminal Functions, section for pin details. See Section 2.7, Terminal Functions, section for pin details. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 75 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.3 www.ti.com Peripheral Selection After Device Reset After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing of shared device pins between peripherals, as given in Section 2.7, Terminal Functions. Section 3.5.4, PINMUX0 Register Description, Section 3.5.5, PINMUX1 Register Description, and Section 3.5.6, Pin Multiplexing Register Field Details, identify the register settings necessary to configure specific multiplexed functions and show the primary (default) function after reset. 3.5.4 PINMUX0 Register Description The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals. The register format is shown in Figure 3-7 and bit field descriptions are given in Table 3-14. More details on the PINMUX0 pin muxing fields are given in Section 3.5.6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function. Figure 3-7. PINMUX0 Register (1) 31 30 29 EMACEN RSVD HPIEN R/W-0 R/W-0 R/W-D R-0 13 12 15 14 VLYNQEN VLSCREN R/W-0 R/W-0 28 27 RSVD CFLDEN R/W-0 26 25 17 16 CWE LFLDEN LOEEN 24 RGB888 23 RGB666 22 RESERVED ATAEN HDIREN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 9 21 5 18 11 10 VLYNQWD AECS5 AECS4 RESERVED 4 AEAW 0 R/W-00 R/W-0 R/W-0 R-00000 R/W-LLLLL LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; -n = value after reset (1) For proper DM6441 device operation, always write a value of '0' to RSV bit 30. Table 3-14. PINMUX0 Register Field Descriptions Bit Field 31 EMACEN Value Description 30 RESERVED 29 HPIEN 28 RESERVED 27 CFLDEN 26 CWE Enable CCD C_WE function on default GPIO[1] pin 25 LFLDEN Enable LCD_FIELD function on default GPIO[3] pin 24 LOEEN Enable LCD_OE function on default GPIO[0] pin 23 RGB888 Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins 22 RGB666 Enable VPBE RGB666 function on default GPIO[46:47] pins 21 - 18 RESERVED Enable EMAC and MDIO function on default GPIO3V[0:16] pins. Reserved Enable HPI module pins. Default value is derived from BTSEL[1:0] configuration inputs. HPIEN is 1 when the BTSEL[1:0] = 10 and HPIEN is 0 (the default state) when BTSEL[1:0] is 00, 01, or 11. Reserved Enable CCD C_FIELD function on default GPIO[4] pin Reserved 17 ATAEN Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins 16 HDIREN Enable HDDIR function on default GPIO[42] pin 15 VLYNQEN Enable VLYNQ function on default GPIO[9,10:17] pins 14 VLSCREN Enable VLYNQ SCRUN function on default GPIO[9] pin 13 - 12 VLYNQWD VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3] functions on default GPIO[10:17] pins. 11 AECS5 Enable EMIFA EM_CS5 function on GPIO[8] Enable EMIFA EM_CS4 function on GPIO[9] 76 10 AECS4 9-5 RESERVED 4-0 AEAW Reserved EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This enables EMIF address function on default GPIO[10:28] pins. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 3.5.5 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 PINMUX1 Register Description The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing fields are given in Section 3.5.6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function. Figure 3-8. PINMUX1 Register 31 19 15 11 18 17 16 RESERVED TIMIN CLK1 CLK0 R-0000 0000 0000 0 R/W-0 R/W-0 R/W-0 10 9 8 7 RESERVED ASP MSKT SPI I2C R-0000 0 R/W-0 R/W-0 R/W-0 R/W-0 3 2 1 0 PWM2 PWM1 PWM0 6 5 U2FLO UART2 UART1 UART0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 4 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-15. PINMUX1 Register Field Descriptions Bit Field 31 - 19 RESERVED Value Description 18 TIMIN Enable TIM_IN function on default GPIO[49] pin 17 CLK1 Enable CLK_OUT1 function on default GPIO[49] pin 16 CLK0 Enable CLK_OUT0 function on default GPIO[48] pin 15 - 11 RESERVED Reserved Reserved 10 ASP 9 MSKT Enable ASP function on default GPIO[29:34] pins 8 SPI Enable SPI function on default GPIO[37,39:42] pins 7 I2C Enable I2C function on default GPIO[43:44] pins 6 PWM2 Enable PWM2 function on default GPIO[47] pin 5 PWM1 Enable PWM1 function on default GPIO[46] pin 4 PWM0 Enable PWM0 function on default GPIO[45] pin 3 U2FLO Enable UART2 flow control function on default VPFE CI[5:4]/CCD_DATA[13:12] pins 2 UART2 Enable UART2 function on default VPFE CI[7:6]/CCD_DATA[15:14] pins 1 UART1 Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins 0 UART0 Enable UART0 function on default GPIO[35:36] pins Enable Memory Stick/Memory Stick PRO function on default MMC/SD/SDIO pins Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 77 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.6 www.ti.com Pin Multiplexing Register Field Details The bit fields for various pin multiplexing options within the PINMUX0 and PINMUX1 registers are described in the following sections. 3.5.6.1 EMAC and GPIO3V Pin Multiplexing The EMAC pin functions are selected as shown in Table 3-16. The functionality for each of the individual pins affected by the PINMUX0 field settings is given in Table 3-17. Table 3-16. EMAC and GPIO3V Pin Multiplexing Control EMACEN PIN FUNCTIONALITY SELECTED 0 GPIO3V 1 EMAC Table 3-17. EMAC and GPIO3V Multiplexed Pins GPIO 78 EMAC GPIO3V[0] TXEN GPIO3V[1] TXCLK GPIO3V[2] COL GPIO3V[3] TXD[0] GPIO3V[4] TXD[1] GPIO3V[5] TXD[2] GPIO3V[6] TXD[3] GPIO3V[7] RXD[0] GPIO3V[8] RXD[1] GPIO3V[9] RXD[2] GPIO3V[10] RXD[3] GPIO3V[11] RXCLK GPIO3V[12] RXDV GPIO3V[13] RXER GPIO3V[14] CRS GPIO3V[15] MDIO GPIO3V[16] MDCLK Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 3.5.6.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing The CCD and LCD controllers in the VPSS require multiplex control bit settings for certain modes of operation. Bits within the PinMux0 register, which select between the CCD or LCD control signal function and GPIO, are summarized in Table 3-18. Table 3-18. VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing PINMUX0 REGISTER FIELDS MULTIPLEXED PINS C_FIELD/ R0/ GPIO[4] LCD_FIELD/ B0/ GPIO[3] C_WE/ GPIO[1] LCD_OE/ GPIO[0] CFLDEN LFLDEN CWE LOEEN - - - 0 - - - GPIO[0] - - - 1 - - - LCD_OE - - 0 - - - GPIO[1] - - - 1 - - - C_WE - - 0 - - - B0/GPIO[3] (1) - - - 1 - - - LCD_FIELD - - 0 - - - R0/GPIO[4] (1) - - - 1 - - - C_FIELD - - - (1) Depends on RGB888 bit setting, see Table 3-19. 3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-19 and Table 3-20. Enabling PWM2, PWM1, CCD, and LCD functionality overrides the RGB modes. RGB666 interface pin functionality requires setting the RGB666 PINMUX0 register bit field to ‘1’ and PINMUX1 register bit fields PWM2 and PWM1 to ‘0’. Proper RGB888 interface operation requires setting PINMUX0 register bit field RGB888 to ‘1’ and bit fields PWM2, PWM1, CFLDEN, and LFLDEN must be set to ‘0’. Table 3-19. VPBE (RGB666, RGB888, and LCD), VPFE (CCD), and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS PWM2/ LFLDEN B2/ GPIO[47] PWM1/ R2/ GPIO[46] C_FIELD/ R0/ GPIO[4] LCD_FIELD/ B0/ GPIO[3] GPIO[47] GPIO[46] GPIO[4] GPIO[3] 1 - - - LCD_FIELD - - - C_FIELD - - - PWM1 - - RGB888 RGB666 PWM2 PWM1 CFLDEN 0 0 0 0 0 0 - - - - - - - - - 1 - - - 1 - - - 1 - - - PWM2 - - - 0 1 0 0 0 0 B2 R2 GPIO[4] GPIO[3] 1 - 0 0 0 0 B2 R2 R0 B0 Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS RGB888 PWM2 PWM1 CFLDEN LFLDEN R1/ GPIO[38] B1/ GPIO[6] G1/ GPIO[5] G0/ GPIO[2] 0 0 0 0 0 GPIO[38] GPIO[6] GPIO[5] GPIO[2] 1 0 0 0 0 R1 B1 G1 G0 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 79 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.6.4 www.ti.com ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-21. If ATA pin functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1 if the buffer is not being used (i.e. for compact flash). This multiplexing is shown in Table 3-22. When ATAEN=0 and HDIREN=1 it indicates that the ATA interface has been disabled so that the EMIFA can be used, but the ATA buffers are still present. HDDIR is driven low in this situation to ensure that the ATA buffers drive away from DM6441 and don’t cause bus contention with the EMIFA. Note that switching between EMIFA and ATA (clearing or setting ATAEN) must be carefully performed to prevent bus contention. Since the ATA device can be a bus master, software must ensure that all outstanding DMA requests have completed before clearing the ATAEN bit. Table 3-21. ATA, EMIFA, and GPIO Pin Multiplexing Control (1) PINMUX0 REGISTER BIT FIELD ATAEN 0 1 (1) (2) MULTIPLEXED PINS EM_BA[1]/ GPIO[52]/ ATA1 EM_A[0]/ GPIO[53]/ ATA2 EM_D[15:0]/ DD[15:0] EM_WE EM_BA[1]/ GPIO[52] (2) EM_A[0]/ GPIO[53] (2) EM_D[15:0] DIOW ATA1 ATA2 DD[15:0] GPIO[50]/ ATA_CS0 GPIO[51]/ ATA_CS1 EM_R/W INTRQ EM_BA[0]/ ATA0 EM_WAIT/ IORDY DIOR/ EM_OE DIOW/ EM_WE GPIO[50] GPIO[51] EM_R/W EM_BA[0] EM_WAIT EM_OE ATA_CS0 ATA_CS1 INTRQ ATA0 IORDY DIOR This table assumes that the HPIEN bit in the PINMUX0 register is "0". This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9. Table 3-22. ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS 80 MULTIPLEXED PINS UART_TXD1/ DMACK UART_RXD1/ DMARQ SPI_EN1/ HDDIR/ GPIO[42] 0 DMACK DMARQ GPIO[42] 0 1 DMACK DMARQ SPI_EN1 1 - DMACK DMARQ Driven Low 1 0 0 UART_TXD1 UART_RXD1 GPIO[42] 0 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1 0 1 1 - UART_TXD1 UART_RXD1 Driven Low 1 0 0 0 DMACK DMARQ GPIO[42]x 1 0 0 1 DMACK DMARQ SPI_EN1x 1 0 1 - DMACK DMARQ HDDIR 1 1 0 0 UART_TXD1 UART_RXD1 GPIO[42]x 1 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1x 1 1 1 - UART_TXD1 UART_RXD1 HDDIR ATAEN UART1 HDIREN SPI 0 0 0 0 0 0 0 0 Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 3.5.6.5 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 VLYNQ, EMIFA, and GPIO Pin Multiplexing Table 3-23 and Table 3-24 show the VLYNQ pin control and multiplexing. If VLYNQ is disabled (VLYNQEN=0), the AECS5 and AECS4 bits select between the GPIO[8] / EMIFA EM_CS5 and GPIO[9] / EMIFA EM_CS4 functions, and the AEAW field determines the partitioning between GPIO and the upper EMIFA address pins. If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address based on the AEAW value. Table 3-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing PINMUX0 REGISTER BIT FIELDS MULTIPLEXED PINS EM_CS5/ GPIO[8]/ VLYNQ_CLOCK EM_CS4/ GPIO[9]/ VLYNQ_SCRUN VLYNQEN VLSCREN AECS5 AECS4 0 - 0 0 GPIO[8] GPIO[9] 0 - 0 1 GPIO[8] EM_CS4 0 - 1 0 EM_CS5 GPIO[9] 0 - 1 1 EM_CS5 EM_CS4 1 0 - 0 VLYNQ_CLOCK GPIO[9] 1 0 - 1 VLYNQ_CLOCK EM_CS4 1 1 - - VLYNQ_CLOCK VLYNQ_SCRUN Table 3-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing PINMUX0 REGISTER BIT FIELDS MULTIPLEXED PINS VLYNQEN VLYNQWD EM_A[21]/ GPIO[10]/ VL_TXD0 EM_A[20]/ GPIO[11]/ VL_RXD0 EM_A[19]/ GPIO[12]/ VL_TXD1 EM_A[18]/ GPIO[13]/ VL_RXD1 EM_A[17]/ GPIO[14]/ VL_TXD2 EM_A[16]/ GPIO[15]/ VL_RXD2 EM_A[15]/ GPIO[16]/ VL_TXD3 EM_A[14]/ GPIO[17]/ VL_RXD3 0 - EM_A[21]/ GPIO[10] (1) EM_A[20]/ GPIO[11] (1) EM_A[19]/ GPIO[12] (1) EM_A[18]/ GPIO[13] (1) EM_A[17]/ GPIO[14] (1) EM_A[16]/ GPIO[15] (1) EM_A[15]/ GPIO[16] (1) EM_A[14]/ GPIO[17] (1) 1 00 VL_TXD0 VLRXD0 EM_A[19]/ GPIO[12] (1) EM_A[18]/ GPIO[13] (1) EM_A[17]/ GPIO[14] (1) EM_A[16]/ GPIO[15] (1) EM_A[15]/ GPIO[16] (1) EM_A[14]/ GPIO[17] (1) 1 01 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 EM_A[17]/ GPIO[14] (1) EM_A[16]/ GPIO[15] (1) EM_A[15]/ GPIO[16] (1) EM_A[14]/ GPIO[17] (1) 1 10 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 EM_A[15]/ GPIO[16] (1) EM_A[14]/ GPIO[17] (1) 1 11 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 VL_TXD3 VLRXD3 (1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 81 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.6.6 www.ti.com Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing The multiplexing of the CLK_OUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 3-25. Table 3-25. Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS 3.5.6.7 MULTIPLEXED PINS CLK_OUT1/ TIM_IN/ GPIO[49] TIMIN CLK1 0 0 GPIO[49] 0 1 CLK_OUT1 1 - TIM_IN ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as seen in Table 3-26, Table 3-27, and Table 3-28. The SPI_EN1 pin can also function as the HDDIR buffer control when ATAEN is selected and the HDIREN bit is set. Table 3-26. ASP and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELD MULTIPLEXED PINS ASP CLKX/ GPIO[29] CLKR/ GPIO[30] FSX/ GPIO[31] FSR/ GPIO[32] DX/ GPIO[33] DR/ GPIO[34] 0 GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34] 1 CLKX CLKR FSX FSR DX DR Table 3-27. SPI and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS SPI ATAEN HDIREN SP_EN1/ HDDIR/ GPIO[42] SPI_DO/ GPIO[41] SPI_DI/ GPIO[40] SPI_CLK/ GPIO[39] SPI_EN0/ GPIO[37] 0 0 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 0 1 Driven Low GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 1 HDDIR GPIO[41] GPIO[40] GPIO[39] GPIO[37] 1 0 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 0 1 Driven Low SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 1 HDDIR SPI_DO SPI_DI SPI_CLK SPI_EN0 Table 3-28. I2C and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELD 82 MULTIPLEXED PINS I2C I2C_CLK/ GPIO[43] I2C_DATA/ GPIO[44] 0 GPIO[43] GPIO[44] 1 I2C_CLK I2C_DATA Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 3.5.6.8 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 PWM, RGB888, and GPIO Pin Multiplexing Table 3-29 shows the PWM0/1/2 pin multiplexing. Each PWM output is independently controlled by its own enable bit. The PWM function has priority over RGB888 muxing [see Section 3.5.6.3, VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing]. Table 3-29. PWM0/1/2, RGB888, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS PWM2 PWM1 PWM0 RGB888 PWM2/ B2/ GPIO[47] PWM1/ R2/ GPIO[46] PWM0/ GPIO[45] 0 0 0 0 GPIO[47] GPIO[46] GPIO[45] 0 0 0 1 B2 R2 GPIO[45] - - 1 - - - PWM0 - 1 - - - PWM1 - 1 - - - PWM2 - - Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 83 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.6.9 www.ti.com UART, VPFE, ATA, and GPIO Pin Multiplexing Each UART has independent pin multiplexing control bits in the PINMUX1 register. The UART2 peripheral may be used with or without the flow control signals. Table 3-30 shows how UART2 selection reduces the width of the VPFE interface. Setting the UART1 bit enables UART1 transmit and receive pin functionality. Since these are shared with the ATA DMA handshake signals, enabling UART1 effectively disables the ATA DMA mode. However, ATA PIO mode is still supported with UART1 enabled. This is shown in Table 3-31. If the ATA module is not enabled, the pins are always configured for use by UART1. Table 3-30. UART2, VPFE, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS (1) UART2 U2FLO 0 - 1 0 1 1 MULTIPLEXED PINS CCD[15]/ CI[7]/ UART_RXD2 CCD[14]/ CI[6]/ UART_TXD2 CCD[13]/ CI[5]/ UART_CTS2 CCD[12]/ CI[4]/ UART_RTS2 CCD[15]/ CI[7] (1) CCD[14]/ CI[6] (1) CCD[13]/ CI[5] (1) CCD[12]/ CI[4] (1) UART_RXD2 UART_TXD2 CCD[13]/ CI[5] (1) CCD[12]/ CI[4] (1) UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2 Functionality set by VPFE operating mode. Table 3-31. UART1 and ATA Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS UART1 UART_TXD1/ DMACK UART_RXD1/ DMARQ 0 - UART_TXD1 UART_RXD1 1 0 DMACK DMARQ 1 1 UART_TXD1 UART_RXD1 ATAEN As Table 3-32 shows, the UART0 pins are configurable for either UART0 transmit and receive data functions or for GPIO. Table 3-32. UART0 and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELD UART_TXD0/ GPIO[36] UART_RXD0/ GPIO[35] 0 GPIO[36] GPIO[35] 1 UART_TXD0 UART_RXD0 UART0 84 MULTIPLEXED PINS Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.5.6.10 HPI and EMIFA/ATA Pin Multiplexing When the HPIEN bit is set, the HPI module is given control of most of the EMIFA/ATA control pins as well as the EMIFA/ATA data bus. Table 3-33 shows which pins the HPI controls. HPIEN is set to 1 when the state of the BTSEL[1:0] pins = 10 is latched at the rising edge of reset. Also, this bit can be manipulated after reset by software. When the ATAEN bit is set and HPIEN is 0, the ATA mode of operation for pins shared with the HPI is available. EMIFA mode functionality for the shared HPI pins is set when both HPIEN and ATAEN are '0'. Table 3-33. HPI and EMIFA/ATA Pin Multiplexing PINMUX0 REGISTER BIT FIELDS MULTIPLEXED PINS HPI EN ATA EN HCS/ EM_CS2 HHWIL/ EM_A[1] HR/W/ INTRQ/ EM_R/W HRDY/ EM_WAIT/ IORDY HDS1/ DIOR/ EM_OE HDS2/ DIOW/ EM_WE HCNTLA/ EM_A[2] HCNTLB/ ATA2/ EM_A[0] HINT/ ATA0/ EM_BA[0] HD[15:0]/ DD[15:0]/ EM_D[15:0] 0 0 EM_CS2 EM_A[1] (1) EM_R/W EM_WAIT EM_OE EM_WE EM_A[2] (1) EM_A[0] (1) EM_BA[0] EM_D[15:0] 0 1 EM_CS2 EM_A[1] (1) INTRQ IORDY DIOR DIOW EM_A[2] (1) EM_A[0] (1) ATA0 DD[15:0] 1 - HCS HHWIL HR/W HRDY HDS1 HDS2 HCNTLA HCNTLB HINT HD[15:0] (1) This pin shares GPIO functionality and is set by AEAW[4:0] as shown in Table 3-12, Table 3-13, and Table 3-14. Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 85 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 3.6 www.ti.com Emulation Control The flexibility of the DM6441 architecture allows either the ARM or DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal. This allows peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register indicates the emulation suspend source for those peripherals which support emulation suspend. The SUSPSRC register format is shown in Figure 3-9. Brief details on the peripherals which correspond to the register bits is given in Table 3-34. When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator. Figure 3-9. Emulation Suspend Source Register (SUSPSRC) 31 30 VICP SRC VICP EN 29 28 27 26 TIMR2 TIMR1 TIMR0 SRC SRC SRC 25 GPIO SRC 24 23 PWM2 PWM1 PWM0 SRC SRC SRC 22 21 20 19 18 17 16 SPI SRC UART2 SRC UART1 SRC UART0 SRC I2C SRC ASP SRC RSV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 13 12 11 RESERVED HPI SRC R-000 R/W-0 10 9 RESERVED USB SRC R-00 R/W-0 8 6 5 R/W-0 R/W-0 4 R-0 0 RESERVED EMAC SRC RESERVED R-0 00 R/W-0 R-0 0000 LEGEND: R = Read, W = Write, n = value at reset Table 3-34. SUSPSRC Register Descriptions 86 Bit Name Description 31 VICPSRC Video Imaging Coprocessor emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 30 VICPEN Video Imaging Coprocessor emulation suspend enable 0 = Emulation suspend ignored by VICP 1 = VICP emulation suspend enabled 29 TIMR2SRC Timer2 (WD Timer) emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 28 TIMR1SRC Timer1 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 27 TIMR0SRC Timer0 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 26 GPIOSRC GPIO emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 25 PWM2SRC PWM2 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 24 PWM1SRC PWM1 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 23 PWM0SRC PWM0 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 22 SPISRC SPI emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 21 UART2SRC UART2 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 3-34. SUSPSRC Register Descriptions (continued) Bit Name 20 UART1SRC UART1 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 19 UART0SRC UART0 emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 18 I2CSRC I2C emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 17 ASPSRC ASP emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend RESERVED Reserved HPISRC HPI emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend RESERVED Reserved USBSRC USB emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 8-6 RESERVED Reserved 5 EMACSRC Ethernet MAC emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend 4-0 RESERVED Reserved 16 -13 12 11 - 10 9 Description Device Configurations Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 87 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 4 System Interconnect On the DM6441 device, the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture (shown in Figure 4-1). The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals and slave peripherals. Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between master and slave peripherals. Through SCR, the ARM subsystem can send data to the DDR2 Memory Controller without affecting a data transfer between the EMAC and L2 memory. Bridges are mainly used to perform bus-width conversion as well as bus operating frequency conversion. For example, in Figure 4-1, Bridge 8 performs a frequency conversion between a bus operating at DSP/6 clock rate and a bus operating at DSP/3 clock rate. Furthermore, Bridge 3 performs a bus-width conversion between a 64-bit bus and a 32-bit bus. The C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the various system peripherals can be classified into two categories: master peripherals and slave peripherals. Master peripherals are typically capable of initiating read and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, CF/ATA, VLYNQ, EMAC, USB, and VPSS. Not all master peripherals may connect to all slave peripherals. The supported connections are designated by an X in Table 4-1. Table 4-1. System Connection Matrix MASTER SLAVE C64x+ C64x+ ARM ARM DDR2 MEMORY CONTROLLER SCR3 (1) X X X X X X VPSS CF/ATA X X X X VLYNQ X X X X EMAC X X X X USB X X X X EDMA3TC0 X X X X EDMA3TC1 X X X X X X X (2) HPI (1) (2) 88 X The C64x+ megamodule has access to only the following peripherals connected to SCR3: EDMA3, ASP, and Timers. All other peripherals/modules that support a connection to SCR3 have access to all peripherals/modules connected to SCR3. HPI's access to SCR3 is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and HPI configuration registers. System Interconnect Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 4.1 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 System Interconnect Block Diagram Figure 4-1 displays the DM6441 system interconnect block diagram. The following is a list that helps interpret this diagram: • The direction of the arrows indicates either bus master or bus slave. • The arrow originates at a bus master and terminates at a bus slave. • The direction of the arrows does not indicate the direction of data flow. Data flow is typically bi-directional for each of the documented bus paths. • The pattern of each arrow's line indicates the clock rate at which it is operating, either DSP/2, DSP/3, or DSP/6 clock rate. • Some peripherals may have multiple instances shown in the diagram. A peripheral may have multiple instances shown for a variety of reasons, some of which are described below: – The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register access, data access, and/or memory access. Examples of these peripherals are C64x+ megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI. – The peripheral/module has a master port as well as slave memories. Examples of these are the C64x+ megamodule and the ARM subsystem. VLYNQ EMAC USB 2.0 HPI 32 32 32 32 SCR5 32 Bridge2 64 DDR2 Ctrl (Mem/Reg) 64 SDMA CF/ATA 64 DSP/2 Clock Rate DSP/3 Clock Rate DSP/6 Clock Rate MXI/CLKIN Rate 32 64 VPSS Read Write Read Write EDMA3TC0 EDMA3TC1 64 64 64 64 C64x+ L2/L1 32 L2 Cache Bridge3 32 ARM TCM 32 32 128 32 CFG MDMA 64 Bridge5 64 32 32 64 Bridge6 32 32 SCR6 32 32 VICP SCR3 ARM 32 32 SCR2 32 32 32 32 32 32 32 Bridge1 32 32 32 EDMA3CC EDMA3TC0 32 Bridge7 32 Bridge9 32 CF/ATA Reg 32 USB Reg 32 32 EMAC Reg 32 32 32 256 32 EDMA3TC1 32 C64x+ SCR4 SCR1 64 64 32 Bridge8 UART0 UART1 UART2 I2C 32 HPI SCR8 EMAC Ctrl Mod Reg 32 EMAC Ctrl Mod RAM 32 MDIO 32 VPSS Reg 32 SPI 0/1 32 PWM0 PWM1 PWM2 Timer 0 Timer 1 Timer 2 GPIO 32 AINTC System Reg 32 PSC PLLC 0 SCR7 32 ASP VLYNQ MMC/SD PLLC 1 32 32 32 EMIFA/NAND MS/MS PRO Figure 4-1. System Interconnect Block Diagram System Interconnect Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 89 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 5 Device Operating Conditions 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (1) Core (CVDD, VDDA_1P1V, USB_VDDA1P2LDO Supply voltage ranges Input voltage ranges Output voltage ranges I/O, 3.3V (DVDD33, USB_DVDDA_3P3) (2) , CVDDDSP) (3) (3) -0.5 V to 1.5 V -0.5 V to 4.2 V I/O, 1.8V (DVDD18, DVDDR2, DDR_VDDDLL, PLLVDD18, VDDA_1P8V, USB_VDD1P8, MXVDD, M24VDD) (3) -0.5 V to 2.5 V VI I/O, 3.3V -0.5 V to 4.2 V VI I/O, 1.8V -0.5 V to 2.5 V VO I/O, 3.3V -0.5 V to 4.2 V VO I/O, 1.8V -0.5 V to 2.5 V Operating case temperature ranges, TC (default) 0°C to 85°C Storage temperature range, Tstg (default) -55°C to 150°C (1) (2) (3) 90 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO. All voltage values are with respect to VSS. Device Operating Conditions Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 5.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Recommended Operating Conditions CVDD DVDD MIN NOM MAX 1.00 1.05 1.10 1.15 1.2 1.25 Supply voltage, I/O, 3.3V (DVDD33, USB_DVDDA3P3) 3.15 3.3 3.45 V Supply voltage, I/O, 1.8V (DVDD18, DVDDR2, DDR_VDDDLL, PLLVDD18, VDDA_1P8V, USB_VDD1P8, MXVDD, M24VDD) 1.71 1.8 1.89 V 0 0 0 V 0.49DVDDR2 0.5DVDDR2 0.51DVDDR2 V Supply voltage, Core (CVDD, VDDA_1P1V, USB_VDDA1P2LDO CVDDDSP) (2) (1) , VSS Supply ground (VSS, VSSA_1P8V, VSSA_1P1V, DDR_VSSDLL, USB_VSSREF, USB_VSS1P8, USB_VSSA3P3, USB_VSSA1P2LDO, MXVSS (3), M24VSS (3)) DDR_VREF DDR2 reference voltage (4) DDR_ZP DDR2 impedance control, connected via 200 Ω resistor to VSS DDR_ZN DDR2 impedance control, connected via 200 Ω resistor to DVDDR2 DAC_VREF DAC reference voltage input DAC_RBIAS DAC biasing, connected via 4 kΩ resistor to VSSA_1P8V USB_VBUS USB external charge pump input 5 0.35DVDD Default DSP Operating Frequency (SYSCLK1) V V 0.8 Operating case temperature V V 5.25 2 Low-level input voltage, non-DDR I/O, 1.8V FSYSCLK1 V 0.525 0.65DVDD Low-level input voltage, I/O, 3.3V TC 0.5 VSSA_1P8V 4.75 High-level input voltage, non-DDR I/O, 1.8V VIL (3) (4) 0.475 V V DVDDR2 High-level input voltage, I/O, 3.3V VIH (1) (2) VSS UNIT 0 85 1.05 V core 20 405 1.2 V core 20 513 V °C MHz This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO. Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V, 1.1 V, 1.14 V, 1.2, 1.26 V with ±3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC devices. Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDDR2. Device Operating Conditions Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 91 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) PARAMETER VOH VOL II www.ti.com (2) TEST CONDITIONS (1) MIN TYP MAX Low/full speed: USB_DN and USB_DP 2.8 USB_DVDDAP3 High speed: USB_DN and USB_DP 360 440 High-level output voltage (3.3V I/O) DVDD33 = MIN, IOH = MAX 2.4 High-level output voltage (1.8V I/O) DVDD18 = MIN, IOH = MAX DVDD - 0.45 UNIT V mV V V Low/full speed: USB_DN and USB_DP 0.0 0.3 V High speed: USB_DN and USB_DP -10 10 mV Low-level output voltage (3.3V I/O) DVDD33 = MIN, IOL = MAX 0.4 V Low-level output voltage (1.8V I/O) DVDD18 = MIN, IOL = MAX 0.45 V VI = VSS to DVDD without opposing internal resistor ±10 µA Input current VI = VSS to DVDD with opposing internal pullup resistor (3) 50 100 250 µA VI = VSS to DVDD with opposing internal pulldown resistor (3) -250 -100 -50 µA IOH High-level output current All peripherals 4 mA IOL Low-level output current All peripherals 4 mA IOZ (4) I/O Off-state output current VO = DVDD or VSS, internal pull disabled VO = DVDD or VSS, internal pull enabled ±20 ±100 µA ICDD Core (CVDD, APLLREFV, VDDA_1P1V, VDDA1P2LDO (5), CVDDDSP) supply current (6) CVDD = 1.2 V, DSP clock = 513 MHz 659 CVDD = 1.05 V, DSP clock = 405 MHz 521 IDDD 3.3V I/O (DVDD33, USB_DVDDA3P3) supply current (6) DVDD = 3.3 V, DSP clock = 513 MHz 6 DVDD = 3.3 V, DSP clock = 405 MHz 6 1.8V I/O (DVDD18, DVDDR2, DDR_VDDDLL, PLLVDD18, VDDA_1P8V, USB_VDD1P8, MXVDD, M24VDD) supply current (6) DVDD = 1.8 V, DSP clock = 513 MHz 98 IDDD DVDD = 1.8 V, DSP clock = 405 MHz 94 Ci Input capacitance 4 pF Co Output capacitance 4 pF (1) (2) (3) (4) (5) (6) 92 mA mA mA For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in Section 5.2, Recommended Operating Conditions. II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current. This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO. Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other housekeeping activities); DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes, 32 bits, 50% bit switching; 2 MHz ASP at 100% utilization; Timer0 at 100% utilization. At room temperature (25°C) for typical process devices. The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and I/O activity, as well as information relevant to board power supply design, see the TMS320DM6441 Power Consumption Summary application report (literature number SPRAAU3). Device Operating Conditions Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6 Peripheral and Electrical Specifications 6.1 Parameter Information 6.1.1 Parameter Information Device-Specific Information Tester Pin Electronics 42 Ω Data Manual Timing Reference Point Output Under Test 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF Device Pin (see note) 1.85 pF NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data manual timings. Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 6-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 6.1.1.1 Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O, Vref = 1.5 V. For 1.8 V I/O, Vref = 0.9 V. Vref Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 93 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.1.1.2 www.ti.com Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the TMS320DM644x DSP Application Report (literature number SPRAAC5). 6.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6.3 Power Supplies For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower. 6.3.1 Power-Supply Sequencing The DM6441 includes two core supplies — CVDD and CVDDDSP, as well as three I/O supplies — DVDD18, DVDDR2, and DVDD33. To ensure proper device operation, a specific power-up sequence must be followed. The core supply power-up sequence is dependent on the DSP boot mode selected at reset. If the DSP boot mode is configured as self-boot mode, then both core supplies must be powered up at the same time. If the DSP boot mode is configured as host-boot, where the ARM boots the DSP, the two core supplies may be ramped simultaneously or powered up separately. When powered up separately, the CVDDDSP supply must not be ramped prior to the CVDD supply. The CVDDDSP supply must be powered up before the shorting switch is closed (enabled). Prior to powering up the CVDDDSP supply, it should be left floating and not driven to ground. Table 6-1 and Figure 6-4 describe the power-on sequence timing requirements for DSP host-boot mode. To minimize the voltage difference between these two core supplies, a single regulator source must be used to power the CVDD and CVDDDSP supplies. For more information, see Section 3.2.1, Power Configurations at Reset. 94 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see Figure 6-4) 1.05 V and 1.2 V NO. 1 (1) td(CVDD-CVDDDSP) Delay time, CVDD supply ready to CVDDDSP supply ramp start MIN MAX 0 (1) UNIT ns In host-boot mode, the CVDDDSP supply must be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON and DSP power domains. CVDD 1 CVDDDSP Figure 6-4. DSP Host-Boot Mode Core Supply Timings Once the CVDD supply has been powered up, the I/O supplies may be powered up. Table 6-2 and Figure 6-5 show the power-on sequence timing requirements for the Core vs. I/O power-up. DVDDXX is used to denote all I/O supplies. NOTE The DVDDXX supply power-up is specified relative to the CVDD supply power-up, not the CVDDDSP supply. Table 6-2. I/O Supply Power-On Timing Requirements (see Figure 6-5) 1.05 V and 1.2 V NO. 1 td(CVDD-DVDD) Delay time, CVDD supply ready to DVDDXX supply ramp start MIN MAX 0 100 UNIT ms CVDD 1 (A) DVDDXX Note A: DVDDXX denotes all I/O supplies. Figure 6-5. I/O Supply Timings There is not a specific power-up sequence that must be followed with respect to the order of the power-up of the DVDD18, DVDDR2, and DVDD33 supplies. Once the CVDD supply is powered up and the td(CVDD-DVDDXX) specification is met, the DVDD18, DVDDR2, and DVDD33 supplies may be powered up in any order of preference. All other supplies may also be powered up in any order of preference once the td(CVDD-DVDDXX) specification has been met. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 95 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.3.1.1 www.ti.com Power-Supply Design Considerations Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the DM6441 device, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. 6.3.1.2 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to DM6441. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6441 power pins, no more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than eight small and eight medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior". Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 mF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint. Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product’s production lifetime should be considered. 6.3.1.3 DM6441 Power and Clock Domains DM6441 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain is always on when the chip is on. The "Always On" domain is powered by the VDD pins of the DM6441. The majority of the DM6441's modules lie within the "Always On" power domain. A separate domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain is not always on. The "DSP" power domain is powered by the CVDDDSP pins of the DM6441. Table 6-3 provides a listing of the DM6441 power and clock domains. Two primary reference clocks are required for the DM6441 device. These can either be crystal input or driven by external oscillators. A 27-MHz crystal is recommended for the system PLLs, which generate the internal clocks for the ARM, DSP, coprocessors, peripherals (including imaging peripherals), and EDMA3. The recommended 27-MHz input enables the use of the video DACs to drive NTSC/PAL television signals at the proper frequencies. A 24-MHz crystal is also required if the USB peripheral is to be used. For further description of the DM6441 clock domains, see Table 6-4 (DM6441 Clock Domains) and Figure 6-6 (PLL1 and PLL2 Clock Domain Block Diagram). 96 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-3. DM6441 Power and Clock Domains Power Domain Clock Domain Peripheral/Module Always On CLKIN UART0 Always On CLKIN UART1 Always On CLKIN UART2 Always On CLKIN I2C Always On CLKIN Timer0 Always On CLKIN Timer1 Always On CLKIN Timer2 Always On CLKIN PWM0 Always On CLKIN PWM1 Always On CLKIN PWM2 Always On CLKDIV2 ARM subsystem Always On CLKDIV3 DDR2 Always On CLKDIV3 VPSS Always On CLKDIV3 EDMA3 Always On CLKDIV3 SCR Always On CLKDIV6 GPSC Always On CLKDIV6 LPSCs Always On CLKDIV6 Ice Pick Always On CLKDIV6 EMIFA Always On CLKDIV6 USB Always On CLKDIV6 HPI Always On CLKDIV6 VLYNQ Always On CLKDIV6 EMAC Always On CLKDIV6 ATA/CF Always On CLKDIV6 Memory Stick/Memory Stick PRO Always On CLKDIV6 MMC/SD/SDIO Always On CLKDIV6 SPI Always On CLKDIV6 ASP Always On CLKDIV6 GPIO DSP CLKDIV1 C64x+ CPU DSP CLKDIV2 VICP DSP CLKDIV4 VICP DSP CLKDIV6 VICP Table 6-4. DM6441 Clock Domains (1) Subsystem Fixed Ratio vs. PLL1 Clock Modes (Frequency) PLL Bypass PLL Enabled PLL1 – 27 MHz 405 MHz DSP 1:1 27 MHz 405 MHz ARM 1:2 13.5 MHz 202.5 MHz EDMA3/VPSS 1:3 9 MHz 135 MHz Peripherals 1:6 4.5 MHz 67.5 MHz (1) These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 15. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 97 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 27 MHz www.ti.com Bypass Clock UARTs (x3) SYSCLK1 DSP Subsystem I2C PLLDIV2 (/2) ARM Subsystem PWMs (x3) PLLDIV4 (/4) VICP Timers (x3) PLLDIV1 (/1) SYSCLK2 PLLDIV5 (/6) SYSCLK5 USB PHY SYSCLK3 PLLDIV3 (/3) 24 MHz 60 MHz SCR USB 2.0 PLL Controller 1 EDMA3 VLYNQ EMAC VPFE PCLK ATA/CF VPBE VPBECLK EMIF/NAND MMC/SD SPI DACs PLLDIV1 (/10) ASP PLLDIV2 (/2) DDR2 PHY BPDIV DDR2 VTP GPIO PLL Controller 2 DDR2 Mem Ctlr HPI Memory Stick ARM INTC Figure 6-6. PLL1 and PLL2 Clock Domain Block Diagram For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-7 and Figure 6-8, respectively. 98 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 CLKMODE PLLEN CLKIN 1 PLL OSCIN Post−DIV PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV3 (/3) SYSCLK3 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/6) SYSCLK5 1 0 0 PLLM AUXCLK SYSCLKBP BPDIV Figure 6-7. PLL1 Structure Block Diagram CLKMODE PLLEN CLKIN 1 PLL OSCIN 0 Post−Div (/1) 1 PLLDIV1 PLL2_SYSCLK1 (VPSS−VPBE) 0 PLLDIV2 PLL2_SYSCLK2 (DDR2 PHY) PLLM PLL2_SYSCLKBP (DDR2 VTP) BPDIV Figure 6-8. PLL2 Structure Block Diagram Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 99 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.3.1.4 www.ti.com Power and Sleep Controller (PSC) Module The power and sleep controller (PSC) controls DM6441 device power by turning off unused power domains or gating off clocks to individual peripherals/modules. The PSC consists of a global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, power domain control, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The GPSC controls all of DM6441’s LPSCs. The ARM subsystem does not have an LPSC module. ARM sleep mode is accomplished through the wait for interrupt instruction. The LPSCs for DM6441 are shown in Table 6-5. The PSC Register memory map is given in Table 6-6. For more details on the PSC, see Section 2.8.3, Documentation Support, for the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Table 6-5. DM6441 LPSC Assignments LPSC Number Peripheral/Module LPSC Number Peripheral/Module LPSC Number Peripheral/Module 0 VPSS DMA 14 EMIFA 28 TIMER1 1 VPSS MMR 15 MMC/SD/SDIO 29 Reserved 2 EDMA3CC 16 Memory Stick/Memory Stick PRO 30 Reserved 3 EDMA3TC0 17 ASP 31 Reserved 4 EDMA3TC1 18 I2C 32 Reserved 5 EMAC 19 UART0 33 Reserved 6 EMAC Memory Controller 20 UART1 34 Reserved 7 MDIO 21 UART2 35 Reserved 8 Reserved 22 SPI 36 Reserved 9 USB 23 PWM0 37 Reserved 10 ATA/CF 24 PWM1 38 Reserved 11 VLYNQ 25 PWM2 39 C64x+ CPU 12 HPI 26 GPIO 40 VICP 13 DDR2 Memory Controller 27 TIMER0 Table 6-6. PSC Register Memory Map HEX ADDRESS RANGE 0x01C4 1000 0x01C4 1004 - 0x01C4 1014 0x01C4 1018 0x01C4 101C - 0x01C4 103F REGISTER ACRONYM PID DESCRIPTION Peripheral Revision and Class Information Register - Reserved INTEVAL - Interrupt Evaluation Register Reserved 0x01C4 1040 MERRPR0 Module Error Pending 0 (mod 0 - 31) Register 0x01C4 1044 MERRPR1 Module Error Pending 1 (mod 32- 63) Register 0x01C4 1048 - 0x01C4 104F - Reserved 0x01C4 1050 MERRCR0 Module Error Clear 0 (mod 0 - 31) Register 0x01C4 1054 MERRCR1 Module Error Clear 1 (mod 32 - 63) Register 0x01C4 1058 - 0x01C4 105F 0x01C4 1060 0x01C4 1064 - 0x01C4 1067 0x01C4 1068 0x01C4 106C - 0x01C4 106F 0x01C4 1070 0x01C4 1074 - 0x01C4 1077 0x01C4 1078 100 - Reserved PERRPR - Power Error Pending Register Reserved PERRCR - Power Error Clear Register Reserved EPCPR - External Power Error Pending Register Reserved EPCCR External Power Control Clear Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-6. PSC Register Memory Map (continued) HEX ADDRESS RANGE 0x01C4 107C - 0x01C4 111F 0x01C4 1120 0x01C4 1124 - 0x01C4 1127 0x01C4 1128 0x01C4 112C - 0x01C4 11FF REGISTER ACRONYM - DESCRIPTION Reserved PTCMD - Power Domain Transition Command Register Reserved PTSTAT - Power Domain Transition Status Register Reserved 0x01C4 1200 PDSTAT0 Power Domain Status 0 Register (Always On) 0x01C4 1204 PDSTAT1 Power Domain Status 1 Register (DSP) 0x01C4 1208 - 0x01C4 12FF - Reserved 0x01C4 1300 PDCTL0 Power Domain Control 0 Register (Always On) 0x01C4 1304 PDCTL1 Power Domain Control 1 Register (DSP) 0x01C4 1308 - 0x01C4 17FF - Reserved 0x01C4 1800 MDSTAT0 Module Status 0 Register (VPSS DMA) 0x01C4 1804 MDSTAT1 Module Status 1 Register (VPSS MMR) 0x01C4 1808 MDSTAT2 Module Status 2 Register (EDMA3CC) 0x01C4 180C MDSTAT3 Module Status 3 Register (EDMA3TC0) 0x01C4 1810 MDSTAT4 Module Status 4 Register (EDMA3TC1) 0x01C4 1814 MDSTAT5 Module Status 5 Register (EMAC) 0x01C4 1818 MDSTAT6 Module Status 6 Register (EMAC Memory Controller) 0x01C4 181C MDSTAT7 Module Status 7 Register (MDIO) 0x01C4 1820 Reserved 0x01C4 1824 MDSTAT9 Module Status 9 Register (USB) 0x01C4 1828 MDSTAT10 Module Status 10 Register (ATA/CF) 0x01C4 182C MDSTAT11 Module Status 11 Register (VLYNQ) 0x01C4 1830 MDSTAT12 Module Status 12 Register (HPI) 0x01C4 1834 MDSTAT13 Module Status 13 Register (DDR2) 0x01C4 1838 MDSTAT14 Module Status 14 Register (EMIFA) 0x01C4 183C MDSTAT15 Module Status 15 Register (MMC/SD/SDIO) 0x01C4 1840 MDSTAT16 Module Status 16 Register (Memory Stick/Memory Stick PRO) 0x01C4 1844 MDSTAT17 Module Status 17 Register (ASP) 0x01C4 1848 MDSTAT18 Module Status 18 Register (I2C) 0x01C4 184C MDSTAT19 Module Status 19 Register (UART0) 0x01C4 1850 MDSTAT20 Module Status 20 Register (UART1) 0x01C4 1854 MDSTAT21 Module Status 21 Register (UART2) 0x01C4 1858 MDSTAT22 Module Status 22 Register (SPI) 0x01C4 185C MDSTAT23 Module Status 23 Register (PWM0) 0x01C4 1860 MDSTAT24 Module Status 24 Register (PWM1) 0x01C4 1864 MDSTAT25 Module Status 25 Register (PWM2) 0x01C4 1868 MDSTAT26 Module Status 26 Register (GPIO) 0x01C4 186C MDSTAT27 Module Status 27 Register (TIMER0) 0x01C4 1870 MDSTAT28 Module Status 28 Register (TIMER1) 0x01C4 1874 - 0x01C4 189B - Reserved 0x01C4 189C MDSTAT39 Module Status 39 Register (C64x+ CPU) 0x01C4 18A0 MDSTAT40 Module Status 40 Register (VICP) 0x01C4 18A4 - 0x01C4 19FF - Reserved 0x01C4 1A00 MDCTL0 Module Control 0 Register (VPSS DMA) 0x01C4 1A04 MDCTL1 Module Control 1 Register (VPSS MMR) 0x01C4 1A08 MDCTL2 Module Control 2 Register (EDMA3CC) Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 101 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-6. PSC Register Memory Map (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 1A0C M DCTL3 Module Control 3 Register (EDMA3TC0) 0x01C4 1A10 MDCTL4 Module Control 4 Register (EDMA3TC1) 0x01C4 1A14 MDCTL5 Module Control 5 Register (EMAC) 0x01C4 1A18 MDCTL6 Module Control 6 Register (EMAC Memory Controller) 0x01C4 1A1C MDCTL7 Module Control 7 Register (MDIO) 0x01C4 1A20 Reserved 0x01C4 1A24 MDCTL9 Module Control 9 Register (USB) 0x01C4 1A28 MDCTL10 Module Control 10 Register (ATA/CF) 0x01C4 1A2C MDCTL11 Module Control 11 Register (VLYNQ) 0x01C4 1A30 MDCTL12 Module Control 12 Register (HPI) 0x01C4 1A34 MDCTL13 Module Control 13 Register (DDR2) 0x01C4 1A38 MDCTL14 Module Control 14 Register (EMIFA) 0x01C4 1A3C MDCTL15 Module Control 15 Register (MMC/SD/SDIO) 0x01C4 1A40 MDCTL16 Module Control 16 Register (Memory Stick/Memory Stick PRO) 0x01C4 1A44 MDCTL17 Module Control 17 Register (ASP) 0x01C4 1A48 MDCTL18 Module Control 18 Register (I2C) 0x01C4 1A4C MDCTL19 Module Control 19 Register (UART0) 0x01C4 1A50 MDCTL20 Module Control 20 Register (UART1) 0x01C4 1A54 MDCTL21 Module Control 21 Register (UART2) 0x01C4 1A58 MDCTL22 Module Control 22 Register (SPI) 0x01C4 1A5C MDCTL23 Module Control 23 Register (PWM0) 0x01C4 1A60 MDCTL24 Module Control 24 Register (PWM1) 0x01C4 1A64 MDCTL25 Module Control 25 Register (PWM2) 0x01C4 1A68 MDCTL26 Module Control 26 Register (GPIO) 0x01C4 1A6C MDCTL27 Module Control 27 Register (TIMER0) 0x01C4 1A70 MDCTL28 Module Control 28 Register (TIMER1) 0x01C4 1A74 - 0x01C4 1A9B - Reserved 0x01C4 1A9C MDCTL39 Module Control 39 Register (C64x+ CPU) 0x01C4 1AA0 MDCTL40 Module Control 40 Register (VICP) 0x01C4 1AA4 - 0x01C4 1FFF 102 - Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.4 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Reset DM6441 supports various types of resets. Power-on-reset (POR), warm reset, max reset, system reset, C64x+ local reset, and module reset are summarized in Table 6-7. Table 6-7. DM6441 Resets Type Initiator Description Power-on-reset (POR) RESET pin active low while TRST is low. Global chip reset (Cold reset). Activates the POR signal on chip, which is used to reset test and emulation logic. Warm reset RESET pin active low while TRST is high. Resets everything except for test and emulation logic. ARM emulator stays alive during warm reset, but the C64x+ emulator does not. Maximum reset Emulator, WD Timer Same as Warm reset, except for initiators. System reset Emulator A system reset maintains memory contents and does not reset the test and emulation circuitry. The device boot and configuration pin are also not re-latched. C64x+ Local reset Software (register bit) MMR controls the C64x+ reset input. This is used for control of C64x+ reset by the ARM. The C64x+ Slave DMA port is still alive when in local reset. Power-on-reset (POR) is the global chip reset and it affects test, emulation, and other circuitry. It is invoked by driving the RESET pin active low while TRST is held low. A POR is required to place DM6441 into a known good initial state. POR can be asserted prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be asserted (held low) during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions and if an external 27 MHz oscillator is used on the MXI/CLKIN pin, the external clock should also be running at the correct frequency. Warm reset is activated by driving the RESET pin active low, while TRST is inactive high. This does not reset test or ARM emulation logic. An ARM emulator session will stay alive during warm reset, but a C64x+ emulator session will not. Maximum reset is initiated by the emulator or the watchdog timer and the reset effects are the same as a warm reset. The emulator initiates a maximum reset via the ICEPICK module. When the watchdog timer counter reaches zero, this will initiate a maximum reset to recover from a runaway condition. Both of the maximum reset initiators can be masked by the ARM emulator. System reset is initiated by the emulator and is a soft reset. Memory contents are maintained. Test, emulation, clock, and power control logic are unaffected. The emulator initiates a system reset via the C64x+ emulation logic, or through ICECRUSHER. Both of these reset initiators are non-maskable resets. The C64x+ DSP has an internal reset input that allows a host to control it. This reset is configured through a MMR bit (MDCTL[39].LRSTz) in the PSC module. When in C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be accessible, including access to the VICP memory through the L2 port (UMAP port). For details on reset control/status registers, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14) For information on peripheral selection at the rising edge of RESET, see Section 3, Device Configurations, of this data manual. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 103 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.4.1 www.ti.com Reset Electrical Data/Timing Table 6-8. Timing Requirements for Reset (see Figure 6-9) 1.05 V and 1.2 V NO. MIN MAX UNIT 1 tw(RST) Width of the RESET pulse 444 ns 2 tsu(BOOT) Setup time, boot configuration bits valid before RESET high 444 ns 3 th(BOOT) Hold time, boot configuration bits valid after RESET high 444 ns Table 6-9. Switching Characteristics Over Recommended Operating Conditions During Reset (1) (see Figure 6-9) 1.05 V and 1.2 V NO. MIN MAX UNIT 26 td(PLL_LOCK) Delay time, PLL1 lock time 2000P ns 4 td(RSTL-DDRZZ) Delay time, RESET low to DDR2 Z Group high impedance 0 2P + 20 ns 5 td(RSTL-DDRLL) Delay time, RESET low to DDR2 Low Group low 0 20 ns 6 td(RSTL-DDRHH) Delay time, RESET low to DDR2 High Group high 0 20 ns 16 td(RSTL-DDRZHZ) Delay time, RESET low to DDR2 Z/High Group high impedance 0 5P + 20 ns 17 td(RSTL-DDRLHL) Delay time, RESET low to DDR2 Low/High Group low 0 20 ns 7 td(RSTL-ZZ) Delay time, RESET low to Z Group high impedance 0 20 ns 8 td(RSTL-LOWL) Delay time, RESET low to Low Group low 0 20 ns 9 td(RSTL-HIGHH) Delay time, RESET low to High Group high 0 20 ns 18 td(RSTL-HIGHLOWH) Delay time, RESET low to High/Low Group high 0 20 ns 19 td(RSTL-LOWHIGHL) Delay time, RESET low to Low/High Group low 0 20 ns 24 td(RSTL-ZIZ) Delay time, RESET low to Z/Invalid Group high impedance 0 20 ns ns 10 td(RSTH-DDRZV) Delay time, RESET high to DDR2 Z Group valid (2) 11 td(RSTH-DDRLV) Delay time, RESET high to DDR2 Low Group valid (2) ns 12 td(RSTH-DDRHV) Delay time, RESET high to DDR2 High Group valid (2) ns 20 td(RSTH-DDRZHV) Delay time, RESET high to DDR2 Z/High Group valid high 4000P ns 21 td(RSTH-DDRLHV) Delay time, RESET high to DDR2 Low/High Group valid high 4000P ns 13 td(RSTH-ZV) Delay time, RESET high to Z Group valid (2) ns ns 14 td(RSTH-LOWV) Delay time, RESET high to Low Group valid (2) 15 td(RSTH-HIGHV) Delay time, RESET high to High Group valid (2) ns 22 td(RSTH-HIGHLOWV) Delay time, RESET high to High/Low Group valid low 5100P ns 23 td(RSTH-LOWHIGHV) Delay time, RESET high to Low/High Group valid high 5100P ns td(RSTH-ZIIV) Delay time, RESET high to Z/Invalid Group invalid 4000P ns 25 (1) (2) 104 P = MXI/CLKIN cycle time, in ns. Following RESET high, this signal group maintains the state the pins(s) achieved while RESET was driven low until the peripheral is enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low and remains in the high-impedance state following RESET high until the DDR2 controller is enabled via the PSC. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 1 RESET 2 3 Boot Configuration Pins 4 10 5 11 6 12 16 20 17 21 7 13 8 14 9 15 18 22 19 23 24 25 (A) DDR2 Z Group (A) DDR2 Low Group (A) DDR2 High Group (A) DDR2 Z/High Group (A) DDR2 Low/High Group (A) Z Group (A) Low Group (A) High Group (A) High/Low Group (A) Low/High Group (A) Z/Invalid Group A. DDR2 Z Group: DDR_DQS[3:0], DDR_D[12:0] DDR2 Low Group: DDR_CLK0, DDR_CKE, DDR_A[12:0] DDR2 High Group: DDR_CLK0, DDR_CS, DDR_WE, DDR_RAS, DDR_CAS DDR2 Z/High Group: DDR_DQM[3:0] DDR2 Low/High Group: DDR_BS[2:0] Low Group: DMARQ/UART_RXD1, VCLK, RTCK, TDO, VPBECLK, YOUT0/G5/AEAW0, YOUT1/G6/AEAW1, YOUT2/G7/AEAW2, YOUT3/R3/AEAW3, YOUT4/R4/AEAW4, COUT3/B6/DSP_BT, COUT2/B5/EM_WIDTH, COUT1/B4/BTSEL1, COUT0/B3/BTSEL0, TRST High Group: DMACK/UART_TXD1, EM_A[2]/(CLE), EM_A[1]/(ALE), EM_CS3, EM_WE/(WE)/(IOWR)/DIOW Z Group: All other pins not listed above, with the exception of power and ground pins. • The following Z Group pins have an internal pullup (IPU): DMARQ/UART_RXD1, VPBECLK, HSYNC, VSYNC, TRST, YI/CCD[7:0], CI[3:0]/CCD[11:8], CI4/CCD12/UART_RTS2, CI5/CCD13/UART_CTS2, CI6/CCD14/UART_TXD2, CI7/CCD15/UART_RXD2 • The following Z Group pins have an internal pulldown (IPD): EM_WAIT/IORDY, TCK, TDI, TMS, EMU[1:0] High/Low Group: EM_BA[0]/DA0, EM_CS2, EM_OE/(RE)/(IORD)/DIOR Low/High Group: EM_R/W/INTRQ Z/Invalid Group: EM_D[15:0] Figure 6-9. Reset Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 105 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.5 www.ti.com External Clock Input From MXI/CLKIN Pin The DM6441 device has two input pins for an external clock source, MXI/CLKIN and M24XI. The MXI/CLKIN pin provides the clock source for PLL1 and PLL2 whose optimal frequency is 27 MHz. The M24XI pin provides the clock source for the USB PLL whose optimal frequency is 24 MHz. The DM6441 device includes two options to provide an external clock input: 1. Use an on-chip oscillator with external crystal or ceramic resonator circuit (only supporting parallel-resonant mode; it does not provide overtone support). For more details, see Section 6.5.1, Clock Input Option 1 – Crystal. 2. Use an external 1.8-V LVCMOS-compatible clock input. For more details, see Section 6.5.2, Clock Input Option 2 – 1.8-V LVCMOS-Compatible Clock Input. 6.5.1 Clock Input Option 1 – Crystal 6.5.1.1 27-MHz crystal for System Oscillator In this option, a crystal is used as the external clock input to the DM6441 PLL1 and PLL2. The 27-MHz oscillator provides the reference clock for all DM6441 subsystems and peripherals. The on-chip oscillator requires an external 27-MHz crystal connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 6-10. The external crystal load capacitors must be connected only to the 27-MHz oscillator ground pin (MXVSS). Do not connect to board ground (VSS). The MXVDD pin can be connected to the same 1.8 V power supply as DVDD18. MXI/CLKIN MXO MXVDD MXVSS RBIAS (optional) Crystal 27 MHz C1 C2 1.8 V Figure 6-10. 27-MHz System Oscillator The RBIAS resistor is optional. If the RBIAS resistor is used, it should equal 1 MΩ ± 5%. The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (MXI and MXO) and to the MXVSS pin. CL + 106 C 1C 2 (C1 ) C2) Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-10. Crystal Requirements for a 27-MHz System Oscillator PARAMETER MIN TYP Start-up time (from power up until oscillating at stable frequency of 27 MHz) UNIT 4 Oscillation frequency 27 ESR Frequency stability 6.5.1.2 MAX ms MHz 60 Ω ±50 ppm 24-MHz Crystal for USB Oscillator In this option, a crystal is used as the external clock input to the DM6441 USB PLL. The 24-MHz oscillator provides the reference clock for the DM6441 USB peripheral. The on-chip oscillator requires an external 24-MHz crystal connected across the M24XI and M24XO pins, along with two load capacitors, as shown in Figure 6-11.The external crystal load capacitors must be connected only to the 24-MHz oscillator ground pin (M24VSS). Do not connect to board ground (VSS). M24XI M24XO M24VSS M24VDD RBIAS (optional) Crystal 24 MHz C1 C2 1.8 V Figure 6-11. 24-MHz USB Oscillator The RBIAS resistor is optional. If the RBIAS resistor is used, it should equal 1 MΩ ± 5%. The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (M24XI and M24XO) and to the M24XVSS pin. CL + C 1C 2 (C1 ) C2) Table 6-11. Crystal Requirements for a 24-MHz USB Oscillator PARAMETER MIN TYP Start-up time (from power up until oscillating at stable frequency of 24 MHz) Oscillation frequency MAX 24 ESR Frequency stability UNIT 4 ms MHz 60 Ω ±50 ppm Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 107 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.5.2 www.ti.com Clock Input Option 2 – 1.8-V LVCMOS-Compatible Clock Input In this option, a 1.8-V LVCMOS-compatible clock input is used as the external clock input to the DM6441 device. The external connections are shown in Figure 6-12. The MXI/CLKIN pin is connected to the 1.8-V LVCMOS-compatible clock source. The MXO pin is left unconnected. The MXVSS pin is connected to board ground (VSS). The MXVDD pin can be connected to the same 1.8-V power supply as DVDD18. The clock source must meet the MXI/CLKIN timing requirements shown in Table 6-16, Timing Requirements for MXI/CLKIN. MXI/CLKIN MXO MXVSS MXVDD NC 1.8 V Figure 6-12. 1.8-V LVCMOS-Compatible Clock Input Figure 6-12 also applies to the USB external clock input. When a 1.8-V LVCMOS-compatible clock input is used as the external clock input, the M24XI pin is connected to the 1.8-V LVCMOS-compatible clock source. The M24XO pin is left unconnected. The M24VSS pin is connected to board ground (VSS). The M24VDD pin can be connected to the same 1.8-V power supply as DVDDR2. The clock source must meet the MXI/CLKIN timing requirements shown in Table 6-17, Timing Requirements for M24XI Devices. 108 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.6 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Clock PLLs There are two independently controlled PLLs on DM6441. PLL1 generates the frequencies required for the DSP, ARM, VICP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the DDR2 interface and the VPBE in certain modes. The recommended reference clock for both PLLs is the 27-MHz crystal input. The USB2.0 PHY contains a third PLL embedded within it and the 24-MHz oscillator is its reference clock source. This particular PLL is only usable for USB operation, and is discussed further in the TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number SPRUE35). See also the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19). A summary of the PLL controller registers is shown in Table 6-12. For more details, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Table 6-12. PLL and Reset Controller Registers Memory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION PLL1 Controller Registers 0x01C4 0800 PID Peripheral Identification and Revision Information Register 0x01C4 08E4 RSTYPE Reset Type Register 0x01C4 0900 PLLCTL PLL Controller 1 Operations Control Register 0x01C4 0910 PLLM 0x01C4 0918 PLLDIV1 PLL Controller 1 Control-Divider 1 Register (SYSCLK1) 0x01C4 091C PLLDIV2 PLL Controller 1 Control-Divider 2 Register (SYSCLK2) 0x01C4 0920 PLLDIV3 PLL Controller 1 Control-Divider 3 Register (SYSCLK3) 0x01C4 0928 POSTDIV PLL Controller 1 Post-Divider Control Register PLL Controller 1 Multiplier Control Register 0x01C4 092C BPDIV 0x01C4 0938 PLLCMD PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP) PLL Controller 1 Command Register 0x01C4 093C PLLSTAT PLL Controller 1 Status Register (Shows PLLCTRL Status) 0x01C4 0940 ALNCTL PLL Controller 1 Alignment Control Register (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) 0x01C4 0944 DCHANGE PLL Controller 1 Divider Change Register (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0948 CKEN 0x01C4 094C CKSTAT PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx) SYSTAT PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off Status) 0x01C4 0960 PLLDIV4 PLL Controller 1 Control-Divider 4 Register (SYSCLK4) 0x01C4 0964 PLLDIV5 PLL Controller 1 Control-Divider 5 Register (SYSCLK5) 0x01C4 0C00 PID 0x01C4 0D00 PLLCTL 0x01C4 0D10 PLLM 0x01C4 0D18 PLLDIV1 PLL Controller 2 Control-Divider 1 Register (SYSCLK1) 0x01C4 0950 PLL Controller 1 Clock Enable Register Peripheral Identification and Revision Information Register PLL Controller 2 Operations Control Register PLL Controller 2 Multiplier Control Register 0x01C4 0D1C PLLDIV2 PLL Controller 2 Control-Divider 2 Register (SYSCLK2) 0x01C4 0D20 - 0x01C4 0D2B POSTDIV PLL Controller 2 Post-Divider Control Register 0x01C4 0D2C BPDIV PLL Controller 2 Bypass Control-Divider Register (SYSCLKBP) 0x01C4 0D38 PLLCMD PLL Controller 2 Command Register 0x01C4 0D3C PLLSTAT PLL Controller 2 Status Register (Shows PLLCTRL Status) 0x01C4 0D40 ALNCTL PLL Controller 2 Alignment Control Register (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) 0x01C4 0D44 DCHANGE 0x01C4 0D48 CKEN 0x01C4 0D4C CKSTAT PLL Controller 2 Divider Change Register (Indicates if SYSCLK Divide Ratio has Been Modified) PLL Controller 2 Clock Enable Register PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx) Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 109 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-12. PLL and Reset Controller Registers Memory Map (continued) HEX ADDRESS RANGE REGISTER ACRONYM 0x01C4 0D50 SYSTAT 6.6.1 DESCRIPTION PLL Controller 2 System Clock Status 1 Register (Indicates SYSCLK on/off Status) PLL1 and PLL2 Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLLVDD18). It is recommended that an external EMI filter circuit be added to PLLVDD18, as shown in Figure 6-13. The 1.8-V supply of the EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O power-supply pins (DVDD). TI recommends EMI filter manufacturer Murata, part number NFM18CC222R1C3. All PLL external components (C1, C2, and the EMI Filter) should be placed as close to the device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown in Figure 6-13. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). DM644x PLL1 PLLVDD18 +1.8 V EMI Filter C1 C2 0.1 µF 0.01 µF PLL2 Figure 6-13. PLL1 and PLL2 External Connection The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks). There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios might not be supported). 110 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-13. PLLC1 Clock Frequency Ranges CLOCK SIGNAL NAME MIN MAX UNIT 20 30 MHz At 1.05-V CVDD 400 405 MHz At 1.2-V CVDD 400 513 MHz At 1.05-V CVDD 405 MHz At 1.2-V CVDD 513 MHz MIN MAX UNIT 20 30 MHz At 1.05-V CVDD 400 600 MHz At 1.2-V CVDD 400 900 MHz MXI/CLKIN (1) PLLOUT SYSCLK1 (CLKDIV1 Domain) (1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2). Table 6-14. PLLC2 Clock Frequency Ranges CLOCK SIGNAL NAME MXI/CLKIN (1) PLLOUT (1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2). Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed. The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0 transition). The PLL should not be operated until this stabilization time has expired. This stabilization step must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-15. The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0) before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-15. The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the PLL lock time value, see Table 6-15. Table 6-15. PLL1 and PLL2 Stabilization, Lock, and Reset Times PLL STABILIZATION/LOCK/RESET TIME PLL Stabilization Time MIN TYP 150 (1) 128C (1) UNIT ms 2000C (1) PLL Lock Time PLL Reset Time MAX ns ns C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns. For details on the PLL initialization software sequence, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). 6.6.2 Clock PLL Considerations with External Clock Sources If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power both the DM6441 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks). Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature and Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks). Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 111 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.6.3 www.ti.com Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 6-16. Timing Requirements for MXI/CLKIN Devices (1) (2) (3) (4) 1.05 V and 1.2 V NO. (1) (see Figure 6-14) MIN MAX UNIT 1 tc(MXI) Cycle time, MXI/CLKIN 33.3 50 ns 2 tw(MXIH) Pulse duration, MXI/CLKIN high 0.45C 0.55C ns 3 tw(MXIL) Pulse duration, MXI/CLKIN low 0.45C 0.55C ns 4 tt(MXI) Transition time, MXI/CLKIN 0.05C ns 5 tJ(MXI) Period jitter, MXI/CLKIN 0.02C ns Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-23 and Figure 6-24 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors, see the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14). C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns. (2) (3) (4) 1 5 4 2 MXI/CLKIN 3 4 Figure 6-14. MXI/CLKIN Timing Table 6-17. Timing Requirements for M24XI Devices (1) (2) (3) (see Figure 6-15) 1.05 V and 1.2 V NO. MIN TYP MAX 1 tc(M24XI) Cycle time, M24XI 2 tw(M24XIH) Pulse duration, M24XI high 0.45C 0.55C ns 3 tw(M24XIL) Pulse duration, M24XI low 0.45C 0.55C ns 4 tt(M24XI) Transition time, M24XI 0.05C ns 5 tJ(M24XI) Period jitter, M24XI 0.02C ns (1) (2) (3) 41.6 UNIT ns The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL, see the TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number SPRUE35). C = M24XI cycle time in ns. For example, when M24XI frequency is 24 MHz, use C = 41.6 ns. 1 5 4 2 MXI/CLKIN 3 4 Figure 6-15. M24XI Timing 112 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-18. Switching Characteristics Over Recommended Operating Conditions for CLK_OUT0 (1) (see Figure 6-16) NO. (1) (2) 1.05 V and 1.2 V PARAMETER MIN MAX (2) UNIT 1 tC Cycle time, CLK_OUT0 37.037 74.074 ns 2 tw(CLKOUT0H) Pulse duration, CLK_OUT0 high 0.45P 0.55P ns 3 tw(CLKOUT0L) Pulse duration, CLK_OUT0 low 0.45P 0.55P ns 4 tt(CLKOUT0) Transition time, CLK_OUT0 0.05P ns 5 td(CLKINH-CLKO0H) Delay time, CLKIN/MXI high to CLK_OUT0 high (divide-by-1 only) 1 8 ns 6 td(CLKINL-CLKO0L) Delay time, CLKIN/MXI low to CLK_OUT0 low (divide-by-1 only) 1 8 ns 7 td(CLKINH-CLKO0L) Delay time, CLKIN/MXI high to CLK_OUT0 low (divide-by-2 only) 1 8 ns 8 td(CLKINH-CLKO0H) Delay time, CLKIN/MXI high to CLK_OUT0 high (divide-by-2 only) 1 8 ns The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. P = 1/CLK_OUT0 clock frequency in nanoseconds (ns). For example, when CLK_OUT0 frequency is 27 MHz, use P = 37.04 ns. 5 6 8 7 CLKIN/MXI 2 4 1 CLKOUT0 (Divide-by-1) 3 4 CLKOUT0 (Divide-by-2) Figure 6-16. CLK_OUT0 Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 113 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-19. Switching Characteristics Over Recommended Operating Conditions for CLK_OUT1 (1) (see Figure 6-17) NO. 1.05 V and 1.2 V PARAMETER MIN MAX (2) UNIT 1 tC Cycle time, CLK_OUT1 41.667 83.33 ns 2 tw(CLKOUT1H) Pulse duration, CLK_OUT1 high 0.45P 0.55P ns 3 tw(CLKOUT1L) Pulse duration, CLK_OUT1 low 0.45P 0.55P ns 4 tt(CLKOUT1) Transition time, CLK_OUT1 0.05P ns 5 td(CLKINH-CLKO1H) Delay time, CLKIN/MXI high to CLK_OUT1 high (divide-by-1 only) 1 8 ns 6 td(CLKINL-CLKO1L) Delay time, CLKIN/MXI low to CLK_OUT1 low (divide-by-1 only) 1 8 ns 7 td(CLKINH-CLKO1L) Delay time, CLKIN/MXI high to CLK_OUT1 low (divide-by-2 only) 1 8 ns 8 td(CLKINH-CLKO1H) Delay time, CLKIN/MXI high to CLKOUT1 high (divide-by-2 only) 1 8 ns (1) (2) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. P = 1/CLK_OUT1 clock frequency in nanoseconds (ns). For example, when CLK_OUT1 frequency is 24 MHz, use P = 41.6 ns. 5 6 8 7 CLKIN/MXI 2 4 1 CLK_OUT1 (Divide-by-1) 3 4 CLK_OUT1 (Divide-by-2) Figure 6-17. CLK_OUT1 Timing 114 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.7 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Interrupts The DM6441 device has a large number of interrupts to service the needs of its many peripherals and subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt controller. The interrupts can be selectively enabled or disabled in either of the controllers. In typical applications, the ARM handles most of the peripheral interrupts and grants control, to the C64x+, of interrupts that are relevant to DSP algorithms. Also, the ARM and DSP can communicate with each other through interrupts. 6.7.1 ARM CPU Interrupts The ARM9 CPU core supports two direct interrupts: FIQ and IRQ. The DM6441 ARM interrupt controller prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed in Table 6-20, and interrupts the ARM CPU. Each interrupt is programmable for up to eight levels of priority. There are six levels for IRQ and two levels for FIQ. Interrupts at the same priority level are serviced in order by the ARM Interrupt Number, with the lowest number having the highest priority. Table 6-21 shows the ARM interrupt controller registers and memory locations. For more details on ARM interrupt control, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 115 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-20. DM6441 ARM Interrupts ARM INTERRUPT NUMBER SOURCE ARM INTERRUPT NUMBER ACRONYM SOURCE 0 VDINT0 VPSS CCDC 0 32 TINT0 Timer 0 – TINT12 1 VDINT1 VPSS CCDC 1 33 TINT1 Timer 0 – TINT34 2 VDINT2 VPSS CCDC 2 34 TINT2 Timer 1 – TINT12 3 HISTINT VPSS Histogram 35 TINT3 Timer 1 – TINT34 4 H3AINT VPSS AE/AWB/AF 36 PWMINT0 PWM 0 5 PRVUINT VPSS Previewer 37 PWMINT1 PWM 1 6 RSZINT VPSS Resizer 38 PWMINT2 PWM 2 7 VFOVINT VPSS VPFE 39 I2CINT I2C 7 - Reserved 39 I2CINT I2C 8 VENCINT VPSS VPBE 40 UARTINT0 UART 0 9 ASQINT VICP Sqr (ARM int) 41 UARTINT1 UART 1 10 IMXINT VICP IMX 42 UARTINT2 UART 2 11 VLCDINT VICP VLCD 43 SPINT0 SPI 12 USBINT USB 44 SPINT1 SPI 13 EMACINT EMAC Memory Controller 45 - Reserved 14 - Reserved 46 DSP2ARM0 DSP Controller to ARM 0 15 - Reserved 47 DSP2ARM1 DSP Controller to ARM 1 16 EDMA3CC_INT0 EDMA3 CC Region 0 48 GPIO0 GPIO 0 17 EDMA3CC_ERRINT EDMA3 CC Error 49 GPIO1 GPIO 1 18 EDMA3TC_ERRINT0 EDMA3 TC 0 Error 50 GPIO2 GPIO 2 19 EDMA3TC_ERRINT1 EDMA3 TC 1 Error 51 GPIO3 GPIO 3 20 PSCINT PSC ALLINT 52 GPIO4 GPIO 4 21 - Reserved 53 GPIO5 GPIO 5 22 IDEINT ATA / IDE 54 GPIO6 GPIO 6 23 HPINT HPI 55 GPIO7 GPIO 7 24 ASPXINT ASP Transmit 56 GPIOBNK0 GPIO Bank 0 25 ASPRINT ASP Receive 57 GPIOBNK1 GPIO Bank 1 26 MMCINT MMC 58 GPIOBNK2 GPIO Bank 2 27 SDIOINT SD 59 GPIOBNK3 GPIO Bank 3 MSINT Memory Stick/Memory Stick PRO 60 GPIOBNK4 GPIO Bank 4 29 DDRINT DDR2 Memory Controller 61 COMMTX ARMSS 30 EMIFAINT EMIFA 62 COMMRX ARMSS 31 VLQINT VLYNQ 63 EMUINT E2ICE 28 116 ACRONYM Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-21. ARM Interrupt Controller Registers HEX ADDRESS 0x01C4 8000 ACRONYM REGISTER DESCRIPTION FIQ0 FIQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to FIQ)] 0x01C4 8004 FIQ1 FIQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to FIQ)] 0x01C4 8008 IRQ0 IRQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to IRQ)] 0x01C4 800C IRQ1 IRQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to IRQ)] 0x01C4 8010 FIQENTRY Entry Address [28:0] for Valid FIQ Interrupt 0x01C4 8014 IRQENTRY Entry Address [28:0] for Valid IRQ Interrupt 0x01C4 8018 EINT0 Interrupt Enable Register 0 0x01C4 801C EINT1 Interrupt Enable Register 1 0x01C4 8020 INCTL Interrupt Operation Control Register 0x01C4 8024 EABASE 0x01C4 8028 - 0x01C4 802F - Interrupt Entry Table Base Address Register Reserved 0x01C4 8030 INTPRI0 Interrupt 0-7 Priority Select 0x01C4 8034 INTPRI1 Interrupt 8-15 Priority Select 0x01C4 8038 INTPRI2 Interrupt 16-23 Priority Select 0x01C4 803C INTPRI3 Interrupt 24-31 Priority Select 0x01C4 8040 INTPRI4 Interrupt 32-39 Priority Select 0x01C4 8044 INTPRI5 Interrupt 40-47 Priority Select 0x01C4 8048 INTPRI6 Interrupt 48-55 Priority Select 0x01C4 804C INTPRI7 Interrupt 56-63 Priority Select 0x01C4 8050 - 0x01C4 83FF - Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 117 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.7.2 www.ti.com DSP Interrupts The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-22. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-23 summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP interrupt control, see the TMS320DM644x DMSoC DSP Subsystem Reference Guide (literature number SPRUE15). Table 6-22. DM6441 DSP Interrupts DSP INTERRUPT NUMBER ACRONYM DSP INTERRUPT NUMBER ACRONYM SOURCE 0 EVT0 C64x+ Int Ctl 0 64 Reserved 1 EVT1 C64x+ Int Ctl 1 65 Reserved 2 EVT2 C64x+ Int Ctl 2 66 Reserved 3 EVT3 C64x+ Int Ctl 3 67 Reserved 4 TINT0 Timer 0 – TINT12 68 Reserved 5 TINT1 Timer 0 – TINT34 69 Reserved 6 TINT2 Timer 1 – TINT12 70 Reserved 7 TINT3 Timer 1 – TINT34 71 Reserved Reserved 72 Reserved C64x+ EMC 73 Reserved 8 9 EMU_DTDMA 10 Reserved 74 Reserved 11 EMU_RTDXRX C64x+ RTDX 75 Reserved 12 EMU_RTDXTX C64x+ RTDX 76 Reserved 13 IDMAINT0 C64x+ EMC 0 77 Reserved 14 IDMAINT1 C64x+ EMC 1 78 Reserved Reserved 79 Reserved 15 16 ARM2DSP0 ARM to DSP Controller 0 80 Reserved 17 ARM2DSP1 ARM to DSP Controller 1 81 Reserved 18 ARM2DSP2 ARM to DSP Controller 2 82 Reserved 19 ARM2DSP3 ARM to DSP Controller 3 83 Reserved 20 Reserved 84 Reserved 21 Reserved 85 Reserved 22 Reserved 86 Reserved 23 Reserved 87 Reserved 24 Reserved 88 Reserved 25 Reserved 89 Reserved 26 Reserved 90 Reserved 27 Reserved 91 Reserved 28 Reserved 92 Reserved 29 Reserved 93 Reserved 30 Reserved 94 Reserved 31 Reserved 95 Reserved 32 34 97 Reserved 35 36 96 Reserved 33 118 SOURCE EDMA3CC_INT1 Reserved INTERR C64x+ interrupt controller Dropped CPU Interrupt Event EMC_IDMAERR C64x+ EMC Invalid IDMA Parameters 98 Reserved Reserved 99 Reserved EDMA3CC Interrupt Region 1 100 Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-22. DM6441 DSP Interrupts (continued) DSP INTERRUPT NUMBER ACRONYM SOURCE DSP INTERRUPT NUMBER ACRONYM SOURCE 37 EDMA3CC_ERRINT EDMA3 CC Error 101 Reserved 38 EDMA3TC_ERRINT0 EDMA3 TC0 Error 102 Reserved 39 EDMA3TC_ERRINT1 EDMA3 TC1 Error 103 Reserved 40 PSCINT PSC ALLINT 104 Reserved 41 Reserved 105 Reserved 42 Reserved 106 Reserved 43 Reserved 107 Reserved 44 Reserved 108 Reserved 45 Reserved 109 Reserved 46 Reserved 110 Reserved 47 Reserved 111 48 ASPXINT ASP Transmit 112 49 ASPRINT Reserved PMC_ED C64x+ PMC ASP Receive 113 Reserved 50 Reserved 114 Reserved 51 Reserved 115 52 Reserved 116 UMCED1 C64x+ UMC 1 53 Reserved 117 UMCED2 C64x+ UMC 2 54 Reserved 118 PDCERR C64x+ PDC 55 Reserved 119 PVCINT C64x+ PDC 56 Reserved 120 PMCCMPA C64x+ PMC 57 Reserved 121 PMCDMPA C64x+ PMC 58 Reserved 122 DMCCMPA C64x+ DMC 59 Reserved 123 DMCDMPA C64x+ DMC 60 Reserved 124 UMCCMPA C64x+ UMC 61 Reserved 125 UMCDMPA C64x+ UMC 62 Reserved 126 EMCCMPA C64x+ EMC 63 Reserved 127 EMCDMPA C64x+ EMC Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 119 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-23. C64x+ Interrupt Controller Registers 120 HEX ADDRESS ACRONYM 0x0180 0000 EVTFLAG0 Event flag register 0 REGISTER DESCRIPTION 0x0180 0004 EVTFLAG1 Event flag register 1 0x0180 0008 EVTFLAG2 Event flag register 2 0x0180 000C EVTFLAG3 Event flag register 3 0x0180 0020 EVTSET0 Event set register 0 0x0180 0024 EVTSET1 Event set register 1 0x0180 0028 EVTSET2 Event set register 2 0x0180 002C EVTSET3 Event set register 3 0x0180 0040 EVTCLR0 Event clear register 0 0x0180 0044 EVTCLR1 Event clear register 1 0x0180 0048 EVTCLR2 Event clear register 2 0x0180 004C EVTCLR3 Event clear register 3 0x0180 0080 EVTMASK0 Event mask register 0 0x0180 0084 EVTMASK1 Event mask register 1 0x0180 0088 EVTMASK2 Event mask register 2 0x0180 008C EVTMASK3 Event mask register 3 0x0180 00A0 MEVTFLAG0 Masked event flag register 0 0x0180 00A4 MEVTFLAG1 Masked event flag register 1 0x0180 00A8 MEVTFLAG2 Masked event flag register 2 0x0180 00AC MEVTFLAG3 Masked event flag register 3 0x0180 00C0 EXPMASK0 Exception mask register 0 0x0180 00C4 EXPMASK1 Exception mask register 1 0x0180 00C8 EXPMASK2 Exception mask register 2 0x0180 00CC EXPMASK3 Exception mask register 3 0x0180 00E0 MEXPFLAG0 Masked exception flag register 0 0x0180 00E4 MEXPFLAG1 Masked exception flag register 1 0x0180 00E8 MEXPFLAG2 Masked exception flag register 2 0x0180 00EC MEXPFLAG3 Masked exception flag register 3 0x0180 0104 INTMUX1 Interrupt mux register 1 0x0180 0108 INTMUX2 Interrupt mux register 2 0x0180 010C INTMUX3 Interrupt mux register 3 0x0180 0140 - 0x0180 0147 – 0x0180 0180 INTXSTAT Interrupt exception status 0x0180 0184 INTXCLR Interrupt exception clear 0x0180 0188 INTDMASK Dropped interrupt mask register 0x0180 01C0 EVTASRT Event assert register Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.7.3 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 ARM/DSP Communications Interrupts The INTGEN register is used for generating interrupts between the ARM and DSP. The INTGEN register format is shown in Figure 6-18. Table 6-24 describes the register bit fields. The ARM may generate an interrupt to the DSP by setting one of the four INTDSP[3:0] bits or the INTNMI bit. The interrupt bit automatically self clears and the corresponding DSP[3:0]STAT or NMISTAT bit is automatically set to indicate that the interrupt was generated. After servicing the interrupt, the DSP clears the status bit by writing ‘0’. The ARM may poll the status bit to determine when the DSP has completed servicing the interrupt. The DSP may generate an interrupt to the ARM in the same manner using the INTARM[1:0] bits and monitor ARM interrupt servicing via the ARM[1:0]STAT bits. Figure 6-18. INTGEN Register 31 30 29 28 RESERVED ARM1 STAT ARM0 STAT R-00 R/W-0 R/W-0 15 14 13 12 RESERVED INT ARM1 INT ARM0 R-00 R/W-0 R/W-0 27 24 23 22 21 20 RESERVED DSP3 STAT DSP2 STAT DSP1 STAT DSP0 STAT RESERVED NMI STAT R-0000 R/W-0 R/W-0 R/W-0 R/W-0 R-000 R/W-0 11 8 19 17 3 1 16 7 6 5 4 RESERVED INT DSP3 INT DSP2 INT DSP1 INT DSP0 RESERVED INT NM I 0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 R-000 R/W-0 LEGEND: R = Read, W = Write, n = value at reset Table 6-24. INTGEN Register Bit Field Descriptions Bit Field 31 - 30 RESERVED Reserved 29 ARM1STAT DSP to ARM Int1 Status/Clear (1) 28 ARM0STAT DSP to ARM Int0 Status/Clear (1) 27 - 24 RESERVED Reserved 23 DSP3STAT ARM to DSP Int3 Status/Clear (1) 22 DSP2STAT ARM to DSP Int2 Status/Clear (1) 21 DSP1STAT ARM to DSP Int1 Status/Clear (1) 20 DSP0STAT ARM to DSP Int0 Status/Clear (1) 19 - 17 RESERVED Reserved 16 NMISTAT 15 - 14 RESERVED 13 INTARM1 DSP to ARM Int1 Set (2) 12 INTARM0 DSP to ARM Int0 Set (2) 11 - 8 RESERVED 7 INTDSP3 ARM to DSP Int3 Set (2) 6 INTDSP2 ARM to DSP Int2 Set (2) 5 INTDSP1 ARM to DSP Int1 Set (2) 4 INTDSP0 ARM to DSP Int0 Set (2) 3-1 RESERVED 0 INTNMI (1) (2) Value Description DSP NMI Status/Clear (1) Reserved Reserved Reserved DSP NMI Set (2) Write '0' to clear. Writing '1' has no effect. Write '1' to generate the interrupt. The register bit automatically clears to a value of '0'. Writing a '0' has no effect. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 121 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.8 www.ti.com General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA3 events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). The DM6441 GPIO peripheral supports the following: • Up to 54 1.8v GPIO pins, GPIO[0:53] • Up to 17 3.3v GPIO pins, GPIO3V[0:16] (GPIO[54:70]) • Interrupts: – Up to eight unique GPIO[0:7] interrupts from Bank 0 – Five GPIO bank (aggregated) interrupt signals from each of the five banks of GPIOs – Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO signal • DMA events: – Up to eight unique GPIO DMA events from Bank 0 – Five GPIO bank (aggregated) DMA event signals from each of the five banks of GPIOs • Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming). • Separate Input/Output registers • Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s). • Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented. The memory map for the GPIO registers is shown in Table 6-25. For more detailed information on GPIOs, see the TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (literature number SPRUE25). 122 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.8.1 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 GPIO Peripheral Register Description(s) Table 6-25. GPIO Registers HEX ADDRESS RANGE ACRONYM 0x01C6 7000 PID 0x01C6 7004 - 0x01C6 7008 BINTEN REGISTER NAME Peripheral Identification Register Reserved GPIO interrupt per-bank enable GPIO Banks 0 and 1 0x01C6 700C - 0x01C6 7010 DIR01 Reserved 0x01C6 7014 OUT_DATA01 GPIO Banks 0 and 1 Output Data Register (GPIO[0:31]) GPIO Banks 0 and 1 Direction Register (GPIO[0:31]) 0x01C6 7018 SET_DATA01 GPIO Banks 0 and 1 Set Data Register (GPIO[0:31]) 0x01C6 701C CLR_DATA01 GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GPIO[0:31]) 0x01C6 7020 IN_DATA01 GPIO Banks 0 and 1 Input Data Register (GPIO[0:31]) 0x01C6 7024 SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GPIO[0:31]) 0x01C6 7028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GPIO[0:31]) 0x01C6 702C SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GPIO[0:31]) 0x01C6 7030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GPIO[0:31]) 0x01C6 7034 INSTAT01 GPIO Banks 0 and 1 Interrupt Status Register (GPIO[0:31]) GPIO Banks 2 and 3 0x01C6 7038 DIR23 GPIO Banks 2 and 3 Direction Register (GPIO[32:63]) 0x01C6 703C OUT_DATA23 GPIO Banks 2 and 3 Output Data Register (GPIO[32:63]) 0x01C6 7040 SET_DATA23 GPIO Banks 2 and 3 Set Data Register (GPIO[32:63]) 0x01C6 7044 CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register (GPIO[32:63]) GPIO Banks 2 and 3 Input Data Register (GPIO[32:63]) 0x01C6 7048 IN_DATA23 0x01C6 704C SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (GPIO[32:63]) 0x01C6 7050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (GPIO[32:63]) 0x01C6 7054 SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (GPIO[32:63]) 0x01C6 7058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (GPIO[32:63]) 0x01C6 705C INSTAT23 GPIO Banks 2 and 3 Interrupt Status Register (GPIO[32:63]) GPIO Bank 4 0x01C6 7060 DIR4 0x01C6 7064 OUT_DATA4 GPIO Bank 4 Direction Register (GPIO[64:70]) GPIO Bank 4 Output Data Register (GPIO[64:70]) 0x01C6 7068 SET_DATA4 GPIO Bank 4 Set Data Register (GPIO[64:70]) 0x01C6 706C CLR_DATA4 GPIO Bank 4 Clear Data Register (GPIO[64:70]) 0x01C6 7070 IN_DATA4 GPIO Bank 4 Input Data Register (GPIO[64:70]) 0x01C6 7074 SET_RIS_TRIG4 GPIO Bank 4 Set Rising Edge Interrupt Register (GPIO[64:70]) 0x01C6 7078 CLR_RIS_TRIG4 GPIO Bank 4 Clear Rising Edge Interrupt Register (GPIO[64:70]) 0x01C6 707C SET_FAL_TRIG4 GPIO Bank 4 Set Falling Edge Interrupt Register (GPIO[64:70]) 0x01C6 7080 CLR_FAL_TRIG4 GPIO Bank 4 Clear Falling Edge Interrupt Register (GPIO[64:70]) 0x01C6 7084 INSTAT4 0x01C6 7088 - 0x01C6 7FFF - GPIO Bank 4 Interrupt Status Register (GPIO[64:70]) Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 123 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.8.2 www.ti.com GPIO Peripheral Input/Output Electrical Data/Timing Table 6-26. Timing Requirements for GPIO Inputs (1) (see Figure 6-19) 1.05 V and 1.2 V NO. UNIT MIN MAX 1 2 (1) tw(GPIH) Pulse duration, GPIx high 52 ns tw(GPIL) Pulse duration, GPIx low 52 ns The pulse width given is sufficient to generate a CPU interrupt or an EDMA3 event. However, if a user wants to have DM6441 recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow DM6441 enough time to access the GPIO register through the internal bus. Table 6-27. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 6-19) NO. 3 4 (1) 1.05 V and 1.2 V PARAMETER tw(GPOH) tw(GPOL) MIN Pulse duration, GPOx high Pulse duration, GPOx low MAX UNIT 26 (1) ns (1) ns 26 This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. 2 1 GPIx 4 3 GPOx Figure 6-19. GPIO Port Timing 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing Table 6-28. Timing Requirements for External Interrupts (1) (see Figure 6-20) 1.05 V and 1.2 V NO. 1 2 (1) MIN MAX UNIT tw(ILOW) Width of the external interrupt pulse low 52 ns tw(IHIGH) Width of the external interrupt pulse high 52 ns The pulse width given is sufficient to generate an interrupt or an EDMA3 event. However, if a user wants to have DM6441recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow DM6441 enough time to access the GPIO register through the internal bus. 2 1 EXT_INTx Figure 6-20. GPIO External Interrupt Timing 124 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.9 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Enhanced Direct Memory Access (EDMA3) Controller The EDMA3 controller handles all data transfers between memories and the device slave peripherals on the DM6441 device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. These are summarized as follows: • Transfer to/from on-chip memories – Coprocessor shared memory – DSP L1D memory – DSP L2 memory – ARM program/data RAM • Transfer to/from external storage – DDR2 SDRAM – NAND flash – Asynchronous EMIF – Smart Media, SD/SDIO, Memory Stick/Memory Stick PRO, MMC, xD media storage – ATA/CF • Transfer to/from peripherals/hosts – VLYNQ – ASP – SPI – PWM – UART The EDMA3 controller supports two addressing modes: constant addressing mode. On the DM6441 device, constant addressing mode or internal memory. For more information on these two addressing DMSoC Enhanced Direct Memory Access (EDMA3) Controller SPRUE23). 6.9.1 addressing mode and increment is not supported by any peripheral modes, see the TMS320DM644x User's Guide (literature number EDMA3 Channel Synchronization Events The EDMA3 supports up to 64 EDMA3 channels which service peripheral devices and external memory. Table 6-29 lists the source of EDMA3 synchronization events associated with each of the programmable EDMA3 channels. For the DM6441 device, the association of an event to a channel is fixed; each of the EDMA3 channels has one specific event associated with it. These specific events are captured in the EDMA3 event registers (ER, ERH) even if the events are disabled by the EDMA3 event enable registers (EER, EERH). For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23). Table 6-29. DM6441 EDMA3 Channel Synchronization Events (1) EDMA3 CHANNEL EVENT NAME EVENT DESCRIPTION 2 XEVT ASP Transmit Event 3 REVT ASP Receive Event 4 HISTEVT VPSS Histogram Event 5 H3AEVT VPSS H3A Event 6 PRVUEVT VPSS Previewer Event 0-1 (1) Reserved In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA3 event-transfer chaining, see the TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide (literature number SPRUE23). Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 125 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-29. DM6441 EDMA3 Channel Synchronization Events (continued) EDMA3 CHANNEL EVENT NAME EVENT DESCRIPTION 7 RSZEVT VPSS Resizer Event 8 IMXINT VICP Interrupt 9 VLCDINT VICP VLCD Interrupt 10 ASQINT VICP ASQ Interrupt 11 DSQINT VICP DSQ Interrupt 12-15 Reserved 16 SPIXEVT 17 SPIREVT SPI Receive Event 18 URXEVT0 UART 0 Receive Event 19 UTXEVT0 UART 0 Transmit Event 20 URXEVT1 UART 1 Receive Event 21 UTXEVT1 UART 1 Transmit Event 22 URXEVT2 UART 2 Receive Event 23 UTXEVT2 UART 2 Transmit Event 24 MSEVT Memory Stick/Memory Stick PRO Event 24 Reserved 25 Reserved 26 MMCRXEVT MMC Receive Event 27 MMCTXEVT MMC Transmit Event 28 I2CREVT I2C Receive Event 29 I2CXEVT I2C Transmit Event 32 GPINT0 GPIO 0 Interrupt 33 GPINT1 GPIO 1 Interrupt 34 GPINT2 GPIO 2 Interrupt 35 GPINT3 GPIO 3 Interrupt 36 GPINT4 GPIO 4 Interrupt 37 GPINT5 GPIO 5 Interrupt 38 GPINT6 GPIO 6 Interrupt 39 GPINT7 GPIO 7 Interrupt 40 GPBNKINT0 GPIO Bank 0 Interrupt 41 GPBNKINT1 GPIO Bank 1 Interrupt 42 GPBNKINT2 GPIO Bank 2 Interrupt 43 GPBNKINT3 GPIO Bank 3 Interrupt 44 GPBNKINT4 GPIO Bank 4 Interrupt 30-31 Reserved 45-47 Reserved 48 TINT0 49 TINT1 Timer 1 Interrupt 50 TINT2 Watchdog timer Interrupt 51 TINT3 Timer 3 Interrupt 52 PWM0 PWM 0 Event 53 PWM1 PWM 1 Event 54 PWM2 PWM 2 Event 55-63 126 SPI Transmit Event Timer 0 Interrupt Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.9.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 EDMA3 Peripheral Register Descriptions Table 6-30 lists the EDMA3 registers, their corresponding acronyms, and DM6441 device memory locations. Table 6-30. DM6441 EDMA3 Registers HEX ADDRESS ACRONYM REGISTER NAME Channel Controller Registers 0x01c0 0000 - 0x01c0 0003 0x01c0 0004 Reserved CCCFG 0x01c0 0008 - 0x01c0 01FF EDMA3CC Configuration Register Reserved Global Registers 0x01c0 0200 QCHMAP0 QDMA Channel 0 Mapping to PaRAM Register 0x01c0 0204 QCHMAP1 QDMA Channel 1 Mapping to PaRAM Register 0x01c0 0208 QCHMAP2 QDMA Channel 2 Mapping to PaRAM Register 0x01c0 020C QCHMAP3 QDMA Channel 3 Mapping to PaRAM Register 0x01c0 0210 QCHMAP4 QDMA Channel 4 Mapping to PaRAM Register 0x01c0 0214 QCHMAP5 QDMA Channel 5 Mapping to PaRAM Register 0x01c0 0218 QCHMAP6 QDMA Channel 6 Mapping to PaRAM Register 0x01c0 021C QCHMAP7 QDMA Channel 7 Mapping to PaRAM Register 0x01c0 0240 DMAQNUM0 DMA Queue Number Register 0 (Channels 00 to 07) 0x01c0 0244 DMAQNUM1 DMA Queue Number Register 1 (Channels 08 to 15) 0x01c0 0248 DMAQNUM2 DMA Queue Number Register 2 (Channels 16 to 23) 0x01c0 024C DMAQNUM3 DMA Queue Number Register 3 (Channels 24 to 31) 0x01c0 0250 DMAQNUM4 DMA Queue Number Register 4 (Channels 32 to 39) 0x01c0 0254 DMAQNUM5 DMA Queue Number Register 5 (Channels 40 to 47) 0x01c0 0258 DMAQNUM6 DMA Queue Number Register 6 (Channels 48 to 55) 0x01c0 025C DMAQNUM7 DMA Queue Number Register 7 (Channels 56 to 63) 0x01c0 0260 QDMAQNUM CC QDMA Queue Number 0x01c0 0264 - 0x01c0 0283 – 0x01c0 0284 QUEPRI 0x01c0 0288 - 0x01c0 02FF – Reserved Queue Priority Register Reserved 0x01c0 0300 EMR 0x01c0 0304 EMRH Event Missed Register Event Missed Register High 0x01c0 0308 EMCR Event Missed Clear Register 0x01c0 030C EMCRH Event Missed Clear Register High 0x01c0 0310 QEMR 0x01c0 0314 QEMCR QDMA Event Missed Register QDMA Event Missed Clear Register 0x01c0 0318 CCERR EDMA3CC Error Register 0x01c0 031C CCERRCLR 0x01c0 0320 EEVAL Error Evaluate Register 0x01c0 0340 DRAE0 DMA Region Access Enable Register for Region 0 0x01c0 0344 DRAEH0 0x01c0 0348 DRAE1 0x01c0 034C DRAEH1 0x01c0 0350 DRAE2 0x01c0 0354 DRAEH2 0x01c0 0358 DRAE3 0x01c0 035C DRAEH3 0x01c0 0360 - 0x01c0 037C – EDMA3CC Error Clear Register DMA Region Access Enable Register High for Region 0 DMA Region Access Enable Register for Region 1 DMA Region Access Enable Register High for Region 1 DMA Region Access Enable Register for Region 2 DMA Region Access Enable Register High for Region 2 DMA Region Access Enable Register for Region 3 DMA Region Access Enable Register High for Region 3 Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 127 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c0 0380 QRAE0 QDMA Region Access Enable Register for Region 0 0x01c0 0384 QRAE1 QDMA Region Access Enable Register for Region 1 0x01c0 0388 QRAE2 QDMA Region Access Enable Register for Region 2 0x01c0 038C QRAE3 QDMA Region Access Enable Register for Region 3 0x01c0 0390 - 0x01c0 039C – 0x01c0 0400 Q0E0 Event Q0 Entry 0 Register 0x01c0 0404 Q0E1 Event Q0 Entry 1 Register Reserved 0x01c0 0408 Q0E2 Event Q0 Entry 2 Register 0x01c0 040C Q0E3 Event Q0 Entry 3 Register 0x01c0 0410 Q0E4 Event Q0 Entry 4 Register 0x01c0 0414 Q0E5 Event Q0 Entry 5 Register 0x01c0 0418 Q0E6 Event Q0 Entry 6 Register 0x01c0 041C Q0E7 Event Q0 Entry 7 Register 0x01c0 0420 Q0E8 Event Q0 Entry 8 Register 0x01c0 0424 Q0E9 Event Q0 Entry 9 Register 0x01c0 0428 Q0E10 Event Q0 Entry 10 Register 0x01c0 042C Q0E11 Event Q0 Entry 11 Register 0x01c0 0430 Q0E12 Event Q0 Entry 12 Register 0x01c0 0434 Q0E13 Event Q0 Entry 13 Register 0x01c0 0438 Q0E14 Event Q0 Entry 14 Register 0x01c0 043C Q0E15 Event Q0 Entry 15 Register 0x01c0 0440 Q1E0 Event Q1 Entry 0 Register 0x01c0 0444 Q1E1 Event Q1 Entry 1 Register 0x01c0 0448 Q1E2 Event Q1 Entry 2 Register 0x01c0 044C Q1E3 Event Q1 Entry 3 Register 0x01c0 0450 Q1E4 Event Q1 Entry 4 Register 0x01c0 0454 Q1E5 Event Q1 Entry 5 Register 0x01c0 0458 Q1E6 Event Q1 Entry 6 Register 0x01c0 045C Q1E7 Event Q1 Entry 7 Register 0x01c0 0460 Q1E8 Event Q1 Entry 8 Register 0x01c0 0464 Q1E9 Event Q1 Entry 9 Register 0x01c0 0468 Q1E10 Event Q1 Entry 10 Register 0x01c0 046C Q1E11 Event Q1 Entry 11 Register 0x01c0 0470 Q1E12 Event Q1 Entry 12 Register 0x01c0 0474 Q1E13 Event Q1 Entry 13 Register 0x01c0 0478 Q1E14 Event Q1 Entry 14 Register 0x01c0 047C Q1E15 Event Q1 Entry 15 Register 0x01c0 0480 - 0x01c0 05FF Reserved 0x01c0 0600 QSTAT0 Queue 0 Status Register 0x01c0 0604 QSTAT1 Queue 1 Status Register 0x01c0 0608 - 0x01c0 061F Reserved 0x01c0 0620 QWMTHRA 0x01c0 0624 – 0x01c0 0640 CCSTAT 0x01c0 0644 - 0x01c0 0FFF 128 REGISTER NAME Queue Watermark Threshold A Register for Q[3:0] Reserved EDMA3CC Status Register Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME Global Channel Registers 0x01c0 1000 ER 0x01c0 1004 ERH Event Register Event Register High 0x01c0 1008 ECR Event Clear Register 0x01c0 100C ECRH 0x01c0 1010 ESR 0x01c0 1014 ESRH Event Set Register High Chained Event Register Event Clear Register High Event Set Register 0x01c0 1018 CER 0x01c0 101C CERH 0x01c0 1020 EER 0x01c0 1024 EERH Event Enable Register High Event Enable Clear Register Chained Event Register High Event Enable Register 0x01c0 1028 EECR 0x01c0 102C EECRH 0x01c0 1030 EESR 0x01c0 1034 EESRH 0x01c0 1038 SER 0x01c0 103C SERH Secondary Event Register High 0x01c0 1040 SECR Secondary Event Clear Register 0x01c0 1044 SECRH 0x01c0 1048 - 0x01c0 104F Event Enable Clear Register High Event Enable Set Register Event Enable Set Register High Secondary Event Register Secondary Event Clear Register High Reserved 0x01c0 1050 IER Interrupt Enable Register 0x01c0 1054 IERH Interrupt Enable Register High 0x01c0 1058 IECR Interrupt Enable Clear Register 0x01c0 105C IECRH Interrupt Enable Clear Register High 0x01c0 1060 IESR 0x01c0 1064 IESRH Interrupt Enable Set Register 0x01c0 1068 IPR 0x01c0 106C IPRH 0x01c0 1070 ICR 0x01c0 1074 ICRH Interrupt Clear Register High 0x01c0 1078 IEVAL Interrupt Evaluate Register Interrupt Enable Set Register High Interrupt Pending Register Interrupt Pending Register High Interrupt Clear Register 0x01c0 1080 QER 0x01c0 1084 QEER 0x01c0 1088 QEECR QDMA Event Enable Clear Register 0x01c0 108C QEESR QDMA Event Enable Set Register 0x01c0 1090 QSER QDMA Secondary Event Register 0x01c0 1094 QSECR 0x01c0 1098 - 0x01c0 1FFF QDMA Event Register QDMA Event Enable Register QDMA Secondary Event Clear Register Reserved Shadow Region 0 Channel Registers 0x01c0 2000 ER 0x01c0 2004 ERH Event Register Event Register High Event Clear Register 0x01c0 2008 ECR 0x01c0 200C ECRH 0x01c0 2010 ESR 0x01c0 2014 ESRH Event Set Register High 0x01c0 2018 CER Chained Event Register 0x01c0 201C CERH Event Clear Register High Event Set Register Chained Event Register High Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 129 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c0 2020 EER REGISTER NAME 0x01c0 2024 EERH Event Enable Register High 0x01c0 2028 EECR Event Enable Clear Register 0x01c0 202C EECRH Event Enable Register Event Enable Clear Register High 0x01c0 2030 EESR 0x01c0 2034 EESRH Event Enable Set Register 0x01c0 2038 SER 0x01c0 203C SERH Secondary Event Register High 0x01c0 2040 SECR Secondary Event Clear Register 0x01c0 2044 SECRH 0x01c0 2048 - 0x01c0 204C - Event Enable Set Register High Secondary Event Register Secondary Event Clear Register High Reserved 0x01c0 2050 IER 0x01c0 2054 IERH Interrupt Enable Register Interrupt Enable Register High 0x01c0 2058 IECR Interrupt Enable Clear Register 0x01c0 205C IECRH 0x01c0 2060 IESR 0x01c0 2064 IESRH Interrupt Enable Clear Register High Interrupt Enable Set Register Interrupt Enable Set Register High 0x01c0 2068 IPR 0x01c0 206C IPRH 0x01c0 2070 ICR 0x01c0 2074 ICRH Interrupt Clear Register High Interrupt Evaluate Register 0x01c0 2078 IEVAL 0x01c0 207C - 0x01c0 2080 QER Interrupt Pending Register Interrupt Pending Register High Interrupt Clear Register Reserved QDMA Event Register 0x01c0 2084 QEER 0x01c0 2088 QEECR QDMA Event Enable Register QDMA Event Enable Clear Register 0x01c0 208C QEESR QDMA Event Enable Set Register 0x01c0 2090 QSER QDMA Secondary Event Register 0x01c0 2094 QSECR 0x01c0 2098 - 0x01c0 21FC - QDMA Secondary Event Clear Register Reserved Shadow Region 1 Channel Registers 130 0x01c0 2200 ER 0x01c0 2204 ERH Event Register Event Register High 0x01c0 2208 ECR Event Clear Register 0x01c0 220C ECRH 0x01c0 2210 ESR 0x01c0 2214 ESRH Event Set Register High Chained Event Register Event Clear Register High Event Set Register 0x01c0 2218 CER 0x01c0 221C CERH 0x01c0 2220 EER 0x01c0 2224 EERH Event Enable Register High Event Enable Clear Register 0x01c0 2228 EECR 0x01c0 222C EECRH 0x01c0 2230 EESR 0x01c0 2234 EESRH 0x01c0 2238 SER 0x01c0 223C SERH Chained Event Register High Event Enable Register Event Enable Clear Register High Event Enable Set Register Event Enable Set Register High Secondary Event Register Secondary Event Register High Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c0 2240 SECR REGISTER NAME Secondary Event Clear Register 0x01c0 2244 SECRH 0x01c0 2248 - 0x01c0 224C - 0x01c0 2250 IER 0x01c0 2254 IERH Interrupt Enable Register High 0x01c0 2258 IECR Interrupt Enable Clear Register 0x01c0 225C IECRH 0x01c0 2260 IESR 0x01c0 2264 IESRH 0x01c0 2268 IPR 0x01c0 226C IPRH Secondary Event Clear Register High Reserved Interrupt Enable Register Interrupt Enable Clear Register High Interrupt Enable Set Register Interrupt Enable Set Register High Interrupt Pending Register Interrupt Pending Register High 0x01c0 2270 ICR 0x01c0 2274 ICRH Interrupt Clear Register High 0x01c0 2278 IEVAL Interrupt Evaluate Register 0x01c0 227C - 0x01c0 2280 QER 0x01c0 2284 QEER Interrupt Clear Register Reserved QDMA Event Register QDMA Event Enable Register 0x01c0 2288 QEECR QDMA Event Enable Clear Register 0x01c0 228C QEESR QDMA Event Enable Set Register 0x01c0 2290 QSER QDMA Secondary Event Register 0x01c0 2294 QSECR 0x01c0 2298 - 0x01c0 23FC - QDMA Secondary Event Clear Register Reserved Shadow Region 2 Channel Registers 0x01c0 2400 ER Event Register 0x01c0 2404 ERH Event Register High 0x01c0 2408 ECR Event Clear Register 0x01c0 240C ECRH Event Clear Register High 0x01c0 2410 ESR 0x01c0 2414 ESRH Event Set Register Event Set Register High 0x01c0 2418 CER Chained Event Register 0x01c0 241C CERH Chained Event Register High 0x01c0 2420 EER 0x01c0 2424 EERH Event Enable Register Event Enable Register High 0x01c0 2428 EECR Event Enable Clear Register 0x01c0 242C EECRH 0x01c0 2430 EESR 0x01c0 2434 EESRH Event Enable Clear Register High Event Enable Set Register Event Enable Set Register High 0x01c0 2438 SER 0x01c0 243C SERH Secondary Event Register Secondary Event Register High 0x01c0 2440 SECR Secondary Event Clear Register 0x01c0 2444 SECRH Secondary Event Clear Register High 0x01c0 2448 - 0x01c0 244C - 0x01c0 2450 IER 0x01c0 2454 IERH Interrupt Enable Register High Interrupt Enable Clear Register 0x01c0 2458 IECR 0x01c0 245C IECRH 0x01c0 2460 IESR Reserved Interrupt Enable Register Interrupt Enable Clear Register High Interrupt Enable Set Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 131 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c0 2464 IESRH 0x01c0 2468 IPR 0x01c0 246C IPRH 0x01c0 2470 ICR REGISTER NAME Interrupt Enable Set Register High Interrupt Pending Register Interrupt Pending Register High Interrupt Clear Register 0x01c0 2474 ICRH Interrupt Clear Register High 0x01c0 2478 IEVAL Interrupt Evaluate Register 0x01c0 247C - Reserved 0x01c0 2480 QER 0x01c0 2484 QEER QDMA Event Register 0x01c0 2488 QEECR QDMA Event Enable Clear Register 0x01c0 248C QEESR QDMA Event Enable Set Register 0x01c0 2490 QSER QDMA Secondary Event Register 0x01c0 2494 QSECR 0x01c0 2498 - 0x01c0 25FC - QDMA Event Enable Register QDMA Secondary Event Clear Register Reserved Shadow Region 3 Channel Registers 132 0x01c0 2600 ER 0x01c0 2604 ERH Event Register Event Register High Event Clear Register 0x01c0 2608 ECR 0x01c0 260C ECRH 0x01c0 2610 ESR 0x01c0 2614 ESRH Event Set Register High Chained Event Register Event Clear Register High Event Set Register 0x01c0 2618 CER 0x01c0 261C CERH 0x01c0 2620 EER 0x01c0 2624 EERH Event Enable Register High 0x01c0 2628 EECR Event Enable Clear Register 0x01c0 262C EECRH Chained Event Register High Event Enable Register Event Enable Clear Register High 0x01c0 2630 EESR 0x01c0 2634 EESRH Event Enable Set Register 0x01c0 2638 SER 0x01c0 263C SERH Secondary Event Register High 0x01c0 2640 SECR Secondary Event Clear Register 0x01c0 2644 SECRH 0x01c0 2648 - 0x01c0 264C - Event Enable Set Register High Secondary Event Register Secondary Event Clear Register High Reserved 0x01c0 2650 IER 0x01c0 2654 IERH Interrupt Enable Register High 0x01c0 2658 IECR Interrupt Enable Clear Register 0x01c0 265C IECRH 0x01c0 2660 IESR 0x01c0 2664 IESRH 0x01c0 2668 IPR 0x01c0 266C IPRH 0x01c0 2670 ICR 0x01c0 2674 ICRH Interrupt Clear Register High Interrupt Evaluate Register 0x01c0 2678 IEVAL 0x01c0 267C - 0x01c0 2680 QER Interrupt Enable Register Interrupt Enable Clear Register High Interrupt Enable Set Register Interrupt Enable Set Register High Interrupt Pending Register Interrupt Pending Register High Interrupt Clear Register Reserved QDMA Event Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c0 2684 QEER REGISTER NAME QDMA Event Enable Register 0x01c0 2688 QEECR QDMA Event Enable Clear Register 0x01c0 268C QEESR QDMA Event Enable Set Register 0x01c0 2690 QSER QDMA Secondary Event Register 0x01c0 2694 QSECR 0x01c0 2698 - 0x01c0 27FC - QDMA Secondary Event Clear Register Reserved 0x01c0 2800 - 0x01c0 29FC - Reserved 0x01c0 2A00 - 0x01c0 2BFC - Reserved 0x01c0 2C00 - 0x01c0 2DFC - Reserved 0x01c0 2E00 - 0x01c0 2FFC - Reserved 0x01c0 2FFD - 0x01c0 3FFF - Reserved 0x01c0 4000 - 0x01c0 4FFF - Parameter Set RAM (see Table 6-31) 0x01c0 5000 - 0x01c0 7FFF - Reserved 0x01c0 8000 - 0x01c0 FFFF - Reserved 0x01c1 0000 - 0x01c1 0004 TCCFG Transfer Controller 0 Registers Reserved EDMA3 TC0 Configuration Register 0x01c1 0008 - 0x01c1 00FF - 0x01c1 0100 TCSTAT Reserved 0x01c1 0104 - 0x01c1 0110 - Reserved 0x01c1 0114 - 0x01c1 011F - Reserved 0x01c1 0120 ERRSTAT EDMA3 TC0 Error Status Register 0x01c1 0124 ERREN EDMA3 TC0 Error Enable Register 0x01c1 0128 ERRCLR EDMA3 TC0 Error Clear Register 0x01c1 012C ERRDET EDMA3 TC0 Error Details Register 0x01c1 0130 ERRCMD EDMA3 TC0 Error Interrupt Command Register 0x01c1 0134 - 0x01c1 013F - EDMA3 TC0 Channel Status Register Reserved 0x01c1 0140 RDRATE 0x01c1 0144 - 0x01c1 01FF - EDMA3 TC0 Read Rate Register Reserved 0x01c1 0200 - 0x01c1 023F - Reserved 0x01c1 0240 SAOPT EDMA3 TC0 Source Active Options Register 0x01c1 0244 SASRC EDMA3 TC0 Source Active Source Address Register 0x01c1 0248 SACNT EDMA3 TC0 Source Active Count Register 0x01c1 024C SADST EDMA3 TC0 Source Active Destination Address Register 0x01c1 0250 SABIDX EDMA3 TC0 Source Active Source B-Index Register 0x01c1 0254 SAMPPRXY EDMA3 TC0 Source Active Memory Protection Proxy Register 0x01c1 0258 SACNTRLD EDMA3 TC0 Source Active Count Reload Register 0x01c1 025C SASRCBREF EDMA3 TC0 Source Active Source Address B-Reference Register 0x01c1 0260 SADSTBREF EDMA3 TC0 Source Active Destination Address B-Reference Register 0x01c1 0264 - 0x01c1 027F - 0x01c1 0280 DFCNTRLD 0x01c1 0284 DFSRCBREF EDMA3 TC0 Destination FIFO Set Source Address B-Reference Register 0x01c1 0288 DFDSTBREF EDMA3 TC0 Destination FIFO Set Destination Address B-Reference Register Reserved EDMA3 TC0 Destination FIFO Set Count Reload Register 0x01c1 028C - 0x01c1 02FF - 0x01c1 0300 DFOPT0 Reserved EDMA3 TC0 Destination FIFO Options Register 0 0x01c1 0304 DFSRC0 EDMA3 TC0 Destination FIFO Source Address Register 0 0x01c1 0308 DFCNT0 EDMA3 TC0 Destination FIFO Count Register 0 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 133 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c1 030C DFDST0 EDMA3 TC0 Destination FIFO Destination Address Register 0 REGISTER NAME 0x01c1 0310 DFBIDX0 EDMA3 TC0 Destination FIFO BIDX Register 0 0x01c1 0314 DFMPPRXY0 0x01c1 0318 - 0x01c1 033F - EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 0 Reserved 0x01c1 0340 DFOPT1 EDMA3 TC0 Destination FIFO Options Register 1 0x01c1 0344 DFSRC1 EDMA3 TC0 Destination FIFO Source Address Register 1 0x01c1 0348 DFCNT1 EDMA3 TC0 Destination FIFO Count Register 1 0x01c1 034C DFDST1 EDMA3 TC0 Destination FIFO Destination Address Register 1 0x01c1 0350 DFBIDX1 EDMA3 TC0 Destination FIFO BIDX Register 1 0x01c1 0354 DFMPPRXY1 0x01c1 0358 - 0x01c1 037F - EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 1 Reserved 0x01c1 0380 DFOPT2 EDMA3 TC0 Destination FIFO Options Register 2 0x01c1 0384 DFSRC2 EDMA3 TC0 Destination FIFO Source Address Register 2 0x01c1 0388 DFCNT2 EDMA3 TC0 Destination FIFO Count Register 2 0x01c1 038C DFDST2 EDMA3 TC0 Destination FIFO Destination Address Register 2 0x01c1 0390 DFBIDX2 EDMA3 TC0 Destination FIFO BIDX Register 2 0x01c1 0394 DFMPPRXY2 EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 2 0x01c1 0398 - 0x01c1 03BF - 0x01c1 03C0 DFOPT3 Reserved EDMA3 TC0 Destination FIFO Options Register 3 0x01c1 03C4 DFSRC3 EDMA3 TC0 Destination FIFO Source Address Register 3 0x01c1 03C8 DFCNT3 EDMA3 TC0 Destination FIFO Count Register 3 0x01c1 03CC DFDST3 EDMA3 TC0 Destination FIFO Destination Address Register 3 0x01c1 03D0 DFBIDX3 EDMA3 TC0 Destination FIFO BIDX Register 3 0x01c1 03D4 DFMPPRXY3 0x01c1 03D8 - 0x01c1 03FF - EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 3 Reserved Transfer Controller 1 Registers 134 0x01c1 0400 - Reserved 0x01c1 0404 TCCFG 0x01c1 0408 - 0x01c1 04FF - EDMA3 TC1 Configuration Register 0x01c1 0500 TCSTAT 0x01c1 0504 - 0x01c1 0510 - Reserved 0x01c1 0514 - 0x01c1 051F - Reserved 0x01c1 0520 ERRSTAT EDMA3 TC1 Error Status Register 0x01c1 0524 ERREN EDMA3 TC1 Error Enable Register Reserved EDMA3 TC1 Channel Status Register 0x01c1 0528 ERRCLR EDMA3 TC1 Error Clear Register 0x01c1 052C ERRDET EDMA3 TC1 Error Details Register 0x01c1 0530 ERRCMD EDMA3 TC1 Error Interrupt Command Register 0x01c1 0534 - 0x01c1 053F - 0x01c1 0540 RDRATE Reserved 0x01c1 0544 - 0x01c1 05FF - Reserved 0x01c1 0600 - 0x01c1 063F - Reserved EDMA3 TC1 Read Rate Register 0x01c1 0640 SAOPT EDMA3 TC1 Source Active Options Register 0x01c1 0644 SASRC EDMA3 TC1 Source Active Source Address Register 0x01c1 0648 SACNT EDMA3 TC1 Source Active Count Register 0x01c1 064C SADST EDMA3 TC1 Source Active Destination Address Register 0x01c1 0650 SABIDX EDMA3 TC1 Source Active Source B-Index Register 0x01c1 0654 SAMPPRXY EDMA3 TC1 Source Active Memory Protection Proxy Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-30. DM6441 EDMA3 Registers (continued) HEX ADDRESS ACRONYM 0x01c1 0658 SACNTRLD REGISTER NAME 0x01c1 065C SASRCBREF EDMA3 TC1 Source Active Source Address B-Reference Register 0x01c1 0660 SADSTBREF EDMA3 TC1 Source Active Destination Address B-Reference Register 0x01c1 0664 - 0x01c1 067F - EDMA3 TC1 Source Active Count Reload Register Reserved 0x01c1 0680 DFCNTRLD 0x01c1 0684 DFSRCBREF EDMA3 TC1 Destination FIFO Set Count Reload Register EDMA3 TC1 Destination FIFO Set Source Address B-Reference Register 0x01c1 0688 DFDSTBREF EDMA3 TC1 Destination FIFO Set Destination Address B-Reference Register 0x01c1 068C - 0x01c1 06FF - 0x01c1 0700 DFOPT0 Reserved EDMA3 TC1 Destination FIFO Options Register 0 0x01c1 0704 DFSRC0 EDMA3 TC1 Destination FIFO Source Address Register 0 0x01c1 0708 DFCNT0 EDMA3 TC1 Destination FIFO Count Register 0 0x01c1 070C DFDST0 EDMA3 TC1 Destination FIFO Destination Address Register 0 0x01c1 0710 DFBIDX0 EDMA3 TC1 Destination FIFO BIDX Register 0 0x01c1 0714 DFMPPRXY0 0x01c1 0718 - 0x01c1 073F - EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 0 0x01c1 0740 DFOPT1 EDMA3 TC1 Destination FIFO Options Register 1 0x01c1 0744 DFSRC1 EDMA3 TC1 Destination FIFO Source Address Register 1 0x01c1 0748 DFCNT1 EDMA3 TC1 Destination FIFO Count Register 1 0x01c1 074C DFDST1 EDMA3 TC1 Destination FIFO Destination Address Register 1 0x01c1 0750 DFBIDX1 EDMA3 TC1 Destination FIFO BIDX Register 1 Reserved 0x01c1 0754 DFMPPRXY1 0x01c1 0758 - 0x01c1 077F - EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 1 0x01c1 0780 DFOPT2 EDMA3 TC1 Destination FIFO Options Register 2 0x01c1 0784 DFSRC2 EDMA3 TC1 Destination FIFO Source Address Register 2 0x01c1 0788 DFCNT2 EDMA3 TC1 Destination FIFO Count Register 2 0x01c1 078C DFDST2 EDMA3 TC1 Destination FIFO Destination Address Register 2 0x01c1 0790 DFBIDX2 EDMA3 TC1 Destination FIFO BIDX Register 2 0x01c1 0794 DFMPPRXY2 0x01c1 0798 - 0x01c1 07BF - 0x01c1 07C0 DFOPT3 EDMA3 TC1 Destination FIFO Options Register 3 0x01c1 07C4 DFSRC3 EDMA3 TC1 Destination FIFO Source Address Register 3 0x01c1 07C8 DFCNT3 EDMA3 TC1 Destination FIFO Count Register 3 0x01c1 07CC DFDST3 EDMA3 TC1 Destination FIFO Destination Address Register 3 0x01c1 07D0 DFBIDX3 EDMA3 TC1 Destination FIFO BIDX Register 3 0x01c1 07D4 DFMPPRXY3 0x01c1 07D8 - 0x01c1 07FF - Reserved EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 2 Reserved EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 3 Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 135 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-31 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA3 events. Each of the parameter register sets consist of eight 32-bit word entries. Table 6-32 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. Table 6-31. EDMA3 Parameter Set RAM HEX ADDRESS RANGE DESCRIPTION 0x01c0 4000 - 0x01c0 401F Parameters Set 0 (8 32-bit words) 0x01c0 4020 - 0x01c0 403F Parameters Set 1 (8 32-bit words) 0x01c0 4040 - 0x01c0 405F Parameters Set 2 (8 32-bit words) 0x01c0 4060 - 0x01c0 407F Parameters Set 3 (8 32-bit words) 0x01c0 4080 - 0x01c0 409F Parameters Set 4 (8 32-bit words) 0x01c0 40A0 - 0x01c0 40BF Parameters Set 5 (8 32-bit words) ... ... 0x01c0 4FC0 - 0x01c0 4FDF Parameters Set 126 (8 32-bit words) 0x01c0 4FE0 - 0x01c0 4FFF Parameters Set 127 (8 32-bit words) Table 6-32. Parameter Set Entries HEX OFFSET ADDRESS WITHIN THE PARAMETER SET 136 ACRONYM PARAMETER ENTRY 0x0000 OPT Option 0x0004 SRC Source Address 0x0008 A_B_CNT A Count, B Count 0x000C DST 0x0010 SRC_DST_BIDX Destination Address Source B Index, Destination B Index 0x0014 LINK_BCNTRLD Link Address, B Count Reload 0x0018 SRC_DST_CIDX Source C Index, Destination C Index 0x001C CCNT C Count Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.10 External Memory Interface (EMIF) DM6441 supports several memory and external device interfaces, including: • Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc. • NAND Flash • Memory Stick/Memory Stick PRO • ATA/CF 6.10.1 Asynchronous EMIF (EMIFA) The DM6441 Asynchronous EMIF (EMIFA) provides an 8-bit or 16-bit data bus, an address bus width up to 24-bits, and four dedicated chip selects, along with memory control signals. These signals are multiplexed between three peripherals: • EMIFA and NAND interfaces • ATA/CF • Host Port Interface 6.10.1.1 NAND (NAND, SmartMedia, xD) The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided and each are individually configurable to provide either EMIFA or NAND support. The NAND features supported are as follows. • NAND flash on up to four asynchronous chip selects. • 8- and 16-bit data bus widths. • Programmable cycle timings. • Performs ECC calculation. • NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory cards • ARM ROM supports booting of the DM6441 ARM processor from NAND flash located at CS2 The memory map for EMIFA and NAND registers is shown in Table 6-33. For more details on the EMIFA and NAND interfaces, see the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19) and the TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) Reference Guide (literature number SPRUE20). Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 137 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-33. EMIFA/NAND Registers HEX ADDRESS RANGE ACRONYM 0x01E0 0000 - 0x01E0 0003 0x01E0 0004 REGISTER NAME Reserved AWCCR 0x01E0 0008 - 0x01E0 000F Asynchronous Wait Cycle Configuration Register Reserved 0x01E0 0010 A1CR Asynchronous 1 Configuration Register (CS2 Space) 0x01E0 0014 A2CR Asynchronous 2 Configuration Register (CS3 Space) 0x01E0 0018 A3CR Asynchronous 3 Configuration Register (CS4 Space) 0x01E0 001C A4CR Asynchronous 4 Configuration Register (CS5 Space) 0x01E0 0020 - 0x01E0 003F 0x01E0 0040 - Reserved EIRR EMIF Interrupt Raw Register 0x01E0 0044 EIMR EMIF Interrupt Mask Register 0x01E0 0048 EIMSR EMIF Interrupt Mask Set Register 0x01E0 004C EIMCR EMIF Interrupt Mask Clear Register 0x01E0 0050 - 0x01E0 005F - Reserved 0x01E0 0060 NANDFCR NAND Flash Control Register 0x01E0 0064 NANDFSR NAND Flash Status Register 0x01E0 0070 NANDF1ECC NAND Flash 1 ECC Register (CS2 Space) 0x01E0 0074 NANDF2ECC NAND Flash 2 ECC Register (CS3 Space) 0x01E0 0078 NANDF3ECC NAND Flash 3 ECC Register (CS4 Space) 0x01E0 007C NANDF4ECC NAND Flash 4 ECC Register (CS5 Space) 0x01E0 0080 - 0x01E0 0FFF 138 - Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.10.1.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 EMIFA Electrical Data/Timing Table 6-34. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module (1) (see Figure 6-21 and Figure 6-22) 1.05 V and 1.2 V NO. MIN MAX UNIT READS and WRITES 2 tw(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion 2E ns 10.5 ns READS 12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 14 tsu (EMWAIT-EMOEH) Setup time, EM_WAIT asserted before EM_OE high (2) 0 ns 4E + 10.4 ns 4E + 10.4 ns WRITES 28 (1) (2) t su(EMWAIT-EMWEH) Setup time, EM_WAIT asserted before EM_WE high (2) E = SYSCLK5 period in ns for EMIFA. For example, when running the DSP CPU at 405 MHz, use E = 14.8 ns. Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-23 and Figure 6-24 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 139 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-35. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module (1) (2) (see Figure 6-21 and Figure 6-22) NO. 1.05 V and 1.2 V PARAMETER UNIT MIN MAX (TA + 1) * E - 2 (TA + 1) * E + 2 ns EMIF read cycle time (EW = 0) (RS + RST + RH + TA + 4) * E - 0.5 (RS + RST + RH + TA + 4) * E + 0.5 ns EMIF read cycle time (EW = 1) (RS + RST + RH + TA + 4) * E - 0.5 4184 * E + 0.5 ns Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0) (RS + 1) * E - 1 (RS + 1) * E + 1.4 ns Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1) -1 Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0) (RH + 1) * E - 2.1 Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1) -2.2 READS and WRITES 1 td(TURNAROUND) Turn around time READS 3 4 5 tc(EMRCYCLE) tsu(EMCSL-EMOEL) th(EMOEH-EMCSH) ns (RH + 1) * E + 1.4 ns ns 6 tsu(EMBAV-EMOEL) Output setup time, EM_BA[1:0] valid to EM_OE low (RS + 1) * E - 1.8 (RS + 1) * E + 1.3 ns 7 th(EMOEH-EMBAIV) Output hold time, EM_OE high to EM_BA[1:0] invalid (RH + 1) * E - 2.3 (RH + 1) * E + 1.1 ns 8 tsu(EMAV-EMOEL) Output setup time, EM_A[21:0] valid to EM_OE low (RS + 1) * E - 1.9 (RS + 1) * E + 1.5 ns 9 th(EMOEH-EMAIV) Output hold time, EM_OE high to EM_A[21:0] invalid (RH + 1) * E - 2.6 (RH + 1) * E + 1.2 ns EM_OE active low width (EW = 0) (RST + 1) * E - 2 (RST + 1) * E + 2 ns EM_OE active low width (EW = 1) (RST + 1) * E - 2 (RST + 4097) * E + 2 ns 4E + 10.4 ns 10 tw(EMOEL) 11 td(EMWAITH-EMOEH) Delay time from EM_WAIT deasserted to EM_OE high WRITES 15 16 17 EMIF write cycle time (EW = 0) (WS + WST + WH + TA + 4) * E - 0.5 (WS + WST + WH + TA + 4) * E + 0.5 ns EMIF write cycle time (EW = 1) (WS + WST + WH + TA + 4) * E -0.5 4184 * E + 0.5 ns Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS + 1) * E - 0.9 (WS + 1) * E + 1.4 ns Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1) -1 Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0) (WH + 1) * E - 2.1 Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1) -2.1 tc(EMWCYCLE) tsu(EMCSL-EMWEL) th(EMWEH-EMCSH) ns (WH + 1) * E + 1.1 ns ns 18 tsu(EMRNW-EMWEL) Output setup time, EM_R/W valid to EM_WE low (WS + 1) * E - 0.7 (WS + 1) * E + 0.9 ns 19 th(EMWEH-EMRNW) Output hold time, EM_WE high to EM_R/W invalid (WH + 1) * E - 0.9 (WH + 1) * E + 0.9 ns 20 tsu(EMBAV-EMWEL) Output setup time, EM_BA[1:0] valid to EM_WE low (WS + 1) * E - 1.7 (WS + 1) * E + 1.5 ns 21 th(EMWEH-EMBAIV) Output hold time, EM_WE high to EM_BA[1:0] invalid (WH + 1) * E - 2.3 (WH + 1) * E + 0.9 ns 22 tsu(EMAV-EMWEL) Output setup time, EM_A[21:0] valid to EM_WE low (WS + 1) * E - 1.8 (WS + 1) * E + 1.7 ns 23 th(EMWEH-EMAIV) Output hold time, EM_WE high to EM_A[21:0] invalid (WH + 1) * E - 2.6 (WH + 1) * E + 1 ns 24 tw(EMWEL) EM_WE active low width (EW = 0) (WST + 1) * E - 2 (WST + 1) * E + 2 ns EM_WE active low width (EW = 1) (WST + 1) * E - 2 (WST + 4097) * E + 2 ns 25 td(EMWAITH-EMWEH) Delay time from EM_WAIT deasserted to EM_WE high 4E + 10.4 ns 26 tsu(EMDV-EMWEL) Output setup time, EM_D[15:0] valid to EM_WE low (WS + 1) * E + 1.4 ns (1) (2) 140 (WS + 1) * E - 2.2 RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STrobe, WH = Write Hold, TA = Turn Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers and support the following range of values: TA[3:0], RS[15:0], RST[63:0], RH[7:0], WS[15:0], WST[63:0], WH[7:0], and EW[255:0]. For more information, see the TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) Reference Guide (literature number SPRUE20). E = SYSCLK5 period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-35. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module (see Figure 6-21 and Figure 6-22) (continued) NO. 27 1.05 V and 1.2 V PARAMETER th(EMWEH-EMDIV) Output hold time, EM_WE high to EM_D[15:0] invalid MIN MAX (WH + 1) * E - 2.2 (WH + 1) * E + 1.4 UNIT ns 3 1 EM_CS[5:2] EM_R/W EM_BA[1:0] EM_A[21:0] 4 8 5 9 6 7 10 EM_OE 13 12 EM_D[15:0] EM_WE Figure 6-21. Asynchronous Memory Read Timing for EMIF Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 141 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 15 1 EM_CS[5:2] EM_R/W EM_BA[1:0] EM_A[21:0] 16 17 18 19 20 21 24 22 23 EM_WE 27 26 EM_D[15:0] EM_OE Figure 6-22. Asynchronous Memory Write Timing for EMIF EM_CS[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_BA[1:0] EM_A[21:0] EM_D[15:0] 14 11 EM_OE 2 Asserted EM_WAIT 2 Deasserted Figure 6-23. EM_WAIT Read Timing Requirements 142 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 EM_CS[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_BA[1:0] EM_A[21:0] EM_D[15:0] 28 25 EM_WE 2 EM_WAIT Asserted 2 Deasserted Figure 6-24. EM_WAIT Write Timing Requirements 6.10.2 DDR2 Memory Controller The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM devices. For details on the DDR2 Memory Controller, see the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19) and the TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUE22). DDR2 SDRAM plays a key role in a DM6441-based system. Such a system is expected to require a significant amount of high-speed external memory for: • Buffering of input image data from sensors or video sources • Intermediate buffering for processing/resizing of image data in the VPFE • Numerous OSD display buffers • Intermediate buffering for large raw Bayer data image files while performing image processing functions • Buffering for intermediate data while performing video encode and decode functions • Storage of executable code for both the ARM and DSP A memory map of the DDR2 memory controller registers is shown in Table 6-36. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 143 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-36. DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM 0x01C4 004C DDRVTPER 0x01C4 2030 DDRVTPR 0x2000 0000 - 0x2000 0003 - REGISTER NAME DDR2 VTP Enable Register DDR2 VTP Register Reserved 0x2000 0004 SDRSTAT 0x2000 0008 SDBCR SDRAM Bank Configuration Register 0x2000 000C SDRCR SDRAM Refresh Control Register 0x2000 0010 SDTIMR SDRAM Timing Register 0x2000 0014 SDTIMR2 SDRAM Timing Register 2 0x2000 0020 PBBPR 0x2000 0024 - 0x2000 00BF - 0x2000 00C0 SDRAM Status Register Peripheral Bus Burst Priority Register Reserved IRR Interrupt Raw Register 0x2000 00C4 IMR Interrupt Masked Register 0x2000 00C8 IMSR Interrupt Mask Set Register 0x2000 00CC IMCR Interrupt Mask Clear Register 0x2000 00D0 - 0x2000 00E3 - 0x2000 00E4 DDRPHYCR 0x2000 00E8 - 0x2000 00EF - 0x2000 00F0 VTPIOCR 0x2000 00F4 - 0x2000 7FFF - Reserved DDR PHY Control Register Reserved VTP IO Control Register Reserved 6.10.2.1 DDR2 Memory Controller Electrical Data/Timing The Implementing DDR2 PCB Layout on the TMS320DM644x DSP application report (literature number SPRAAC5) specifies a complete DDR2 interface solution for the DM6441 as well as a list of compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met. TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout on the TMS320DM644x DSP application report (literature number SPRAAC5). Table 6-37. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller (1) (2)(see Figure 6-25) NO. 1 (1) (2) PARAMETER tc(DDR_CLK0) Cycle time, DDR_CLK0 1.05 V 1.2 V MIN MAX MIN MAX 7.4 8 6 8 UNIT ns DDR_CLK0 cycle time = 2 x PLL2 - SYSCLK2 cycle time. The PLL2 Controller must be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range. 1 DDR_CLK0 Figure 6-25. DDR2 Memory Controller Clock Timing 144 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.11 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 ATA/CF The ATA/CF peripheral supports the following features: • PIO, multiword DMA, and Ultra ATA 33/66 • Up to mode four timings on PIO mode • Up to mode two timings on multiword DMA • Up to mode four timings on Ultra ATA • Programmable timing parameters • Supports TrueIDE mode for Compact Flash In addition, the host IDE controller supports multiword DMA transfers between external IDE/ATAPI devices and a system memory bus interface. 6.11.1 ATA/CF Peripheral Register Description(s) The ATA registers are shown in Table 6-38. Table 6-38. ATA Register Memory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME ATA Bus Master Interface DMA Engine Registers 0x01C6 6000 BMICP Primary IDE Channel DMA Control Register 0x01C6 6002 BMISP Primary IDE Channel DMA Status Register 0x01C6 6004 BMIDTP Primary IDE Channel DMA Descriptor Table Pointer Register 0x01C6 6008 - 0x01C6 600A - 0x01C6 600C - 0x01C6 6040 IDETIMP 0x01C6 6042 - 0x01C6 6044 - 0x01C6 6045 - 0x01C6 6047 IDESTAT IDE Controller Status Register 0x01C6 6048 UDMACTL Ultra-DMA Control Register 0x01C6 604A - Reserved 0x01C6 6050 MISCCTL Miscellaneous Control Register 0x01C6 6054 REGSTB Task File Register Strobe Timing Register 0x01C6 6058 REGRCVR Task File Register Recovery Timing Register 0x01C6 605C DATSTB Data Register Access PIO Strobe Timing Register 0x01C6 6060 DATRCVR Data Register Access PIO Recovery Timing Register 0x01C6 6064 DMASTB Multiword DMA Strobe Timing Register 0x01C6 6068 DMARCVR Multiword DMA Recovery Timing Register 0x01C6 606C UDMASTB Ultra-DMA Strobe Timing Register 0x01C6 6070 UDMATRP Ultra-DMA Ready-to-Pause Timing Register 0x01C6 6074 UDMATENV Ultra-DMA Timing Envelope Register 0x01C6 6078 IORDYTMP Primary IO Ready Timer Configuration Register 0x01C6 607C - 0x01C6 67FF - Reserved Reserved ATA Configuration Registers Primary IDE Channel Timing Register Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 145 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.11.2 ATA/CF Electrical Data/Timing All ATA/CF AC timing data described in Table 6-39 – Figure 6-26 is provided at the DM6441 device pins. For more details, see Section 6.1, Parameter Information. The AC timing specifications described in Table 6-39 – Figure 6-26 assume correct configuration of the ATA/CF memory-mapped control registers for the selected ATA/CF frequency of operation. 6.11.2.1 ATA/CF PIO Data Transfer AC Timing Table 6-39. Timings for ATA/CF Module — PIO Data Transfer (1) NO. (2) (see Figure 6-26) 1.05 V and 1.2 V MODE MIN MAX UNIT 1 t0 Cycle time 0-4 (3) (DATSTB + DATRCVR + 2)P - 0.5 ns 2 t1 Address valid to DIOW/ DIOR setup 0-4 (3) 12P - 1.6 ns 3 t2 DIOW/ DIOR pulse duration low 0-4 (3) (DATSTB + 1)P - 1 ns 4 t2i DIOW/DIOR recovery time, pulse duration high 5 6 7 – ns 3-4 (3) 0-2 (DATRCVR + 1)P - 1 ns t3 DIOW data setup time, DD[15:0] valid before DIOW rising edge 0-4 (3) (DATSTB + 1)P ns t4 DIOW data hold time, DD[15:0] valid after DIOW rising edge 0-4 (3) (HWNHLD + 1)P + 1 ns 0 50 ns t5 DIOR data setup time, DD[15:0] valid before DIOR rising edge 1 35 ns 2-4 (3) 20 ns 0-4 (3) 5 ns 8 t6 DIOR data hold time, DD[15:0] valid after DIOR rising edge 9 t6Z Output data 3-state, DD[15:0] 3-state after DIOR rising edge 0-4 (3) 10 t9 DIOW/DIOR to address valid hold 0-4 (3) (HWNHLD + 1)P - 2.1 ns 11 tRD Read data setup time, DD[15:0] valid before IORDY active 0-4 (3) 0 ns 12 tA IORDY setup 0-4 (3) (4) 35 ns 1250 ns 5 ns tB IORDY pulse width 0-4 14 tC IORDY assertion to release 0-4 (3) (3) (4) 146 ns (3) 13 (1) (2) 30 P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns. DATSTB equals the value programmed in the DATSTBxP bit field in the DATSTB register. DATRCVR equals the value programmed in the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21). The sustained throughput for PIO modes 3 and 4 is limited to the throughput equivalent of PIO mode 2. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21). The tA parameter must be met only when the IORDY timer is enabled to allow a device to insert wait states during a transaction. In order to meet the tA parameter, a minimum frequency for SYSCLK5 is specified for each PIO as follows: • PIO mode 0, MIN frequency = 15 MHz • PIO mode 1, MIN frequency = 22 MHz • PIO mode 2, MIN frequency = 31 MHz • PIO mode 3, MIN frequency = 45 MHz • PIO mode 4, MIN frequency = 57 MHz Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 t0 DA[2:0], ATA_CS0, ATA_CS1 t1 t2 t9 DIOW/DIOR t2i t3 t4 DD[15:0](OUT) t6 t5 DD[15:0] (IN) t6Z IORDY(A) tA tRD tC IORDY(B) tC tB IORDY(C) A. IORDY is not negated for transfer (no wait generated) B. IORDY is negative but is re-assert before tA (no wait is generated) C. IORDY is negative before tA and remains asserted until tB; data is driven valid at tRD (wait is generated) Figure 6-26. ATA/CF PIO Data Transfer Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 147 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.11.2.2 ATA/CF Multiword DMA Timing Table 6-40. Timings for ATA/CF Module — Multiword DMA AC Timing (1) NO. (2) (see Figure 6-27) 1.05 V and 1.2 V MODE MIN 1 t0 Cycle time 0-2 (DMASTB + DMARCVR + 2)P - 0.5 2 tD DIOW/DIOR active low pulse duration 0-2 (DMASTB + 1)P - 1 3 4 5 MAX UNIT ns ns 0 150 ns 1 60 ns 2 50 ns tE DIOR data access, DIOR falling edge to DD[15:0] valid tF DIOR data hold time, DD[15:0] valid after DIOR rising edge 0-2 5 ns DIOW/DIOR data setup time, DD[15:0] (OUT) valid before DIOW/DIOR rising edge 0-2 (DMASTB)P ns 0 100 ns 1 30 ns 2 20 ns tG DIOW/DIOR data setup time, DD[15:0] (IN) valid before DIOW/DIOR rising edge 6 tH DIOW data hold time, DD[15:0] valid after DIOW rising edge 7 tI DMACK to DIOW/DIOR setup 0-2 (DMARCVR + 1)P - 1.7 ns 8 tJ DIOW/DIOR to DMACK hold 0-2 5P - 5.9 ns 9 tKR DIOR negated pulse width 0-2 (DMARCVR + 1)P - 1 ns 10 tKW DIOW negated pulse width 0-2 (DMARCVR + 1)P - 1 ns 11 tLR DIOR to DMARQ delay 0-2 (HWNHLD + 1)P + 1 ns 0 120 ns 1 45 ns 2 35 ns 0-1 40 ns 2 35 ns 12 tLW DIOW to DMARQ delay 13 tM ATA_CSx valid to DIOW/DIOR setup 0-2 (DATRCVR)P - 1.7 14 tN ATA_CSx valid after DIOW/DIOR rising edge hold 0-2 5P - 1.7 15 (1) (2) 148 tZ DMACK to read data (DD[15:0]) released ns ns 0 20 ns 1-2 25 ns P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns. DMASTB equals the value programmed in the DMASTBxP bit field in the DMASTB register. DMARCVR equals the value programmed in the DMARCVRxP bit field in the DMARCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21). Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DA[2:0], ATA_CS0, ATA_CS1 t0 tM tN DMARQ tL DMACK tI tD tK DIOW/DIOR tJ tH tG DD[15:0](OUT) tG tZ tF tE DD[15:0] (IN) Figure 6-27. ATA/CF Multiword DMA Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 149 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.11.2.3 ATA/CF Ultra DMA Timing Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing (1) (see Figure 6-28 through Figure 6-37) NO. 28 1 1.05 V and 1.2 V MODE f(SYSCLK5) t2CYCTYP Operating frequency, SYSCLK5 Typical sustained average two cycle time MIN 3 25 MHz 0 240 ns 1 160 ns 2 120 ns 3 90 ns 60 ns Cycle time, Strobe edge to Strobe edge 0-4 (UDMASTB + 1)P ns t2CYC Two cycle time, rising to rising edge or falling to falling edge 0-4 2(UDMASTB + 1)P ns 0 15 ns 1 10 ns 2-3 7 ns tDS Data setup, data valid before STROBE edge 5 tDH Data hold, data valid after STROBE edge 7 UNIT tCYC 4 6 MAX 0-4 4 2 (2) tDVS tDVH Data valid INPUT setup time, data valid before STROBE 4 5 ns 0-4 5 ns 0 70 ns 1 48 ns 2 31 ns 3 20 ns 4 6.7 ns Data valid OUTPUT setup time, data valid before STROBE 0-4 (UDMASTB)P - 3.5 ns Data valid INPUT hold time, data valid after STROBE 0-4 6.2 ns Data valid OUTPUT hold time, data valid after STROBE 0-4 1P - 2 ns 10 tCVS CRC word valid setup time at host, CRC valid before DMACK negation 0-4 (UDMASTB)P ns 11 tCVH CRC word valid hold time at sender, CRC valid after DMACK negation 0-4 2P ns 12 tZFS Time from STROBE output released-to-driving until the first transition of critical timing 0-4 0 ns 0 70 ns 1 48 ns 2 31 ns 3 20 ns 4 6.7 13 14 tDZFS tFS Time from data output released-to-driving until the first transition of critical timing First STROBE time 230 ns 1 200 ns 2 170 ns 3 130 ns 120 ns 150 ns 4 15 (1) (2) 150 tLI Limited interlock time ns 0 0-4 0 P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns. UDMASTB equals the value programmed in the UDMSTBxP bit field in the UDMASTB register. UDMATRP equals the value programmed in the UDMTRPxP bit field in the UDMATRP register. TENV equals the value programmed in the UDMATNVxP bit field in the UDMATENV register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21). Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing (see Figure 6-28 through Figure 6-37) (continued) NO. 1.05 V and 1.2 V MODE MIN MAX UNIT 16 tMLI Interlock time with minimum 0-4 20 ns 17 tUI Unlimited interlock time 0-4 0 ns 18 tAZ Maximum time allowed for output drivers to release 0-4 19 tZAH Minimum delay time required for output 0-4 20 ns 20 tZAD Minimum delay time for driver to assert or negate (from released) 0-4 0 ns 21 tENV Envelope time, DMACK to STOP and DMACK to HDMARDY during in-burst initiation and from DMACK to STOP during data out burst initiation 0-4 (TENV + 1)P - 0.5 22 tRFS Ready-to-final-STROBE time Ready to pause time, (HDMARDY (DIOR) to STOP (DIOW)) 23 tRP Ready to pause time, (DDMARDY (IORDY) to DMARQ) 10 ns (TENV + 1)P + 1.4 ns 0 75 ns 1 70 ns 2-4 60 ns 0-4 (UDMATRP + 1)P - 0.8 ns 0 160 ns 1 125 ns 2-4 100 ns 24 tIORDYZ Maximum time before releasing IORDY 0-4 25 tZIORDY Minimum time before driving IORDY 0-4 0 20 ns ns 26 tACK Setup and hold time for DMACK (before assertion or negation) 0-4 20 ns 27 tSS STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) 0-4 50 ns DMARQ tUI DMACK tFS tACK tENV tZAD STOP (DIOW) (A) tACK tENV HDMARDY (DIOR) (A) tFS tZIORDY tZAD tZFS DSTROBE (IORDY) (A) tDZFS tAZ tDVS tDVH DD[15:0] DA[2:0], ATA_CS0, ATA_CS1 A. tACK The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 6-28. ATA/CF Initiating an Ultra DMA Data-In Burst Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 151 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com t2CYC tCYC(A) tCYC(A) DSTROBE (IORDY) tDH tDS tDS tDH tDH DD[15:0] A. While DSTROBE (IORDY) timing is tCYC at the device, it may be different at the host due to propagation delay differences on the cable. Figure 6-29. ATA/CF Sustained Ultra DMA Data-In Data Transfer Timing DMARQ at Device DMACK at Host STOP (DIOW) at Host tRP HDMARDY (DIOR) at Host tRFS DSTROBE (IORDY) at Device DD[15:0] at Device Figure 6-30. ATA/CF Host Pausing an Ultra DMA Data-In Burst Timing DMARQ tMLI DMACK tLI tACK tLI STOP (DIOW) tLI tACK HDMARDY (DIOR) tSS tIORDYZ DSTROBE (IORDY) tZAH tAZ tCVH tCVS CRC DD[15:0] tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 6-31. ATA/CF Device Terminating an Ultra DMA Data-In Burst Timing 152 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DMARQ tLI tMLI DMACK tACK tRP STOP (DIOW) tZAH tACK tAZ HDMARDY (DIOR) tLI tRFS tMLI tIORDYZ DSTROBE (IORDY) tCVS tCVH CRC DD[15:0] tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 6-32. ATA/CF Host Terminating an Ultra DMA Data-In Burst Timing DMARQ tUI DMACK tACK tENV STOP (DIOW) (A) tLI tZIORDY tUI DDMARDY (IORDY) (A) tACK HSTROBE (DIOR) (A) tDZFS tDVS tDVH DD[15:0] DA[2:0], ATA_CS0, ATA_CS1 A. tACK The definitions for the DIOW:STOP, IORDY:DDMARDY, and DIOR:HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 6-33. ATA/CF Initiating an Ultra DMA Data-Out Burst Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 153 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com t2CYC t2CYC tCYC(A) tCYC(A) HSTROBE (DIOR) tDVS tDVH tDVH tDVS tDVH DD[15:0] (OUT) A. While HSTROBE (DIOR) timing is tCYC at the host, it may be different at the device due to propagation delay differences on the cable. Figure 6-34. ATA/CF Sustained Ultra DMA Data-Out Transfer Timing DMARQ tRP DMACK STOP (DIOW) DDMARDY (IORDY) tRFS HSTROBE (DIOR) DD[15:0] Figure 6-35. ATA/CF Device Pausing an Ultra DMA Data-Out Burst Timing tLI DMARQ tMLI DMACK tLI STOP (DIOW) tACK tSS tLI tIORDYZ DDMARDY (IORDY) tACK HSTROBE (DIOR) tCVS tCVH DD[15:0] CRC tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 6-36. ATA/CF Host Terminating an Ultra DMA Data-Out Burst Timing 154 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DMARQ DMACK tLI tACK tMLI STOP (DIOW) tRP tIORDYZ DDMARDY (IORDY) tRFS tLI tACK tMLI HSTROBE (DIOR) tCVS tCVH DD[15:0] CRC tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 6-37. ATA/CF Device Terminating an Ultra DMA Data-Out Burst Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 155 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.11.2.4 ATA/CF HDDIR Timing Figure 6-38 through Figure 6-41 show the behavior of HDDIR for the different types of transfers. Table 6-42. Timing Requirements for HDDIR (1) 1.05 V and 1.2 V NO. 1 (1) tc Cycle time, ATA_CS[1:0] to HDDIR low MIN MAX E - 3.1 2.1 UNIT ns E = ATA clock cycle DA[2:0], ATA_CS0, ATA_CS1 tC(A) tC(A) HDDIR DIOW DD[15:0] (OUT) A. tC ≥ one cycle Figure 6-38. ATA/CF HDDIR Taskfile Write/Single PIO Write Timing DA[2:0], ATA_CS0, ATA_CS1 tC(A) tC(A) HDDIR DIOW DD[15:0] (OUT) A. tC ≥ one cycle Figure 6-39. ATA/CF HDDIR PIO Postwrite Start Timing 156 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DA[2:0], ATA_CS0, ATA_CS1 DMACK tC(A) tC(A) HDDIR DIOW DD[15:0] (OUT) A. tC ≥ one cycle Figure 6-40. ATA/CF HDDIR Multiword DMA Write Transfer Timing DA[2:0], ATA_CS0, ATA_CS1 DMACK tC(A) HDDIR DIOW DD[15:0] (OUT) CRC A. tC ≥ one cycle Figure 6-41. ATA/CF HDDIR Ultra DMA Write Transfer Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 157 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.12 MMC/SD/SDIO The DM6441 MMC/SD/SDIO controller has following features: • MultiMediaCard (MMC). • Secure Digital (SD) memory card with Secure Data I/O (SDIO). • MMC/SD/SDIO protocol support. • Programmable clock frequency. • 256 bit Read/Write FIFO to lower system overhead. • Slave DMA transfer capability. SDIO is only supported for WLAN operation through TI third parties. For more information about third-party WLAN products, go to http://www.ti.com.davinciwlan. The MMC/SD/SDIO register memory mapping is shown in Table 6-43. 6.12.1 MMC/SD/SDIO Peripheral Description(s) Table 6-43. MMC/SD/SDIO Register Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E1 0000 MMCCTL MMC Control Register 0x01E1 0004 MMCCLK MMC Memory Clock Control Register 0x01E1 0008 MMCST0 MMC Status Register 0 0x01E1 000C MMCST1 MMC Status Register 1 0x01E1 0010 MMCIM MMC Interrupt Mask Register 0x01E1 0014 MMCTOR MMC Response Time-Out Register 0x01E1 0018 MMCTOD MMC Data Read Time-Out Register 0x01E1 001C MMCBLEN MMC Block Length Register 0x01E1 0020 MMCNBLK MMC Number of Blocks Register 0x01E1 0024 MMCNBLC MMC Number of Blocks Counter Register 0x01E1 0028 MMCDRR MMC Data Receive Register 0x01E1 002C MMCDXR MMC Data Transmit Register 0x01E1 0030 MMCCMD MMC Command Register 0x01E1 0034 MMCARGHL MMC Argument Register 0x01E1 0038 MMCRSP01 MMC Response Register 0 and 1 0x01E1 003C MMCRSP23 MMC Response Register 2 and 3 0x01E1 0040 MMCRSP45 MMC Response Register 4 and 5 0x01E1 0044 MMCRSP67 MMC Response Register 6 and 7 0x01E1 0048 MMCDRSP MMC Data Response Register 0x01E1 004C - 0x01E1 004F - Reserved 0x01E1 0050 MMCCIDX MMC Command Index Register 0x01E1 0054 - 0x01E1 0063 - Reserved 0x01E1 0064 SDIOCTL SDIO Control Register 0x01E1 0068 SDIOST0 SDIO Status Register 0 0x01E1 006C SDIOIEN SDIO Interrupt Enable Register 0x01E1 0070 SDIOIST SDIO Interrupt Status Register 0x01E1 0074 MMCFIFOCTL MMC FIFO Control Register 0x01E1 0078 - 0x01E1 FFFF - Reserved 158 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.12.2 MMC/SD/SDIO Electrical Data/Timing Table 6-44. Timing Requirements for MMC/SD/SDIO Module (see Figure 6-43 and Figure 6-45) 1.05 V and 1.2 V NO. MIN MAX UNIT 1 tsu(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK high 5 ns 2 th(CLKH-CMDV) Hold time, SD_CMD valid after SD_CLK high 5 ns 3 tsu(DATV-CLKH) Setup time, SD_DATx valid before SD_CLK high 5 ns 4 th(CLKH-DATV) Hold time, SD_DATx valid after SD_CLK high 5 ns Table 6-45. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO Module (see Figure 6-42 through Figure 6-45) NO. PARAMETER 1.05 V and 1.2 V MIN MAX UNIT 7 f(CLK) Operating frequency, SD_CLK 0 25 MHz 8 f(CLK_ID) Identification mode frequency, SD_CLK 0 400 KHz 9 tW(CLKL) Pulse width, SD_CLK low 10 ns 10 tW(CLKH) Pulse width, SD_CLK high 10 ns 11 tr(CLK) Rise time, SD_CLK 10 ns 12 tf(CLK) Fall time, SD_CLK 10 ns 13 td(CLKLL-CMD) Delay time, SD_CLK low to SD_CMD transition -7.5 13 ns 14 tdis(CLKL-DAT) Disable time, SD_CLK low to SD_DATx transition -7.5 13 ns Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 159 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 9 10 7 SD_CLK 13 13 13 START SD_CMD XMIT Valid Valid 13 Valid END Figure 6-42. MMC/SD/SDIO Host Command Timing 9 7 10 SD_CLK 1 2 START SD_CMD XMIT Valid Valid Valid END Figure 6-43. MMC/SD/SDIO Card Response Timing 9 10 7 SD_CLK 14 14 SD_DATx 14 START D0 D1 14 Dx END Figure 6-44. MMC/SD/SDIO Host Write Timing 9 10 7 SD_CLK 4 4 3 SD_DATx Start 3 D0 D1 Dx End Figure 6-45. MMC/SD/SDIO Host Read and Card CRC Status Timing 160 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.13 Video Processing Sub-System (VPSS) Overview The DM6441 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital LCD panels, HDTV video encoders, etc. Note: The VPSS module is supported with Linux Application Peripheral Interfaces (APIs) commonly used by video application developers. Video for Linux 2 or V4L2 uses APIs commonly used for video capture. The typical use cases of the VPSS Video Front-End (VPFE) have been ported to this Linux API structure. V4L2 supports standard video interfaces such as: BT.656 and Y/C mode. Other modules within the VPSS VPFE for example, the Preview Engine, H3A, and Histogram are not currently supported within the software APIs. The VPSS Back-End (VPBE) uses FBDev/DirectFB as the APIs. Certain functionalities within the VPBE have not been implemented in the FBDev/DirectFB APIs. For modes/functions not implemented in software, it is user's responsibility to modify the software drivers/APIs. The VPSS register memory mapping is shown in Table 6-46. Table 6-46. VPSS Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM Description 0x01C7 3400 PID Peripheral Revision and Class Information 0x01C7 3404 PCR VPSS Control Register 0x01C7 3408 - Reserved 0x01C7 3508 SDR_REG_EXP SDRAM Non Real-Time Read Request Expand - Reserved 0x01C7 350C 0x01C7 3FFF To ensure NTSC- and PAL-compliant output video, the stability of the input clock source is very important. TI recommends a 27-MHz, 50-ppm crystal. Ceramic oscillators are not recommended. The NTSC/PAL color sub-carrier frequency is derived from the 27-MHz clock. Therefore, if the 27-MHz clock drifts, then the color sub-carrier frequency will drift as well. Assuming no 27-MHz frequency drift, the color sub-carrier frequency is generated as follows: æ 35 ö fsc -ntsc = 27 MHz ç ÷ = 3.5795454545 MHz è 264 ø æ 167 ö fsc - pal = 27 MHz ç ÷ = 4.4332628318 MHz è 1017 ø To ensure the color sub-carrier frequency will not drift out of spec, the user must follow the crystal requirements discussed in Section 6.5.1, Clock Input Option 1 – Crystal. Alternatively, if the VPBE input clock is sourced from the VPBECLK or VPFE clock inputs, these clocks must have a frequency stability of ±50 ppm to ensure the NTSC and PAL compliant output video. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 161 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.13.1 Video Processing Front-End (VPFE) The video processing front-end (VPFE) consists of the CCD Controller (CCDC), Preview Engine, Resizer, Hardware 3A (H3A) Statistic Generator, and Histogram blocks. Together, these modules provide DM6441 with a powerful and flexible front-end interface. These modules are briefly described below: • The CCDC provides an interface to image sensors and digital video sources. • The preview engine is a parameterized hardwired image processing block which is used for converting RAW color data from a Bayer pattern to YUV 4:2:2. • The resizer module re-sizes the input image data to the desired display or video encoding resolution • The H3A module provides control loops for auto focus (AF), auto white balance (AWB) and auto exposure (AE). • The histogram module bins input color pixels, depending on the amplitude, and provides statistics required to implement various 3A (AE/AF/AWB) algorithms and tune the final image/video output. The VPFE register memory mapping is shown in Table 6-47. Table 6-47. VPFE Register Address Range Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C7 0400 – 0x01C7 07FF CCDC VPFE – CCD Controller 0x01C7 0800 – 0x01C7 0BFF PREV VPFE – Preview Engine/Image Signal Processor 0x01C7 0C00 – 0x01C7 09FF RESZ VPFE – Resizer 0x01C7 1000 – 0x01C7 13FF HIST VPFE – Histogram 0x01C7 1400 – 0x01C7 17FF H3A VPFE – Hardware 3A (Auto-Focus/WB/Exposure) 0x01C7 3400 – 0x01C7 3FFF VPSS VPSS Shared Buffer Logic Registers 6.13.1.1 CCD Controller (CCDC) The CCDC receives raw image/video data from sensors (CMOS or CCD) or YUV video data in numerous formats from video decoder devices. The following features are supported by the CCDC module. • Conventional Bayer pattern formats. • Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to an external timing generator. • Interface to progressive and interlaced sensors. • REC656/CCIR-656 standard (YCbCr 4:2:2 format, either 8- or 16-bit). • YCbCr 4:2:2 format, either 8- or 16-bit with discrete H and VSYNC signals. • Up to 16-bit input. • Optical black clamping signal generation. • Shutter signal control. • Digital clamping and black level compensation. • 10-bit to 8-bit A-law compression. • Low-pass filter prior to writing to SDRAM. If this filter is enabled, two pixels each in the left and right edges of each line are cropped from the output. • Output range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area). • Downsampling via programmable culling patterns. • Control output to the DDR2 via an external write enable signal. • Up to 16K pixels (image size) in both the horizontal and vertical direction. The CCDC register memory mapping is shown in Table 6-48. 162 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-48. CCDC Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0400 PID Peripheral Revision and Class Information 0x01C7 0404 PCR Peripheral Control Register 0x01C7 0408 SYN_MODE SYNC and Mode Set Register 0x01C7 040C HD_VD_WID HD and VD Signal Width 0x01C7 0410 PIX_LINES Number of Pixels in a Horizontal Line and Number of Lines in a Frame 0x01C7 0414 HORZ_INFO Horizontal Pixel Information 0x01C7 0418 VERT_START Vertical Line - Settings for the Starting Pixel 0x01C7 041C VERT_LINES Number of Vertical Lines 0x01C7 0420 CULLING Culling Information in Horizontal and Vertical Directions 0x01C7 0424 HSIZE_OFF Horizontal Size 0x01C7 0428 SDOFST SDRAM/DDRAM Line Offset 0x01C7 042C SDR_ADDR SDRAM Address 0x01C7 0430 CLAMP Optical Black Clamping Settings 0x01C7 0434 DCSUB DC Clamp 0x01C7 0438 COLPTN CCD Color Pattern 0x01C7 043C BLKCMP Black Compensation 0x01C7 0440 - Reserved 0x01C7 0444 - Reserved 0x01C7 0448 VDINT VD Interrupt Timing 0x01C7 044C ALAW A-Law Setting 0x01C7 0450 REC656IF REC656 Interface 0x01C7 0454 CCDCFG CCD Configuration 0x01C7 0458 FMTCFG Data Reformatter/Video Port Configuration 0x01C7 045C FMT_HORZ Data Reformatter/Video Input Interface Horizontal Information 0x01C7 0460 FMT_VERT Data Reformatter/Video Input Interface Vertical Information 0x01C7 0464 FMT_ADDR0 Address Pointer 0 Setup 0x01C7 0468 FMT_ADDR1 Address Pointer 1 Setup 0x01C7 046C FMT_ADDR2 Address Pointer 2 Setup 0x01C7 0470 FMT_ADDR3 Address Pointer 3 Setup 0x01C7 0474 FMT_ADDR4 Address Pointer 4 Setup 0x01C7 0478 FMT_ADDR5 Address Pointer 5 Setup 0x01C7 047C FMT_ADDR6 Address Pointer 6 Setup 0x01C7 0480 FMT_ADDR7 Address Pointer 7 Setup 0x01C7 0484 PRGEVEN_0 Program Entries 0-7 for Even Line 0x01C7 0488 RRGEVEN_1 Program Entries 8-15 for Even Line 0x01C7 048C PRGGODD_0 Program Entries 0-7 for Odd Line 0x01C7 0490 PRGGODD_1 Program Entries 8-15 for Odd Line 0x01C7 0494 VP_OUT Video Port Output Settings Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 163 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.13.1.2 Preview Engine The preview engine transforms raw unprocessed image/video data from a sensor (CMOS or CCD) into YCbCr 4:2:2 data. The output of the preview engine is used for both video compression and external display devices such as a NTSC/PAL analog encoder or a digital LCD. The following features are supported by the preview engine. • Accepts conventional Bayer pattern formats. • Input image/video data from either the CCD/CMOS controller or the DDR2 memory. • Output width up to 1280 pixels wide. • Automatic/mandatory cropping of pixels/lines when edge processing is performed. If all the corresponding modules are enabled, a total of 14 pixels per line (seven left most and seven right most) and eight lines (four top most and four bottom most) will not be output. • Simple horizontal averaging (by factors of 2, 4, or 8) to handle input widths that are greater than 1280 (plus the cropped number) pixels wide. • Dark frame capture to DDR2. • Dark frame subtraction for every input raw data frame, fetched from DDR2, pixel-by-pixel to improve video quality. • Lens shading compensation. Each input pixel is multiplied with a corresponding 8-bit gain value and the result is right shifted by a programmable parameter (0-7 bits). • A-law decompression to transform non-linear 8-bit data to 10-bit linear data. This feature allows data in DDR2 to be 8-bits, which saves 50% of the area if the input to the preview engine is from the DDR2. • Horizontal median filter for reducing temperature induced noise in pixels. • Programmable noise filter that operates on a 3x3 grid of the same color (effectively, this is a five line storage requirement). • Digital gain and white balance (color separate gain for white balance). • Programmable CFA interpolation that operates on a 5x5 grid. • Conventional Bayer pattern RGB and complementary color sensors. • Support for an image that is downsampled by 2x in the horizontal direction (with and without phase correction). In this case, the image is 2/3 populated instead of the conventional 1/3 colors. • Support for an image that is downsampled by 2x in both the horizontal and vertical direction. In this case, the image is fully populated instead of the conventional 1/3 colors. • Programmable RGB-to-RGB blending matrix (nine coefficients for the 3x3 matrix). • Fully programmable gamma correction (1024 entries for each color held in an on-chip RAM). • Programmable color conversion (RGB to YUV) coefficients (nine coefficients for the 3x3 matrix). • Luminance enhancement (non-linear) and chrominance suppression & offset. The preview engine register memory mapping is shown in Table 6-49. Table 6-49. Preview Engine Register Descriptions HEX ADDRESS RANGE 164 REGISTER ACRONYM DESCRIPTION 0x01C7 0800 PID Peripheral Revision and Class Information 0x01C7 0804 PCR Peripheral Control Register 0x01C7 0808 HORZ_INFO Horizontal Information/Setup 0x01C7 080C VERT_INFO Vertical Information/Setup 0x01C7 0810 RSDR_ADDR Read Address From SDRAM 0x01C7 0814 RADR_OFFSET Line Offset for the Read Data 0x01C7 0818 DSDR_ADDR Dark Frame Address From SDRAM 0x01C7 081C DRKF_OFFSET Line Offset for the Dark Frame Data 0x01C7 0820 WSDR_ADDR Write Address to the SDRAM 0x01C7 0824 WADD_OFFSET Line Offset for the Write Data Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-49. Preview Engine Register Descriptions (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0828 AVE Input Formatter/Averager 0x01C7 082C HMED Horizontal Median Filter 0x01C7 0830 NF Noise Filter 0x01C7 0834 WB_DGAIN White Balance Digital Gain 0x01C7 0838 WBGAIN White Balance Coefficients 0x01C7 083C WBSEL White Balance Coefficients Selection 0x01C7 0840 CFA CFA Register 0x01C7 0844 BLKADJOFF Black Adjustment Offset 0x01C7 0848 RGB_MAT1 RGB2RGB Blending Matrix Coefficients 0x01C7 084C RGB_MAT2 RGB2RGB Blending Matrix Coefficients 0x01C7 0850 RGB_MAT3 RGB2RGB Blending Matrix Coefficients 0x01C7 0854 RGB_MAT4 RGB2RGB Blending Matrix Coefficients 0x01C7 0858 RGB_MAT5 RGB2RGB Blending Matrix Coefficients 0x01C7 085C RGB_OFF1 RGB2RGB Blending Matrix Offsets 0x01C7 0860 RGB_OFF2 RGB2RGB Blending Matrix Offsets 0x01C7 0864 CSC0 Color Space Conversion Coefficients 0x01C7 0868 CSC1 Color Space Conversion Coefficients 0x01C7 086C CSC2 Color Space Conversion Coefficients 0x01C7 0870 CSC_OFFSET Color Space Conversion Offsets 0x01C7 0874 CNT_BRT Contrast and Brightness Settings 0x01C7 0878 CSUP Chrominance Suppression Settings 0x01C7 087C SETUP_YC Maximum/Minimum Y and C Settings 0x01C7 0880 SET_TBL_ADDRESS Setup Table Addresses 0x01C7 0884 SET_TBL_DATA Setup Table Data 6.13.1.3 Resizer The resizer module can accept input image/video data from either the preview engine or DDR2. The output of the resizer module is sent to DDR2. The following features are supported by the resizer module. • An output width up to 1280 horizontal pixels. • Input from external DDR2. • Up to 4x upsampling (digital zoom). • Bi-cubic interpolation (4-tap horizontal, 4-tap vertical) can be implemented with the programmable filter coefficients. • Eight phases of filter coefficients. • Optional bi-linear interpolation for the chrominance components. • Up to 1/4x downsampling • 4-tap horizontal and 4-tap vertical filter coefficients (with 8-phases) for 1x to 1/2x downsampling • 1/2x to 1/4x downsampling, for 7-tap mode with 4-phases. • Resizing either YUV 4:2:2 packed data (16-bits) or color separate data (8-bit data within DDR) that is contiguous. • Separate/independent resizing factor for the horizontal and vertical directions. • Upsampling and downsampling ratios that are available are: 256/N, with N ranging from 64 to 1024. • Programmable luminance sharpening after the horizontal resizing and before the vertical resizing step. The resizer register memory mapping is shown in Table 6-50. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 165 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-50. Resizer Register Descriptions HEX ADDRESS RANGE 166 REGISTER ACRONYM DESCRIPTION 0x01C7 0C00 PID Peripheral Revision and Class Information 0x01C7 0C04 PCR Peripheral Control Register 0x01C7 0C08 RSZ_CNT Resizer Control Bits 0x01C7 0C0C OUT_SIZE Output Width and Height After Resizing 0x01C7 0C10 IN_START Input Starting Information 0x01C7 0C14 IN_SIZE Input Width and Height Before Resizing 0x01C7 0C18 SDR_INADD Input SDRAM Address 0x01C7 0C1C SDR_INOFF SDRAM Offset for the Input Line 0x01C7 0C20 SDR_OUTADD Output SDRAM Address 0x01C7 0C24 SDR_OUTOFF SDRAM Offset for the Output Line 0x01C7 0C28 HFILT10 Horizontal Filter Coefficients 1 and 0 0x01C7 0C2C HFILT32 Horizontal Filter Coefficients 3 and 2 0x01C7 0C30 HFILT54 Horizontal Filter Coefficients 5 and 4 0x01C7 0C34 HFILT76 Horizontal Filter Coefficients 7 and 6 0x01C7 0C38 HFILT98 Horizontal Filter Coefficients 9 and 8 0x01C7 0C3C HFILT1110 Horizontal Filter Coefficients 11 and 10 0x01C7 0C40 HFILT1312 Horizontal Filter Coefficients 13 and 12 0x01C7 0C44 HFILT1514 Horizontal Filter Coefficients 15 and 14 0x01C7 0C48 HFILT1716 Horizontal Filter Coefficients 17 and 16 0x01C7 0C4C HFILT1918 Horizontal Filter Coefficients 19 and 18 0x01C7 0C50 HFILT2120 Horizontal Filter Coefficients 21 and 20 0x01C7 0C54 HFILT2322 Horizontal Filter Coefficients 23 and 22 0x01C7 0C58 HFILT2524 Horizontal Filter Coefficients 25 and 24 0x01C7 0C5C HFILT2726 Horizontal Filter Coefficients 27 and 26 0x01C7 0C60 HFILT2928 Horizontal Filter Coefficients 29 and 28 0x01C7 0C64 HFILT3130 Horizontal Filter Coefficients 31 and 30 0x01C7 0C68 VFILT10 Vertical Filter Coefficients 1 and 0 0x01C7 0C6C VFILT32 Vertical Filter Coefficients 3 and 2 0x01C7 0C70 VFILT54 Vertical Filter Coefficients 5 and 4 0x01C7 0C74 VFILT76 Vertical Filter Coefficients 7 and 6 0x01C7 0C78 VFILT98 Vertical Filter Coefficients 9 and 8 0x01C7 0C7C VFILT1110 Vertical Filter Coefficients 11 and 10 0x01C7 0C80 VFILT1312 Vertical Filter Coefficients 13 and 12 0x01C7 0C84 VFILT1514 Vertical Filter Coefficients 15 and 14 0x01C7 0C88 VFILT1716 Vertical Filter Coefficients 17 and 16 0x01C7 0C8C VFILT1918 Vertical Filter Coefficients 19 and 18 0x01C7 0C90 VFILT2120 Vertical Filter Coefficients 21 and 20 0x01C7 0C94 VFILT2322 Vertical Filter Coefficients 23 and 22 0x01C7 0C98 VFILT2524 Vertical Filter Coefficients 25 and 24 0x01C7 0C9C VFILT2726 Vertical Filter Coefficients 27 and 26 0x01C7 0CA0 VFILT2928 Vertical Filter Coefficients 29 and 28 0x01C7 0CA4 VFILT3130 Vertical Filter Coefficients 31 and 30 0x01C7 0CA8 YENH Luminance Enhancer Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.13.1.4 Hardware 3A (H3A) The Hardware 3A (H3A) module provides control loops for Auto Focus, Auto White Balance and Auto Exposure. There are 2 main components of the H3A module: • Auto focus (AF) engine • Auto exposure (AE) & auto white balance (AWB) engine The AF engine extracts and filters the Red, Green, and Blue data from the input image/video data and provides either the accumulation or peaks of the data in a specified region. The specified region is a two dimensional block of data and is referred to as a “paxel” for the case of AF. The AE/AWB engine accumulates the values and checks for saturated values in a sub sampling of the video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a “window”. The number, dimensions, and starting position of the AF paxels and the AE/AWB windows are separately programmable. The H3A register memory mapping is shown in Table 6-51. Table 6-51. H3A Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 1400 PID Peripheral Revision and Class Information 0x01C7 1404 PCR Peripheral Control Register 0x01C7 1408 AFPAX1 Setup for the AF Engine Paxel Configuration 0x01C7 140C AFPAX2 Setup for the AF Engine Paxel Configuration 0x01C7 1410 AFPAXSTART Start Position for AF Engine Paxels 0x01C7 1414 AFIIRSH Start Position for IIRSH 0x01C7 1418 AFBUFST SDRAM/DDRAM Start Address for AF Engine 0x01C7 141C AFCOEF010 IIR Filter Coefficient Data for SET 0 0x01C7 1420 AFCOEF032 IIR Filter Coefficient Data for SET 0 0x01C7 1424 AFCOEFF054 IIR Filter Coefficient Data for SET 0 0x01C7 1428 AFCOEFF076 IIR Filter Coefficient Data for SET 0 0x01C7 142C AFCOEFF098 IIR Filter Coefficient Data for SET 0 0x01C7 1430 AFCOEFF0010 IIR Filter Coefficient Data for SET 0 0x01C7 1434 AFCOEF110 IIR Filter Coefficient Data for SET 1 0x01C7 1438 AFCOEF132 IIR Filter Coefficient Data for SET 1 0x01C7 143C AFCOEFF154 IIR Filter Coefficient Data for SET 1 0x01C7 1440 AFCOEFF176 IIR Filter Coefficient Data for SET 1 0x01C7 1444 AFCOEFF198 IIR Filter Coefficient Data for SET 1 0x01C7 1448 AFCOEFF1010 IIR Filter Coefficient Data for SET 1 0x01C7 144C AEWWIN1 Configuration for AE/AWB Windows 0x01C7 1450 AEWINSTART Start Position for AE/AWB Windows 0x01C7 1454 AEWINBLK Start Position and Height for Black Line of AE/AWB Windows 0x01C7 1458 AEWSUBWIN Configuration for Subsample Data in AE/AWB Window 0x01C7 145C AEWBUFST SDRAM/DDRAM Start Address for AE/AWB Engine Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 167 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.13.1.4.1 Auto Focus (AF) Engine The following features are supported by the auto focus (AF) engine. • Peak mode in a paxel (a paxel is defined as a two dimensional block of pixels). • Accumulate the maximum focus value of each line in a paxel • Accumulation/Sum mode (instead of peak mode). • Accumulate focus value in a paxel. • Up to 36 paxels in the horizontal direction and up to 128 paxels in the vertical direction. • Programmable width and height for the paxel. All paxels in the frame will be of same size. • Programmable Red, Green, and Blue position within a 2x2 matrix. • Separate horizontal start for paxel and filtering. • Programmable vertical line increments within a paxel. • Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11 coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on. 6.13.1.4.2 Auto Exposure (AE) and Auto White Balance (AWB) Engine The following features are supported by the auto exposure (AE) and auto white balance (AWB) engine. • Accumulate clipped pixels along with all non-saturated pixels. • Up to 36 horizontal windows. • Up to 128 vertical windows. • Programmable width and height for the windows. All windows in the frame will be of same size. • Separate vertical start coordinate and height for a black row of paxels that is different than the remaining color paxels. • Programmable horizontal sampling points in a window. • Programmable vertical sampling points in a window. 168 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.13.1.5 Histogram The histogram module accepts raw image/video data and bins the pixels on a value (and color separate) basis. The value of the pixel itself is not stored, but each bin contains the number of pixels that are within the appropriate set range. The source of the raw data for the histogram is typically a CCD/CMOS sensor (via the CCDC module) or optionally from DDR2. The following features are supported by the histogram module. • Up to four regions/areas. • Separate horizontal/vertical start and end position for each region. • Pixels from overlapping regions are accumulated into the highest priority region. The priority is: region0 > region1 > region2 > region3. • Interface to conventional Bayer pattern. Each region can accumulate either three or four colors. • 32, 64, 128, or 256 bins per color per region. • 32, 64, or 128 bins per color for two regions. • 32 or 64 bins per color for three or four regions. • Automatic clear of histogram RAM after an ARM read. • Saturation of the pixel count if the count exceeds the maximum value (each memory location is 20-bit wide). • Downshift ranging from 0 to 7 bits (maximum bin range 128). • The last bin (highest range of values) will accumulate any value that is higher than the lower bound. The Histogram register memory mapping is shown in Table 6-52. Table 6-52. Histogram Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 1000 PID Peripheral Revision and Class Information Register 0x01C7 1004 PCR Peripheral Control Register 0x01C7 1008 HIST_CNT Histogram Control Bits Register 0x01C7 100C WB_GAIN White/Channel Balance Settings Register 0x01C7 1010 R0_HORZ Region 0 Horizontal Information Register 0x01C7 1014 R0_VERT Region 0 Vertical Information Register 0x01C7 1018 R1_HORZ Region 1 Horizontal Information Register 0x01C7 101C R1_VERT Region 1 Vertical Information Register 0x01C7 1020 R2_HORZ Region 2 Horizontal Information Register 0x01C7 1024 R2_VERT Region 2 Vertical Information Register 0x01C7 1028 R3_HORZ Region 3 Horizontal Information Register 0x01C7 102C R3_VERT Region 3 Vertical Information Register 0x01C7 1030 HIST_ADDR Histogram Address for Data to be Read Register 0x01C7 1034 HIST_DATA Histogram Data That is Read From the Memory Register 0x01C7 1038 RADD Read Address From DDR2 Memory Register 0x01C7 103C RADD_OFF Read Address Offset for Each Line in the DDR2 Memory Register 0x01C7 1040 H_V_INFO Horizontal/Vertical Information Register (Horizontal/Vertical Number of Pixels When Data is Read From DDR2 Memory Information Register) Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 169 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.13.1.6 VPFE Electrical Data/Timing Table 6-53. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 6-46) 1.05 V and 1.2 V NO. (1) MIN MAX UNIT 10.204 or 13.33 (1) ns Pulse duration, PCLK high 4.4 ns tw(PCLKL) Pulse duration, PCLK low 4.4 tt(PCLK) Transition time, PCLK 1 tc(PCLK) Cycle time, PCLK 2 tw(PCLKH) 3 4 ns 3 ns When PCLK sources the clock for both the VPFE and VPBE, the minimum cycle time of 13.33 ns (specified in Table 6-60, Timing Requirements for VPBE CLK Inputs for VPBE) must be met. When PCLK sources the clock for only the VPFE, a minimum cycle time of 10.2 ns may be used. 2 3 1 PCLK 4 4 Figure 6-46. VPFE PCLK Timing Table 6-54. Timing Requirements for VPFE (CCD) Slave Mode (1) (see Figure 6-47) 1.05 V and 1.2 V NO. MIN MAX UNIT 5 tsu(CCDV-PCLK) Setup time, CCD valid before PCLK edge 3 ns 6 th(PCLK-CCDV) Hold time, CCD valid after PCLK edge 2 ns 7 tsu(HDV-PCLK) Setup time, HD valid before PCLK edge 3 ns 8 th(PCLK-HDV) Hold time, HD valid after PCLK edge 2 ns 9 tsu(VDV-PCLK) Setup time, VD valid before PCLK edge 3 ns 10 th(PCLK-VDV) Hold time, VD valid after PCLK edge 2 ns 11 tsu(C_WEV-PCLK) Setup time, C_WE valid before PCLK edge 3 ns 12 th(PCLK-C_WEV) Hold time, C_WE valid after PCLK edge 2 ns 13 tsu(C_FIELDV-PCLK) Setup time, C_FIELD valid before PCLK edge 3 ns 14 th(PCLK-C_FIELDV) Hold time, C_FIELD valid after PCLK edge 2 ns (1) 170 The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 8, 10 7, 9 HD/VD 11, 13 12, 14 C_WE/C_FIELD 5 6 CCD[15:0] Figure 6-47. VPFE (CCD) Slave Mode Input Data Timing Table 6-55. Timing Requirements for VPFE (CCD) Master Mode (1) (see Figure 6-48) 1.05 V and 1.2 V NO. (1) MIN MAX UNIT 15 tsu(CCDV-PCLK) Setup time, CCD valid before PCLK edge 3 ns 16 th(PCLK-CCDV) Hold time, CCD valid after PCLK edge 2 ns 23 tsu(CWEV-PCLK) Setup time, C_WE valid before PCLK edge 3 ns 24 th(PCLK-CWEV) Hold time, C_WE valid after PCLK edge 2 ns The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced. PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 15 16 CCD[15:0] 23 24 C_WE Figure 6-48. VPFE (CCD) Master Mode Input Data Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 171 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-56. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master Mode (see Figure 6-49) NO. 1.05 V PARAMETER 1.2 V MIN MAX MIN MAX UNIT 18 td(PCLKL-HDIV) Delay time, PCLK low to HD invalid 0.5 8 0.5 8 ns 20 td(PCLKL-VDIV) Delay time, PCLK low to VD invalid 0.5 8 0.5 8 ns 22 td(PCLKL-C_FIELDIV) Delay time, PCLK low to C_FIELD invalid 0.5 8.9 0.5 8.3 ns PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 18 HD 20 VD 22 C_FIELD Figure 6-49. VPFE (CCD) Master Mode Control Output Data Timing 172 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.13.2 Video Processing Back-End (VPBE) The video processing back-end (VPBE) consists of the on-screen display (OSD) module, the video encoder (VENC) including the digital LCD (DLCD) and analog (i.e., DAC) interfaces. The video encoder generates analog video output. The DLCD controller generates digital RGB/YCbCr data output and timing signals. The VPBE register memory mapping is shown in Table 6-57. Table 6-57. VPBE Register Descriptions Address Register Description 0x01C7 2780 PID Peripheral Revision and Class Information Register 0x01C7 2784 PCR Peripheral Control Register 6.13.2.1 On-Screen Display (OSD) The major function of the OSD module is to gather and blend video data and display/bitmap data before feeding it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from an external memory, typically DDR2. The OSD is programmed via control and parameter registers. The following are the primary features that are supported by the OSD. • Simultaneous display of two video windows and two OSD windows (VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1). – Separate enable for each window – Programmable width, height, and base starting coordinates for each window – External memory address and offset registers for each window – Support for x2 and x4 zoom in both the horizontal and vertical direction – OSDWIN1 can be used as an attribute window for OSDWIN0 – Attribute window blinking intervals – Field/frame mode for the windows (interlaced/progressive) – Eight step blending process between the OSD and video windows – Transparency support for the OSD and video data (when a bitmap pixel is zero, there will be no blending for that corresponding video pixel) – Resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows – Reads in YCbCr data in 4:2:2 format from external memory, with the capability for swapping the order of the CbCr component in the 32-bit word (this is relevant to the two video windows) – Support for a ping-pong buffer scheme that can be used for VIDWIN0 (allows for video data to be accessed from two different locations in DDR2) – Each OSD window (either one, but not both at the same time) is capable of reading in RGB data (16-bit data with six bits for the Green and five bits each for the Red and Blue colors) instead of bitmap data in YCbCr format restricted to a maximum of 8-bits – The OSD bitmap data width is selectable between 1, 2, 4, or 8-bits. – Each OSD window supports 16 entries for the bitmap (to index into a 256 entry RAM/ROM CLUT table). – Indirect support for 24-bit RGB input data (which will be transformed into 16-bit YCbCr video window data) via the wrapper interface in the VPBE. • Support for a rectangular cursor window and a programmable background color selection. – Programmable color palette with the ability to select between a RAM/ROM table with support for 256 colors. – The width, height, and color of the cursor is programmable. – The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 > background color • Support for attenuation of the YCbCr values for the REC601 standard. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 173 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com The following restrictions exist in the OSD module. • Both the OSD windows and VIDWIN1 should be fully contained inside VIDWIN0. • When one of the OSD windows is set in RGB mode, it cannot overlap with VIDWIN1. • The OSD cannot support more than 256 color entries in the CLUT RAM/ROM. Some applications require higher number of entries, and one workaround is to use VIDWIN1 as an overlay mimicking the OSD window. Another option is to use the RGB mode for one of the OSD windows which allows for a total of 16-bits for the R, G, and B colors (64K colors). • The OSD can only read YCbCr in 4:2:2 interleaved format for the video windows. Other formats, either color separate storage or 4:4:4/4:2:0 interleaved data is not supported. • If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 720 currently. • It is not possible to use both of the CLUT ROMs at the same time. However, one window can use RAM while another uses ROM. • The 24-bit RGB input mode is only valid for one of the two video windows (programmable) and does not apply to the OSD windows. The OSD register memory mapping is shown in Table 6-58. Table 6-58. OSD Register Descriptions Address 174 Register Description 0x01C7 2600 MODE OSD Mode Register 0x01C7 2604 VIDWINMD Video Window Mode Setup 0x01C7 2608 OSDWIN0MD OSD Window Mode Setup 0x01C7 260C OSDWIN1MD OSD Window 1 Mode Setup (when used as a second OSD window) 0x01C7 260C OSDATRMD OSD Attribute Window Mode Setup (when used as an attribute window) 0x01C7 2610 RECTCUR Rectangular Cursor Setup 0x01C7 2614 RSV0 Reserved 0x01C7 2618 VIDWIN0OFST Video Window 0 Offset 0x01C7 261C VIDWIN1OFST Video Window 1 Offset 0x01C7 2620 OSDWIN0OFST OSD Window 0 Offset 0x01C7 2624 OSDWIN1OFST OSD Window 1 Offset 0x01C7 2628 RSV1 Reserved 0x01C7 262C VIDWIN0ADR Video Window 0 Address 0x01C7 2630 VIDWIN1ADR Video Window 1 Address 0x01C7 2634 RSV2 Reserved 0x01C7 2638 OSDWIN0ADR OSD Window 0 Address 0x01C7 263C OSDWIN1ADR OSD Window 1 Address 0x01C7 2640 BASEPX Base Pixel X 0x01C7 2644 BASEPY Base Pixel Y 0x01C7 2648 VIDWIN0XP Video Window 0 X-Position 0x01C7 264C VIDWIN0YP Video Window 0 Y-Position 0x01C7 2650 VIDWIN0XL Video Window 0 X-Size 0x01C7 2654 VIDWIN0YL Video Window 0 Y-Size 0x01C7 2658 VIDWIN1XP Video Window 1 X-Position 0x01C7 265C VIDWIN1YP Video Window 1 Y-Position 0x01C7 2660 VIDWIN1XL Video Window 1 X-Size 0x01C7 2664 VIDWIN1YL Video Window 1 Y-Size 0x01C7 2668 OSDWIN0XP OSD Bitmap Window 0 X-Position 0x01C7 266C OSDWIN0YP OSD Bitmap Window 0 Y-Position 0x01C7 2670 OSDWIN0XL OSD Bitmap Window 0 X-Size Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-58. OSD Register Descriptions (continued) 0x01C7 2674 OSDWIN0YL OSD Bitmap Window 0 Y-Size 0x01C7 2678 OSDWIN1XP OSD Bitmap Window 1 X-Position 0x01C7 267C OSDWIN1YP OSD Bitmap Window 1 Y-Position 0x01C7 2680 OSDWIN1XL OSD Bitmap Window 1 X-Size 0x01C7 2684 OSDWIN1YL OSD Bitmap Window 1 Y-Size 0x01C7 2688 CURXP Rectangular Cursor Window X-Position 0x01C7 268C CURYP Rectangular Cursor Window Y-Position 0x01C7 2690 CURXL Rectangular Cursor Window X-Size 0x01C7 2694 CURYL Rectangular Cursor Window Y-Size 0x01C7 2698 RSV3 Reserved 0x01C7 269C RSV4 Reserved 0x01C7 26A0 W0BMP01 Window 0 Bitmap Value to Palette Map 0/1 0x01C7 26A4 W0BMP23 Window 0 Bitmap Value to Palette Map 2/3 0x01C7 26A8 W0BMP45 Window 0 Bitmap Value to Palette Map 4/5 0x01C7 26AC W0BMP67 Window 0 Bitmap Value to Palette Map 6/7 0x01C7 26B0 W0BMP89 Window 0 Bitmap Value to Palette Map 8/9 0x01C7 26B4 W0BMPAB Window 0 Bitmap Value to Palette Map A/B 0x01C7 26B8 W0BMPCD Window 0 Bitmap Value to Palette Map C/D 0x01C7 26BC W0BMPEF Window 0 Bitmap Value to Palette Map E/F 0x01C7 26C0 W1BMP01 Window 1 Bitmap Value to Palette Map 0/1 0x01C7 26C4 W1BMP23 Window 1 Bitmap Value to Palette Map 2/3 0x01C7 26C8 W1BMP45 Window 1 Bitmap Value to Palette Map 4/5 0x01C7 26CC W1BMP67 Window 1 Bitmap Value to Palette Map 6/7 0x01C7 26D0 W1BMP89 Window 1 Bitmap Value to Palette Map 8/9 0x01C7 26D4 W1BMPAB Window 1 Bitmap Value to Palette Map A/B 0x01C7 26D8 W1BMPCD Window 1 Bitmap Value to Palette Map C/D 0x01C7 26DC W1BMPEF Window 1 Bitmap Value to Palette Map E/F 0x01C7 26E0 - Reserved 0x01C7 26E4 RSV5 Reserved 0x01C7 26E8 MISCCTL Miscellaneous Control 0x01C7 26EC CLUTRAMYCB CLUT RAMYCB Setup 0x01C7 26F0 CLUTRAMCR CLUT RAM Setup 0x01C7 26F4 TRANSPVAL CLUT RAM Setup 0x01C7 26F8 RSV6 Reserved 0x01C7 26FC PPVWIN0ADR Ping-Pong Video Window 0 Address Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 175 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.13.2.2 Video Encoder (VENC) Analog/DACs interface of the video encoder (VENC) supports the following features. • Master clock input - 27MHz (x2 Upsampling) • SDTV support – Composite NTSC-M, PAL-B/D/G/H/I – S-video (Y/C) – Component YPbPr (SMPTE/EBU N10, Betacam, MII) – RGB – Non-interlace – CGMS/WSS – Line 21 closed caption data encoding – Chroma low pass filter 1.5MHz/3MHz – Programmable SC-H phase • HDTV support – Progressive output (525p/625p) – Component YPbPr – RGB – CGMS/WSS • 4 10-bit over-sampling D/A converters • Optional 7.5% pedestal • 16-235/0-255 input amplitude selectable • Programmable luma delay • Master/slave operation • Internal color bar generation (100%/75%) The digital LCD controller (DLCD) of the VENC supports the following features. • Programmable DCLK • Various output formats – YCbCr 16-bit – YCbCr 8-bit – ITU-R BT. 656 – Parallel RGB 24-bit • Low pass filter for digital RGB output • Programmable timing generator • Master/slave operation • Internal color bar generation (100%/75%) The VENC register memory mapping including the digital LCD and DACs is shown in Table 6-59. 176 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-59. VENC (Including Digital LCD and DACs) Register Descriptions ADDRESS REGISTER DESCRIPTION 0x01C7 2400 VMOD Video Mode 0x01C7 2404 VIDCTL Video Interface I/O Control 0x01C7 2408 VDPRO Video Data Processing 0x01C7 240C SYNCCTL Sync Control 0x01C7 2410 HSPLS Horizontal Sync Pulse Width 0x01C7 2414 VSPLS Vertical Sync Pulse Width 0x01C7 2418 HINT Horizontal Interval 0x01C7 241C HSTART Horizontal Valid Data Start Position 0x01C7 2420 HVALID Horizontal Data Valid Range 0x01C7 2424 VINT Vertical Interval 0x01C7 2428 VSTART Vertical Valid Data Start Position 0x01C7 242C VVALID Vertical Data Valid Range 0x01C7 2430 HSDLY Horizontal Sync Delay 0x01C7 2434 VSDLY Vertical Sync Delay 0x01C7 2438 YCCTL YCbCr Control 0x01C7 243C RGBCTL RGB Control 0x01C7 2440 RGBCLP RGB Level Clipping 0x01C7 2444 LINECTL Line Id Control 0x01C7 2448 CULLLINE Culling line control 0x01C7 244C LCDOUT LCD Output Signal Control 0x01C7 2450 BRTS Brightness Start Position Signal Control 0x01C7 2454 BRTW Brightness Width Signal Control 0x01C7 2458 ACCTL LCD_AC Signal Control 0x01C7 245C PWMP PWM Start Position Signal Control 0x01C7 2460 PWMW PWM Width Signal Control 0x01C7 2464 DCLKCTL DCLK Control 0x01C7 2468 DCLKPTN0 DCLK Pattern 0 0x01C7 246C DCLKPTN1 DCLK Pattern 1 0x01C7 2470 DCLKPTN2 DCLK Pattern 2 0x01C7 2474 DCLKPTN3 DCLK Pattern 3 0x01C7 2478 DCLKPTN0A DCLK Auxiliary Pattern 0 0x01C7 247C DCLKPTN1A DCLK Auxiliary Pattern 1 0x01C7 2480 DCLKPTN2A DCLK Auxiliary Pattern 2 0x01C7 2484 DCLKPTN3A DCLK Auxiliary Pattern 3 0x01C7 2488 DCLKHS Horizontal DCLK Mask Start 0x01C7 248C DCLKHSA Horizontal Auxiliary DCLK Mask Start 0x01C7 2490 DCLKHS Horizontal DCLK Mask Range 0x01C7 2494 DCLKHS Vertical DCLK Mask Start 0x01C7 2498 DCLKVR Vertical DCLK Mask Range 0x01C7 249C CAPCTL Caption Control 0x01C7 24A0 CAPDO Caption Data Odd Field 0x01C7 24A4 CAPDE Caption Data Even Field 0x01C7 24A8 ATR0 Video Attribute Data # 0 0x01C7 24AC ATR1 Video Attribute Data # 1 0x01C7 24B0 ATR2 Video Attribute Data # 2 0x01C7 24B4 0x01C7 24B8 Reserved VSTAT Video Status Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 177 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-59. VENC (Including Digital LCD and DACs) Register Descriptions (continued) ADDRESS REGISTER 0x01C7 24BC 0x01C7 24C0 0x01C7 24C4 DACTST DAC Test 0x01C7 24C8 YCOLVL YOUT and COUT Levels 0x01C7 24CC SCPROG Sub-Carrier Programming 0x01C7 24D0 0x01C7 24D8 Reserved 0x01C7 24DC CVBS Composite Mode 0x01C7 24E0 CMPNT Component Mode 0x01C7 24E4 ETMG0 CVBS Timing Control 0 0x01C7 24E8 ETMG1 CVBS Timing Control 1 0x01C7 24EC ETMG2 Component Timing Control 0 0x01C7 24F0 ETMG3 Component Timing Control 1 0x01C7 24F4 DACSEL DAC Output Select 0x01C7 24F8 0x01C7 24FC 178 DESCRIPTION Reserved Reserved 0x01C7 2500 ARGBX0 Analog RGB Matrix 0 0x01C7 2504 ARGBX1 Analog RGB Matrix 1 0x01C7 2508 ARGBX2 Analog RGB Matrix 2 0x01C7 250C ARGBX3 Analog RGB Matrix 3 0x01C7 2510 ARGBX4 Analog RGB Matrix 4 0x01C7 2514 DRGBX0 Digital RGB Matrix 0 0x01C7 2518 DRGBX1 Digital RGB Matrix 1 0x01C7 251C DRGBX2 Digital RGB Matrix 2 0x01C7 2520 DRGBX3 Digital RGB Matrix 3 0x01C7 2524 DRGBX4 Digital RGB Matrix 4 0x01C7 2528 VSTARTA Vertical Data Valid Start Position for Even Field 0x01C7 252C OSDCLK0 OSD Clock Control 0 0x01C7 2530 OSDCLK1 OSD Clock Control 1 0x01C7 2534 HVLDCL0 Horizontal Valid Culling Control 0 0x01C7 2538 HVLDCL1 Horizontal Valid Culling Control 1 0x01C7 253C OSDHADV OSD Horizontal Sync Advance Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.13.2.3 VPBE Electrical Data/Timing Table 6-60. Timing Requirements for VPBE CLK Inputs (see Figure 6-50) 1.05 V and 1.2 V NO. MIN MAX 13.33 160 UNIT 1 tc(PCLK) Cycle time, PCLK 2 tw(PCLKH) Pulse duration, PCLK high 5.7 ns 3 tw(PCLKL) Pulse duration, PCLK low 5.7 4 tt(PCLK) Transition time, PCLK 5 tc(VPBECLK) Cycle time, VPBECLK 6 tw(VPBECLKH) Pulse duration, VPBECLK high 5.7 ns 7 tw(VPBECLKL) Pulse duration, VPBECLK low 5.7 ns 8 tt(VPBECLK) Transition time, VPBECLK ns ns 13.33 3 ns 160 ns 3 ns 3 1 2 PCLK 4 6 5 7 4 VPBECLK 8 8 Figure 6-50. VPBE PCLK and VPBECLK Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 179 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-61. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK (1) (see Figure 6-51) 1.05 V and 1.2 V NO. MIN 9 tsu(VCTLV-VCLKIN) Setup time, VCTL valid before VCLKIN edge 10 th(VCLKIN-VCTLV) Hold time, VCTL valid after VCLKIN edge 27 tsu(VCTLV-VPBECLK) Setup time, VCTL valid before VPBECLK rising edge 28 th(VPBECLK-VCTLV) Hold time, VCTL valid after VPBECLK rising edge 33 tsu(FIELD-PCLK) Setup time, LCD_FIELD valid before PCLK edge MAX UNIT 2 ns 0.5 ns 2 ns 0.5 ns 5P (2) ns (2) ns 34 th(PCLK-FIELD) Hold time, LCD_FIELD valid after PCLK edge 5P 35 tsu(FIELD-VPBECLK) Setup time, LCD_FIELD valid before VPBECLK edge 5P (2) ns 36 th(VPBECLK-FIELD) Hold time, LCD_FIELD valid after VPBECLK edge 5P (2) ns (1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced. P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used. (2) VPBECLK PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 10 9 28 27 VCTL(A) 34 33 36 35 LCD_FIELD A. VCTL = HSYNC and VSYNC Figure 6-51. VPBE Input Timing With Respect to PCLK and VPBECLK 180 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-62. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and VPBECLK (1) (see Figure 6-52) NO. (1) 1.05 V PARAMETER MIN 11 td(PCLK-VCTLV) Delay time, PCLK edge to VCTL valid 12 td(PCLK-VCTLIV) Delay time, PCLK edge to VCTL invalid 13 td(PCLK-VDATAV) Delay time, PCLK edge to VDATA valid 14 td(PCLK-VDATAIV) Delay time, PCLK edge to VDATA invalid 29 td(VPBECLK-VCTLV) Delay time, VPBECLK rising edge to VCTL valid 30 td(VPBECLK-VCTLIV) Delay time, VPBECLK rising edge to VCTL invalid 31 td(VPBECLK-VDATAV) Delay time, VPBECLK rising edge to VDATA valid 32 td(VPBECLK-VDATAIV) Delay time, VPBECLK rising edge to VDATA invalid 1.2 V MAX MIN 16 MAX 13.3 2 2 16 2 16 2 16 ns ns 13.3 2 ns ns 13.3 2 ns ns 13.3 2 UNIT 2 ns ns PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced. VPBECLK PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 11, 29 12, 30 13, 31 14, 32 VCTL(A) VDATA(B) A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] Figure 6-52. VPBE Output Timing With Respect to PCLK and VPBECLK Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 181 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-63. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK (1) (2) (see Figure 6-53) NO. 17 18 19 20 MODE (3) PARAMETER tc(VCLK) tw(VCLKH) tw(VCLKL) Cycle time, VCLK 1.05 V 1.2 V MIN MAX MIN MAX UNIT 13.33 160 13.33 160 ns Pulse duration, VCLK high (positive-edge clocking) H - 1.3 (4) H - 0.3 (4) H - 1.3 (4) H - 0.3 (4) ns Pulse duration, VCLK high (negative-edge clocking) L - 1.3 (4) L - 0.3 (4) L - 1.3 (4) L - 0.3 (4) ns Pulse duration, VCLK low (positive-edge clocking) L + 0.3 (4) L + 1.3 (4) L + 0.3 (4) L + 1.3 (4) ns Pulse duration, VCLK low (negative-edge clocking) H + 0.3 (4) H + 1.3 (4) H + 0.3 (4) H + 1.3 (4) ns 3 ns tt(VCLK) Transition time, VCLK 21 td(VCLKINH-VCLKH) Delay time, VCLKIN high to VCLK high 2 12 2 12 ns 22 td(VCLKINL-VCLKL) Delay time, VCLKIN low to VCLK low 2 12 2 12 ns 9.1 7.5 ns 8 6.9 ns 23 24 25 26 td(VCLK-VCTLV) td(VCLKL-VCTLIV) td(VCLK-VDATAV) td(VCLKL-VDATAIV) Delay time, VCLK negative edge to VCTL valid Delay time, VCLK positive edge to VCTL valid Delay time, VCLK negative edge to VCTL invalid 2.3 2 ns Delay time, VCLK positive edge to VCTL invalid 1.9 1.5 ns Delay time, VCLK negative edge to VDATA valid Delay time, VCLK positive edge to VDATA valid (2) (3) (4) 182 8 6.8 ns 7.3 6.3 ns Delay time, VCLK negative edge RGB to VDATA invalid YCC 2.8 2.1 ns 2.8 2.5 ns RGB 2.3 1.9 ns YCC 2.6 2.1 ns Delay time, VCLK positive edge to VDATA invalid (1) 3 The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced. VCLKIN = PCLK or VPBECLK RGB and YCC modes utilize different data pins. RGB mode uses data pins: R[7:0], G[7:0], and B[7:0]. YCC mode uses data pins: COUT[7:0] and YOUT[7:0]. H and L are the high and low pulse widths of the input clock to the VPBE, respectively. For example, if VPBECLK is used as the input clock and it has a high pulse duration of 6.67 ns, the resulting high pulse duration of VCLK, if positive-edge clocking is selected, will be a MAX of 6.37 ns and a MIN of 5.27 ns. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 VCLKIN(A) 21 VCLK 18 17 22 19 (Positive Edge Clocking) VCLK (Negative Edge Clocking) 23 24 25 26 20 20 VCTL(B) VDATA(C) A. VCLKIN = PCLK or VPBECLK B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] Figure 6-53. VPBE Control and Data Output Timing With Respect to VCLK Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 183 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.13.2.4 DAC Electrical Data/Timing Table 6-64. Switching Characteristics Over Recommended Operating Conditions for DAC Static Specifications (see Figure 6-54) NO. PARAMETER 1.05 V and 1.2 V TEST CONDITIONS MIN DC Accuracy Integral Non-Linearity (INL) Differential Non-Linearity (DNL) TYP -1.0 -0.5 Analog Output Offset Error Gain Error Full-Scale Output Voltage RLOAD = 500 Ω Output Capacitance Reference Reference Voltage Range (VREF) Full-Scale Current Adjust Resistor (RBIAS) 0.475 3.8 MAX 1.0 0.5 UNIT LSB LSB 0.5 5 500 LSB %FS mVPP 200 pF 0.5 4.0 0.525 4.2 V kΩ Table 6-65. Switching Characteristics Over Recommended Operating Conditions for DAC Dynamic Specifications (see Figure 6-54) NO. PARAMETER 1.05 V and 1.2 V TEST CONDITIONS MIN Output Update Rate (FCLK) Signal Bandwidth FCLK = 27 MHz FOUT = 2.0 MHz SFDR to Nyquist FCLK = 60 MHz FOUT = 2.0 MHz FCLK = 27 MHz FOUT = 2.0 MHz SFDR within Bandwidth FCLK = 60 MHz FOUT = 2.0 MHz PSRR Over Temp vs Power Supply TYP MAX 27 60 UNIT MHz 6 MHz 60 dB 60 dB 60 db 60 dB 50 dB The DM6441's analog video DAC outputs are designed to drive a 500-Ω load. Figure 6-54 describes a typical circuit that will permit connecting the analog video output from the DM6441 device to standard 75-Ω impedance video systems. Another solution is to use a Video Amplifier with an integrated filter to provide a complete solution to the typical output circuit shown in Figure 6-54. DAC IOUT Low-Pass Filter fc = 6.5 MHz ~RLOAD = 500 Ω Amplifier Gain = 5.6 V/V 75 Ω 75 Ω Figure 6-54. Typical Output Circuit for NTSC/PAL Video From DACs 184 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.14 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 USB 2.0 The DM6441 USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s) • USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s) • All transfer modes (control, bulk, interrupt, and isochronous) • Four transmit (TX) and four receive (RX) endpoints in addition to endpoint 0 • FIFO RAM – 4K endpoint – Programmable size • Connects to a standard charge pump for VBUS 5 V generation • RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB 6.14.1 USBPHY_CTL Register Description The USB physical interface control register USBPHY_CTL is described in Figure 6-55 and Table 6-66. Figure 6-55. USBPHY_CTL Register 31 9 8 RESERVED PHYCLKGD R-0000 0000 0000 0000 0000 000 R-0 7 6 5 4 3 2 1 0 SESNDEN VBDTCTEN RSV PHYPLLON CLKO1SEL OSCPDWN RSV PHYPDWN R/W-1 R/W-1 R-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 LEGEND: R = Read, W = Write, n = value at reset Table 6-66. USBPHY_CTL Register Field Descriptions Bit Field 31 - 9 RESERVED Reserved 8 PHYCLKGD USB PHY Power and Clock Good 7 6 Value Description 0 PHY power not ramped or PLL not locked 1 PHY power is good and PLL is locked SESNDEN Session End Comparator enable 0 Comparator disabled 1 Comparator enabled VBDTCTEN vbus comparator enable 0 Comparators (except session end) disabled 1 Comparators (except session end) enabled 5 RESERVED Reserved 4 PHYPLLON USB PHY PLL suspend override 3 2 1 0 Normal PLL operation 1 Override PLL suspend state CLKO1SEL CLK_OUT1 frequency select 0 24 MHz 1 12 MHz OSCPDWN RESERVED USB PHY oscillator power down control 0 PHY oscillator powered 1 PHY oscillator power off Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 185 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-66. USBPHY_CTL Register Field Descriptions (continued) Bit Field 0 PHYPDWN Value Description USB PHY power down control 0 PHY powered 1 PHY power off 6.14.2 USB2.0 Peripheral Register Description(s) The USB register memory mapping is shown in Table 6-67. Table 6-67. USB2.0 Register Descriptions Acronym Register Description 0x01C6 4000 Address REVR Revision Register 0x01C6 4004 CTRLR Control Register 0x01C6 4008 STATR Status Register 0x01C6 4010 RNDISR RNDIS Register 0x01C6 4014 AUTOREQ Auto Request Register 0x01C6 4020 INTSRCR USB Interrupt Source Register 0x01C6 4024 INTSETR USB Interrupt Source Set Register 0x01C6 4028 INTCLRR USB Interrupt Source Clear Register 0x01C6 402C INTMSKR USB Interrupt Mask Register 0x01C6 4030 INTMSKSETR USB Interrupt Mask Set Register 0x01C6 4034 INTMSKCLRR USB Interrupt Mask Clear Register 0x01C6 4038 INTMASKEDR USB Interrupt Source Masked Register 0x01C6 403C EOIR USB End of Interrupt Register 0x01C6 4040 INTVECTR USB Interrupt Vector Register 0x01C6 4080 TCPPICR TX CPPI Control Register 0x01C6 4084 TCPPITDR TX CPPI Teardown Register 0x01C6 4088 TCPPIEOIR TX CPPI DMA Controller End of Interrupt Register 0x01C6 408C TCPPIIVECTR TX CPPI DMA Controller Interrupt Vector Register 0x01C6 4090 TCPPIMSKSR TX CPPI Masked Status Register 0x01C6 4094 TCPPIRAWSR TX CPPI Raw Status Register 0x01C6 4098 TCPPIIENSETR TX CPPI Interrupt Enable Set Register 0x01C6 409C TCPPIIENCLRR TX CPPI Interrupt Enable Clear Register 0x01C6 40C0 RCPPICR RX CPPI Control Register 0x01C6 40D0 RCPPIMSKSR RX CPPI Masked Status Register 0x01C6 40D4 RCPPIRAWSR RX CPPI Raw Status Register 0x01C6 40D8 RCPPIENSETR RX CPPI Interrupt Enable Set Register 0x01C6 40DC RCPPIIENCLRR RX CPPI Interrupt Enable Clear Register 0x01C6 40E0 RBUFCNT0 RX Buffer Count 0 Register 0x01C6 40E4 RBUFCNT1 RX Buffer Count 1 Register 0x01C6 40E8 RBUFCNT2 RX Buffer Count 2 Register 0x01C6 40EC RBUFCNT3 RX Buffer Count 3 Register TX/RX CCPI Channel 0 State Block 186 0x01C6 4100 TCPPIDMASTATEW0 TX CPPI DMA State Word 0 0x01C6 4104 TCPPIDMASTATEW1 TX CPPI DMA State Word 1 0x01C6 4108 TCPPIDMASTATEW2 TX CPPI DMA State Word 2 0x01C6 410C TCPPIDMASTATEW3 TX CPPI DMA State Word 3 0x01C6 4110 TCPPIDMASTATEW4 TX CPPI DMA State Word 4 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-67. USB2.0 Register Descriptions (continued) Acronym Register Description 0x01C6 4114 Address TCPPIDMASTATEW5 TX CPPI DMA State Word 5 0x01C6 4118 TCPPIDMASTATEW6 TX CPPI DMA State Word 6 0x01C6 411C TCPPICOMPPTR TX CPPI Completion Pointer 0x01C6 4120 RCPPIDMASTATEW0 RX CPPI DMA State Word 0 0x01C6 4124 RCPPIDMASTATEW1 RX CPPI DMA State Word 1 0x01C6 4128 RCPPIDMASTATEW2 RX CPPI DMA State Word 2 0x01C6 412C RCPPIDMASTATEW3 RX CPPI DMA State Word 3 0x01C6 4130 RCPPIDMASTATEW4 RX CPPI DMA State Word 4 0x01C6 4134 RCPPIDMASTATEW5 RX CPPI DMA State Word 5 0x01C6 4138 RCPPIDMASTATEW6 RX CPPI DMA State Word 6 0x01C6 413C RCPPICOMPPTR RX CPPI Completion Pointer 0x01C6 4140 TCPPIDMASTATEW0 TX CPPI DMA State Word 0 0x01C6 4144 TCPPIDMASTATEW1 TX CPPI DMA State Word 1 TX/RX CCPI Channel 1 State Block 0x01C6 4148 TCPPIDMASTATEW2 TX CPPI DMA State Word 2 0x01C6 414C TCPPIDMASTATEW3 TX CPPI DMA State Word 3 0x01C6 4150 TCPPIDMASTATEW4 TX CPPI DMA State Word 4 0x01C6 4154 TCPPIDMASTATEW5 TX CPPI DMA State Word 5 0x01C6 4158 TCPPIDMASTATEW6 TX CPPI DMA State Word 6 0x01C6 415C TCPPICOMPPTR TX CPPI Completion Pointer 0x01C6 4160 RCPPIDMASTATEW0 RX CPPI DMA State Word 0 0x01C6 4164 RCPPIDMASTATEW1 RX CPPI DMA State Word 1 0x01C6 4168 RCPPIDMASTATEW2 RX CPPI DMA State Word 2 0x01C6 416C RCPPIDMASTATEW3 RX CPPI DMA State Word 3 0x01C6 4170 RCPPIDMASTATEW4 RX CPPI DMA State Word 4 0x01C6 4174 RCPPIDMASTATEW5 RX CPPI DMA State Word 5 0x01C6 4178 RCPPIDMASTATEW6 RX CPPI DMA State Word 6 0x01C6 417C RCPPICOMPPTR RX CPPI Completion Pointer TX/RX CCPI Channel 2 State Block 0x01C6 4180 TCPPIDMASTATEW0 TX CPPI DMA State Word 0 0x01C6 4184 TCPPIDMASTATEW1 TX CPPI DMA State Word 1 0x01C6 4188 TCPPIDMASTATEW2 TX CPPI DMA State Word 2 0x01C6 418C TCPPIDMASTATEW3 TX CPPI DMA State Word 3 0x01C6 4190 TCPPIDMASTATEW4 TX CPPI DMA State Word 4 0x01C6 4194 TCPPIDMASTATEW5 TX CPPI DMA State Word 5 0x01C6 4198 TCPPIDMASTATEW6 TX CPPI DMA State Word 6 0x01C6 419C TCPPICOMPPTR TX CPPI Completion Pointer 0x01C6 41A0 RCPPIDMASTATEW0 RX CPPI DMA State Word 0 0x01C6 41A4 RCPPIDMASTATEW1 RX CPPI DMA State Word 1 0x01C6 41A8 RCPPIDMASTATEW2 RX CPPI DMA State Word 2 0x01C6 41AC RCPPIDMASTATEW3 RX CPPI DMA State Word 3 0x01C6 41BA RCPPIDMASTATEW4 RX CPPI DMA State Word 4 0x01C6 41B4 RCPPIDMASTATEW5 RX CPPI DMA State Word 5 0x01C6 41B8 RCPPIDMASTATEW6 RX CPPI DMA State Word 6 0x01C6 41BC RCPPICOMPPTR RX CPPI Completion Pointer Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 187 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-67. USB2.0 Register Descriptions (continued) Address Acronym Register Description TX/RX CCPI Channel 3 State Block 0x01C6 41C0 TCPPIDMASTATEW0 TX CPPI DMA State Word 0 0x01C6 41C4 TCPPIDMASTATEW1 TX CPPI DMA State Word 1 0x01C6 41C8 TCPPIDMASTATEW2 TX CPPI DMA State Word 2 0x01C6 41CC TCPPIDMASTATEW3 TX CPPI DMA State Word 3 0x01C6 41D0 TCPPIDMASTATEW4 TX CPPI DMA State Word 4 0x01C6 41D4 TCPPIDMASTATEW5 TX CPPI DMA State Word 5 0x01C6 41D8 TCPPIDMASTATEW6 TX CPPI DMA State Word 6 0x01C6 41DC TCPPICOMPPTR TX CPPI Completion Pointer 0x01C6 41E0 RCPPIDMASTATEW0 RX CPPI DMA State Word 0 0x01C6 41E4 RCPPIDMASTATEW1 RX CPPI DMA State Word 1 0x01C6 41E8 RCPPIDMASTATEW2 RX CPPI DMA State Word 2 0x01C6 41EC RCPPIDMASTATEW3 RX CPPI DMA State Word 3 0x01C6 41F0 RCPPIDMASTATEW4 RX CPPI DMA State Word 4 0x01C6 41F4 RCPPIDMASTATEW5 RX CPPI DMA State Word 5 0x01C6 41F8 RCPPIDMASTATEW6 RX CPPI DMA State Word 6 0x01C6 41FC RCPPICOMPPTR RX CPPI Completion Pointer 0x01C6 4400 FADDR Function Address Register 0x01C6 4401 POWER Power Management Register 0x01C6 4402 INTRTX Interrupt Register for Endpoint 0 plus TX Endpoints 1 to 4 0x01C6 4404 INTRRX Interrupt Register for RX Endpoints 1 to 4 0x01C6 4406 INTRTXE Interrupt Enable Register for INTRTX 0x01C6 4408 INTRRXE Interrupt Enable Register for INTRRX 0x01C6 440A INTRUSB Interrupt Register for Common USB Interrupts 0x01C6 440B INTRUSBE Interrupt Enable Register for INTRUSB 0x01C6 440C FRAME Frame Number Register 0x01C6 440E INDEX Index register for selecting the endpoint status and control registers 0x01C6 440F TESTMODE Register to enable the USB 2.0 test modes 0x01C6 4410 TXMAXP Maximum packet size for peripheral/host TX endpoint (Index register set to select Endpoints 1 - 4 only) PERI_CSR0 Control Status register for Endpoint 0 in Peripheral mode. (Index register set to select Endpoint 0) HOST_CSR0 Control Status register for Endpoint 0 in Host mode. (Index register set to select Endpoint 0) PERI_TXCSR Control Status register for peripheral TX endpoint. (Index register set to select Endpoints 1 - 4) HOST_TXCSR Control Status register for host TX endpoint. (Index register set to select Endpoints 1 - 4) RXMAXP Maximum packet size for peripheral/host RX endpoint (Index register set to select Endpoints 1 - 4 only) PERI_RXCSR Control Status register for peripheral RX endpoint. (Index register set to select Endpoints 1 - 4) HOST_RXCSR Control Status register for host RX endpoint. (Index register set to select Endpoints 1 - 4) COUNT0 Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) RXCOUNT Number of bytes in host RX endpoint FIFO. (Index register set to select Endpoints 1 - 4) HOST_TYPE0 Defines the speed of Endpoint 0 Core Registers 0x01C6 4412 0x01C6 4414 0x01C6 4416 0x01C6 4418 0x01C6 441A 188 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-67. USB2.0 Register Descriptions (continued) Acronym Register Description 0x01C6 441A Address HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host TX endpoint. (Index register set to select Endpoints 1 - 4 only) 0x01C6 441B HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0. (Index register set to select Endpoint 0) 0x01C6 441B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host TX endpoint. (Index register set to select Endpoints 1 - 4 only) 0x01C6 441C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. (Index register set to select Endpoints 1 - 4 only) 0x01C6 441D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. (Index register set to select Endpoints 1 - 4 only) 0x01C6 441F CONFIGDATA Returns details of core configuration (Index register set to select Endpoint 0) 0x01C6 4420 FIFO0 TX and RX FIFO Register for Endpoint 0 0x01C6 4424 FIFO1 TX and RX FIFO Register for Endpoint 1 0x01C6 4428 FIFO2 TX and RX FIFO Register for Endpoint 2 0x01C6 442C FIFO3 TX and RX FIFO Register for Endpoint 3 0x01C6 4430 FIFO4 TX and RX FIFO Register for Endpoint 4 0x01C6 4462 TXFIFOSZ TX Endpoint FIFO Size (Index register set to select Endpoints 0 - 4 only) 0x01C6 4463 RXFIFOSZ RX Endpoint FIFO Size (Index register set to select Endpoints 0 - 4 only) 0x01C6 4464 TXFIFOADDR TX Endpoint FIFO Address (Index register set to select Endpoints 0 - 4 only) 0x01C6 4466 RXFIFOADDR RX Endpoint FIFO Address (Index register set to select Endpoints 0 - 4 only) 0x01C6 4480 TXFUNCADDR Address of the target function that has to be accessed through the associated TX Endpoint 0x01C6 4482 TXHUBADDR Address of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4483 TXHUBPORT Port of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4484 RXFUNCADDR Address of the target function that has to be accessed through the associated RX Endpoint 0x01C6 4486 RXHUBADDR Address of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4487 RXHUBPORT Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG0 Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG1 0x01C6 4488 TXFUNCADDR Address of the target function that has to be accessed through the associated TX Endpoint 0x01C6 448A TXHUBADDR Address of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 448B TXHUBPORT Port of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 448C RXFUNCADDR Address of the target function that has to be accessed through the associated RX Endpoint 0x01C6 448E RXHUBADDR Address of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 448F RXHUBPORT Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 189 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-67. USB2.0 Register Descriptions (continued) Address Acronym Register Description Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG2 0x01C6 4490 TXFUNCADDR Address of the target function that has to be accessed through the associated TX Endpoint 0x01C6 4492 TXHUBADDR Address of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4493 TXHUBPORT Port of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4494 RXFUNCADDR Address of the target function that has to be accessed through the associated RX Endpoint 0x01C6 4496 RXHUBADDR Address of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4497 RXHUBPORT Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 4498 TXFUNCADDR Address of the target function that has to be accessed through the associated TX Endpoint 0x01C6 449A TXHUBADDR Address of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 449B TXHUBPORT Port of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 449C RXFUNCADDR Address of the target function that has to be accessed through the associated RX Endpoint 0x01C6 449E RXHUBADDR Address of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 449F RXHUBPORT Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 44A0 TXFUNCADDR Address of the target function that has to be accessed through the associated TX Endpoint 0x01C6 44A2 TXHUBADDR Address of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 44A3 TXHUBPORT Port of the hub that has to be accessed through the associated TX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 44A4 RXFUNCADDR Address of the target function that has to be accessed through the associated RX Endpoint 0x01C6 44A6 RXHUBADDR Address of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub 0x01C6 44A7 RXHUBPORT Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG3 Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG4 190 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-67. USB2.0 Register Descriptions (continued) Address Acronym Register Description Control and Status Register for Endpoint 0 - EOCSR0 0x01C6 4502 PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral mode HOST_CSR0 Control Status Register for Endpoint 0 in Host mode 0x01C6 4508 COUNT0 Number of Received Bytes in Endpoint 0 FIFO 0x01C6 450A HOST_TYPE0 Defines the Speed of Endpoint 0 0x01C6 450B HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0. 0x01C6 450F CONFIGDATA Returns details of core configuration 0x01C6 4510 TXMAXP Maximum Packet size for Peripheral/Host TX Endpoint 0x01C6 4512 PERI_TXCSR Control Status Register for Peripheral TX Endpoint HOST_TXCSR Control Status Register for Host TX Endpoint 0x01C6 4514 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint 0x01C6 4516 PERI_RXCSR Control Status Register for Peripheral RX Endpoint HOST_RXCSR Control Status Register for Host RX Endpoint Control and Status Register for Endpoint 1 - EOCSR1 0x01C6 4518 RXCOUNT Number of Bytes in Host RX Endpoint FIFO 0x01C6 451A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host TX endpoint. 0x01C6 451B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host TX endpoint. 0x01C6 451C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. 0x01C6 451D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. 0x01C6 4520 TXMAXP Maximum Packet Size for Peripheral/Host TX Endpoint 0x01C6 4522 PERI_TXCSR Control Status Register for Peripheral TX Endpoint HOST_TXCSR Control Status Register for Host TX Endpoint 0x01C6 4524 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint 0x01C6 4526 PERI_RXCSR Control Status Register for Peripheral RX Endpoint HOST_RXCSR Control Status Register for Host RX Endpoint 0x01C6 4528 RXCOUNT Number of Bytes in Host RX Endpoint FIFO 0x01C6 452A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host TX endpoint. 0x01C6 452B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host TX endpoint. 0x01C6 452C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. 0x01C6 452D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. Control and Status Register for Endpoint 2 - EOCSR2 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 191 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-67. USB2.0 Register Descriptions (continued) Address Acronym Register Description Control and Status Register for Endpoint 3 - EOCSR3 0x01C6 4530 TXMAXP Maximum Packet Size for Peripheral/Host TX Endpoint 0x01C6 4532 PERI_TXCSR Control Status Register for Peripheral TX Endpoint HOST_TXCSR Control Status Register for Host TX Endpoint 0x01C6 4534 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint 0x01C6 4536 PERI_RXCSR Control Status Register for Peripheral RX Endpoint HOST_RXCSR Control Status Register for Host RX Endpoint 0x01C6 4538 RXCOUNT Number of Bytes in Host RX Endpoint FIFO 0x01C6 453A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host TX endpoint. 0x01C6 453B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host TX endpoint. 0x01C6 453C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. 0x01C6 453D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. 0x01C6 4540 TXMAXP Maximum Packet Size for Peripheral/Host TX Endpoint 0x01C6 4542 PERI_TXCSR Control Status Register for Peripheral TX Endpoint HOST_TXCSR Control Status Register for Host TX Endpoint 0x01C6 4544 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint 0x01C6 4546 PERI_RXCSR Control Status Register for Peripheral RX Endpoint HOST_RXCSR Control Status Register for Host RX Endpoint 0x01C6 4548 RXCOUNT Number of Bytes in Host RX Endpoint FIFO 0x01C6 454A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host TX endpoint. 0x01C6 454B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host TX endpoint. 0x01C6 454C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. 0x01C6 454D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. Control and Status Register for Endpoint 4 - EOCSR4 192 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.14.3 USB2.0 Electrical Data/Timing Table 6-68. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see Figure 6-56) 1.05 V and 1.2 V NO. LOW SPEED 1.5 Mbps PARAMETER HIGH SPEED 480 Mbps MIN MAX MIN MAX MIN 1 tr(D) Rise time, USB_DP and USB_DM signals (1) 75 300 4 20 0.5 2 tf(D) Fall time, USB_DP and USB_DM signals (1) 75 300 4 20 0.5 3 trfM Rise/Fall time, matching (2) 80 125 90 111.11 – 1.3 2 1.3 2 – (1) 4 VCRS Output signal cross-over voltage 5 tjr(source)NT Source (Host) Driver jitter, next transition tjr(FUNC)NT Function Driver jitter, next transition 6 tjr(source)PT Source (Host) Driver jitter, paired transition tjr(FUNC)PT Function Driver jitter, paired transition 7 tw(EOPT) Pulse duration, EOP transmitter 8 tw(EOPR) Pulse duration, EOP receiver 9 t(DRATE) Data Rate 10 ZDRV Driver Output Resistance 11 USB_R1 USB reference resistor (1) (2) (3) (4) FULL SPEED 12 Mbps (4) 1250 UNIT MAX ns ns – % – V 2 2 (3) ns 25 2 (3) ns 1 1 (3) ns 10 1 (3) ns – ns 1500 160 670 175 82 – – 1.5 12 ns 480 Mb/s – – 28 49.5 40.5 49.5 Ω 9.9 10.1 9.9 10.1 9.9 10.1 kΩ Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.] For more detailed information, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7, Electrical. tjr = tpx(1) - tpx(0) USB_DM VCRS USB_DP tper − tjr 90% VOH 10% VOL tf tr Figure 6-56. USB2.0 Integrated Transceiver Interface Timing USB USB_VSSREF USB_R1 10 K Ω ±1% (A) A. Place the 10 K Ω ± 1% as close to the device as possible. Figure 6-57. USB Reference Resistor Routing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 193 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.15 www.ti.com Universal Asynchronous Receiver/Transmitter (UART) DM6441 has three UART peripherals. Each UART has the following features: • 16-byte storage space for both the transmitter and receiver FIFOs • 1-, 4-, 8-, or 14-byte selectable receiver FIFO trigger level for autoflow control and DMA • DMA signaling capability for both received and transmitted data • Programmable auto-rts and auto-cts for autoflow control • Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates • Prioritized interrupts • Programmable serial data formats – 5-, 6-, 7-, or 8-bit characters – Even, odd, or no parity bit generation and detection – 1-, 1.5-, or 2-stop bit generation • False start bit detection • Line break generation and detection • Internal diagnostic capabilities – Loopback controls for communications link fault isolation – Break, parity, overrun, and framing error simulation • Modem control functions (CTS, RTS) on UART2 only. The UART0/1/2 registers are listed in Table 6-69, Table 6-70, and Table 6-71. 6.15.1 UART Peripheral Register Description(s) Table 6-69. UART0 Register Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 0000 RBR UART0 Receiver Buffer Register (Read Only) 0x01C2 0000 THR UART0 Transmitter Holding Register (Write Only) 0x01C2 0004 IER UART0 Interrupt Enable Register 0x01C2 0008 IIR UART0 Interrupt Identification Register (Read Only) 0x01C2 0008 FCR UART0 FIFO Control Register (Write Only) 0x01C2 000C LCR UART0 Line Control Register 0x01C2 0010 MCR UART0 Modem Control Register 0x01C2 0014 LSR UART0 Line Status Register 0x01C2 0018 - Reserved 0x01C2 001C - Reserved 0x01C2 0020 DLL UART0 Divisor Latch (LSB) 0x01C2 0024 DLH UART0 Divisor Latch (MSB) 0x01C2 0028 PID1 Peripheral Identification Register 1 0x01C2 002C PID2 Peripheral Identification Register 2 0x01C2 0030 PWREMU_MGMT UART0 Power and Emulation Management Register 0x01C2 0034 - 0x01C2 03FF - Reserved 194 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-70. UART1 Register Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 0400 RBR UART1 Receiver Buffer Register (Read Only) 0x01C2 0400 THR UART1 Transmitter Holding Register (Write Only) 0x01C2 0404 IER UART1 Interrupt Enable Register 0x01C2 0408 IIR UART1 Interrupt Identification Register (Read Only) 0x01C2 0408 FCR UART1 FIFO Control Register (Write Only) 0x01C2 040C LCR UART1 Line Control Register 0x01C2 0410 MCR UART1 Modem Control Register 0x01C2 0414 LSR UART1 Line Status Register 0x01C2 0418 - Reserved 0x01C2 041C - Reserved 0x01C2 0420 DLL UART1 Divisor Latch (LSB) 0x01C2 0424 DLH UART1 Divisor Latch (MSB) 0x01C2 0428 PID1 Peripheral Identification Register 1 0x01C2 042C PID2 Peripheral Identification Register 2 0x01C2 0430 PWREMU_MGMT UART1 Power and Emulation Management Register 0x01C2 0434 - 0x01C2 07FF - Reserved Table 6-71. UART2 Register Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 0800 RBR UART2 Receiver Buffer Register (Read Only) 0x01C2 0800 THR UART2 Transmitter Holding Register (Write Only) 0x01C2 0804 IER UART2 Interrupt Enable Register 0x01C2 0808 IIR UART2 Interrupt Identification Register (Read Only) 0x01C2 0808 FCR UART2 FIFO Control Register (Write Only) 0x01C2 080C LCR UART2 Line Control Register 0x01C2 0810 MCR UART2 Modem Control Register 0x01C2 0814 LSR UART2 Line Status Register 0x01C2 0818 - Reserved 0x01C2 081C - Reserved 0x01C2 0820 DLL UART2 Divisor Latch (LSB) 0x01C2 0824 DLH UART2 Divisor Latch (MSB) 0x01C2 0828 PID1 Peripheral Identification Register 1 0x01C2 082C PID2 Peripheral Identification Register 2 0x01C2 0830 PWREMU_MGMT UART2 Power and Emulation Management Register 0x01C2 0834 - 0x01C2 0BFF - Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 195 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.15.2 UART Electrical Data/Timing Table 6-72. Timing Requirements for UARTx Receive (1) (see Figure 6-58) 1.05 V and 1.2 V NO. (1) MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (RXDn) [15/30/100 pF] 0.96U 1.05U ns 5 tw(URXSB) Pulse duration, receive start bit [15/30/100 pF] 0.96U 1.05U ns U = UART baud time = 1/programmed baud rate. Table 6-73. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1) (see Figure 6-58) NO. (1) 1.05 V and 1.2 V PARAMETER MIN MAX 128 UNIT 1 f(baud) Maximum programmable baud rate kHz 2 tw(UTXDB) Pulse duration, transmit data bit (TXDn) [15/30/100 pF] U-2 U+2 ns 3 tw(UTXSB) Pulse duration, transmit start bit [15/30/100 pF] U-2 U+2 ns U = UART baud time = 1/programmed baud rate. 3 2 UART_TXDn Start Bit Data Bits 5 4 UART_RXDn Start Bit Data Bits Figure 6-58. UART Transmit/Receive Timing 196 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.16 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Serial Port Interface (SPI) The DM6441 SPI peripheral provides a programmable length shift register which allows serial communication with other SPI devices through a 3- or 4-wire interface. The SPI supports the following features: • Master mode operation • Two chip selects for interfacing to multiple slave SPI devices. • 3- or 4-wire interface The SPI registers are shown in Table 6-74. 6.16.1 SPI Peripheral Register Description(s) Table 6-74. SPI Register Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C6 6800 SPIGCR0 SPI Global Control Register 0 0x01C6 6804 SPIGCR1 SPI Global Control Register 1 0x01C6 6808 SPIINT SPI Interrupt Register 0x01C6 680C SPILVL SPI Interrupt Level Register 0x01C6 6810 SPIFLG SPI Flag Status Register 0x01C6 6814 SPIPC0 SPI Pin Control Register 0 0x01C6 6818 – Reserved 0x01C6 681C SPIPC2 SPI Pin Control Register 2 0x01C6 6820 - 0x01C6 6838 – Reserved 0x01C6 683C SPIDAT1 SPI Shift Register 1 0x01C6 6840 SPIBUF SPI Buffer Register 0x01C6 6844 SPIEMU SPI Emulation Register 0x01C6 6848 SPIDELAY SPI Delay Register 0x01C6 684C SPIDEF SPI Default Chip Select Register 0x01C6 6850 SPIFMT0 SPI Data Format Register 0 0x01C6 6854 SPIFMT1 SPI Data Format Register 1 0x01C6 6858 SPIFMT2 SPI Data Format Register 2 0x01C6 685C SPIFMT3 SPI Data Format Register 3 0x01C6 6860 INTVEC0 SPI Interrupt Vector Register 0 0x01C6 6864 INTVEC1 SPI Interrupt Vector Register 1 0x01C6 6868 - 0x01C6 6FFF Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 197 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.16.2 SPI Electrical Data/Timing Table 6-75. Timing Requirements for SPI (All Modes) (1) (see Figure 6-59) 1.05 V NO. MIN 1.2 V MAX MAX 30.3 56888.89 UNIT 1 tc(CLK) Cycle time, SPI_CLK 2 tw(CLKH) Pulse duration, SPI_CLK high (All Master Modes) 0.45*T 0.55*T 0.45*T 0.55*T ns 3 tw(CLKL) Pulse duration, SPI_CLK low (All Master Modes 0.45*T 0.55*T 0.45*T 0.55*T ns (1) 44.4 56888.89 MIN ns T = tc(CLK) [SPI_CLK period is equal to the SPI module clock divided by a configurable divider.] 1 2 SPIx_CLK (Clock Polarity = 0) 3 SPIx_CLK (Clock Polarity = 1) Figure 6-59. SPI_CLK Timing 198 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.16.2.1 SPI Master Mode Timings (Clock Phase = 0) Table 6-76. Timing Requirements for SPI Master Mode [Clock Phase = 0] (1) (see Figure 6-60) 1.05 V and 1.2 V NO. MIN UNIT MAX 4 tsu(DIV-CLKL) Setup time, SPI_DI (input) valid before SPI_CLK (output) falling edge Clock Polarity = 0 0.5P + 9.4 ns 5 tsu(DIV-CLKH) Setup time, SPI_DI (in put) valid before SPI_CLK (output) rising edge Clock Polarity = 1 0.5P + 9.4 ns 6 th(CLKL-DIV) Hold time, SPI_DI (input) valid after SPI_CLK (output) falling edge Clock Polarity = 0 0.5P - 4.5 ns 7 th(CLKH-DIV) Hold time, SPI_DI (input) valid after SPI_CLK (output) rising edge Clock Polarity = 1 0.5P - 4.5 ns (1) P = Period of the SPI module clock in nanoseconds (SYSCLK5). Table 6-77. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase = 0] (see Figure 6-60) NO. 1.05 V and 1.2 V PARAMETER MIN MAX UNIT 8 td(CLKH-DOV) Delay time, SPI_CLK (output) rising edge to SPI_DO (output) transition Clock Polarity = 0 -4 5 ns 9 td(CLKL-DOV) Delay time, SPI_CLK (output) falling edge to SPI_DO (output) transition Clock Polarity = 1 -4 5 ns 10 td(ENL-CLKH/L) Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling edge (1) (2) 11 td(CLKH/L-ENH) Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output) rising edge (1) (2) (3) (1) (2) (3) 2P - 2.3 ns 1P + 0.5C - 0.2 ns P = Period of the SPI module clock in nanoseconds (SYSCLK5). This delay can be increased under software control by the C2TDELAY register bit field in the SPIDELAY register. C = Period of SPI_CLK signal in ns. 11 SPI_EN SPI_CLK (Clock Polarity = 0) 10 SPI_CLK (Clock Polarity = 1) 7 6 4 5 SPI_DI (Input) MSB IN 8 SPI_DO (Output) DATA LSB IN 9 MSB OUT DATA LSB OUT Figure 6-60. SPI Master Mode External Timing (Clock Phase = 0) Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 199 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.16.2.2 SPI Master Mode Timings (Clock Phase = 1) Table 6-78. Timing Requirements for SPI Master Mode [Clock Phase = 1] (1) (see Figure 6-61) 1.05 V and 1.2 V NO. MIN MAX UNIT 13 tsu(DIV-CLKL) Setup time, SPI_DI (input) valid before SPI_CLK (output) rising edge Clock Polarity = 0 0.5P + 9.4 ns 14 tsu(DIV-CLKH) Setup time, SPI_DI (in put) valid before SPI_CLK (output) falling edge Clock Polarity = 1 0.5P + 9.4 ns 15 th(CLKL-DIV) Hold time, SPI_DI (input) valid after SPI_CLK (output) rising edge Clock Polarity = 0 0.5P - 4.5 ns 16 th(CLKH-DIV) Hold time, SPI_DI (input) valid after SPI_CLK (output) falling edge Clock Polarity = 1 0.5P - 4.5 ns (1) P = Period of the SPI module clock in nanoseconds (SYSCLK5). Table 6-79. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase = 1] (see Figure 6-61) NO. 1.05 V and 1.2 V PARAMETER MIN MAX UNIT 17 td(CLKL-DOV) Delay time, SPI_CLK (output) falling edge to SPI_DO (output) transition Clock Polarity = 0 -4 5 ns 18 td(CLKH-DOV) Delay time, SPI_CLK (output) rising edge to SPI_DO (output) transition Clock Polarity = 1 -4 5 ns 19 td(ENL-CLKH/L) Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling edge (1) (2) (3) 20 td(CLKL/H-DOHz) Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance (1) (2) (3) 2P + 0.5C - 2.3 ns 1P - 0.2 ns P = Period of the SPI module clock in nanoseconds (SYSCLK5). This delay can be increased under software control by the C2TDELAY register bit field in the SPIDELAY register. C = Period of SPI_CLK signal in ns. 20 SPI_EN SPI_CLK (Clock Polarity = 0) 19 SPI_CLK (Clock Polarity = 1) 15 13 SPI_DI (Input) 16 14 MSB IN DATA 18 17 SPI_DO (Output) MSB OUT LSB IN DATA LSB OUT Figure 6-61. SPI Master Mode External Timing (Clock Phase = 1) 200 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.17 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between DM6441 and other devices compliant with Philips Semiconductor's Inter-IC bus (I2C-Bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module. The I2C port does not support CBUS compatible devices. The I2C port supports: • Compatible with Philips I2C Specification, Revision 2.1 (January 2000) • Fast mode up to 400 Kbps (no fail-safe I/O buffers) • Noise filter to remove noise 50 ns or less • 7- and 10-bit device addressing modes • Master (transmit/receive) and slave (transmit/receive) functionality • Events: DMA, interrupt, or polling • Slew-rate limited open-drain output buffers For more detailed information on the I2C peripheral, see Section 2.8.3, Documentation Support, for the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19). CAUTION The DM6441 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/O buffer defined in the I2C specification. Series resistors may be necessary to reduce noise at the system level. 6.17.1 I2C Peripheral Register Description(s) Table 6-80. I2C Registers HEX ADDRESS RANGE ACRONYM 0x1c2 1000 ICOAR I2C Own Address Register REGISTER NAME 0x1c2 1004 ICIMR I2C Interrupt Mask Register 0x1c2 1008 ICSTR I2C Interrupt Status Register 0x1c2 100C ICCLKL I2C Clock Divider Low Register 0x1c2 1010 ICCLKH I2C Clock Divider High Register 0x1c2 1014 ICCNT I2C Data Count Register 0x1c2 1018 ICDRR I2C Data Receive Register 0x1c2 101C ICSAR I2C Slave Address Register 0x1c2 1020 ICDXR I2C Data Transmit Register 0x1c2 1024 ICMDR I2C Mode Register 0x1c2 1028 ICIVR I2C Interrupt Vector Register 0x1c2 102C ICEMDR I2C Extended Mode Register 0x1c2 1030 ICPSC I2C Prescaler Register 0x1c2 1034 ICPID1 I2C Peripheral Identification Register 1 0x1c2 1038 ICPID2 I2C Peripheral Identification Register 2 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 201 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.17.2 www.ti.com I2C Electrical Data/Timing 6.17.2.1 Inter-Integrated Circuits (I2C) Timing Table 6-81. Timing Requirements for I2C Timings (1) (see Figure 6-62) 1.05 V and 1.2 V STANDARD MODE NO. FAST MODE MIN MAX (2) (3) (4) (5) MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 (2) (3) (3) 7 (1) UNIT th(SDA-SCLL) Hold time, SDA valid after SCL low 0 8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 9 tr(SDA) Rise time, SDA 0 ns 0.9 (4) 1.3 µs µs 1000 20 + 0.1Cb (5) 300 ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (5) 300 ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (5) 300 ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (5) 300 ns 13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 14 tw(SP) Pulse duration, spike (must be suppressed) 15 Cb (5) 4 0.6 0 Capacitive load for each bus line 400 µs 50 ns 400 pF The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. A Fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 11 9 SDA 6 8 14 4 13 5 10 SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop Figure 6-62. I2C Receive Timings 202 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-82. Switching Characteristics for I2C Timings (see Figure 6-63) 1.05 V and 1.2 V NO. STANDARD MODE PARAMETER MIN MAX FAST MODE MIN UNIT MAX 16 tc(SCL) Cycle time, SCL 10 2.5 µs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 µs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high µs 21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 29 Cp Capacitance for each I2C pin 4 0.6 250 100 0 0 4.7 1.3 4 ns 0.9 µs 0.6 10 µs µs 10 pF SDA 21 23 19 28 20 SCL 16 18 17 22 18 Stop Start Repeated Start Stop Figure 6-63. I2C Transmit Timings CAUTION The DM6441 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/O buffer defined in the I2C specification. Series resistors may be necessary to reduce noise at the system level. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 203 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.18 Audio Serial Port (ASP) The ASP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • External shift clock or an internal, programmable frequency shift clock for data transfer For more detailed information on the ASP peripheral, see the TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (literature number SPRUE29). 6.18.1 ASP Peripheral Register Description(s) Table 6-83. ASP Register Descriptions 204 HEX ADDRESS RANGE ACRONYM 0x01E0 2000 DRR ASP Data Receive Register REGISTER NAME 0x01E0 2004 DXR ASP Data Transmit Register 0x01E0 2008 SPCR ASP Serial Port Control Register 0x01E0 200C RCR ASP Receive Control Register 0x01E0 2010 XCR ASP Transmit Control Register 0x01E0 2014 SRGR 0x01E0 2024 PCR ASP Sample Rate Generator Register ASP Pin Control Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.18.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 ASP Electrical Data/Timing 6.18.2.1 Audio Serial Port (ASP) Timing Table 6-84. Timing Requirements for ASP (1) (see Figure 6-64) 1.05 V and 1.2 V NO. 2 tc(CKRX) 3 (1) (2) (3) (4) MIN tw(CKRX) Cycle time, CLKR/X CLKR/X ext Pulse duration, CLKR/X high or CLKR/X low 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKR/X ext 38.5 or 2P (2) 19.25 or P MAX UNIT (3) ns (2) (3) (4) ns CLKR int 11.8 CLKR ext 1.3 CLKR int 6 CLKR ext 3 CLKR int 10.7 CLKR ext 0.9 CLKR int 3 CLKR ext 3.1 CLKX int 12.2 CLKX ext 1.4 CLKX int 6 CLKX ext 3 ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/SYSCLK5 clock frequency in ns. For example, when running parts at DSP frequency of 405 MHz, use P = 14.8 ns. Use whichever value is greater. The ASP does not require a duty cycle specification, just ensure the minimum pulse duration specification is met. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 205 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-85. Switching Characteristics Over Recommended Operating Conditions for ASP (1) (see Figure 6-64) NO. (2) 1.05 V and 1.2 V PARAMETER MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 38.5 (3) 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 1 (4) C + 1 (4) ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -2.1 3 ns CLKX int -1.7 3 CLKX ext 1.7 14.4 CLKX int -3.9 4 CLKX ext 2.1 13 CLKX int -3.9 + D1 (5) 4 + D2 (5) ns CLKX ext 2.1 + D1 (5) 14.5 + D2 (5) ns -2.3 + D1 (6) 4 + D2 (6) 1.9 + D1 (6) 12.1 + D2 (6) 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 (1) (2) (3) (4) (5) (6) 206 td(FXH-DXV) Delay time, FSX high to DX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX int FSX ext ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA3 limitations and AC timing requirements. C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency [SYSCLK1]) S = sample rate generator input clock = Not Supported if CLKSM = 0 (no CLKS pin on DM6441) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit [see footnote (3) above]. Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 8 Bit(n-1) DR (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13(A) Bit(n-1) 13(A) (n-2) (n-3) A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0. Figure 6-64. ASP Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 207 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.19 Ethernet Media Access Controller (EMAC) The Ethernet media access controller (EMAC) provides an efficient interface between DM6441 and the network. The DM6441 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The EMAC controls the flow of packet data from the DM6441 device to the PHY. The MDIO module controls PHY configuration and status monitoring. Both the EMAC and the MDIO modules interface to the DM6441 device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts. For more detailed information on the EMAC peripheral, see the TMS320DM644x DMSoC Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide (literature number SPRUE24). For a list of supported registers and register fields, see Table 6-86 [Ethernet MAC (EMAC) Control Registers] and Table 6-87 [EMAC Statistics Registers] in this data manual. 6.19.1 EMAC Peripheral Register Description(s) Table 6-86. Ethernet MAC (EMAC) Control Registers 208 HEX ADDRESS RANGE ACRONYM 01C8 0000 TXIDVER 01C8 0004 TXCONTROL 01C8 0008 TXTEARDOWN 01C8 0010 RXIDVER REGISTER NAME Transmit Identification and Version Register Transmit Control Register Transmit Teardown Register Receive Identification and Version Register 01C8 0014 RXCONTROL 01C8 0018 RXTEARDOWN Receive Control Register Receive Teardown Register 01C8 0080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register 01C8 0084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register 01C8 0088 TXINTMASKSET 01C8 008C TXINTMASKCLEAR Transmit Interrupt Mask Set Register 01C8 0090 MACINVECTOR MAC Input Vector Register 01C8 00A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register 01C8 00A4 RXINTSTATMASKED 01C8 00A8 RXINTMASKSET 01C8 00AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register 01C8 00B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register 01C8 00B4 MACINTSTATMASKED 01C8 00B8 MACINTMASKSET 01C8 00BC MACINTMASKCLEAR 01C8 0100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register 01C8 0104 RXUNICASTSET Receive Unicast Enable Set Register Transmit Interrupt Mask Clear Register Receive Interrupt Status (Masked) Register Receive Interrupt Mask Set Register MAC Interrupt Status (Masked) Register MAC Interrupt Mask Set Register MAC Interrupt Mask Clear Register 01C8 0108 RXUNICASTCLEAR 01C8 010C RXMAXLEN Receive Unicast Clear Register 01C8 0110 RXBUFFEROFFSET 01C8 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register 01C8 0120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register 01C8 0124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register 01C8 0128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register 01C8 012C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register Receive Maximum Length Register Receive Buffer Offset Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-86. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRONYM 01C8 0130 RX4FLOWTHRESH REGISTER NAME Receive Channel 4 Flow Control Threshold Register 01C8 0134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register 01C8 0138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register 01C8 013C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register 01C8 0140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register 01C8 0144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register 01C8 0148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register 01C8 014C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register 01C8 0150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register 01C8 0154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register 01C8 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register 01C8 015C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register 01C8 0160 MACCONTROL MAC Control Register 01C8 0164 MACSTATUS MAC Status Register Emulation Control Register 01C8 0168 EMCONTROL 01C8 016C FIFOCONTROL 01C8 0170 MACCONFIG MAC Configuration Register Soft Reset Register FIFO Control Register (Transmit and Receive) 01C8 0174 SOFTRESET 01C8 01D0 MACSRCADDRLO MAC Source Address Low Bytes Register (Lower 16-bits) 01C8 01D4 MACSRCADDRHI MAC Source Address High Bytes Register (Upper 32-bits) 01C8 01D8 MACHASH1 MAC Hash Address Register 1 01C8 01DC MACHASH2 MAC Hash Address Register 2 01C8 01E0 BOFFTEST Back Off Test Register 01C8 01E4 TPACETEST Transmit Pacing Algorithm Test Register 01C8 01E8 RXPAUSE Receive Pause Timer Register 01C8 01EC TXPAUSE Transmit Pause Timer Register 01C8 0200 - 01C8 02FC (see Table 6-87) 01C8 0500 MACADDRLO MAC Address Low Bytes Register 01C8 0504 MACADDRHI MAC Address High Bytes Register 01C8 0508 MACINDEX 01C8 0600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register 01C8 0604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 01C8 0608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register 01C8 060C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register 01C8 0610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register 01C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 01C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 01C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 01C8 0620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register 01C8 0624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register 01C8 0628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register 01C8 062C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register 01C8 0630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register 01C8 0634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register EMAC Statistics Registers MAC Index Register 01C8 0638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register 01C8 063C RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register 01C8 0640 TX0CP Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 209 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-86. Ethernet MAC (EMAC) Control Registers (continued) 210 HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0644 TX1CP Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register 01C8 0648 TX2CP Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register 01C8 064C TX3CP Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register 01C8 0650 TX4CP Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register 01C8 0654 TX5CP Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register 01C8 0658 TX6CP Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register 01C8 065C TX7CP Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register 01C8 0660 RX0CP Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register 01C8 0664 RX1CP Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register 01C8 0668 RX2CP Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register 01C8 066C RX3CP Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register 01C8 0670 RX4CP Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register 01C8 0674 RX5CP Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register 01C8 0678 RX6CP Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register 01C8 067C RX7CP Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-87. EMAC Statistics Registers HEX ADDRESS RANGE ACRONYM 01C8 0200 RXGOODFRAMES REGISTER NAME Good Receive Frames Register 01C8 0204 RXBCASTFRAMES Broadcast Receive Frames Register (Total number of good broadcast frames received) 01C8 0208 RXMCASTFRAMES Multicast Receive Frames Register (Total number of good multicast frames received) 01C8 020C RXPAUSEFRAMES Pause Receive Frames Register 01C8 0210 RXCRCERRORS 01C8 0214 RXALIGNCODEERRORS 01C8 0218 RXOVERSIZED 01C8 021C RXJABBER 01C8 0220 RXUNDERSIZED Receive Undersized Frames Register (Total number of undersized frames received) 01C8 0224 RXFRAGMENTS Receive Frame Fragments Register Receive CRC Errors Register (Total number of frames received with CRC errors) Receive Alignment/Code Errors Register (Total number of frames received with alignment/code errors) Receive Oversized Frames Register (Total number of oversized frames received) Receive Jabber Frames Register (Total number of jabber frames received) 01C8 0228 RXFILTERED 01C8 022C RXQOSFILTERED Filtered Receive Frames Register 01C8 0230 RXOCTETS 01C8 0234 TXGOODFRAMES Good Transmit Frames Register (Total number of good frames transmitted) 01C8 0238 TXBCASTFRAMES Broadcast Transmit Frames Register 01C8 023C TXMCASTFRAMES Multicast Transmit Frames Register 01C8 0240 TXPAUSEFRAMES Pause Transmit Frames Register 01C8 0244 TXDEFERRED Deferred Transmit Frames Register 01C8 0248 TXCOLLISION Transmit Collision Frames Register 01C8 024C TXSINGLECOLL 01C8 0250 TXMULTICOLL 01C8 0254 TXEXCESSIVECOLL Received QOS Filtered Frames Register Receive Octet Frames Register (Total number of received bytes in good frames) Transmit Single Collision Frames Register Transmit Multiple Collision Frames Register Transmit Excessive Collision Frames Register 01C8 0258 TXLATECOLL 01C8 025C TXUNDERRUN Transmit Late Collision Frames Register 01C8 0260 TXCARRIERSENSE 01C8 0264 TXOCTETS 01C8 0268 FRAME64 01C8 026C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register 01C8 0270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register 01C8 0274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register 01C8 0278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register 01C8 027C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register Transmit Underrun Error Register Transmit Carrier Sense Errors Register Transmit Octet Frames Register Transmit and Receive 64 Octet Frames Register 01C8 0280 NETOCTETS 01C8 0284 RXSOFOVERRUNS Network Octet Frames Register Receive FIFO or DMA Start of Frame Overruns Register 01C8 0288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register 01C8 028C RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 211 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-88. EMAC Control Module Registers HEX ADDRESS RANGE ACRONYM 0x01C8 1004 EWCTL 0x01C8 1008 EWINTTCNT REGISTER NAME Interrupt control register Interrupt timer count Table 6-89. EMAC Control Module RAM HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 2000 - 0x01C8 3FFF 6.19.2 EMAC Control Module Descriptor Memory EMAC Electrical Data/Timing Table 6-90. Timing Requirements for MRCLK (see Figure 6-65) 1.05 V and 1.2 V NO. MIN UNIT MAX 1 tc(MRCLK) Cycle time, MRCLK 40 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 14 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 14 ns 1 2 3 MRCLK Figure 6-65. MRCLK Timing (EMAC - Receive) Table 6-91. Timing Requirements for MTCLK (see Figure 6-65) 1.05 V and 1.2 V NO. MIN UNIT MAX 1 tc(MTCLK) Cycle time, MTCLK 40 ns 2 tw(MTCLKH) Pulse duration, MTCLK high 14 ns 3 tw(MTCLKL) Pulse duration, MTCLK low 14 ns 1 2 3 MTCLK Figure 6-66. MTCLK Timing (EMAC - Transmit) 212 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-92. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (1) (see Figure 6-67) 1.05 V and 1.2 V NO. MIN UNIT MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. 1 2 MRCLK (Input) MRXD3−MRXD0, MRXDV, MRXER (Inputs) Figure 6-67. EMAC Receive Interface Timing Table 6-93. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (1) (see Figure 6-68) 1.05 V and 1.2 V NO. 1 (1) td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid MIN MAX 5 25 UNIT ns Transmit selected signals include: MTXD3-MTXD0, and MTXEN. 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) Figure 6-68. EMAC Transmit Interface Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 213 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.20 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared 2-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time. For more detailed information on the MDIO peripheral, see the TMS320DM644x DMSoC Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide (literature number SPRUE24). For a list of supported registers and register fields, see Table 6-94 [MDIO Registers] in this data manual. 6.20.1 Peripheral Register Description(s) Table 6-94. MDIO Registers HEX ADDRESS RANGE ACRONYM 0x01C8 4000 – REGISTER NAME 0x01C8 4004 CONTROL 0x01C8 4008 ALIVE MDIO PHY Alive Status Register 0x01C8 400C LINK MDIO PHY Link Status Register 0x01C8 4010 LINKINTRAW 0x01C8 4014 LINKINTMASKED Reserved MDIO Control Register MDIO Link Status Change Interrupt (Unmasked) Register MDIO Link Status Change Interrupt (Masked) Register 0x01C8 4018 – 0x01C8 4020 USERINTRAW Reserved 0x01C8 4024 USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register MDIO User Command Complete Interrupt Mask Set Register MDIO User Command Complete Interrupt (Unmasked) Register 0x01C8 4028 USERINTMASKSET 0x01C8 402C USERINTMASKCLEAR 0x01C8 4030 - 0x01C8 407C – 0x01C8 4080 USERACCESS0 MDIO User Access Register 0 0x01C8 4084 USERPHYSEL0 MDIO User PHY Select Register 0 0x01C8 4088 USERACCESS1 MDIO User Access Register 1 0x01C8 408C USERPHYSEL1 MDIO User PHY Select Register 1 0x01C8 4090 - 0x01C8 47FF – 214 MDIO User Command Complete Interrupt Mask Clear Register Reserved Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com 6.20.2 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Management Data Input/Output (MDIO) Electrical Data/Timing Table 6-95. Timing Requirements for MDIO Input (see Figure 6-69 and Figure 6-70) 1.05 V and 1.2 V NO. MIN 1 tc(MDCLK) Cycle time, MDCLK 400 2 tw(MDCLK) Pulse duration, MDCLK high/low 180 3 tt(MDCLK) Transition time, MDCLK 4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high UNIT MAX ns ns 5 ns 15 ns 0 ns 1 3 3 MDCLK 4 5 MDIO (input) Figure 6-69. MDIO Input Timing Table 6-96. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 6-70) 1.05 V and 1.2 V NO. 7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid MIN MAX - 0.6 100 UNIT ns 1 MDCLK 7 MDIO (output) Figure 6-70. MDIO Output Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 215 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.21 Timer The DM6441 device has three 64-bit general-purpose timers which have the following features: • 64-bit count-up counter • Timer modes: – 64-bit general-purpose timer mode – Dual 32-bit general-purpose timer mode (Timer 0 and 1) – Watchdog timer mode • Two possible clock sources: – Internal clock – External clock input via timer input pin TIM_IN (Timer 0 only) • Two operation modes: – One-time operation (timer runs for one period then stops) – Continuous operation (timer automatically resets after each period) • Generates interrupts to both the DSP and the ARM CPUs • Generates sync event to EDMA3 For more detailed information, see the TMS320DM644x DMSoC 64-Bit Timer User's Guide (literature number SPRUE26). 6.21.1 Timer Peripheral Register Description(s) Table 6-97. Timer 0 Registers HEX ADDRESS RANGE ACRONYM 0x01C2 1400 - DESCRIPTION 0x01C2 1404 EMUMGT_CLKSPD 0x01C2 1410 TIM12 Timer 0 Counter Register 12 0x01C2 1414 TIM34 Timer 0 Counter Register 34 0x01C2 1418 PRD12 Timer 0 Period Register 12 0x01C2 141C PRD34 Timer 0 Period Register 34 0x01C2 1420 TCR 0x01C2 1424 TGCR 0x01C2 1428 - 0x01C2 17FF - Reserved Timer 0 Emulation Management/Clock Speed Register Timer 0 Control Register Timer 0 Global Control Register Reserved Table 6-98. Timer 1 Registers HEX ADDRESS RANGE 216 ACRONYM DESCRIPTION 0x01C2 1800 - 0x01C2 1804 EMUMGT_CLKSPD Reserved 0x01C2 1810 TIM12 Timer 1 Counter Register 12 0x01C2 1814 TIM34 Timer 1 Counter Register 34 0x01C2 1818 PRD12 Timer 1 Period Register 12 0x01C2 181C PRD34 Timer 1 Period Register 34 0x01C2 1820 TCR 0x01C2 1824 TGCR 0x01C2 1828 - 0x01C2 1BFF - Timer 1 Emulation Management/Clock Speed Register Timer 1 Control Register Timer 1 Global Control Register Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-99. Watchdog Timer Registers HEX ADDRESS RANGE ACRONYM 0x01C2 1C00 - 0x01C2 1C04 EMUMGT_CLKSPD 0x01C2 1C10 TIM12 Watchdog timer Counter Register 12 0x01C2 1C14 TIM34 Watchdog timer Counter Register 34 0x01C2 1C18 PRD12 Watchdog timer Period Register 12 0x01C2 1C1C PRD34 Watchdog timer Period Register 34 0x01C2 1C20 TCR 0x01C2 1C24 TGCR 0x01C2 1C28 WDTCR 0x01C2 1C2C - 0x01C2 1FFF - 6.21.2 DESCRIPTION Reserved Watchdog timer Emulation Management/Clock Speed Register Watchdog timer Control Register Watchdog timer Global Control Register Watchdog timer Watchdog Timer Control Register Reserved Timer Electrical Data/Timing Table 6-100. Timing Requirements for Timer Input (1) (2) (see Figure 6-71) 1.05 V and 1.2 V NO. (1) (2) MIN MAX 4P UNIT 1 tc(TIN) Cycle time, TIM_IN ns 2 tw(TINPH) Pulse duration, TIM_IN high 0.45C 0.55C ns 3 tw(TINPL) Pulse duration, TIM_IN low 0.45C 0.55C ns 4 tt(TIN) Transition time, TIM_IN 0.05C ns P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns. C = TIM_IN cycle time in ns. For example, when TIM_IN frequency is 27 MHz, use C = 37.037 ns 1 2 4 3 4 TIM_IN Figure 6-71. Timer Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 217 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.22 www.ti.com Pulse Width Modulator (PWM) The three pulse width modulator (PWM) peripherals support the following features: • Period counter • First-phase duration counter • Repeat count for one-shot operation • Configurable to operate in either one-shot or continuous mode • Buffered period and first-phase duration registers • One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or high-to-low). • One-shot operation generates N+1 periods of waveform, N being the repeat count register value • Emulation support The register memory maps for PWM0/1/2 are shown in Table 6-101, Table 6-102, and Table 6-103. Table 6-101. PWM0 Register Memory Map HEX ADDRESS RANGE ACRONYM 0x01C2 2000 REGISTER NAME Reserved 0x01C2 2004 PCR PWM0 Peripheral Control Register 0x01C2 2008 CFG PWM0 Configuration Register 0x01C2 200C START PWM0 Start Register 0x01C2 2010 RPT PWM0 Repeat Count Register 0x01C2 2014 PER PWM0 Period Register 0x01C2 2018 PH1D PWM0 First-Phase Duration Register 0x01C2 201C - 0x01C2 23FF - Reserved Table 6-102. PWM1 Register Memory Map HEX ADDRESS RANGE ACRONYM 0x01C2 2400 REGISTER NAME Reserved 0x01C2 2404 PCR PWM1 Peripheral Control Register 0x01C2 2408 CFG PWM1 Configuration Register 0x01C2 240C START PWM1 Start Register 0x01C2 2410 RPT PWM1 Repeat Count Register 0x01C2 2414 PER PWM1 Period Register 0x01C2 2418 PH1D PWM1 First-Phase Duration Register 0x01C2 241C -0x01C2 27FF - Reserved Table 6-103. PWM2 Register Memory Map HEX ADDRESS RANGE ACRONYM 0x01C2 2800 REGISTER NAME Reserved 0x01C2 2804 PCR PWM2 Peripheral Control Register 0x01C2 2808 CFG PWM2 Configuration Register 0x01C2 280C START PWM2 Start Register 0x01C2 2810 RPT PWM2 Repeat Count Register 0x01C2 2814 PER PWM2 Period Register 0x01C2 2818 PH1D PWM2 First-Phase Duration Register 0x01C2 281C - 0x01C2 2BFF - Reserved 218 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.22.1 PWM0/1/2 Electrical/Timing Data Table 6-104. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2 Outputs (see Figure 6-72 and Figure 6-73) NO. 1.05 V and 1.2 V PARAMETER MIN 1 tw(PWMH) Pulse duration, PWMx high 37 2 tw(PWML) Pulse duration, PWMx low 37 3 tt(PWM) Transition time, PWMx 4 td(CCDC-PWMV) Delay time, CCDC(VD) trigger event to PWMx valid 2 UNIT MAX ns ns 5 ns 10 ns 1 2 PWM0/1/2 3 3 Figure 6-72. PWM Output Timing VD(CCDC) 4 PWM0 INVALID VALID 4 PWM1 INVALID VALID 4 PWM2 INVALID VALID Figure 6-73. PWM Output Delay Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 219 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.23 www.ti.com VLYNQ The DM6441 VLYNQ peripheral provides a high speed serial communications interface with the following features. • Low pin count • Scalable performance/support • Simple packet based transfer protocol for memory mapped access – Write request/data packet – Read request packet – Read response data packet – Interrupt request packet • Supports both symmetric and asymmetric operation – Tx pins on first device connect to Rx pins on second device and vice versa – Data pin widths are automatically detected after reset – Request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins – Supports both host/peripheral and peer-to-peer communication • Simple block code packet formatting (8-b/10-b) • In band flow control – No extra pins needed – Allows receiver to momentarily throttle back transmitter when overflow is about to occur – Uses built in special code capability of block code to seamlessly interleave flow control information with user data – Allows system designer to balance cost of data buffering versus performance • Multiple outstanding transactions • Automatic packet formatting optimizations • Internal loop-back mode 6.23.1 VLYNQ Peripheral Register Description(s) Table 6-105. VLYNQ Registers 220 HEX ADDRESS RANGE ACRONYM 0x01E0 1000 - REGISTER NAME 0x01E0 1004 CTRL VLYNQ Local Control Register VLYNQ Local Status Register Reserved 0x01E0 1008 STAT 0x01E0 100C INTPRI 0x01E0 1010 INTSTATCLR VLYNQ Local Unmasked Interrupt Status/Clear Register 0x01E0 1014 INTPENDSET VLYNQ Local Interrupt Pending/Set Register 0x01E0 1018 INTPTR 0x01E0 101C XAM VLYNQ Local Interrupt Priority Vector Status/Clear Register VLYNQ Local Interrupt Pointer Register VLYNQ Local Transmit Address Map Register 0x01E0 1020 RAMS1 VLYNQ Local Receive Address Map Size 1 Register 0x01E0 1024 RAMO1 VLYNQ Local Receive Address Map Offset 1 Register 0x01E0 1028 RAMS2 VLYNQ Local Receive Address Map Size 2 Register 0x01E0 102C RAMO2 VLYNQ Local Receive Address Map Offset 2 Register 0x01E0 1030 RAMS3 VLYNQ Local Receive Address Map Size 3 Register 0x01E0 1034 RAMO3 VLYNQ Local Receive Address Map Offset 3 Register 0x01E0 1038 RAMS4 VLYNQ Local Receive Address Map Size 4 Register 0x01E0 103C RAMO4 VLYNQ Local Receive Address Map Offset 4 Register 0x01E0 1040 CHIPVER VLYNQ Local Chip Version Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-105. VLYNQ Registers (continued) HEX ADDRESS RANGE ACRONYM 0x01E0 1044 AUTNGO REGISTER NAME VLYNQ Local Auto Negotiation Register 0x01E0 1048 - Reserved 0x01E0 104C - Reserved 0x01E0 1050 - 0x01E0 105C - Reserved 0x01E0 1060 - Reserved 0x01E0 1064 - Reserved 0x01E0 1068 - 0x01E0 107C - Reserved for future use 0x01E0 1080 RREVID VLYNQ Remote Revision Register 0x01E0 1084 RCTRL VLYNQ Remote Control Register 0x01E0 1088 RSTAT VLYNQ Remote Status Register 0x01E0 108C RINTPRI VLYNQ Remote Interrupt Priority Vector Status/Clear Register 0x01E0 1090 RINTSTATCLR VLYNQ Remote Unmasked Interrupt Status/Clear Register 0x01E0 1094 RINTPENDSET VLYNQ Remote Interrupt Pending/Set Register 0x01E0 1098 RINTPTR VLYNQ Remote Interrupt Pointer Register 0x01E0 109C RXAM 0x01E0 10A0 RRAMS1 VLYNQ Remote Transmit Address Map Register VLYNQ Remote Receive Address Map Size 1 Register 0x01E0 10A4 RRAMO1 VLYNQ Remote Receive Address Map Offset 1 Register 0x01E0 10A8 RRAMS2 VLYNQ Remote Receive Address Map Size 2 Register 0x01E0 10AC RRAMO2 VLYNQ Remote Receive Address Map Offset 2 Register 0x01E0 10B0 RRAMS3 VLYNQ Remote Receive Address Map Size 3 Register 0x01E0 10B4 RRAMO3 VLYNQ Remote Receive Address Map Offset 3 Register 0x01E0 10B8 RRAMS4 VLYNQ Remote Receive Address Map Size 4 Register 0x01E0 10BC RRAMO4 VLYNQ Remote Receive Address Map Offset 4 Register 0x01E0 10C0 RCHIPVER VLYNQ Remote Chip Version Register (values on the device_id and device_rev pins of remote VLYNQ) 0x01E0 10C4 RAUTNGO VLYNQ Remote Auto Negotiation Register 0x01E0 10C8 RMANNGO VLYNQ Remote Manual Negotiation Register VLYNQ Remote Negotiation Status Register 0x01E0 10CC RNGOSTAT 0x01E0 10D0 - 0x01E0 10DC - 0x01E0 10E0 RINTVEC0 VLYNQ Remote Interrupt Vectors 3 - 0 (sourced from vlynq_int_i[3:0] port of remote VLYNQ) 0x01E0 10E4 RINTVEC1 VLYNQ Remote Interrupt Vectors 7 - 4 (sourced from vlynq_int_i[7:4] port of remote VLYNQ) 0x01E0 10E8 - 0x01E0 10FC - Reserved for future use 0x01E0 1100 - 0x01E0 1FFF - Reserved Reserved Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 221 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.23.2 VLYNQ Electrical Data/Timing Table 6-106. Timing Requirements for VLYNQ_CLK for VLYNQ (see Figure 6-74) 1.05 V and 1.2 V NO. 1 2 MIN tc(VCLK) tw(VCLKH) 3 tw(VCLKL) 4 tt(VCLK) Cycle time, VLYNQ_CLK MAX UNIT 10 ns Pulse duration, VLYNQ_CLK high [CLK external] 3 ns Pulse duration, VLYNQ_CLK high [CLK internal] 4 ns Pulse duration, VLYNQ_CLK low [CLK external] 3 ns Pulse duration, VLYNQ_CLK low [CLK internal] 4 ns Transition time, VLYNQ_CLK 3 1 ns 4 2 VLYNQ_CLK 4 3 Figure 6-74. VLYNQ_CLK Timing for VLYNQ 222 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-107. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-75) NO. 1 2 1.05 V and 1.2 V PARAMETER td(VCLKH-TXDI) td(VCLKH-TXDV) MIN MAX UNIT Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid [SLOW Mode] 1 ns Delay time, VLYNQ_CLK high to VLYNQ_ TXD[3:0] invalid [FAST Mode] 0.5 ns Delay time, VLYNQ_CLK to VLYNQ_TXD[3:0] valid 9.75 ns Table 6-108. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-75) 1.05 V NO. 3 4 MIN tsu(RXDV-VCLKH) th(VCLKH-RXDV) Setup time, VLYNQ_RXD[3:0] valid before VLYNQ_CLK high Hold time, VLYNQ_RXD[3:0] valid after VLYNQ_CLK high 1.2 V MAX MIN MAX UNIT RTM disabled, RTM sample =3 1.1 0.8 ns RTM enabled, RXD Flop = 0 2.8 2.2 ns RTM enabled, RXD Flop = 1 2.5 1.9 ns RTM enabled, RXD Flop = 2 1.8 1.4 ns RTM enabled, RXD Flop = 3 1.1 0.8 ns RTM enabled, RXD Flop = 4 0.4 0.4 ns RTM enabled, RXD Flop = 5 0 0.1 ns RTM enabled, RXD Flop = 6 -0.3 -0.2 ns RTM enabled, RXD Flop = 7 -0.5 -0.4 ns RTM disabled, RTM sample =3 2 2 ns RTM enabled, RXD Flop = 0 0.6 0.6 ns RTM enabled, RXD Flop = 1 1 1.0 ns RTM enabled, RXD Flop = 2 1.5 1.5 ns RTM enabled, RXD Flop = 3 2 2.0 ns RTM enabled, RXD Flop = 4 2.5 2.5 ns RTM enabled, RXD Flop = 5 3 3.0 ns RTM enabled, RXD Flop = 6 3.6 3.5 ns RTM enabled, RXD Flop = 7 4.1 4.0 ns 1 VLYNQ_CLK 2 Data VLYNQ_TXD[3:0] 4 3 VLYNQ_RXD[3:0] Data Figure 6-75. VLYNQ Transmit/Receive Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 223 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.24 Memory Stick/Memory Stick PRO This DM6441 Memory Stick/Memory Stick PRO peripheral conforms to the Memory Stick Standard Format Specification V.1.31 and the Memory Stick PRO Format Specification V. 1.00. The Memory Stick/Memory Stick PRO Controller has the following features: • Memory Stick and Memory Stick PRO memory card support. • Data transmit/receive FIFO size of 32-Bytes. Embedded memory can be used in place of the FIFO. • CRC circuit. • DMA support. • Memory Stick Clock [Version 1.3: 20 MHz (max), PRO: 40 MHz (max)] with a programmable divider. • Endian Conversions • Byte Swap 6.24.1 Memory Stick/Memory Stick PRO Peripheral Description(s) The Memory Stick register memory mapping is shown in Table 6-109. Table 6-109. Memory Stick Register Memory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E2 0000 MSCMD Memory Stick Command Register 0x01E2 0004 MSD Memory Stick Data Register 0x01E2 0008 MSSTAT Memory Stick Status Register 0x01E2 000C MSSYS Memory Stick System Register 0x01E2 0010 - 0x01E2 001F 0x01E2 0020 224 Reserved MSMC Memory Stick Module Control Register Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.24.2 Memory Stick/Memory Stick PRO Electrical Data/Timing Table 6-110. Timing Requirements for Memory Stick/Memory Stick PRO Serial Interface (see Figure 6-76) 1.05 V and 1.2 V NO. MIN UNIT MAX 1 tsu(DV-MSCLKr) Setup time, data valid before MS_CLK rising edge 5 ns 2 th(MCLKr-DV) Hold time, data valid after MS_CLK rising edge 7 ns MS_CLK 1 2 Valid MS_DATA Figure 6-76. Memory Stick/Memory Stick PRO Serial Interface Input Timing Table 6-111. Switching Characteristics Over Recommended Operating Conditions for Memory Stick/Memory Stick PRO Serial Interface (see Figure 6-77) NO. 1.05 V and 1.2 V PARAMETER MIN MAX 20 UNIT 3 f(MS_CLK) MS_CLK frequency 4 tw(MS_CLKH) Pulse duration, MS_CLK high 15 5 tw(MS_CLKL) Pulse duration, MS_CLK low 15 6 tf(MS_CLK) Fall time, MS_CLK 10 ns 7 tr(MS_CLK) Rise time, MS_CLK 10 ns 8 td(MS_CLK - MS_BSV) Delay time, MS_CLK falling edge to MS_BS valid 15 ns 9 tf(MS_BS) Fall time, MS_BS 5 ns 10 tr(MS_BS) Rise time, MS_BS 5 ns 11 td(MS_CLK - MS_DATxV) Delay time, MS_CLK falling edge to MS_DATx valid 15 ns 12 tf(MS_DATx) Fall time, MS_DATx 5 ns 13 tr(MS_DATx) Rise time, MS_DATx 5 ns 4 6 -15 -15 MHz ns ns 5 3 7 MS_CLK 8 10 9 MS_BS 11 13 12 Valid MS_DATA Figure 6-77. Memory Stick/Memory Stick PRO Serial Interface Output Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 225 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com Table 6-112. Timing Requirements for Memory Stick/Memory Stick PRO Parallel Interface (see Figure 6-78) 1.05 V NO. MIN 1 tsu(DV-MSCLKf) Setup time, data valid before MS_CLK falling edge 2 th(MCLKf-DV) Hold time, data valid after MS_CLK falling edge 1.2 V MAX MIN 2 MAX UNIT 6 ns 2 ns MS_CLK 1 2 Valid MS_DATA Figure 6-78. Memory Stick/Memory Stick PRO Parallel Interface Input Timing Table 6-113. Switching Characteristics Over Recommended Operating Conditions for Memory Stick/Memory Stick PRO Parallel Interface (see Figure 6-79) NO. 1.05 V PARAMETER MIN 1.2 V MAX MIN MAX 40 40 3 f(MS_CLK) MS_CLK frequency 4 tw(MS_CLKH) Pulse duration, MS_CLK high 5 5 5 tw(MS_CLKL) Pulse duration, MS_CLK low 5 5 6 tf(MS_CLK) Fall time, MS_CLK 7 tr(MS_CLK) Rise time, MS_CLK 8 td(MS_CLK - MS_BSV) Delay time, MS_CLK falling edge to MS_BS valid 9 tf(MS_BS) Fall time, MS_BS 10 tr(MS_BS) Rise time, MS_BS 11 td(MS_CLK - MS_DATxV) Delay time, MS_CLK falling edge to MS_DATx valid 12 tf(MS_DATx) Fall time, MS_DATx 13 tr(MS_DATx) Rise time, MS_DATx 5 5 16 2 5 5 4 6 2 2 UNIT MHz ns ns 5 ns 5 ns 16 ns 5 ns 5 ns 16 ns 5 5 ns 5 5 ns 16.6 2 5 3 7 MS_CLK 8 10 9 MS_BS 11 13 12 Valid MS_DATA Figure 6-79. Memory Stick/Memory Stick PRO Parallel Interface Output Timing 226 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.25 Host-Port Interface (HPI) The host port interface (HPI) provides a parallel port through which an external host processor can access the DM6441 memory space. The host device is asynchronous to the DM6441 clocks and functions as a master to the HPI interface. The HPI enables a host device and DM6441 to exchange information via internal or external memory. Both the host and DM6441 can access the HPI control register (HPIC) and the HPI address registers (HPIAR, HPIAW). The host can access the HPI data register (HPID) and the HPIC by using the external data and interface control signals. The HPI interface shares the DM6441 EMIFA 16-bit data bus pins for multiplexed address/data and supports the following modes: • 16 Bit Multiplexed mode / dual half-word cycles (16 bit host data bus/32 bit memory width) • ARM ROM supports booting of DM6441 ARM processor from an external processor The HPI registers are summarized in Table 6-114. For more detailed information on the HPI peripheral, see the TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (literature number SPRUE97). Table 6-114. Host-Port Interface (HPI) Register Descriptions HEX ADDRESS RANGE ACRONYM 0x01C4 0030 HPI_CTL REGISTER NAME Host-Port Interface Configuration Register 0x01C6 7800 HPI_PID 0x01C6 7804 HPIPWREMU 0x01C6 7808 - 0x01C6 782F – 0x01C6 7830 HPIC 0x01C6 7834 HPIAW Host-Port Interface Write Address Register 0x01C6 7838 HPIAR Host-Port Interface Read Address Register 0x01C6 783C - 0x01C6 7FFF – HPI Power and Emulation Management Register Reserved Host-Port Interface Control Register Reserved The HPI_CTL register sets the owner of HPIA(R/W) and HPIC registers for HPI address and control. The details for HPI_CTL are shown in Figure 6-80 and Table 6-115. Figure 6-80. HPI_CTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved R-0000000000000000 15 14 13 12 11 10 9 8 7 CTL ADD MODE MODE Reserved R-0 R/W-0 TIMOUT R/W-0 R/W-10000000 LEGEND: R = Read, W = Write, n = value at reset Table 6-115. HPI_CTL Register Description Name Description CTLMODE HPIC register write access 0 = External Host 1 = DM6441 (if ADDMODE = 1) ADDMODE HPIA register write access 0 = External Host 1 = DM6441 TIMOUT Host burst write timeout value Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 227 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.25.1 www.ti.com Host-Port Interface (HPI) Electrical Data/Timing Table 6-116. Timing Requirements for Host-Port Interface Cycles (1) (see Figure 6-81 through Figure 6-82) (2) 1.05 V and 1.2 V NO. MIN UNIT MAX 1 tsu(SELV-HSTBL) Setup time, select signals (3) valid before HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals (3) valid after HSTROBE low 2 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 15 ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 2P ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 0 ns th(HRDYL-HSTBH) Hold time, HSTROBE high after HRDY low. HSTROBE should not beinactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 14 (1) (2) (3) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 405 MHz, use P = 2.47 ns. Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. Table 6-117. Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles (1) (see Figure 6-81 through Figure 6-82) NO. 1.05 V and 1.2 V PARAMETER MIN MAX 12 UNIT 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high (2) 0 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 0 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only) 20 td(HCSL-HRDYH) Delay time, HCS low to HRDY high (1) (2) 228 0 ns 4 ns 15 ns 12 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA3 internal address generation hardware, and HRDY remains high until the EDMA3 internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full. Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 3 HSTROBE(A) HCS 15 9 7 15 9 16 HD[15:0] (output) HRDY A. 1st half-word 6 20 2nd half-word 8 HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 6-81. HPI16 Read Timing 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 HSTROBE(A) HCS 12 12 13 13 HD[15:0] (input) 1st half-word HRDY A. 20 6 2nd half-word 14 HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 6-82. HPI16 Write Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 229 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 6.26 IEEE 1149.1 JTAG The JTAG (3) interface is used for BSDL testing and emulation of the DM6441 device. The DM6441 device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For maximum reliability, DM6441 includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Note: The sequencing of all the JTAG signals must follow the IEEE.1149.1 JTAG standard. 6.26.1 JTAG Peripheral Register Description(s) – JTAG ID Register Table 6-118. JTAG ID Register HEX ADDRESS RANGE 0x01C4 0028 (3) ACRONYM REGISTER NAME JTAGID COMMENTS Read-only. Provides 32-bit JTAG ID of the device. JTAG Identification Register IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the DM6441 device, the JTAG ID register resides at address location 0x01C4 0028. The register hex value for DM6441 is: 0x0B70 002F for silicon revisions 1.3 and earlier, and 0x1B70 002F for silicon revision 2.1 and later. For the actual register bit names and their associated bit field descriptions, see Figure 6-83 and Table 6-119. 31-28 27-12 11-1 0 VARIANT (4-Bit)(A) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB R-000x R-1011 0111 0000 0000 R-0000 0010 111 R-1 LEGEND: R = Read, W = Write, n = value at reset (A) For silicon revisions 1.3 and earlier, VARIANT = 0000. For silicon revision 2.1 and later, VARIANT = 0001. Figure 6-83. JTAG ID Register Description - DM6441 Register Value - 0xXB70 002F 230 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-119. JTAG ID Register Selection Bit Descriptions BIT NAME 31:28 VARIANT 27:12 PART NUMBER 11-1 MANUFACTURER 0 LSB 6.26.2 DESCRIPTION Variant (4-Bit) value. DM6441 value: 0000 for silicon revisions 1.3 and earlier, and 0001 for silicon revision 2.1 and later. Part Number (16-Bit) value. DM6441 value: 1011 0111 0000 0000. Manufacturer (11-Bit) value. DM6441 value: 0000 0010 111. LSB. This bit is read as a "1" for DM6441. JTAG Test-Port Electrical Data/Timing Table 6-120. Timing Requirements for JTAG Test Port (see Figure 6-84) 1.05 V and 1.2 V NO. MIN UNIT MAX 1 tc(TCK) Cycle time, TCK 20 ns 2 tw(TCKH) Pulse duration, TCK high 8 ns 3 tw(TCKL) Pulse duration, TCK low 8 ns 4 tc(RTCK) Cycle time, RTCK 20 ns 5 tw(RTCKH) Pulse duration, RTCK high 10 ns 6 tw(RTCKL) Pulse duration, RTCK low 10 ns 7 tsu(TDIV-RTCKH) Setup time, TDI/TMS valid before RTCK high 10 ns 8 th(RTCKH-TDIV) Hold time, TDI/TMS valid after RTCK high 1 ns Table 6-121. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 6-84) NO. 1.05 V and 1.2 V PARAMETER MIN 9 td(RTCKL-TDOV) Delay time, RTCK low to TDO valid UNIT MAX 15 ns 1 2 3 TCK 4 5 6 RTCK 9 TDO 8 7 TDI/TMS Figure 6-84. JTAG Test-Port Timing Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 231 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 7 Mechanical Packaging and Orderable Information The following table(s) show the thermal resistance characteristics for the PBGA–ZWT mechanical package. 7.1 Thermal Data for ZWT Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZWT] NO. °C/W (1) AIR FLOW (m/s) (2) N/A 1 RΘJC Junction-to-case 6.54 2 RΘJB Junction-to-board 15.62 N/A 29.75 0.00 3 4 26.78 1.0 26.20 2.00 6 25.80 3.00 7 0.11 0.00 8 0.15 1.0 0.16 2.00 10 0.16 3.00 11 14.79 0.00 12 14.66 1.0 14.66 2.00 14.66 3.00 5 9 13 RΘJA PsiJT PsiJB Junction-to-free air Junction-to-package top Junction-to-board 14 (1) (2) 7.2 These measurements were conducted in a JEDEC defined 1S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. m/s = meters per second Packaging Information The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document. 232 Mechanical Packaging and Orderable Information Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 PACKAGE OPTION ADDENDUM www.ti.com 13-May-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SN3490586 ACTIVE NFBGA ZWT 361 90 RoHS & Green Call TI Level-3-260C-168 HR DM6441AZWT TMS320 DAVINCI TMS320DM6441AZWT ACTIVE NFBGA ZWT 361 90 RoHS & Green Call TI Level-3-260C-168 HR DM6441AZWT TMS320 DAVINCI TMS320DM6441BZWT ACTIVE NFBGA ZWT 361 90 RoHS & Green Call TI Level-3-260C-168 HR DM6441BZWT TMS320 DAVINCI TNETV1647GSTZWT ACTIVE NFBGA ZWT 361 90 RoHS & Green Call TI Level-3-260C-168 HR DM6441AZWT TMS320 DAVINCI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of