TMS320VC5420GGU200

   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core Each Core Has a 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/ Accumulate (MAC) Operations Each Core Has a Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Each Core Has an Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Each Core Has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) 16-Bit Data Bus With Data Bus Holder Feature 256K × 16 Extended Program Address Space Total of 192K × 16 Dual- and Single-Access On-Chip RAM Single-Instruction Repeat and Block-Repeat Operations Instructions With 32-Bit Long Word Operands Instructions With 2 or 3 Operand Reads Fast Return From Interrupts D Arithmetic Instructions With Parallel Store D D D D D D D D D D D D D D D and Parallel Load Conditional Store Instructions Output Control of CLKOUT Output Control of TOUT Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions Dual 1.8-V (Core) and 3.3-V (I/O) Power Supplies for Low Power, Fast Operation 10-ns Single-Cycle Fixed-Point Instruction Execution Interprocessor Communication via Two Internal 8-Element FIFOs 12 Channels of Direct Memory Access (DMA) for Data Transfers With No CPU Loading (6 Channels Per Subsystem) Six Multichannel Buffered Serial Ports (McBSPs) (Three McBSPs Per Subsystem) 16-Bit Host-Port Interface (HPI16) Multiplexed With External Memory Interface Pins Software-Programmable Phase-Locked Loop (PLL) Provides Several Clocking Options (Requires External TTL Oscillator) On-Chip Scan-Based Emulation Logic Two Software-Programmable Timers (One Per Subsystem) Software-Programmable Wait-State Generator (14 Wait States Maximum) Provided in 144-pin BGA Ball Grid Array (GGU Suffix) and 144-pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) Packages NOTE: This data sheet is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C54x is a trademark of Texas Instruments. All trademarks are the property of their respective owners. Copyright  2008, Texas Instruments Incorporated 
 
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   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multicore Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16-bit Host-Port Interface (HPI16) . . . . . . . . . . . . . . . . . . 24 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . 26 Direct Memory Access Unit (DMA) . . . . . . . . . . . . . . . . . . 27 Subsystem Communications . . . . . . . . . . . . . . . . . . . . . . . 29 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IDLE3 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . 39 Emulating the 5420 Device . . . . . . . . . . . . . . . . . . . . . . . . 39 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . External Multiply-By-N Clock Option . . . . . . . . . . . . . . . . Bypass Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface Timing for One Wait State . . Ready Timing for Externally Generated Wait States . . . Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . I/O Port Timing for Externally Generated Wait States . . Reset, BIO, Interrupt, and XIO Timing . . . . . . . . . . . . . . . External Flag (XF) and Timer Output (TOUT) Timing . . General-Purpose Input/Output (GPIO) Timing . . . . . . . . SELA/B Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port Timing . . . . . . . . . . . . . HPI16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 42 43 44 45 49 51 53 55 57 58 59 60 68 76 REVISION HISTORY REVISION PRODUCT STATUS HIGHLIGHTS * March 1999 Advance Information Original A April 1999 Advance Information Updated characteristics data. B September 1999 Production Data Updated characteristics data. C April 2000 Production Data Updated characteristics data. D June 2000 Production Data Updated characteristics data. E April 2001 Production Data Removed 4K × 16-bit block of on-chip memory labeled SARAM4. This is no longer a supported feature of this device. Production Data Signal Descriptions table: − Added footnote about TRST Mechanical Data section: − Added paragraph about packaging information − Added “Package Thermal Resistance Characteristics” section − Mechanical drawings will be appended to this document via an automated process F 2 DATE October 2008 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 description The TMS320VC5420 fixed-point digital signal processor (DSP) is a dual CPU device capable of up to 200-MIPS performance. The 5420 consists of two independent 54x subsystems capable of core-to-core communications. Each subsystem CPU is based on an advanced, modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. Each subsystem has separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit manipulation operations that can be performed in a single machine cycle. In addition, the 5420 includes the control mechanisms to manage interrupts, repeated operations, and function calls. The 5420 is offered in two temperature ranges and individual part numbers as shown below. (Please note that the industrial temperature device part numbers do not follow the typical numbering tradition.) Commercial temperature devices (0°C to 100°C) TMS320VC5420PGE200 (144-pin LQFP) TMS320VC5420GGU200 (144-pin BGA) Industrial temperature range devices (−40°C to 100°C) TMS320C5420PGEA200 (144-pin LQFP) TMS320C5420GGUA200 (144-pin BGA) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 3 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 109 111 110 112 113 114 115 116 117 119 118 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 75 35 74 36 73 PPA14 PPA15 VSS PPA16 PPA17 B_INT0 B_INT1 B_NMI IS B_GPIO2/BIO B_GPIO1 B_GPIO0 B_BFSR1 B_BDR1 CVDD VSS B_BCLKR1 B_BFSX1 VSS B_BDX1 B_BCLKX1 CVDD VSS TEST XIO B_RS B_XF B_CLKOUT HMODE HPIRS PPA13 PPA12 VSS DVDD PPA11 PPA10 VSS PPD15 PPD14 VSS PPD13 PPD12 A_BFSR0 A_BDR0 A_BCLKR0 A_BFSX0 VSS CVDD A_BDX0 A_BCLKX0 MSTRB DS PS B_BCLKX0 B_BDX0 DV DD V SS B_BFSX0 B_BCLKR0 B_BDR0 CVDD V SS B_BFSR0 R/W PPA2 PPA3 SELA/B PPD8 PPD9 PPD10 PPD11 VSS 72 76 34 71 77 33 70 78 32 69 79 31 68 80 30 67 81 29 66 82 28 65 83 27 64 84 26 63 85 25 62 86 24 61 87 23 60 88 22 59 89 21 58 90 20 57 91 19 56 92 18 55 93 17 54 94 16 53 95 15 52 96 14 51 97 13 50 98 12 49 99 11 48 100 10 47 101 9 46 102 8 45 103 7 44 104 6 43 105 5 42 106 4 41 3 40 107 39 108 2 38 1 37 PPD7 PPA8 PPA0 DVDD PPA9 PPD1 A_INT1 A_NMI IOSTRB A_GPIO2/BIO A_GPIO1 A_RS A_GPIO0 VSS VSS CVDD A_BFSR1 A_BDR1 A_BCLKR1 A_BFSX1 CVDD VSS A_BDX1 A_BCLKX1 A_XF A_CLKOUT VCO TCK TMS TDI TRST EMU1/OFF DVDD A_INT0 EMU0 TDO 143 144 VSS PPD0 PPD5 PPD4 PPD6 A_BFSX2 A_BDX2 A_BFSR2 A_BDR2 A_BCLKR2 VSS CV DD A_BCLKX2 READY DVDD CLKIN NC VSSA AV DD VSS B_BCLKX2 B_BDX2 B_BFSX2 B_BCLKR2 CVDD VSS B_BDR2 B_BFSR2 PPD2 PPD3 PPA1 PPA5 DV DD PPA4 PPA6 PPA7 TMS320VC5420 PGE PACKAGE†‡§ (TOP VIEW) † NC = No internal connection ‡ DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. § Pin configuration shown for nonmultiplexed mode only. See the Pin Assignments for the TMS320VC5420PGE table for multiplexed functions of specific pins. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 TMS320VC5420 GGU PACKAGE ( BOTTOM VIEW ) 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N The pin assignments table for the TMS320VC5420GGU lists each pin name and its associated pin number for this 144-pin ball grid array (BGA) package. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 pin assignments The 5420 pin assignments tables list each pin name and corresponding pin number for the two package types. Some of the 5420 pins can be configured for one of two functions. For these pins, the primary pin name is listed in the primary column. The secondary pin name is listed in the secondary column and is shaded grey. Pin Assignments for the TMS320VC5420PGE (144-Pin Low-Profile Quad Flatpack) PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME PIN NO. PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME PIN NO. PPD7 HD7 1 PPA8 PPA0 A_HINT 3 DVDD 5 PPD1 7 A_NMI 8 9 A_GPIO2/BIO 10 A_GPIO1 11 A_RS 12 A_GPIO0 13 14 VSS A_BFSR1 15 VSS CVDD 17 A_BDR1 18 A_BCLKR1 19 A_BFSX1 20 CVDD 21 23 VSS A_BCLKX1 22 A_BDX1 A_XF 25 A_CLKOUT 26 VCO 27 TCK 28 TMS 29 TDI 30 TRST 31 EMU1 32 DVDD 33 A_INT0 34 EMU0 35 TDO 36 PPA9 A_INT1 2 4 HD1 6 A_GPIO3 IOSTRB A_TOUT VSS PPD14 37 PPD15 HD14 39 PPD13 HD13 24 HD15 38 41 VSS PPD12 A_BFSR0 43 A_BDR0 44 A_BCLKR0 45 A_BFSX0 46 VSS A_BDX0 47 CVDD 48 49 A_BCLKX0 MSTRB HCS 51 DS PS HDS1 40 HD12 42 50 HDS2 52 53 B_BCLKX0 54 B_BDX0 55 DVDD 56 VSS B_BCLKR0 57 B_BFSX0 58 59 B_BDR0 60 CVDD 61 62 63 VSS R/W HR/W 64 65 PPA3 HCNTL0 66 B_BFSR0 PPA2 HCNTL1 SELA/B 6 16 67 PPD8 HD8 68 PPD9 HD9 69 PPD10 HD10 70 PPD11 HD11 71 VSS POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 72 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Pin Assignments for the TMS320VC5420PGE (144-Pin Low-Profile Quad Flatpack) (Continued) PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME PIN NO. PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME PIN NO. PPA10 73 PPA11 74 DVDD 75 76 PPA12 77 VSS PPA13 HPIRS 79 HMODE 80 B_CLKOUT 81 B_XF 82 B_RS 83 XIO 84 TEST 85 86 CVDD 87 VSS B_BCLKX1 B_BDX1 89 90 B_BFSX1 91 VSS B_BCLKR1 VSS B_BDR1 93 CVDD 94 95 B_BFSR1 96 B_GPIO0 97 B_GPIO1 B_GPIO2/BIO 99 B_NMI 101 B_INT1 102 B_INT0 103 PPA17 104 PPA16 105 107 VSS PPA14 106 PPA15 109 PPA6 110 111 DVDD 113 PPA1 B_HINT 114 HD2 116 PPA7 PPA4 HAS PPA5 PPD3 88 92 98 B_GPIO3 100 108 112 115 PPD2 B_BFSR2 117 B_BDR2 118 VSS B_BCLKR2 119 CVDD 120 121 B_BFSX2 122 B_BDX2 123 B_BCLKX2 124 VSS VSSA 125 AVDD NC 126 127 CLKIN 129 DVDD 130 READY HD3 IS 78 HRDY 128 131 A_BCLKX2 132 CVDD 133 134 A_BCLKR2 135 VSS A_BDR2 A_BFSR2 137 A_BDX2 A_BFSX2 139 PPD6 HD6 140 HD5 142 PPD4 HD4 141 PPD5 PPD0 HD0 143 VSS POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 136 138 144 7 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Pin Assignments for the TMS320VC5420GGU (144-Pin MicroStar BGA) PRIMARY SIGNAL NAME PPD7 SECONDARY SIGNAL NAME HD7 BALL NO. PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME BALL NO. A1 PPA8 B1 C1 A_NMI D1 A_RS E1 CVDD F1 A_BDR1 G1 CVDD H1 A_XF J1 TMS K1 EMU1/OFF L1 EMU0 M1 VSS N1 PPD0 HD0 A2 VSS B2 PPA0 A_HINT C2 A_INT1 D2 A_GPIO1 E2 VSS F2 A_BFSR1 G2 VSS H2 A_CLKOUT J2 TDI K2 DVDD L2 TDO M2 PPD15 HD15 DVDD N2 PDD6 HD6 A3 PPD4 HD4 B3 PPD5 HD5 C3 PPD1 HD1 D3 A_GPIO2/BIO E3 VSS F3 A_BCLKR1 G3 A_BDX1 H3 VCO J3 TRST A_INT0 L3 PPD14 VSS N3 A_BFSR2 A4 A_BDX2 B4 A_BFSX2 C4 PPA9 D4 IOSTRB A_GPIO0 F4 A_BFSX1 G4 A_BCLKX1 H4 TCK J4 K3 HD14 M3 A_GPIO3 PPD13 K4 PPD12 M4 A_BDR0 N4 CVDD A5 VSS B5 A_BCLKR2 C5 A_BDR2 D5 A_BCLKR0 K5 A_BFSX0 L5 VSS M5 CVDD N5 CLKIN A6 DVDD B6 C6 A_BCLKX2 D6 K6 A_BCLKX0 L6 M6 DS AVDD A7 VSS B7 VSSA C7 NC D7 HRDY A_BDX0 MSTRB HCS MicroStar BGA is a trademark of Texas Instruments. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HD12 E4 A_BFSR0 READY HD13 A_TOUT HDS2 L4 N6 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Pin Assignments for the TMS320VC5420GGU (144-Pin MicroStar BGA) (Continued) PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME DVDD BALL NO. PRIMARY SIGNAL NAME SECONDARY SIGNAL NAME BALL NO. K7 B_BDX0 L7 M7 B_BCLKX0 N7 B_BCLKX2 A8 B_BDX2 B8 B_BFSX2 C8 B_BCLKR2 D8 B_BDR0 K8 B_BCLKR0 L8 B_BFSX0 M8 VSS N8 CVDD A9 VSS B9 B_BDR2 C9 B_BFSR2 D9 HR/W K9 B_BFSR0 L9 M9 CVDD PPD2 HD2 A10 PPD3 PPA1 B_HINT C10 PPA5 D10 E10 B_BFSR1 F10 B_BCLKR1 G10 TEST H10 B_CLKOUT J10 PPA12 K10 SELA/B L10 PPA3 PS R/W HDS1 VSS N9 HD3 B10 B_GPIO3 IS B_TOUT HCNTL0 M10 PPA2 HCNTL1 N10 DVDD A11 PPA4 HAS B11 VSS C11 D11 B_GPIO2/BIO E11 B_INT0 B_BDR1 F11 B_BFSX1 G11 VSS H11 B_XF J11 PPA13 K11 PPD10 HD10 L11 M11 PPD8 HD8 N11 PPA6 A12 PPA14 B12 PPA16 C12 B_INT1 D12 B_GPIO1 E12 CVDD F12 B_BDX1 G12 CVDD H12 B_RS J12 HPIRS K12 DVDD L12 VSS M12 N12 PPA7 A13 PPA15 B13 PPA17 C13 B_NMI D13 B_GPIO0 E13 VSS F13 VSS G13 B_BCLKX1 H13 XIO J13 HMODE K13 VSS L13 PPA11 M13 PPA10 N13 PPD9 PPD11 HD9 HD11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 signal descriptions The 5420 signal descriptions table lists each pin name, function, and operating mode(s) for the 5420 device. Some of the 5420 pins can be configured for one of two functions; a primary function and a secondary function. The names of these pins in secondary mode are shaded in grey in the following table. Signal Descriptions NAME TYPE† DESCRIPTION DATA SIGNALS PPA17 (MSB) PPA16 PPA15 PPA14 PPA13 PPA12 PPA11 PPA10 PPA9 PPA8 PPA7 PPA6 PPA5 PPA4‡§ PPA3 PPA2 PPA1 PPA0 (LSB) PPD15 (MSB) PPD14 PPD13 PPD12 PPD11 PPD10 PPD9 PPD8 PPD7 PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 PPD0 (LSB) Parallel port address bus. The DSP can access the external memory locations by way of the external memory interface using PPA[17:0] in external memory interface (EMIF) mode when the XIO pin is logic high. I/O/Z The PPA[17:0] pins are also multiplexed with the HPI interface. In HPI mode (XIO pin is low), the external address pins PPA[17:0] are used by a host processor for access to the memory map by way of the on-chip HPI. Refer to the HPI section of this table for details on the secondary functions of these pins. These pins are placed into the high-impedance state when OFF is low. Parallel port data bus. The DSP uses this bidirectional data bus to access external memory when the device is in external memory interface (EMIF) mode (the XIO pin is logic high). This data bus is also multiplexed with the 16-bit HPI data bus. When in HPI mode, the bus is used to transfer data between the host processor and internal DSP memory via the HPI. Refer to the HPI section of this table for details on the secondary functions of these pins. I/O/Z¶ The data bus includes bus holders to reduce power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external pullup resistors on unused pins. When the data bus is not being driven by the 5420, the bus holders keep data pins at the last driven logic level. The data bus keepers are disabled at reset and can be enabled/disabled via the BH bit of the BSCR register. These pins are placed into high-impedance state when OFF is low. INITIALIZATION, INTERRUPT, AND RESET OPERATIONS A_INT0§ B_INT0§ A_INT1§ B_INT1§ A_NMI§ B_NMI§ I External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and the interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register (IFR). I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins have Schmitt trigger inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A. # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. k Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Signal Descriptions (Continued) NAME TYPE† DESCRIPTION INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED) A_RS§ B_RS§ I Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits. The XIO pin is used to configure the parallel port as a host-port interface (HPI mode when XIO pin is low), or as an asynchronous memory interface (EMIF mode when XIO pin is high). XIO I At device reset, the logic combination of the XIO, HMODE, and SELA/B pin levels determines the initialization value of the MP/MC bit (a bit in the processor mode status (PMST) register ) Refer to the memory section for details. GENERAL-PURPOSE I/O SIGNALS A_XF B_XF A_GPIO0 B_GPIO0 A_GPIO1 B_GPIO1 O External flag output (latched software-programmable output-only signal). Bit addressable. A_XF and B_XF are placed into the high-impedance state when OFF is low. General-purpose I/O pins (software-programmable I/O signal). Values can be latched (output) by writing into the GPIO register. The states of GPIO pins (inputs) can be read by reading the GPIO register. The GPIO direction is also programmable by way of the DIRn field in the GPIO register. I/O General-purpose I/O. These pins can be configured in the same manner as GPIO0–1; however in input mode, the pins also operate as the traditional branch control bit (BIO). If application code does not perform BIO-conditional instructions, these pins operate as general inputs. A_GPIO2/BIO B_GPIO2/BIO PRIMARY A_GPIO3 (A_TOUT) B_GPIO3 (B_TOUT) IOSTRB I/O O IS When the device is in HPI mode and HMODE = 0 (multiplexed), these pins are controlled by the general-purpose I/O control register. TOUT bit must be set to “1” to drive the timer output on the pin. IF TOUT = 0, then these pins are general-purpose I/Os. In EMIF mode (XIO pin high), these signals serve their primary functions and are active during external I/O space accesses. MEMORY CONTROL SIGNALS Program space select signal. The PS signal is asserted during external program space accesses. This pin is placed into the high-impedance state when OFF is low. PS‡ O This pin is also multiplexed with the HPI, and functions as the HDS1 data strobe input signal in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin. Data space select signal. The DS signal is asserted during external data space accesses. This pin is placed into the high-impedance state when OFF is low. DS‡ O This pin is also multiplexed with the HPI, and functions as the HDS2 data strobe input signal in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin. I/O space select signal. The IS signal is asserted during external I/O space accesses. This pin is placed into the high-impedance state when OFF is low. IS O MSTRB‡§ O This pin is also multiplexed with the general purpose I/O feature, and functions as the B_GPIO3 (B_TOUT) input/output signal in HPI mode. Refer to the General Purpose I/O section of this table for details on the secondary function of this pin. Program and data memory strobe (active in EMIF mode). This pin is placed into the high-impedance state when OFF is low. † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins have Schmitt trigger inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A. # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. k Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Signal Descriptions (Continued) NAME TYPE† DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) READY I Data-ready input signal. READY indicates that the external device is prepared for a bus transaction to be completed. If the device is not ready (READY = 0), the processor waits one cycle and checks READY again. The processor performs the READY detection if at least two software wait states are programmed. This pin is also multiplexed with the HPI, and functions as the Host-port data ready (output) in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin. Read/write output signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W O This pin is also multiplexed with the HPI, and functions as the Host-port Read/write input in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin. This pin is placed into the high-impedance state when OFF is low. I/O space memory strobe. External I/O space is accessible by the CPU and not the direct memory access (DMA) controller. The DMA has its own dedicated I/O space that is not accessible by the CPU. IOSTRB O This pin is also multiplexed with the general pupose I/O feature, and functions as the A_GPIO3(A_TOUT) signal in HPI mode. Refer to the general purpose I/O section of this table for details on the secondary function of this pin. This pin is placed into the high-impedance state when OFF is low. The SELA/B pin designates which DSP subsystem has access to the parallel-port interface. Furthermore, this pin determines which subsystem is accessible by the host via the HPI. For external memory accesses (XIO pin high), when SELA/B is low subsystem A has control of the external memory interface. Similarly, when SELA/B is high subsystem B has control. SELA/B I See Table 7 for a truth table of SELA/B, HMODE and XIO pins and functionality. At device reset, the logic combination of the XIO, HMODE, and SELA/B pin levels determines the initialization value of the MP/MC bit (a bit in the processor mode status (PMST) register ) Refer to the memory section for details. CLOCKING SIGNALS A_CLKOUT B_CLKOUT O Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1” to the CLKOFF bit of the PMST register. CLKOUT goes into the high-impedance state when EMU1/OFF is low. CLKIN§ I Input clock to the device. CLKIN connects to an oscillator circuit/device. VCO O VCO is the output of the voltage-controlled oscillator stage of the PLL. This is a 3-state output during normal operation. Active in silicon test/debug mode. † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins have Schmitt trigger inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A. # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. k Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Signal Descriptions (Continued) NAME TYPE† DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS A_BCLKR0‡§ B_BCLKR0‡§ A_BCLKR1‡§ B_BCLKR1‡§ A_BCLKR2‡§ B_BCLKR2‡§ A_BCLKX0‡§ B_BCLKX0‡§ A_BCLKX1‡§ B_BCLKX1‡§ A_BCLKX2‡§ B_BCLKX2‡§ I/O/Z Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input from an external clock source for clocking data into the McBSP. When not being used as a clock, these pins can be used as general-purpose I/O by setting RIOEN = 1. BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register. I/O/Z Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be configured as an input by setting the CLKXM = 0 in the PCR register. BCLKX can be sampled as an input by way of the IN1 bit in the SPC register. When not being used as a clock, these pins can be used as general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF is low. A_BDR0 B_BDR0 A_BDR1 B_BDR1 A_BDR2 B_BDR2 I Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can be used as general-purpose I/O by setting RIOEN = 1. A_BDX0 B_BDX0 A_BDX1 B_BDX1 A_BDX2 B_BDX2 O/Z Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins can be used as general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF is low. A_BFSR0 B_BFSR0 A_BFSR1 B_BFSR1 A_BFSR2 B_BFSR2 I/O/Z Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the receive-data process over BDR pin. When not being used as data-receive synchronization pins, these pins can be used as general-purpose I/O by setting RIOEN = 1. A_BFSX0 Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the transmit-data B_BFSX0 process over BDX pin. If RS is asserted when BFSX is configured as output, then BFSX is turned into input mode A_BFSX1 by the reset operation. When not being used as data-transmit synchronization pins, these pins can be used as I/O/Z B_BFSX1 general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF is A_BFSX2 low. B_BFSX2 † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins have Schmitt trigger inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A. # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. k Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Signal Descriptions (Continued) NAME TYPE† DESCRIPTION HOST-PORT INTERFACE SIGNALS PRIMARY HA[0:17] HD[0:15] I I/O/Z PPA[0:17] PPD[0:15] O I/O/Z HPI address inputs. HA[0:17] are used by the host device, in the HPI non-multiplexed mode (HMODE pin is high), to address the on-chip RAM of the 5420. These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low). Parallel bidirectional data bus. HD[0:15] are used by the host device to transfer data to and from the on-chip RAM of the 5420. These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low). The data bus includes bus holders to reduce power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external pullup resistors on unused pins. When the data bus is not being driven by the 5420, the bus holders keep data pins at the last driven logic level. The data bus keepers are disabled at reset and can be enabled/disabled via the BH bit of the BSCR register. These pins are placed into the high-impedance state when OFF is low. PRIMARY HCNTL0 HCNTL1 HAS‡§ HCS‡§ HDS1‡§ HDS2‡§ HR/W HRDY A_HINT B_HINT I PPA3 PPA2 I PPA4‡§ I MSTRB‡§ I PS‡§ DS‡§ I R/W O READY O PPA0 PPA1 O HPI control inputs. The HCNTL0 and HCNTL1 values between HPIA, and HPID registers during HPI reads and writes. These signals are only used in HPI multiplexed address/data mode (HMODE pin is low). These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low). O Address strobe input. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register. This signal is only used in HPI multiplexed address/data mode (HMODE pin is low). This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). O HPI chip-select signal. This signal must be active during HPI transfers, and can remain active between concurrent transfers. This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). O HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control transfer HPI transfers. These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low). O HPI read/write signal. This signal is used by the host to control the direction of an HPI transfer. This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). I HPI data-ready output. The ready output informs the host when the HPI is ready for the next transfer. This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). HRDY is placed into the high-impedance state when OFF is low. O Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear this interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in HPI multiplexed address/data mode (HMODE pin is low). These pins are placed into the high-impedance state when OFF is low. † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins have Schmitt trigger inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A. # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. k Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 Signal Descriptions (Continued) NAME TYPE† DESCRIPTION HOST-PORT INTERFACE SIGNALS (CONTINUED) HPIRS§ I Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems. Host mode select. When this pin is low it selects the HPI multiplexed address/data mode. The multiplexed address/data mode allows hosts with multiplexed address/data lines access to the HPI registers HPIC, HPIA, and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode. HMODE I When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with separate address/data buses to access the HPI address range by way of the 18-bit address bus and the HPI data (HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode. SUPPLY PINS AVDD CVDD S Dedicated power supply that powers the PLL. AVDD = 1.8 V. AVDD can be connected to CVDD. S Dedicated power supply that powers the core CPUs. CVDD = 1.8 V DVDD S Dedicated power supply that powers the I/O pins. DVDD = 3.3 V VSS S Digital ground. Dedicated ground plane for the device. VSSA S Analog ground. Dedicated ground for the PLL. VSSA can be connected to VSS if digital and analog grounds are not separated. TEST PIN TEST# No connection EMULATION/TEST PINS TCK‡§ I Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI‡ I Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. O Test data pin. The contents of the selected register is shifted out of TDO on the falling edge of TCK. TDO is in high-impedance state except when the scanning of data is in progress. These pins are placed into highimpedance state when OFF is low. TMS‡ I Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST||k I Test reset. When high, TRST gives the scan system control of the operations of the device. If TRST is driven low, the device operates in its functional mode and the emulation signals are ignored. Pin with internal pulldown device. I/O/Z Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O. TDO EMU0 Emulator interrupt 1 pin. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as I/O. When TRST transitions from high to low, then EMU1 operates as OFF. EMU/OFF = 0 puts all output drivers into the high-impedance state. EMU1/OFF I/O/Z Note that OFF is used exclusively for testing and emulation purposes (and not for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply: TRST = 0, EMU0 = 1, EMU1 = 0 † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins have Schmitt trigger inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in subchip A. # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. k Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 functional overview 32K Program SARAM C54x Core A 48K Prog/Data SARAM Dbus Ebus Cbus Pbus Dbus Ebus Cbus Pbus Pbus Ebus Dbus Ebus Cbus Pbus P, C, D, E Buses and Control Signals 16K Prog/Data DARAM DMA Bus GPIO[3:0] Peripheral Bus McBSP0 Pheripheral Bus CPU BUS Modified HPI16 Host Access Bus McBSP1 DMA Bus Peripheral Bus Bridge McBSP2 DMA (6 channels) TIMER APLL JTAG Clocks DSP Subsystem A Core-to-Core FIFO Interface Interprocessor IRQ’s 48K Prog/Data SARAM 16K Prog/Data DARAM DMA Bus GPIO[3:0] Host Access Bus DMA (6 channels) DMA Bus Modified HPI16 McBSP0 Peripheral Bus CPU Bus Peripheral Bus Peripheral Bus Bridge McBSP1 McBSP2 TIMER JTAG DSP Subsystem B Figure 1. Functional Block Diagram C54x is a trademark of Texas Instruments. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Ebus Dbus Pbus Cbus Ebus Dbus Pbus Cbus Ebus 32K Program SARAM DMA Bus C54x Core B Pbus Ebus Dbus Pbus Cbus P, C, D, E Buses and Control Signals 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 memory The total memory address range for each 5420 subsystem is 384K 16-bit words. The memory space is divided into three specific memory segments: 256K-word program, 64K-word data, and 64K-word I/O. The program memory space contains the instructions to be executed as well as tables used in execution. The data memory space stores data used by the instructions. The I/O memory space is used to interface to external memory-mapped peripherals and can also serve as extra data storage space. The CPU I/O space should not be confused with the DMA I/O space, which is completely independent and not accessible by the CPU. on-chip dual-access RAM (DARAM) The 5420 subsystems A and B each have 16K × 16-bit on-chip DARAM (2 blocks of 8K words). Each of these RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory space. DARAM can be mapped into program/data memory space by setting the OVLY bit in the PMST register. on-chip single-access RAM (SARAM) The 5420 subsystems A and B each have 80K-word × 16-bit on-chip SARAM (ten blocks of 8K words each). Each of these SARAM blocks is a single-access memory. This memory is intended primarily to store data values; however, it can be used to store program as well. At reset, the SARAM (4000h−7FFFh) is mapped into data memory space. This memory range can be mapped into program/data memory space by setting the OVLY bit in the PMST register. The SARAM at 8000h−FFFFh is program memory at reset and can be configured as program/data memory by setting the DROM bit. SARAM space18000h−1FFFFh is mapped as program memory only. program memory The 5420 device features a paged extended memory scheme in program space to allow access of up to 256K of program memory relative to each subsystem. This extended program memory (each subsystem) is organized into four pages (0−3), each 64K in length. A hardware pin is used to select which DSP subsystem (A or B) has control of the external memory interface. To implement the extended program memory scheme, the 5420 device includes the following features: D Two additional address lines (for a total of 18) D A pin (SELA/B) for external memory interface arbitration between subsystem A and B data memory The data memory space on each 5420 subsystem contains up to 64K 16-bit word addresses. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. parallel I/O ports Each subsystem of the 5420 has a total of 64K I/O ports. These ports can be addressed by PORTR and PORTW. The IS signal indicates the read/write access through an I/O port. The devices can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding logic. The SELA/B pin selects which subsystem has access to the external I/O space. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external memory interface The 5420 has a single external memory interface shared between both subsystems. The external memory interface enables the 5420 subsystems to connect to external memory devices or other parallel interfaces. The SELA/B pin is used to determine which subsystem has access to the external memory interface. When the SELA/B pin is low, subsystem A has access to the external memory interface, and when it is high, subsystem B has access to the interface. The external memory interface is also shared with the host port interface (HPI). The XIO pin is used to select between the external memory interface and the hostport interface. When the XIO pin is high, the external memory interface is active, and when it is low, the host port interface is active. processor mode status register (PMST) Each subsystem has a processor-mode status register (PMST) that controls memory configuration. The bit layout of the PMST register is shown in Figure 1 15 7 6 5 4 3 2 1 0 IPTR MP/MC OVLY AVIS DROM CLKOFF SMUL SST R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R = Read, W = Write Figure 1. Processor Mode Status Register (PMST) Bit Layout The functions of the PMST register bits are illustrated in the memory map. The MP/MC bit is used to map the upper address range of all program space pages (x8000−xFFFF) as either external or internal memory. The OVLY bit is used to overlay the on-chip DARAM0 and SARAM1 blocks from dataspace onto to program space. Similarly, the DROM bit is used to overlay the SARAM2 block from program space onto data space. See the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for a description of the other bits of the PMST register. Due to the dual-processor configuration and the several EMIF/HPI options available, the MP/MC bit is initialized at the time of device reset to a logic level that is dependent on the XIO, HMODE, and SELA/B pins. Table 1 shows the initialized logic level of the MP/MC bit and how it depends on these pins. Table 1. MP/MC Bit Logic Levels at Reset 5420 PINS 18 MP/MC BIT XIO HMODE SELA/B SUBSYSTEM A SUBSYSTEM B 0 X X 0 0 1 0 X 1 1 1 1 0 1 0 1 1 1 0 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 memory map Hex 0000 005F 0060 007F 0080 Data Hex MemoryMapped Registers 0000 Scratch-Pad DARAM Program Page 0 7FFF 8000 FFFF Hex Program Page 2 20000 Hex Program Page 3 30000 On-Chip DARAM 0 (16K Words) Prog/Data (OVLY=1) On-Chip DARAM 0 (16K Words) Prog/Data (OVLY=1) External (OVLY=0)† External (OVLY=0)† External (OVLY=0)† External (OVLY=0)† 13FFF 14000 23FFF 24000 On-Chip SARAM 1 (16K Words) Prog/Data (OVLY=1) On-Chip SARAM 1 (16K Words) Prog/Data (OVLY=1) On-Chip SARAM 1 (16K Words) Prog/Data (OVLY=1) External (OVLY=0)† External (OVLY=0)† External (OVLY=0)† External (OVLY=0)† 17FFF 18000 27FFF 28000 On-Chip SARAM 2 (32K Words) Prog/Data (DROM=1) On-Chip SARAM 2 (32K Words) Prog/Data (MP/MC=0) On-Chip SARAM 3 (32KWords) (MP/MC=0) External (DROM=0)† External (MP/MC=1)† External (MP/MC=1)† FFFF 1FFFF (extended) 64K External I/O Ports† 37FFF 38000 Reserved (MP/MC=0) Reserved (MP/MC=0) External (MP/MC=1)† External (MP/MC=1)† 2FFFF (extended) I/O 33FFF 34000 On-Chip SARAM 1 (16K Words) Prog/Data (OVLY=1) 7FFF 8000 Hex 0000 On-Chip DARAM 0 (16K Words) Prog/Data (OVLY=1) 3FFF 4000 On-Chip SARAM 1 (16K Words) Program Page 1 On-Chip DARAM 0 (16K Words) Prog/Data (OVLY=1) On-Chip DARAM 0 (16K Words) 3FFF 4000 Hex 10000 3FFFF (extended) FFFF (extended) † The external memory interface must be enabled by driving the XIO pin high, in order for external memory accesses to occur. Figure 2. Memory Map for Each CPU Subsystem multicore reset signals The 5420 device includes three reset signals: A_RS, B_RS, and HPIRS. The A_RS and B_RS pins function as the CPU reset signal for subsystem A and subsystem B, respectively. These signals reset the state of the CPU registers and upon release, initiates the reset function. Additionally, the A_RS signal resets the on-chip PLL and initializes the CLKMD register to bypass mode. The HPI reset signal (HPIRS) places the HPI peripheral into a reset state. It is necessary to wait three clock cycles after the rising edge of HPIRS before performing an HPI access. reset vector initialization The 5420 device does not have on-chip ROM and therefore does not contain bootloader routines/software. Consequently, the user must have a valid reset vector in place before releasing the reset signal. This is referred to as reset vector initialization. After reset, the 5420 device fetches the reset vector at address 0xFF80 in program memory and begins to execute the instructions found in memory. The application code is raw program and data words and does not require the traditional boot-table or boot-packet format. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 19 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 reset vector initialization (continued) The selection of the reset initialization option is determined by the state of three pins; XIO, XMODE, and SELA/B. The options include: D D D D HPI (host-dependent) EMIF-to-HPI (stand-alone) Simultaneous EMIF (stand-alone) Sequential EMIF (stand-alone) HPI The HPI method is only valid when the level of the XIO pin is low. The 5420 acts as a slave to an external master host. The host device must keep the 5420 device in reset as it downloads code to the subsystem that is determined by the logic level of the SELA/B pin. When SELA/B is low, the master downloads code to subsystem A. By driving SELA/B high, the master host can subsequently download code to subsystem B. The HMODE pin determines the configuration of the HPI (multiplexed or nonmultiplexed) and is an asynchronous input. Therefore, HMODE can be changed to the desired configuration while A_RS and B_RS are low prior to the transfer. Once the subsystem(s) have been loaded and are ready to execute, the master host can release the reset pin(s). There are two valid options for controlling the reset function of the subsystems. The first option is to hold the A_RS and B_RS pins low while the HPIRS pin transitions from low to high. This keeps the cores in reset while allowing the HPI full access to download the application code. The host can now drive the A_RS and B_RS signals high simultaneously or separately to release the respective subsystem from reset. The subsystems then fetch their respective reset vector. If the subsystems are released from reset seperately, subsystem A should be released from reset first, since the A_RS pin resets the on-chip PLL that is common to both subsystems. Another valid option is to keep the A_RS and B_RS pins high while the host transitions the HPIRS pin from low to high. Special internal logic causes the HPI to be fully operable and the cores remain in reset. As a result, after the host processor has downloaded the application code via the HPI, it must perform an additional HPI write (any value) to address 0x2F. This releases the respective subsystem from reset. By changing the value of SELA/B, the host can write to 0x2F via the HPI to release the other subsystem from reset. EMIF-to-HPI In this particular vector initialization method, the host processor controlling the HPI is one of the subsystems. The master host is subsystem A if SELA/B is low and subsystem B when SELA/B is high. As described in the signal descriptions table, the address, data, and control signals of the program space are multiplexed with the HPI signals. In a special mode when XIO is high (EMIF mode) and HMODE is high (HPI nonmultiplexed mode), these multiplexed signals are connected, making it possible for the master subsystem’s EMIF to initialize the slave subsystem via the slave’s HPI. The master subsystem then releases the slave from reset either by transitioning the hardware reset signal (x_RS) high, or in software, by writing to memory location 0x2F via the HPI. As a result, the slave core fetches the reset vector. simultaneous EMIF The simultaneous EMIF vector initialization option allows both subsystems to access external memory simultaneously. The subsystems are designed to operate synchronized with one another while accessing the same locations simultaneously. In this mode, when XIO is high and HMODE is low, one subsystem is given full control of the EMIF while the other subsystem relies on the synchronization of the two subsystems. Instructions fetched by one subsystem are ready for both subsystems to execute. After the application code is executed or transferred to internal memory, write accesses to external memory are prohibited. This method requires the A_RS and B_RS pins to be tied high while HPIRS transitions from low to high. When HPIRS transitions high, both subsystems fetches the same reset vector. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 sequential EMIF The sequential EMIF option allows one master subsystem to run from external memory while controlling the slave subsystem’s RS signal and the SELA/B pin. At system reset, only the master subsystem is actually reset. Upon a low-to-high transition of the master’s RS signal, the master subsystem fetches the reset vector and proceeds to copy external application code to internal memory space. The master subsystem begins executing the application code, then changes the state of SELA/B, relinquishing the external EMIF to the slave subsystem. The master then releases the slave RS signal. As a result, the slave fetches the reset vector and begins to copy the external application code to internal memory space. Note, GPIO pins on the master subsystem can be used to control the SELA/B and slave reset (x_RS) pins externally. on-chip peripherals All the 54x devices have the same CPU structure; however, they have different on-chip peripherals connected to their CPUs. The on-chip peripheral options provided on each subsystem of the 5420 are: D D D D D D Software-programmable wait-state generator Programmable bank-switching 16-bit host-port interface (HPI16) Multichannel buffered serial ports (McBSPs) A hardware timer A software-programmable clock generator with a phase-locked loop (PLL) software-programmable wait-state generators The Software-programmable wait-state generator can be used to extend external bus cycles up to fourteen machine cycles to interface with slower off-chip memory and I/O devices. Note that all external memory accesses on the 5420 require at least one wait state. The software wait-state register (SWWSR) controls the operation of the wait-state generator. The SWWSR of a particular DSP subsystem (A or B) is used for the external memory interface, depending on the logic level of the SELA/B pin.The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and described in Table 2. 15 XPA R/W-0 14 12 11 I/O R/W-111 9 8 Data R/W-111 6 Data R/W-111 5 3 Program R/W-111 2 0 Program R/W-111 LEGEND: R=Read, W=Write, 0=Value after reset Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 21 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 software-programmable wait-state generator (continued) Table 2. Software Wait-State Register (SWWSR) Bit Fields BIT NO. NAME RESET VALUE 15 XPA 0 Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states. 14−12 I/O 1 I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 11−9 Data 1 Upper data space. The field value (0−7) corresponds to the base number of wait states for external data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 8−6 Data 1 Lower data space. The field value (0−7) corresponds to the base number of wait states for external data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. FUNCTION Upper program space. The field value (0−7) corresponds to the base number of wait states for external program space accesses within the following addresses: 5−3 Program 1 - XPA = 0: x8000 − xFFFFh - XPA = 1: The upper program space bit field has no effect on wait states. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Program space. The field value (0−7) corresponds to the base number of wait states for external program space accesses within the following addresses: 2−0 Program 1 - XPA = 0: x0000−x7FFFh - XPA = 1: 00000−3FFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in Table 3. 15 1 0 SWSM Reserved R/W-0 R/W-0 LEGEND: R = Read, W = Write Figure 4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh] Table 3. Software Wait-State Control Register (SWCR) Bit Fields PIN NO. NAME RESET VALUE 15−1 Reserved 0 FUNCTION These bits are reserved and are unaffected by writes. Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2. 0 22 SWSM 0 - SWSM = 0: wait-state base values are unchanged (multiplied by 1). - SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 programmable bank-switching Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from program-memory space to data-memory space (54x) or one program memory page to another program memory page. This extra cycle allows memory devices to release the bus before other devices start driving the bus; thereby avoiding bus contention. The size of the memory bank for the bank-switching is defined by the bank-switching control register (BSCR). The BSCR of a particular DSP subsystem (A or B) is used for the external memory interface depending on the logic level of the SELA/B pin. 15 12 11 10 9 8 BNKCMP PS-DS Reserved IPIRQ R/W R/W R/W R/W 7 3 Reserved 2 1 0 BH Reserved EXIO R/W R/W LEGEND: R = Read, W = Write Figure 5. BSCR Register Bit Layout for Each DSP Subsystem Table 4. BSCR Register Bit Functions for Each DSP Subsystem BIT NO. BIT NAME RESET VALUE FUNCTION 15−12 BNKCMP 1111 Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed. 11 PS-DS 1 Program read − data read access. PS-DS inserts an extra cycle between consecutive accesses of program read and data read or data read and program read. PS-DS = 0 No extra cycles are inserted by this feature. PS-DS = 1 One extra cycle is inserted between consecutive data and program reads. 10−9 Reserved 0 These bits are reserved and are unaffected by writes. 8 IPIRQ 0 The IPIRQ bit is used to send an interprocessor interrupt to the other subsystem. IPIRQ=1 sends the interrupt. IPIRQ must be cleared before subsequent interrupts can be made. Refer to the interrupts section for more details 7−3 Reserved 0 These bits are reserved and are unaffected by writes. 2 BH 0 Bus holder. BH controls the data bus holder feature: BH is cleared to 0 at reset. BH = 0 The bus holder is disabled. BH = 1 The bus holder is enabled. When not driven, the data bus (PPD[15:0]) is held in the previous logic level. 1 Reserved 0 These bits are reserved and are unaffected by writes. 0 External bus interface off. The EXIO bit controls the external bus-off function. EXIO = 0 The external bus interface functions as usual. EXIO = 1 The address bus, data bus, and control signals become inactive after completing the current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1 cannot be modified when the interface is disabled. 0 EXIO POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 23 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 16-bit host-port interface (HPI16) The HPI16 is an enhanced 16-bit version of the C54x 8-bit host-port interface (HPI). The HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Figure 6 illustrates the available memory accessible by the HPI. It should be noted that neither the CPU nor DMA I/O spaces can be accessed using the host-port interface. 16-bit bidirectional host-port interface (HPI16) Hex Program Page 0 0000 Hex Program Page 1 10000 Hex Program Page 2 20000 Hex Program Page 3 30000 Reserved 001F 0020 005F 0060 McBSP DXR/DRR MMRegs Only Reserved 1005F 10060 13FFF 14000 7FFF 8000 33FFF 34000 27FFF 28000 1FFFF On-Chip DARAM 0 (Overlayed) Prog/Data On-Chip SARAM 1 (Overlayed) Prog/Data On-Chip SARAM 3 (32K Words) Program On-Chip SARAM 2 (32K Words) Prog/Data 3005F 30060 23FFF 24000 17FFF 18000 Reserved On-Chip DARAM 0 (Overlayed) Prog/Data On-Chip SARAM 1 (Overlayed) Prog/Data On-Chip SARAM 1 (Overlayed) Prog/Data FFFF 2005F 20060 On-Chip DARAM 0 (Overlayed) Prog/Data On-Chip DARAM 0 (Overlayed) Prog/Data 3FFF 4000 Reserved On-Chip SARAM 1 (Overlayed) Prog/Data 37FFF 38000 Reserved 2FFFF Reserved 3FFFF Figure 6. Memory Map Relative to Host-Port interface 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 16-bit bidirectional host-port interface (HPI16) (continued) Some of the features of the HPI16 include: D D D D D D D D 16-bit bidirectional data bus Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts Multiplexed and nonmultiplexed address/data modes 18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal extended address pages) 18-bit address register used in multiplexed mode. Includes address autoincrement feature for faster accesses to sequential addresses Interface to on-chip DMA module to allow access to entire internal memory space HRDY signal to hold off host accesses due to DMA latency Control register available in multiplexed mode only. Accessible by either host or DSP to provide host/DSP interrupts, extended addressing, and data prefetch capability The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP. There are two modes of operation as determined by the HMODE signal: multiplexed mode and nonmultiplexed mode. HPI multiplexed mode In multiplexed mode, HPI16 operation is very similar to the standard 8-bit HPI, which is available with other C54x products. A host with a multiplexed address/data bus can access the HPI16 data register (HPID), address register (HPIA), or control register (HPIC) via the HD bidirectional data bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the type of access with the HCNTL, HR/W, and HAS signals. The DSP can interrupt the host via the HINT signal, and can stall host accesses via the HRDY signal. host/DSP interrupts In multiplexed mode, the HPI16 offers the capability for the host and DSP to interrupt each other through the HPIC register. For host-to-DSP interrupts, the host must write a “1” to the DSPINT bit of the HPIC register. This generates an interrupt to the DSP. This interrupt can also be used to wake the DSP from any of the IDLE 1,2, or 3 states. Note that the DSPINT bit is always read as “0” by both the host and DSP. For DSP-to-host interrupts, the DSP must write a “1” to the HINT bit of the HPIC register to interrupt the host via the HINT pin. The host acknowledges and clear this interrupt by also writing a “1” to the HINT bit of the HPIC register. Note that writing a “0” to the HINT bit by either host or DSP has no effect. HPI nonmultiplexed mode In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. other HPI16 system considerations operation during IDLE2 The HPI16 can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power. The DSP CPU does not wake up from the IDLE mode during this process. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 25 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 downloading code during reset The HPI16 can download code while the DSP is in reset. However, the system provides a pin (HPIRS) that provides a way to take the HPI16 module out of reset while leaving the DSP in reset. emulation considerations The HPI16 can continue operation even when the DSP CPU is halted due to debugger breakpoints or other emulation events. 5420 boundary scan implementation The 5420 does not implement a fully compliant IEEE1149.1 boundary scan capability. Observe-only boundary scan cells are used on all of the device pins that allow the pins to be observed (read) but not controlled (driven) using boundary scan. Driving nodes to perform board interconnect test must be accomplished using other boundary scan capable devices on the board. Although this implies some reduction in testability, compared to full boundary scan, this implementation is still compatible with the boundary scan automatic test pattern generation (ATPG) tools. multichannel buffered serial port (McBSP) The 5420 device provides high-speed, full-duplex serial ports that allow direct interface to other C54x devices, codecs, and other devices in a system. There are six multichannel buffered serial ports (McBSPs) on chip (three per subsystem). The McBSP is based on the standard serial port interface found on the 54x devices. Like its predecessors, the McBSP provides: D Full-duplex communication D Double-buffer data registers, which allow a continuous data stream D Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: D Direct interface to: D D D D D − T1/E1 framers − MVIP switching-compatible and ST-BUS compliant devices − IOM-2 compliant device − Serial peripheral interface devices Multichannel transmit and receive of up to 128 channels A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits µ-law and A-law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and BCLKR, connect the control and data paths to external devices. The pins can be programmed as general-purpose I/O pins if they are not used for serial communication. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port (McBSP) (continued) Like the standard serial port interface on the McBSP, the data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for transmit and the data receive (BDR) pin for receive. Control information in the form of clocking and frame synchronization is communicated by way of BCLKX, BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers accessible via the internal peripheral bus. The CPU or DMA reads the received data from the data receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then copied to DRR, which can be read by the CPU or DMA. This allows internal data movement and external data communications simultaneously. The control block consists of internal clock generation, frame synchronization signal generation, and their control, and multichannel selection. This control block sends notification of important events to the CPU and DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT. The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format. When companding is used, transmitted data is encoded according to specified companding law and received data is decoded to 2’s complement format. The sample rate generator provides the McBSP with several means of selecting clocking and framing for both the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently. The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to 32 channels in a bit stream consisting of a maximum of 128 channels can be enabled. The clock stop mode (CLKSTP) in the McBSP provides compatibility with the SPI protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave. direct memory access unit (DMA) The 5420 direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA allows movements of data to and from internal program/data memory, internal peripherals, such as the McBSPs and the HPI to occur in the background of the CPU operation. Each subsystem has its own independent DMA with six programmable channels, allowing six different contexts for DMA operation. The HPI has a dedicated auxiliary DMA channel. Figure 7 illustrates the memory map accessible by the DMA. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 27 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 direct memory access unit (DMA) (continued) Hex Data 0000 Reserved Program Page 0 Reserved Hex McBSP DXR/DRR MMRegs Only Scratch-Pad DARAM 007F 0080 005F 0060 McBSP DXR/DRR MMRegs Only 17FFF 18000 On-Chip SARAM 2 (32K Words) Prog/Data FFFF FFFF I/O XXXX DMA FIFO for Core-Core Communication{ 33FFF 34000 27FFF 28000 1FFFF Hex On-Chip DARAM 0 (Overlayed) Prog/Data On-Chip SARAM 1 (Overlayed) Prog/Data On-Chip SARAM 3 (32K Words) Prog/Data On-Chip SARAM 2 (32K Words) Prog/Data Reserved On-Chip DARAM 0 (Overlayed) Prog/Data On-Chip SARAM 1 (Overlayed) Prog/Data Program Page 3 3005F 30060 23FFF 24000 13FFF 14000 7FFF 8000 7FFF 8000 Hex 30000 2005F 20060 On-Chip DARAM 0 (Overlayed) Prog/Data On-Chip SARAM 1 (Overlayed) Prog/Data On-Chip SARAM 1 (16K Words) Program Page 2 Reserved 1005F 10060 (Overlayed) Prog/Data 3FFF 4000 3FFF 4000 Hex 20000 Reserved On-Chip DARAM 0 On-Chip DARAM 0 (16K Words) Program Page 1 10000 001F 0020 001F 0020 005F 0060 Hex 0000 On-Chip SARAM 1 (Overlayed) Prog/Data 37FFF 38000 Reserved Reserved 2FFFF 3FFFF † When the source or destination for a DMA channel is programmed for I/O space, the channel accesses the core-to-core FIFO irrespective of the address specified. Figure 7. Memory Map Relative to DMA features The 5420 DMA has the following features: D D D D D D D D D 28 The DMA operates independently of the CPU. The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. The DMA has higher priority than the CPU for internal accesses. Each channel has independently programmable priorities. Each channel’s source and destination address registers can have configurable indexes through memory on each read and write transfer, respectively. The address can remain constant, postincrement, postdecrement or be adjusted by a programmable value. Each read or write transfer can be initialized by selected events. On completion of a half-block or full-block transfer, each DMA channel can send an interrupt to the CPU. An on-chip RAM DMA transfer requires 4 clock cycles to complete. External transfers are not supported. The DMA can perform double word transfers (a 32-bit transfer of two16-bit-words). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 DMA controller synchronization events The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in Table 5. Table 5. DMA Synchronization Events DSYN VALUE DMA SYNCHRONIZATION EVENT 0000b No synchronization used 0001b McBSP0 Receive Event 0010b McBSP0 Transmit Event 0011b McBSP2 Receive Event 0100b McBSP2 Transmit Event 0101b McBSP1 Receive Event 0110b McBSP1 Transmit Event 0111b FIFO Receive Buffer Not Empty Event 1000b FIFO Transmit Buffer Not Full Event 1001b − 1111b Reserved DMA channel interrupt selection The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 0 and 1 share an interrupt line with the receive and transmit portions of McBSP2 (IMR/IFR bits 6 and 7), and DMA channels 2 and 3 share an interrupt line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11). When the 5402 is reset, the interrupts from these four DMA channels are deselected. The INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these interrupts, as shown in Table 6. Table 6. DMA Channel Interrupt Selection INTSEL Value IMR/IFR[6] IMR/IFR[7] IMR/IFR[10] IMR/IFR[11] 00b (reset) BRINT2 BXINT2 BRINT1 BXINT1 01b BRINT2 BXINT2 DMAC2 DMAC3 10b DMAC0 DMAC1 DMAC2 DMAC3 11b Reserved subsystem communications The 5420 device provides two options for efficient core-to-core communications: D Core-to-core FIFO communications D EMIF-to-HPI communications (asynchronous external memory interface-to host-port interface) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 29 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 FIFO data communications The subsystems’ FIFO communications interface is shown in the 5420 functional block diagram (Figure 1). Two unidirectional 8-word-deep FIFOs are available in the device for efficient interprocessor communication: one configured for core A-to-core B data transfers, and the other configured for core B-to-core A data transfers. Each subsystem, by way of DMA control, can write to its respective output data FIFO and read from its respective input data FIFO. The FIFOs are accessed using the DMA’s I/O space, which is completely independent of the CPU I/O space. The DMA transfers to or from the FIFOs can be synchronized to “receive FIFO not empty” and “transmit FIFO not full” events providing protection from overflow and underflow. Subsystems can interrupt each other to flag when the FIFOs are either full or empty. The interprocessor interrupt request bit (IPIRQ) (bit 8 in the BSCR register ) is set to “1” to generate an interprocessor interrupt (IPINT) in the other subsystem. See the interrupts section for more information. EMIF-to-HPI data communication The 5420 also provides the capability for one subsystem to act as a master and transfer data to the other subsystem via an EMIF-to-HPI connection. The master device is configured in EMIF mode (XIO pin is high); while by default, when HMODE=1, the slave device external interface is configured to operate as an HPI (nonmultiplexed mode). The data-transfer direction is defined by the logic level of SELA/B. See Table 7 for a complete description of HMODE, SELA/B, and XIO pin functionality. The EMIF-to-HPI option is bidirectional, but does not permit full duplex communication without external SELA/B arbitration. This mode does not offer master/slave interrupts due to the nonmultiplexed HPI configuration. Table 7. EMIF/HPI Modes HMODE SELA/B HPI MODES (XIO PIN =0) EMIF MODES (XIO PIN = 1) 0 0 HPI multiplexed address/data Subsystem A slave to host Subsystem A can access EMIF Subsystem B has no access to EMIF or HPI 0 1 HPI multiplexed address/data Subsystem B slave to host Subsystem B can access EMIF Subsystem A has no access to EMIF or HPI 1 0 HPI nonmultiplexed address/data Subsystem A slave to host EMIF-to-HPI master is subsystem A, slave is subsystem B 1 1 HPI nonmultiplexed address/data Subsystem B slave to host EMIF-to-HPI master is subsystem B, slave is subsystem A general-purpose I/O In addition to the standard XF and BIO pins, the 5420 has eight general-purpose I/O pins. These pins are: A_GPIO0, A_GPIO1, A_GPIO2, A_GPIO3 B_GPIO0, B_GPIO1, B_GPIO2, B_GPIO3 Each subsystem’s CPU has one general-purpose I/O register located at address 0x3c in data memory. Each I/O register controls four general-purpose I/O pins. Figure 8 shows the bit layout of the general-purpose I/O control register and Table 8 describes the bit functions. 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 general-purpose I/O (continued) 15 14 TOUT 12 Reserved R/W 11 10 9 8 7 DIR3 DIR2 DIR1 DIR0 R/W R/W R/W R/W 4 Reserved 3 2 1 0 DAT3 DAT2 DAT1 DAT0 R/W R/W R/W R/W LEGEND: R = Read, W = Write Figure 8. General-Purpose I/O Control Register Bit Layout Table 8. General-Purpose I/O Control Register Bit Functions BIT NO. BIT NAME 15 TOUT 14-12 Reserved 11−8 DIRn† 7−4 Reserved 3−0 DATn† BIT VALUE FUNCTION 0 Timer output disable. Uses GPIO3 as general-purpose I/O. (Reset value) 1 Timer output enable. Overrides DIR3. Timer output is driven on GPIO3 and readable in DAT3. X Register bit is reserved. 0 GPIOn pin is used as an input. (Reset value) 1 GPIOn pin is used as an output. X Register bit is reserved. 0 GPIOn is driven with a 0 (DIRn=1). GPIOn is read as 0 (DIRn=0). 1 GPIOn is driven with a 1 (DIRn=1). GPIOn is read as 1 (DIRn=0). † n = 0, 1, 2, or 3 The TOUT bit is used to multiplex the output of the timer and GPIO3. DIR3 has no affect when TOUT = 1. All pins are programmable as an input or output via the direction bit (DIRn). Data is either driven or read from the data bit field (DATn). GPIO2 is a special case where the logic level determines the operation of BIO-conditional instructions on the CPU. GPIO2 is always mapped as a general-purpose I/O, but the BIO function exists when this pin is configured as an input. hardware timer Each subsystem of the 5420 features a 16-bit timing circuit with a 4-bit prescaler. The timer counter decrements by one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits. The timer output pulse is driven on GPIO3 when the TOUT bit is set to one in the general-purpose I/O control register. The device must be in HPI mode (XIO = 0) to drive TOUT on the GPIO3 pin. software-programmable phase-locked loop (PLL) The clock generator provides clocks to the 5420 device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which must be provided by using an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5420 device. Alternately, the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The default startup mode for the PLL on the 5420 device is bypass (multiply-by-1). The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Only subsystem A controls the PLL. Subsystem B cannot access the PLL registers. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 software-programmable phase-locked loop (PLL) (continued) The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: D PLL mode. The input clock (CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using the PLL circuitry. D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled by the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD) in subsystem A. The CLKMD register is used to define the clock configuration of the PLL clock module. 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 memory-mapped registers Each 5420 subsystem has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to 1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on 5420. Each subsystem device also has a set of memory-mapped registers associated with peripherals. Table 10, and Table 11 show additional peripheral MMRs associated with the 5420. Table 9. Processor Memory-Mapped Registers for Each DSP Subsystem NAME ADDRESS DEC HEX DESCRIPTION IMR 0 0 Interrupt Mask Register IFR 1 1 Interrupt Flag Register — 2−5 2−5 ST0 6 6 Reserved for testing Status Register 0 ST1 7 7 Status Register 1 AL 8 8 Accumulator A Low Word (15−0) AH 9 9 Accumulator A High Word (31−16) AG 10 A Accumulator A Guard Bits (39−32) BL 11 B Accumulator B Low Word (15−0) BH 12 C Accumulator B High Word (31−16) BG 13 D Accumulator B Guard Bits (39−32) TREG 14 E Temporary Register TRN 15 F Transition Register AR0 16 10 Auxiliary Register 0 AR1 17 11 Auxiliary Register 1 AR2 18 12 Auxiliary Register 2 AR3 19 13 Auxiliary Register 3 AR4 20 14 Auxiliary Register 4 AR5 21 15 Auxiliary Register 5 AR6 22 16 Auxiliary Register 6 AR7 23 17 Auxiliary Register 7 SP 24 18 Stack Pointer BK 25 19 Circular Buffer Size Register BRC 26 1A Block-Repeat Counter RSA 27 1B Block-Repeat Start Address REA 28 1C Block-Repeat End Address PMST 29 1D Processor Mode Status Register XPC 30 1E Extended Program Counter — 31 1F Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 33 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 memory-mapped registers (continued) Table 10. Peripheral Memory-Mapped Registers for Each DSP Subsystem NAME ADDRESS DEC HEX DESCRIPTION DRR20 32 20 McBSP 0 Data Receive Register 2 DRR10 33 21 McBSP 0 Data Receive Register 1 DXR20 34 22 McBSP 0 Data Transmit Register 2 DXR10 35 23 McBSP 0 Data Transmit Register 1 TIM 36 24 Timer Register PRD 37 25 Timer Period Register TCR 38 26 Timer Control Register — 39 27 Reserved SWWSR 40 28 Software Wait-State Register BSCR 41 29 Bank-Switching Control Register — 42 2A Reserved SWCR 43 2B Software Wait-State Control Register HPI Control Register (HMODE=0 only) HPIC 44 2C 45−47 2D−2F DRR22 48 30 McBSP 2 Data Receive Register 2 DRR12 49 31 McBSP 2 Data Receive Register 1 DXR22 50 32 McBSP 2 Data Transmit Register 2 DXR12 51 33 McBSP 2 Data Transmit Register 1 SPSA2 52 34 SPSD2 53 35 McBSP 2 Subbank Address Register† McBSP 2 Subbank Data Register† 54−55 36−37 56 38 — — SPSA0 SPSD0 — GPIO — Reserved Reserved McBSP 0 Subbank Address Register† McBSP 0 Subbank Data Register† 57 39 58−59 3A−3B 60 3C Reserved General-Purpose I/O Register 61−63 3D−3F DRR21 64 40 McBSP 1 Data Receive Register 2 DRR11 65 41 McBSP 1 Data Receive Register 1 DXR21 66 42 McBSP 1 Data Transmit Register 2 DXR11 67 43 McBSP 1 Data Transmit Register 1 68−71 44−47 72 48 — SPSA1 SPSD1 Reserved Reserved McBSP 1 Subbank Address Register† McBSP 1 Subbank Data Register† 73 49 74−83 4A−53 DMPREC 84 54 DMSA 85 55 DMSDI 86 56 DMSDN 87 57 DMA Subbank Data Register with Autoincrement‡ DMA Subbank Data Register‡ CLKMD 88 58 Clock Mode Register (CLKMD) — Reserved DMA Priority and Enable Control Register DMA Subbank Address Register‡ — 89−95 59−5F Reserved † See Table 11 for a detailed description of the McBSP control registers and their subaddresses. ‡ See Table 12 for a detailed description of the DMA sub-bank addressed registers. 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 McBSP control registers and subaddresses The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within the subbank. The McBSP data register (SPSDI) and the DMA autoincrement subaddress register (SPSDN) register are used to access (read or write) the selected register. Table 11 shows the McBSP control registers and their corresponding subaddresses. Table 11. McBSP Control Registers and Subaddresses McBSP0 McBSP1 McBSP2 NAME ADDRESS NAME ADDRESS NAME ADDRESS SUBADDRESS SPCR10 39h SPCR11 49h SPCR12 35h 00h Serial port control register 1 SPCR20 39h SPCR21 49h SPCR22 35h 01h Serial port control register 2 RCR10 39h RCR11 49h RCR12 35h 02h Receive control register 1 RCR20 39h RCR21 49h RCR22 35h 03h Receive control register 2 XCR10 39h XCR11 49h XCR12 35h 04h Transmit control register 1 XCR20 39h XCR21 49h XCR22 35h 05h Transmit control register 2 SRGR10 39h SRGR11 49h SRGR12 35h 06h Sample rate generator register 1 SRGR20 39h SRGR21 49h SRGR22 35h 07h Sample rate generator register 2 MCR10 39h MCR11 49h MCR12 35h 08h Multichannel register 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DESCRIPTION MCR20 39h MCR21 49h MCR22 35h 09h Multichannel register 2 RCERA0 39h RCERA1 49h RCERA2 35h 0Ah Receive channel enable register partition A RCERB0 39h RCERB1 49h RCERA2 35h 0Bh Receive channel enable register partition B XCERA0 39h XCERA1 49h XCERA2 35h 0Ch Transmit channel enable register partition A XCERB0 39h XCERB1 49h XCERA2 35h 0Dh Transmit channel enable register partition B PCR0 39h PCR1 49h PCR2 35h 0Eh Pin control register DMA subbank addressed registers The direct memory access (DMA) controller has several control registers associated with it. The main control register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register. When the DMSDI register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. This autoincrement feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller subbank addressed registers and their corresponding subaddresses. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 DMA subbank addressed registers (continued) Table 12. DMA Subbank Addressed Registers ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADDRESS SUBADDRESS DMSRC0 56h/57h 00h DMA channel 0 source address register DMDST0 56h/57h 01h DMA channel 0 destination address register DMCTR0 56h/57h 02h DMA channel 0 element count register DMSFC0 56h/57h 03h DMA channel 0 sync select and frame count register DMMCR0 56h/57h 04h DMA channel 0 transfer mode control register DMSRC1 56h/57h 05h DMA channel 1 source address register DMDST1 56h/57h 06h DMA channel 1 destination address register DMCTR1 56h/57h 07h DMA channel 1 element count register DMSFC1 56h/57h 08h DMA channel 1 sync select and frame count register DMMCR1 56h/57h 09h DMA channel 1 transfer mode control register DMSRC2 56h/57h 0Ah DMA channel 2 source address register DMDST2 56h/57h 0Bh DMA channel 2 destination address register DMCTR2 56h/57h 0Ch DMA channel 2 element count register DMSFC2 56h/57h 0Dh DMA channel 2 sync select and frame count register DMMCR2 56h/57h 0Eh DMA channel 2 transfer mode control register DMSRC3 56h/57h 0Fh DMA channel 3 source address register DMDST3 56h/57h 10h DMA channel 3 destination address register DMCTR3 56h/57h 11h DMA channel 3 element count register DMSFC3 56h/57h 12h DMA channel 3 sync select and frame count register DMMCR3 56h/57h 13h DMA channel 3 transfer mode control register DMSRC4 56h/57h 14h DMA channel 4 source address register DMDST4 56h/57h 15h DMA channel 4 destination address register DMCTR4 56h/57h 16h DMA channel 4 element count register DMSFC4 56h/57h 17h DMA channel 4 sync select and frame count register DMMCR4 56h/57h 18h DMA channel 4 transfer mode control register DMSRC5 56h/57h 19h DMA channel 5 source address register DMDST5 56h/57h 1Ah DMA channel 5 destination address register DMCTR5 56h/57h 1Bh DMA channel 5 element count register DMSFC5 56h/57h 1Ch DMA channel 5 sync select and frame count register DMMCR5 56h/57h 1Dh DMA channel 5 transfer mode control register DMSRCP 56h/57h 1Eh DMA source program page address (common channel) DMDSTP 56h/57h 1Fh DMA destination program page address (common channel) DMIDX0 56h/57h 20h DMA element index address register 0 DMIDX1 56h/57h 21h DMA element index address register 1 DMFRI0 56h/57h 22h DMA frame index register 0 DMFRI1 56h/57h 23h DMA frame index register 1 DMGSA 56h/57h 24h DMA global source address reload register DMGDA 56h/57h 25h DMA global destination address reload register DMGCR 56h/57h 26h DMA global count reload register DMGFR 56h/57h 27h DMA global frame count reload register NAME 36 DESCRIPTION POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 interrupts Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13. Table 13. 5420 Interrupt Locations and Priorities for Each DSP Subsystem NAME LOCATION PRIORITY FUNCTION DECIMAL HEX RS, SINTR 0 00 1 Reset (Hardware and Software Reset) NMI, SINT16 4 04 2 Nonmaskable Interrupt SINT17 8 08 — Software Interrupt #17 SINT18 12 0C — Software Interrupt #18 SINT19 16 10 — Software Interrupt #19 SINT20 20 14 — Software Interrupt #20 SINT21 24 18 — Software Interrupt #21 SINT22 28 1C — Software Interrupt #22 SINT23 32 20 — Software Interrupt #23 SINT24 36 24 — Software Interrupt #24 SINT25 40 28 — Software Interrupt #25 SINT26 44 2C — Software Interrupt #26 SINT27 48 30 — Software Interrupt #27 SINT28 52 34 — Software Interrupt #28 SINT29 56 38 — Software Interrupt #29 SINT30 60 3C — Software Interrupt #30 INT0, SINT0 64 40 3 External User Interrupt #0 INT1, SINT1 68 44 4 External User Interrupt #1 INT2, SINT2 72 48 5 Reserved TINT, SINT3 76 4C 6 External Timer Interrupt BRINT0, SINT4 80 50 7 McBSP #0 Receive Interrupt BXINT0, SINT5 84 54 8 McBSP #0 Transmit Interrupt BRINT2 (DMAC0), SINT6 88 58 9 McBSP #2 Receive Interrupt (default) or DMA Channel 0 interrupt. The selection is made in the DMPREC register. BXINT2 (DMAC1), SINT7 92 5C 10 McBSP #2 Receive Interrupt (default) or DMA Channel 1 interrupt. The selection is made in the DMPREC register. INT3, SINT8 96 60 11 Reserved HPINT, SINT9 100 64 12 HPI Interrupt (from DSPINT in HPIC) BRINT1 (DMAC2), SINT10 104 68 13 McBSP #1 Receive Interrupt (default) or DMA Channel 2 interrupt. The selection is made in the DMPREC register. BXINT1 (DMAC3), SINT11 108 6C 14 McBSP #1 transmit Interrupt (default) or DMA channel 3 interrupt. The selection is made in the DMPREC register. DMAC4, SINT12 112 70 15 DMA Channel 4 DMAC5, SINT13 116 74 16 DMA Channel 5 120 78 17 Interprocessor Interrupt 124−127 7C−7F — Reserved IPINT, SINT14 — POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 interrupts (continued) Figure 9 shows the bit layout of the interrupt mask register (IMR) and the interrupt flag register (IFR). Table 14 describes the bit functions. The interprocessor interrupt (IPINT) bit of the interrupt mask register (IMR) and the interrupt flag register (IFR) allows the subsystem to perform interrupt service routines based on the other subsystem activity. Incoming IPINT interrupts are latched in bit 14 of the IFR. Generating an interprocessor interrupt is performed by writing a “1” to the IPIRQ field of the bank-switching control register (BSCR). Subsequent interrupts must first clear the interrupt by writing “0” to the IPIRQ field. For example, if subsystem A is required to notify subsystem B of a completed task, subsystem A must write a “1” to the IPIRQ field to generate a IPINT interrupt on subsystem B. On subsystem B, the IPINT interrupt is latched in bit 14 of the IFR. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES IPINT DMAC5 DMAC4 BXINT1 or DMAC3 BRINT1 or DMAC2 HPINT RES BXINT2 or DMAC1 BRINT2 or DMAC0 BXINT0 BRINT0 TINT RES INT1 INT0 Figure 9. Bit Layout of the IMR and IFR Registers for Each Subsystem Table 14. Bit Functions for IMR and IFR Registers for Each DSP Subsystem BIT NUMBER 38 FUNCTION NAME 15 − 14 IPINT Reserved 13 DMAC5 DMA channel 5 interrupt flag/mask bit 12 DMAC4 DMA channel 4 interrupt flag/mask bit 11 BXINT1/DMAC3 This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register. 10 BRINT1/DMAC2 This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register. 9 HPINT 8 − 7 BXINT2/DMAC1 This bit can be configured as either the McBSP2 transmit interrupt flag/mask bit, or the DMA channel 1 interrupt flag/mask bit. The selection is made in the DMPREC register. 6 BRINT2/DMAC0 This bit can be configured as either the McBSP2 receive interrupt flag/mask bit, or the DMA channel 0 interrupt flag/mask bit. The selection is made in the DMPREC register. 5 BXINT0 McBSP0 transmit interrupt flag/mask bit 4 BRINT0 McBSP0 receive interrupt flag/mask bit 3 TINT 2 − 1 INT1 External interrupt 1 flag/mask bit 0 INT0 External interrupt 0 flag/mask bit Interprocessor IRQ. Host to 54x interrupt flag/mask Reserved Timer interrupt flag/mask bit Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 IDLE3 power-down mode The IDLE1 and IDLE2 power-down modes operate as described in the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). The IDLE3 mode is special in that the clocking circuitry is shut off to conserve power. The 5420 cannot enter an IDLE3 mode unless both subsystems execute an IDLE3 instruction. The power-reduced benefits of IDLE3 cannot be realized until both subsystems enter the IDLE3 state and the internal clocks are automatically shut off. The order in which subsystems enter IDLE3 does not matter. emulating the 5420 device The 5420 is a single device, but actually consists of two independent subsystems that contain register/status information used by the emulator tools. The emulator tools must be informed of the multicore device by modifying the board.cfg file. The board.cfg file is an ASCII file that can be modified with most editors. This provides the emulator with a description of the JTAG chain. The board.cfg file must identify two processors when using the 5420. The file contents would look something like this: “CPU_B” TI320C5xx “CPU_A” TI320C5xx Use the compose program to make this file into a binary file (board.dat), readable by the emulation tools. Place the board.dat file in the directory that contains the emulator software. The subsystems are serially connected together internally. Emulation information is serially transmitted into the device using TDI. The device responds with serial scan information transmitted out the TDO pin. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 39 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 documentation support Extensive documentation supports all TMS320 DSP family of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the TMS320C5000 platform of DSPs: D D D D D TMS320C54x DSP Functional Overview (literature number SPRU307) Device-specific data sheets Complete User Guides Development-support tools Hardware and software application reports The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of: D D D D D Volume 1: CPU and Peripherals (literature number SPRU131) Volume 2: Mnemonic Instruction Set (literature number SPRU172) Volume 3: Algebraic Instruction Set (literature number SPRU179) Volume 4: Applications Guide (literature number SPRU173) Volume 5: Enhanced Peripherals (literature number SPRU302) The reference set describes in detail the TMS320C54x DSP products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding Texas Instruments (TI) DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). TMS320 and TMS320C5000 are trademarks of Texas Instruments. 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage I/O range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.0 V Supply voltage core range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 2.0 V Supply voltage analog PLL, AVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 2.0 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to DVDD + 0.5 V Output voltage range, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to DVDD + 0.5 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 100°C Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 3.0 3.3 3.6 V Device supply voltage, core 1.71 1.80 1.98 V Device supply voltage, PLL 1.71 1.80 1.98 V DVDD Device supply voltage, I/O CVDD AVDD VSS VIH High-level input voltage, I/O VIL Supply voltage, GND 0 Schmitt trigger inputs, TRST, SELA/B DVDD = 3.3 ± 0.3 V Low-level input voltage, I/O UNIT V 0.7DVDD DVDD All other inputs 2 DVDD Schmitt trigger inputs DVDD = 3.3 ± 0.3 V 0 0.3DVDD All other inputs 0 0.8 V V IOH High-level output current −300 µA IOL Low-level output current 1.5 mA Operating case temperature, industrial TC Operating case temperature, commercial −40 100 0 100 °C Refer to Figure 10 for 3.3-V device test load circuit values. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 41 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 electrical characteristics over recommended operating case temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH VOL High-level output voltage‡ Low-level output voltage‡ DVDD = 3.3 ± 0.3 V, IOH = MAX IOL = MAX 2.4 0.4 V IIZ Input current in high impedance −10 10 µA TRST DVDD = MAX, VO = VSS to DVDD With internal pulldown −10 35 See pin descriptions With internal pullups −35 10 PPD[15:0] Bus holders enabled, DVDD = MAX, VI = VSS to VIL (MAX); VIH (MIN) to DVDD −200 200 II Input current (VI = VSS to VDD) All other input-only pins IDDC IDDP Supply current, both core CPUs IDDA Supply current, PLL IDDC Supply current, standby Ci Input capacitance −10 CVDD = 1.8 V, fx=100 MHz§, TC=25°C¶ DVDD = 3.3 V, fclock = 100 MHz¶, TC = 25°C# Supply current, pins V µA 10 180 mA 54 mA 5 mA IDLE2 PLL × n mode, 20 MHz input 2 mA IDLE3 PLL x n mode, 20 MHz input 600 µA 5 pF Co Output capacitance 5 pF † All values are typical unless otherwise specified. ‡ All input and output voltage levels except A_RS, B_RS, INT0 INT1, NMI, CLKIN, BCLKX, BCLKR, HAS, HCS, TCK, TRST, SELA/B, HDS1, HDS2, and HPIRS are LVTTL-compatible. § Clock mode: PLL × 1 with external source ¶ This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed. # This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex operation of all six McBSPs at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation Application Report (literature number SPRA164). PARAMETER MEASUREMENT INFORMATION IOL 50 Ω Tester Pin Electronics VLoad CT IOH Where: IOL IOH VLoad CT = = = = 1.5 mA (all outputs) 300 µA (all outputs) 1.5 V 40 pF typical load circuit capacitance Figure 10. 3.3-V Test Load Circuit 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Output Under Test 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external multiply-by-N clock option An external frequency can be used by injecting the frequency directly into CLKIN. This external frequency is multiplied by N to generate the internal machine cycle. The external frequency injected must conform to specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 11 and the recommended operating conditions table) PARAMETER MIN TYP MAX 10 tc(CI)/N† 10 16 UNIT tc(CO) td(CIH-CO) Cycle time, CLKOUT tf(CO) tr(CO) Fall time, CLKOUT 2 ns Rise time, CLKOUT 2 ns tw(COL) tw(COH) Pulse duration, CLKOUT low H−2 H−1 H Pulse duration, CLKOUT high H−2 H−1 H ns 35 µs Delay time, CLKIN high/low to CLKOUT high/low 4 tp Transitory phase, PLL lock-up time † N is the PLL multiplier. N = 1 – 15 ns ns ns timing requirements (see Figure 11) tc(CI) tf(CI) tr(CI) Cycle time, CLKIN MIN MAX Integer PLL multiplier N 10N 200 PLL multiplier N = x.5 10N 100 PLL multiplier N = x.25, x.75 10N 50 Fall time, CLKIN Rise time, CLKIN tr(CI) tc(CI) UNIT ns 8 ns 8 ns tf(CI) CLKIN td(CI-CO) tc(CO) tw(COH) tw(COL) tp CLKOUT tf(CO) tr(CO) Unstable Figure 11. External Multiply-By-One Clock POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 43 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 bypass option An external frequency can be used by injecting the frequency directly into CLKIN. The external frequency injected must conform to specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 12 and the recommended operating conditions table) PARAMETER MIN TYP MAX 10 tc(CI) 10 16 UNIT tc(CO) td(CIH-CO) Cycle time, CLKOUT tf(CO) tr(CO) Fall time, CLKOUT 2 ns Rise time, CLKOUT 2 ns tw(COL) tw(COH) Pulse duration, CLKOUT low H−2 H−1 H ns Pulse duration, CLKOUT high H−2 H−1 H ns Delay time, CLKIN high/low to CLKOUT high/low 4 ns ns timing requirements (see Figure 12) MIN tc(CI) tf(CI) Cycle time, CLKIN 10 Fall time, CLKIN MAX † 8 UNIT ns ns tr(CI) Rise time, CLKIN 8 ns † This device utilizes a fully static design and therefore can operate with tc(CI) approaching 1. The device is characterized at frequencies approaching 0 Hz. tf(CI) tr(CI) tc(CI) CLKIN td(CI-CO) tc(CO) CLKOUT tw(COH) tw(COL) Unstable Figure 12. Timing Diagram for Bypass Mode 44 POST OFFICE BOX 1443 tf(CO) • HOUSTON, TEXAS 77251−1443 tr(CO) 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external memory interface timing for one wait state switching characteristics over recommended operating conditions for a one-wait-state memory read (MSTRB = 0)† (see Figure 13) PARAMETER td(CLKL-A) td(CLKH-A) MIN MAX Delay time, CLKOUT low to address valid‡ −1 5 ns Delay time, CLKOUT high (transition) to address valid§ −1 6 ns −1 4 ns −1 4 ns −1 5 ns −1 6 ns td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high th(CLKL-A)R Hold time, address valid after CLKOUT low‡ th(CLKH-A)R Hold time, address valid after CLKOUT high§ † Address, PS, and DS timings are all included in timings referenced as address. ‡ In the case of a memory read preceded by a memory read § In the case of a memory read preceded by a memory write UNIT timing requirements for a one-wait-state memory read (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 13) MIN MAX UNIT ta(A)M ta(MSTRBL) Access time, read data access from address valid (1 wait state required) 4H−15 ns Access time, read data access from MSTRB low 4H−14 ns tsu(D)R th(D)R Setup time, read data before CLKOUT low Hold time, read data after CLKOUT low th(A-D)R Hold time, read data after address invalid th(D)MSTRBH Hold time, read data after MSTRB high † Address, PS, and DS timings are all included in timings referenced as address. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 12 ns 0 ns 0 ns 0 ns 45 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external memory interface timing for one wait state (continued) CLKOUT td(CLKL-A) th(CLKL-A)R PPA[17:0] th(A-D)R tsu(D)R ta(A)M th(D)R PPD[15:0] th(D)MSTRBH td(CLKL-MSL) td(CLKL-MSH) ta(MSTRBL) MSTRB R/W PS, DS 1 Wait State Figure 13. Memory Read (MSTRB = 0) 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external memory interface timing for a memory write for one wait state switching characteristics over recommended operating conditions for a memory write (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 14) MIN MAX td(CLKH-A) td(CLKL-A) Delay time, CLKOUT high to address valid‡ Delay time, CLKOUT low to address valid§ PARAMETER −1 6 ns −1 5 ns td(CLKL-MSL) td(CLKL-D)W Delay time, CLKOUT low to MSTRB low −1 4 ns 0 12 ns td(CLKL-MSH) td(CLKH-RWL) Delay time, CLKOUT low to MSTRB high −1 4 ns 0 4 ns −1 4 ns H−2 H+2 ns −1 6 ns MIN MAX UNIT H−3 H +3§ ns Delay time, CLKOUT low to data valid Delay time, CLKOUT high to R/W low td(CLKH-RWH) Delay time, CLKOUT high to R/W high td(RWL-MSTRBL) Delay time, R/W low to MSTRB low th(A)W Hold time, address valid after CLKOUT high‡ † Address, PS, and DS timings are all included in timings referenced as address. ‡ In the case of a memory write preceded by a memory write § In the case of a memory write preceded by an I/O cycle. UNIT timing requirements for a memory write (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 14) th(D)MSH tw(SL)MS Hold time, write data valid after MSTRB high Pulse duration, MSTRB low§ 4H−4 tsu(A)W Setup time, address valid before MSTRB low tsu(D)MSH Setup time, write data valid before MSTRB high † Address, PS, and DS timings are all included in timings referenced as address. § In the case of a memory write preceded by an I/O cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ns H−4 4H−10 ns 4H+5§ ns 47 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external memory interface timing for a memory write for one wait state (continued) CLKOUT td(CLKH-A) td(CLKL-A) th(A)W A[19:0] td(CLKL-D)W th(D)MSH tsu(D)MSH D[15:0] td(CLKL-MSL) td(CLKL-MSH) tsu(A)W MSTRB td(CLKH-RWL) td(CLKH-RWH) tw(SL)MS td(RWL-MSTRBL) R/W PS, DS 1 Wait State Figure 14. Memory Write (MSTRB = 0) 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 ready timing for externally generated wait states timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 15 and Figure 16) MIN tsu(RDY) th(RDY) Setup time, READY before CLKOUT low Hold time, READY after CLKOUT low tv(RDY)MSTRB Valid time, READY after MSTRB low‡ th(RDY)MSTRB Hold time, READY after MSTRB low‡ MAX UNIT 7 ns 0 ns 4H−8 ns 4H ns † The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states. ‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT CLKOUT A[19:0] tsu(RDY) th(RDY) READY tv(RDY)MSTRB th(RDY)MSTRB MSTRB Wait States Generated Internally Wait State Generated by READY Figure 15. Memory Read With Externally Generated Wait States POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 49 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] th(RDY) tsu(RDY) READY tv(RDY)MSTRB th(RDY)MSTRB MSTRB Wait States Generated Internally Wait State Generated by READY Figure 16. Memory Write With Externally Generated Wait States 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 parallel I/O interface timing switching characteristics over recommended operating conditions for a parallel I/O port read (IOSTRB = 0)† (see Figure 17) PARAMETER td(CLKL-A) Delay time, CLKOUT low to address valid td(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high th(A)IOR Hold time, address after CLKOUT low † Address and IS timings are included in timings referenced as address. MIN MAX −1 5 UNIT ns 0 5 ns 0 5 ns −1 5 ns timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 17) MIN ta(A)IO ta(ISTRBL)IO Access time, read data access from address valid tsu(D)IOR th(D)IOR Setup time, read data before CLKOUT high Access time, read data access from IOSTRB low Hold time, read data after CLKOUT high th(ISTRBH-D)R Hold time, read data after IOSTRB high † Address and IS timings are included in timings referenced as address. MAX UNIT 5H−15 ns 4H−14 ns 10 ns 0 ns 0 ns CLKOUT th(A)IOR td(CLKL-A) PPA[17:0] th(D)IOR tsu(D)IOR ta(A)IO PPD[15:0] th(ISTRBH-D)R td(CLKH-ISTRBH) ta(ISTRBL)IO td(CLKH-ISTRBL) IOSTRB R/W IS 1 Wait State Figure 17. Parallel I/O Port Read (IOSTRB=0) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 51 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port write (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 18) MIN MAX td(CLKL-A) td(CLKH-ISTRBL) Delay time, CLKOUT low to address valid PARAMETER −1 5 ns Delay time, CLKOUT high to IOSTRB low 0 5 ns td(CLKH-D)IOW td(CLKH-ISTRBH) Delay time, CLKOUT high to write data valid H−5 H+11 ns Delay time,CLKOUT high to IOSTRB high 0 5 ns td(CLKL-RWL) td(CLKL-RWH) Delay time, CLKOUT low to R/W low 0 4 ns Delay time, CLKOUT low to R/W high 0 4 ns th(A)IOW th(D)IOW Hold time, address valid after CLKOUT low −1 5 ns Hold time, write data after IOSTRB high tsu(D)IOSTRBH Setup time, write data before IOSTRB high tsu(A)IOSTRBL Setup time, address valid before IOSTRB low † Address and IS timings are included in timings referenced as address. H−3 H+5 ns 3H−9 3H+5 ns H−3 H+3 ns CLKOUT tsu(A)IOSTRBL td(CLKL-A) th(A)IOW PPA[17:0] td(CLKH-D)IOW th(D)IOW PPD[15:0] td(CLKH-ISTRBL) td(CLKH-ISTRBH) tsu(D)IOSTRBH IOSTRB td(CLKL-RWH) td(CLKL-RWL) R/W IS 1 Wait State Figure 18. Parallel I/O Port Write (IOSTRB=0) 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 UNIT 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 I/O port timing for externally generated wait states timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 19 and Figure 20) MIN tsu(RDY) th(RDY) tv(RDY)IOSTRB th(RDY)IOSTRB MAX UNIT Setup time, READY before CLKOUT low 7 ns Hold time, READY after CLKOUT low Valid time, READY after IOSTRB low‡ 0 ns Hold time, READY after IOSTRB low‡ 5H 5H−8 ns ns † The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using READY, at least two software wait states must be programmed. ‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT. CLKOUT PPA[17:0] th(RDY) tsu(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB Wait States Generated Internally Wait State Generated by READY Figure 19. I/O Port Read With Externally Generated Wait States POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 53 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 I/O port timing for externally generated wait states (continued) CLKOUT PPA[17:0] D[15:0] th(RDY) tsu(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB Wait States Generated Internally Wait State Generated by READY Figure 20. I/O Port Write With Externally Generated Wait States 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 reset, BIO, interrupt, and XIO timing timing requirements for reset, BIO, interrupt, and XIO [H = 0.5 tc(CO)] (see Figure 21, Figure 22, and Figure 23) MIN MAX UNIT th(RS) th(BIO) Hold time, A_RS or B_RS after CLKOUT low 0 ns Hold time, BIO after CLKOUT low 0 ns th(INT) th(XIO)‡ Hold time, INTn, NMI, after CLKOUT low† 0 ns Hold time, XIO after CLKOUT low 0 ns tw(RSL) tw(BIO)A Pulse duration, A_RS or B_RS low§¶ 4H+5 ns Pulse duration, BIO low, asynchronous 5H ns tw(INTH)A tw(INTL)A Pulse duration, INTn, NMI high (asynchronous)† Pulse duration, INTn, NMI low (asynchronous)† 4H ns 4H ns tw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup† tsu(RS) Setup time, A_RS or B_RS before CLKIN low¶ 8 ns 7 ns tsu(BIO) tsu(INT) tsu(XIO)‡ Setup time, BIO before CLKOUT low 9 ns Setup time, INTn, NMI, A_RS or B_RS before CLKOUT low† 9 ns Setup time, XIO before CLKOUT low 10 ns † The external interrupts (INT0−INT1, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding to a three-CLKOUT sampling sequence. ‡ Once the setup and hold times are met for XIO, the following falling edge of CLKOUT is either an HPI or EMIF cycle. § If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, A_RS must be held low for at least 50 µs to ensure synchronization and lock-in of the PLL. ¶ Note that A_RS can cause a change in clock frequency, therefore changing the value of H (see the software-programmable phase-locked loop (PLL) section). CLKIN tsu(RS) tw(RSL) A_RS, B_RS, INTn, NMI tsu(INT) th(RS) CLKOUT tsu(BIO) th(BIO) BIO tw(BIO)S Figure 21. Reset and BIO Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 55 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 reset, BIO, interrupt, and XIO timing (continued) CLKOUT tsu(INT) tsu(INT) th(INT) INTn, NMI tw(INTH)A tw(INTL)A Figure 22. Interrupt Timing CLKOUT th(XIO) tsu(XIO) XIO Figure 23. XIO Timing 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 external flag (XF) and timer output (TOUT) timing switching characteristics over recommended operating conditions for external flag (XF) and TOUT [H = 0.5 tc(CO)] (see Figure 24 and Figure 25) MIN MAX Delay time, CLKOUT low to XF high PARAMETER 0 3 Delay time, CLKOUT low to XF low 0 3 td(TOUTH) td(TOUTL) Delay time, CLKOUT high to TOUT high 0 5 ns Delay time, CLKOUT high to TOUT low 0 5 ns tw(TOUT) Pulse duration, TOUT td(XF) 2H−2 UNIT ns ns CLKOUT td(XF) XF Figure 24. External Flag (XF) Timing CLKOUT td(TOUTL) td(TOUTH) TOUT tw(TOUT) Figure 25. Timer (TOUT) Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 57 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 general-purpose input/output (GPIO) timing timing requirements for GPIO (see Figure 26) MIN MAX UNIT tsu(GPIO-COH) Setup time, GPIOx input valid before CLKOUT high, GPIOx configured as general-purpose input. 7 ns th(GPIO-COH) Hold time, GPIOx input valid after CLKOUT high, GPIOx configured as general-purpose input. 0 ns switching characteristics for GPIO (see Figure 26) PARAMETER td(COH-GPIO) Delay time, CLKOUT high to GPIOx output change. GPIOx configured as general-purpose output. MIN MAX UNIT 0 5 ns CLKOUT tsu(GPIO-COH) th(GPIO-COH) GPIOx Input Mode td(COH-GPIO) GPIOx Output Mode Figure 26. GPIO Timings 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 SELA/B timing switching characteristics in XIO = 1 mode for SELA/B (see Figure 27) PARAMETER td(SELA/B-ABUS) Delay time, SELA/B to address bus valid in XIO = 1 mode. PPA[17:0] MIN MAX UNIT 3 10 ns VALID A BUS SELA/B td(SELA/B-ABUS) XIO Figure 27. SELA/B Timing in XIO = 1 Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 59 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing timing requirements for the McBSP† [H=0.5tc(CO)] (see Figure 28 and Figure 29) MIN tc(BCKRX) tw(BCKRX) MAX UNIT Cycle time, BCLKR/X BCLKR/X ext 4H ns Pulse duration, BCLKR/X or BCLKR/X high BCLKR/X ext 6 ns BCLKR int 0 BCLKR ext 4 th(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low th(BCKRL-BDRV) Hold time, BDR valid after BCLKR low th(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low tsu(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low tsu(BDRV-BCKRL) Setup time, BDR valid before BCLKR low tsu(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low BCLKR int 0 BCLKR ext 5 BCLKX int 0 BCLKX ext 4 BCLKR int 10 BCLKR ext 4 BCLKR int 10 BCLKR ext 3 BCLKX int 10 BCLKX ext 6 ns ns ns ns ns ns tr(BCKRX) Rise time, BCKR/X BCLKR/X ext 8 ns tf(BCKRX) Fall time, BCKR/X BCLKR/X ext 8 ns † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) switching characteristics for the McBSP† [H=0.5tc(CO)] (see Figure 28 and Figure 29) PARAMETER MIN tc(BCKRX) tw(BCKRXH) Cycle time, BCLKR/X BCLKR/X int Pulse duration, BCLKR/X high BCLKR/X int 4H D−4‡ tw(BCKRXL) td(BCKRH-BFRV) Pulse duration, BCLKR/X low BCLKR/X int Delay time, BCLKR high to internal BFSR valid td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit Delay time, BCLKX high to BDX valid. This applies to all bits except the first bit transmitted. td(BCKXH-BDXV) te(BCKXH-BDX) td(BFXH-BDXV) te(BFXH-BDX) Delay time, BCLKX high to BDX valid.§ Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes Enable time, BCLKX high to BDX driven.§ Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes Delay time, BFSX high to BDX valid.§ Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. Enable time, BFSX high to BDX driven.§ Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode DXENA = 0 DXENA = 1 DXENA = 0 DXENA = 1 DXENA = 0 DXENA = 1 DXENA = 0 MAX UNIT ns ns C−4‡ D+1‡ C+1‡ BCLKR int −3 3 ns BCLKX int −3 8 BCLKX ext 2 15 BCLKX int −8 5 BCLKX ext 1 19 BCLKX int 0 11 BCLKX ext 5 20 BCLKX int 11 BCLKX ext 20 BCLKX int 25 BCLKX ext ns ns ns ns 27 BCLKX int −4 BCLKX ext 2 BCLKX int 6 BCLKX ext 12 ns BFSX int 9 BFSX ext 12 BFSX int 25 BFSX ext ns 26 BFSX int −1 BFSX ext 2 BFSX int 9 ns DXENA = 1 BFSX ext 13 † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ T=BCLKRX period = (1 + CLKGDV) * 2H C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable (DXENA) and data delay features of the McBSP. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 61 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) tc(BCKRX) tw(BCKRXH) tr(BCKRX) tw(BCKRXL) BCLKR td(BCKRH−BFRV) td(BCKRH−BFRV) tr(BCKRX) BFSR (int) tsu(BFRH−BCKRL) th(BCKRL−BFRH) BFSR (ext) th(BCKRL−BDRV) tsu(BDRV−BCKRL) BDR (RDATDLY=00b) Bit (n−1) (n−2) tsu(BDRV−BCKRL) (n−3) (n−4) th(BCKRL−BDRV) BDR (RDATDLY=01b) Bit (n−1) (n−2) tsu(BDRV−BCKRL) BDR (RDATDLY=10b) (n−3) th(BCKRL−BDRV) Bit (n−1) (n−2) Figure 28. McBSP Receive Timings tc(BCKRX) tw(BCKRXH) tw(BCKRXL) tr(BCKRX) tf(BCKRX) BCLKX td(BCKXH−BFXV) td(BCKXH−BFXV) BFSX (int) tsu(BFXH−BCKXL) th(BCKXL−BFXH) BFSX (ext) te(BDFXH−BDX) BDX (XDATDLY=00b) Bit 0 td(BDFXH−BDXV) Bit (n−1) td(BCKXH−BDXV) (n−2) te(BCKXH−BDX) BDX (XDATDLY=01b) Bit (n−1) Bit 0 td(BCKXH−BDXV) (n−2) (n−3) te(BCKXH−BDX) Bit 0 Bit (n−1) Figure 29. McBSP Transmit Timings 62 (n−4) td(BCKXH−BDXV) tdis(BCKXH−BDXHZ) BDX (XDATDLY=10b) (n−3) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 (n−2) 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) timing requirements for McBSP general-purpose I/O (see Figure 30) MIN tsu(BGPIO-COH) th(COH-BGPIO) Setup time, BGPIOx input mode before CLKOUT high† Hold time, BGPIOx input mode after CLKOUT high† MAX UNIT 9 ns 0 ns † BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. switching characteristics for McBSP general-purpose I/O (see Figure 30) PARAMETER Delay time, CLKOUT high to BGPIOx output mode‡ td(COH-BGPIO) ‡ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output. tsu(BGPIO-COH) MIN MAX −10 10 UNIT ns td(COH-BGPIO) CLKOUT th(COH-BGPIO) BGPIOx Input Mode† BGPIOx Output Mode‡ † BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. ‡ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output. Figure 30. McBSP General-Purpose I/O Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 63 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0† (see Figure 31) MASTER MIN tsu(BDRV-BCKXL) th(BCKXL-BDRV) Setup time, BDR valid before BCLKX low tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high SLAVE MAX MIN MAX UNIT 12 2 − 12H ns 4 6 + 12H ns 10 ns 32H ns Hold time, BDR valid after BCLKX low tc(BCKX) Cycle time, BCLKX 12H † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0† (see Figure 31) MASTER‡ PARAMETER MIN th(BCKXL-BFXL) td(BFXL-BCKXH) Hold time, BFSX low after BCLKX low§ Delay time, BFSX low to BCLKX high¶ td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid tdis(BCKXL-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX low tdis(BFXH-BDXHZ) Disable time, BDX high impedance following last data bit from BFSX high SLAVE MAX MIN MAX UNIT T−5 T+5 ns C−5 C+5 ns −2 12 C−2 C +10 6H + 4 10H + 19 ns ns 4H+ 4 8H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H + 4 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). LSB tc(BCKX) MSB tsu(BFXL-BCKXH) BCLKX th(BCKXL-BFXL) td(BFXL-BCKXH) BFSX tdis(BFXH-BDXHZ) td(BFXL-BDXV) td(BCKXH-BDXV) tdis(BCKXL-BDXHZ) BDX Bit 0 Bit(n-1) tsu(BDRV-BCLXL) BDR Bit 0 (n-2) (n-3) (n-4) th(BCKXL-BDRV) Bit(n-1) (n-2) (n-3) Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 (n-4) 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0† (see Figure 32) MASTER MIN tsu(BDRV-BCKXH) th(BCKXH-BDRV) Setup time, BDR valid before BCLKX high tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high Hold time, BDR valid after BCLKX high SLAVE MAX MIN MAX UNIT 12 2 − 12H ns 4 5 +12H ns 10 ns 32H ns tc(BCKX) Cycle time, BCLKX 12H † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0† (see Figure 32) MASTER‡ PARAMETER SLAVE MIN MAX UNIT MIN MAX C−5 C+5 ns T−5 T+5 ns th(BCKXL-BFXL) td(BFXL-BCKXH) Hold time, BFSX low after BCLKX low§ Delay time, BFSX low to BCLKX high¶ td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid −2 12 6H + 4 10H + 19 ns tdis(BCKXL-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX low −2 10 6H + 4 10H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid D − 2 D +10 4H − 4 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). LSB tc(BCKX) MSB tsu(BFXL-BCKXH) BCLKX td(BFXL-BCKXH) th(BCKXL-BFXL) BFSX tdis(BCKXL-BDXHZ) BDX td(BCKXL-BDXV) td(BFXL-BDXV) Bit 0 Bit(n-1) tsu(BDRV-BCKXH) BDR Bit 0 (n-2) (n-3) (n-4) th(BCKXH-BDRV) Bit(n-1) (n-2) (n-3) (n-4) Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 65 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 1† (see Figure 33) MASTER MIN tsu(BDRV-BCKXH) th(BCKXH-BDRV) Setup time, BDR valid before BCLKX high tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low Hold time, BDR valid after BCLKX high SLAVE MAX MIN MAX UNIT 12 2 − 12H ns 4 6 + 12H ns 10 ns 32H ns tc(BCKX) Cycle time, BCLKX 12H † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 1† (see Figure 33) MASTER‡ PARAMETER MIN th(BCKXH-BFXL) td(BFXL-BCKXL) Hold time, BFSX low after BCLKX high§ Delay time, BFSX low to BCLKX low¶ td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX high tdis(BFXH-BDXHZ) Disable time, BDX high impedance following last data bit from BFSX high SLAVE MAX MIN MAX UNIT T−5 T+5 ns D−5 D+5 ns −2 12 D−2 D +10 6H + 4 10H + 19 ns ns 4H + 4 8H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H − 4 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). tsu(BFXL-BCKXL) LSB tc(BCKX) MSB BCLKX th(BCKXH-BFXL) td(BFXL-BCKXL) BFSX td(BFXL-BDXV) tdis(BFXH-BDXHZ) tdis(BCKXH-BDXHZ) BDX td(BCKXL-BDXV) Bit 0 Bit(n-1) tsu(BDRV-BCKXH) BDR Bit 0 (n-2) (n-3) th(BCKXH-BDRV) Bit(n-1) (n-2) (n-3) Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 66 POST OFFICE BOX 1443 (n-4) • HOUSTON, TEXAS 77251−1443 (n-4) 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1† (see Figure 34) MASTER MIN tsu(BDRV-BCKXL) th(BCKXL-BDRV) Setup time, BDR valid before BCLKX low tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low Hold time, BDR valid after BCLKX low SLAVE MAX MIN UNIT MAX 12 2 − 12H ns 4 6 + 12H ns 10 ns 32H ns tc(BCKX) Cycle time, BCLKX 12H † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1† (see Figure 34) MASTER‡ PARAMETER SLAVE MIN UNIT MIN MAX MAX D−5 D+5 ns T−5 T+5 ns th(BCKXH-BFXL) td(BFXL-BCKXL) Hold time, BFSX low after BCLKX high§ Delay time, BFSX low to BCLKX low¶ td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid −2 12 6H + 4 10H + 19 ns tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX high −2 10 6H + 4 10H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid C − 2 C +10 4H − 4 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). LSB tsu(BFXL-BCKXL) tc(BCKX) MSB BCLKX th(BCKXH-BFXL) td(BFXL-BCKXL) BFSX tdis(BCKXH-BDXHZ) BDX td(BCKXH-BDXV) td(BFXL-BDXV) Bit 0 Bit(n-1) tsu(BDRV-BCKXL) BDR Bit 0 (n-2) (n-3) (n-4) th(BCKXL-BDRV) Bit(n-1) (n-2) (n-3) (n-4) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 67 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing switching characteristics over recommended operating conditions†‡§ [H = 0.5tc(CO)] (see Figure 35 – Figure 42) PARAMETER td(DSL-HDD) Delay time, DS low to HD driven§ MIN MAX UNIT 3 20 ns Case 1a: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) < 18H Case 1b: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) ≥ 18H td(DSL-HDV1) Delay time, DS low to HDx valid for first byte of an HPI read 18H+20 – tw(DSH) 20 Case 1c: Memory access when DMAC is active in 32-bit mode and tw(DSH) < 26H Case 1d: Memory access when DMAC is active in 32-bit mode and tw(DSH) ≥ 26H 26H+20 – tw(DSH) ns 20 Case 2a: Memory accesses when DMAC is inactive and tw(DSH) < 10H 10H+20 – tw(DSH) Case 2b: Memory accesses when DMAC is inactive and tw(DSH) ≥ 10H 20 Case 3: Register accesses td(DSL-HDV2) td(DSH-HYH) Multiplexed reads with autoincrement. Prefetch completed. Delay time, DS high to HRDY high§ (writes and autoincrement reads) 20 No DMA channel active 12H+5 One or more 16-bit DMA channels active 18H+5 One or more 32-bit DMA channels active 26H+5 Writes to DSPINT and HINT 4H + 5 tv(HYH-HDV) th(DSH-HDV)R Valid time, HDx valid after HRDY high td(COH-HYH) td(DSH-HYL) Delay time, CLKOUT rising edge to HRDY high Delay time, HDS or HCS high to HRDY low‡ Hold time, HD valid after DS rising edge, read§ td(COH−HTX) Delay time, CLKOUT rising edge to HINT change † HAD stands for HCNTL0, HCNTL1, and HR/W. ‡ HDS refers to either HDS1 or HDS2. § DS refers to the logical OR of HCS and HDS. 68 20 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 0 ns ns 7 ns 10 ns 5 ns 12 ns 5 ns 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) timing requirements [H = 0.5tc(CO)] (see Figure 35 – Figure 42) MIN MAX UNIT tsu(HBV-DSL) th(DSL-HBV) Setup time, HAD valid before DS falling edge†‡ Hold time, HAD valid after DS falling edge†‡ 5 ns 5 ns tsu(HBV-HSL) th(HSL-HBV) Setup time, HAD valid before HAS falling edge† Hold time, HAD valid after HAS falling edge† 5 ns 5 ns tsu(HAV-DSH) tsu(HAV-DSL) Setup time, address valid before DS rising edge (nonmultiplexed write) th(DSH-HAV) tsu(HSL-DSL) th(HSL-DSL) tw(DSL) tw(DSH) Setup time, address valid before DS falling edge (nonmultiplexed mode)‡ Hold time, address valid after DS rising edge (nonmultiplexed mode)‡ ns ns 1 ns Setup time, HAS low before DS falling edge‡ Hold time, HAS low after DS falling edge‡ 5 ns 2 ns Pulse duration, DS low‡ Pulse duration, DS high‡ 30 ns 10 ns Nonmultiplexed or multiplexed mode (no increment) with no DMA activity. Reads 12H ns Writes 14H ns Nonmultiplexed or multiplexed mode (no increment) with 16-bit DMA activity. Reads 18H ns Writes 20H Nonmultiplexed or multiplexed mode (no increment) with 32-bit DMA activity. Reads 26H Writes 28H Multiplexed (autoincrement) with no DMA activity. 12H ns Multiplexed (autoincrement) with 16-bit DMA activity. 18H ns Multiplexed (autoincrement) with 32-bit DMA activity. 26H ns 8H ns 10 ns Hold time, HD valid after DS rising edge, write‡ 0 ns Setup time, SELA/B valid before DS falling edge‡ Hold time, SELA/B valid after DS Rising edge‡ 5 ns 0 ns Cycle time, DS rising edge to next DS rising edge‡ tc(DSH-DSH) Cycle time, DS rising edge to next DS rising edge‡ (In autoincrement mode, WRITE timings are the same as READ timings.) tsu(HDV-DSH) th(DSH-HDV)W 5 −4H − 5 Cycle time, DS rising edge to next DS rising edge writes to DSPINT and HINT Setup time, HD valid before DS rising edge‡ tsu(SELV-DSL) th(DSH-SELV) † HAD stands for HCNTL0, HCNTL1, and HR/W. ‡ DS refers to the logical OR of HCS and HDS. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ns 69 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) HCS tsu(HSL−DSL) th(HSL−DSL) HAS tc(DSH−DSH) tsu(HBV−HSL) HDS tw(DSH) th(HSL−HBV) tw(DSL) HR/W HCNTL[1:0] 01 01 td(DSL−HDV1) th(DSH−HDV)R td(DSL−HDV2) Data 1 HD[15:0] PF Data td(DSL−HDD) HRDY tv(HYH−HDV) td(DSH−HYL) td(DSH−HYH) Figure 35. Multiplexed Read Timings Using HAS HCS tsu(HBV−DSL) tc(DSH−DSH) HDS th(DSL−HBV) tw(DSH) tw(DSL) HR/W 01 HCNTL[1:0] 01 td(DSL−HDV1) th(DSH−HDV)R td(DSL−HDV2) Data 1 HD[15:0] PF Data td(DSL−HDD) HRDY tv(HYH−HDV) td(DSH−HYL) td(DSH−HYH) Figure 36. Multiplexed Read Timings Without HAS 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Á Á 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) HCS tsu(HBV−HSL) th(HSL−DSL) HAS tsu(HSL−DSL) HR/W th(HSL−HBV) HCNTL[0:1] 01 01 tc(DSH−DSH) HDS tw(DSH) tw(DSL) tsu(HDV−DSH) HD[15:0] Data 1 Data n th(DSH−HDV)W HRDY td(DSH−HYL) td(DSH−HYH) Figure 37. Multiplexed Write Timings Using HAS POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 71 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) HCS tc(DSH−DSH) tw(DSH) HDS tw(DSL) tsu(HBV−DSL) HR/W th(DSL−HBV) HCNTL[1:0] 01 01 tsu(HDV−DSH) HD[15:0] th(DSH−HDV)W Data 1 Data n td(DSH−HYL) HRDY td(DSH−HYH) Figure 38. Multiplexed Write Timings Without HAS 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) HCS tw(DSH) tc(DSH−DSH) HDS tsu(HBV−DSL) tw(DSL) th(DSL−HBV) HR/W tsu(HAV−DSL) th(DSH−HAV) HA[17:0] Valid Address Valid Address td(DSL−HDV1) HD[15:0] Data th(DSH−HDV)R Data Valid td(DSH−HYH) tv(HYH−HDV) HRDY td(DSH−HYL) Figure 39. Nonmultiplexed Read Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 73 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) HCS tw(DSH) tc(DSH−DSH) HDS tsu(HBV−DSL) tw(DSL) th(DSL−HBV) HR/W tsu(HAV−DSH) th(DSH−HAV) HA[17:0] Valid Address Valid Address tsu(HDV−DSH) HD[15:0] Data Valid Data Valid td(DSH−HYH) HRDY td(DSH−HYL) Figure 40. Nonmultiplexed Write Timings 74 th(DSH−HDV)W POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 HPI16 timing (continued) HRDY td(COH−HYH) CLKOUT td(COH−HTX) HINT Figure 41. HRDY and HINT Relative to CLKOUT HCS tsu(DSL−SELV) th(DSH−SELV) SELA/B HDS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 42. SELA/B Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 75 
   

   SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 mechanical data The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. package thermal resistance characteristics Table 15 provides the estimated thermal resistance characteristics for the recommended package types used on the device. Table 15. Thermal Resistance Characteristics 76 PARAMETER PGE PACKAGE GGU PACKAGE UNIT RΘJA 56 38 °C/W RΘJC 5 5 °C/W POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PACKAGE OPTION ADDENDUM www.ti.com 1-Jan-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TMS320C5420GGUA200 OBSOLETE BGA MICROSTAR GGU 144 TBD SNPB Level-3-220C-168 HR 0 to 0 C5420GGUA 200 TMS320C5420GGUR200 OBSOLETE BGA MICROSTAR GGU 144 TBD Call TI Call TI 0 to 0 DVC5420GGU 200 TMS320C5420PGEA200 OBSOLETE LQFP PGE 144 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 0 C5420PGEA200 TMS320VC5420GGU200 OBSOLETE BGA MICROSTAR GGU 144 TBD SNPB Level-3-220C-168 HR TMS320VC5420PGE200 OBSOLETE LQFP PGE 144 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TMS320VC5420ZGU200 OBSOLETE BGA MICROSTAR ZGU 144 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR DVC5420GGU 200 0 to 0 DVC5420PGE200 DVC5420ZGU 200 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Jan-2017 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPBG021C – DECEMBER 1996 – REVISED MAY 2002 GGU (S–PBGA–N144) PLASTIC BALL GRID ARRAY 12,10 SQ 11,90 9,60 TYP 0,80 A1 Corner 0,80 N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 Bottom View 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,10 4073221-2/C 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGAt configuration MicroStar BGA is a trademark of Texas Instruments Incorporated. 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