TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
2.8-W STEREO AUDIO POWER AMPLIFIER
WITH DC VOLUME CONTROL
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Compatible With PC 99 Desktop Line-Out Into
10-kΩ Load
Compatible With PC 99 Portable Into 8-Ω Load
Internal Gain Control, Which Eliminates
External Gain-Setting Resistors
DC Volume Control From 20 dB to -40 dB
2.8-W/Ch Output Power Into a 3-Ω Load
PC-Beep Input
Depop Circuitry
Stereo Input MUX
Fully Differential Input
Low Supply Current and Shutdown Current
Surface-Mount Power Packaging 24-Pin
TSSOP PowerPAD™
PWP PACKAGE
(TOP VIEW)
GND
PCB ENABLE
VOLUME
LOUT+
LLINEIN
LHPIN
PVDD
RIN
LOUT–
LIN
BYPASS
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
RLINEIN
SHUTDOWN
ROUT+
RHPIN
VDD
PVDD
CLK
ROUT–
SE/BTL
PC-BEEP
GND
DESCRIPTION
The TPA0132 is a stereo audio power amplifier in a 24-pin TSSOP thermally enhanced package capable of
delivering 2.8 W of continuous RMS power per channel into 3-Ω loads.
This device minimizes the number of external components needed, which simplifies the design and frees up
board space for other features. When driving 1 W into 8-Ω speakers, the TPA0132 has less than 0.4% THD+N
across its specified frequency range. Included within this device is integrated depop circuitry that virtually
eliminates transients that cause noise in the speakers.
Amplifier gain is controlled by means of a dc voltage input on the VOLUME terminal. There are 31 discrete steps
covering the range of 20 dB (maximum volume setting) to -40 dB (minimum volume setting) in 2-dB steps. When
the VOLUME terminal exceeds 3.54 V, the device is muted. An internal input MUX allows two sets of stereo
inputs to the amplifier. In notebook applications, where internal speakers are driven as bridge-tied load (BTL) and
the line outputs (often headphone drive) are required to be single-ended (SE), the TPA0132 automatically
switches into SE mode when the SE/BTL input is activated, and this effectively reduces the gain by 6 dB.
The TPA0132 consumes only 10 mA of supply current during normal operation. A shutdown mode is included
that reduces the supply current to 150 µA.
The PowerPAD package (PWP) delivers a level of thermal performance that was previously achievable only in
TO-220-type packages. Thermal impedances of approximately 35°C/W are readily realized in multilayer PCB
applications. This allows the TPA0132 to operate at full power into 8-Ω loads at ambient temperatures of 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGED DEVICE
TSSOP (PWP) (1)
-40°C to 85°C
(1)
TPA0132PWP
The PWP package is available taped and reeled. To order a taped
and reeled part, add the suffix R to the part number (e.g.,
TPA0132PWPR).
FUNCTIONAL BLOCK DIAGRAM
RHPIN
RLINEIN
R
MUX
32-Step
Volume
Control
ROUT+
+
VOLUME
32-Step
Volume
Control
RIN
ROUTPC-BEEP
PCB ENABLE
SE/BTL
LHPIN
LLINEIN
+
PC
Beep
MUX
Control
L
MUX
Depop
Circuitry
32-Step
Volume
Control
Power
Management
PVDD
VDD
BYPASS
SHUTDOWN
GND
LOUT+
+
LIN
32-Step
Volume
Control
LOUT+
2
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BYPASS
11
CLK
17
I
If a 47-nF capacitor is attached, the TPA0132 generates an internal clock. An external clock can
override the internal clock input to this terminal.
GND
1, 12
13, 24
I
Ground connection for circuitry. Connected to thermal pad
LHPIN
6
I
Left channel headphone input, selected when SE/BTL is held high
LIN
10
I
Common left input for fully differential input. AC ground for single-ended inputs.
LLINEIN
5
I
Left channel line negative input, selected when SE/BTL is held low
LOUT+
4
O
Left channel positive output in BTL mode and positive output in SE mode
LOUT-
9
O
Left channel negative output in BTL mode and high-impedance in SE mode
PCB ENABLE
2
I
If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP through
the amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier continues to
operate normally.
PC-BEEP
14
I
The input for PC-Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is
input to PC-BEEP or PCB ENABLE is high.
7, 18
I
Power supply for output stage
RHPIN
20
I
Right channel headphone input, selected when SE/BTL is held high
RIN
8
I
Common right input for fully differential input. AC ground for single-ended inputs.
RLINEIN
23
I
Right channel line input, selected when SE/BTL is held low
ROUT+
21
O
Right channel positive output in BTL mode and positive output in SE mode
ROUT-
16
O
Right channel negative output in BTL mode and high-impedance in SE mode
SE/BTL
15
I
Input and output MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output is
selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.
SHUTDOWN
22
I
When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown
mode.
VDD
19
I
Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest
performance.
VOLUME
3
I
VOLUME detects the dc level at the terminal and sets the gain for 31 discrete steps covering a range
of 20 dB to -40 dB for dc levels of 0.15 V to 3.54 V. When the dc level is over 3.54 V, the device is
muted.
PVDD
Tap to voltage divider for internal mid-supply bias generator
Thermal Pad
Connect to ground. Must be soldered down in all applications to properly secure device on PC board.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD
Input voltage, VI
Continuous total power dissipation
6V
-0.3 V to VDD 0.3 V
Internally limited (see Dissipation Rating Table)
Operating free-air temperature range, TA
-40°C to 85°C
Operating junction temperature range, TJ
-40°C to 150°C
Storage temperature range, Tstg
-65°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
DISSIPATION RATING TABLE
PACKAGE
TA≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
PWP
2.7 W (1)
21.8 mW/°C
1.7 W
1.4 W
(1)
See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(SLMA002), for more information on the PowerPAD™ package. The thermal data was measured on
a PCB layout based on the information in the section entitled Texas Instruments Recommended
Board for PowerPAD™ on page 33 of the before mentioned document.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VDD
MAX
4.5
5.5
SHUTDOWN
V
2
V
0.6 × VDD
PCB ENABLE
0.6 × VDD
SE/BTL
Low-level input voltage, VIL
UNIT
0.8 × VDD
SE/BTL
High-level input voltage, VIH
MIN
SHUTDOWN
0.8
V
0.4 × VDD
PCB ENABLE
Operating free-air temperature, TA
-40
85
°C
MAX
UNIT
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
|VOO|
Output offset voltage (measured differentially)
VI = 0 V, AV = 6 dB
PSRR
Power supply rejection ratio
VDD = 4.9 V to 5.1 V
High-level input current - SHUTDOWN, SE/BTL, VOLUME
VDD = 5.5 V, VI = VDD
900
nA
High-level input current - PCB ENABLE
VDD = 5.5 V, VI = VDD
125
µA
Low-level input current - SHUTDOWN, SE/BTL, VOLUME,
PCB ENABLE
VDD = 5.5 V, VI = 0 V
900
nA
|IIH|
|IIL|
IDD
IDD(SD)
Supply current
Supply current, shutdown mode
35
mV
67
dB
BTL mode, SHUTDOWN = 2 V,
SE/BTL = 0.6 × VDD
10
15
SE mode, SHUTDOWN = 2 V,
SE/BTL = 0.8 × VDD
5
7.5
150
300
mA
SHUTDOWN = 0 V, SE/BTL = 0 V
µA
OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 4 Ω , Gain = 2 V/V, BTL mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
W
THD = 1%
2.3
W
Output power
RL = 3 Ω, f = 1 kHz
THD+N
Total harmonic distortion plus noise
PO = 1 W, f = 20 Hz to 15 kHz
BOM
Maximum output power bandwidth
THD = 5%
4
TYP
2.8
PO
Vn
MIN
THD = 10%
0.4%
>15
Supply ripple rejection ratio
f = 1 kHz,
C(BYP) = 0.47 µF
BTL mode
-65
SE mode
-60
Noise output voltage
C(BYP) = 0.47 µF,
f = 20 Hz to 20 kHz
BTL mode
42
SE mode
44
kHz
dB
µVRMS
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output power
1, 4, 6, 8, 10
vs Voltage gain
2
THD+N
Total harmonic distortion plus noise
Vn
Output noise voltage
vs Frequency
13
Supply ripple rejection ratio
vs Frequency
14, 15
Crosstalk
vs Frequency
16, 17, 18
Shutdown attenuation
vs Frequency
19
Signal-to-noise ratio
vs Frequency
vs Frequency
3, 5, 7, 9, 11
vs Output voltage
SNR
12
20
Closed loop response
PO
21, 22
Output power
PD
Power dissipation
Zi
Input impedance
vs Load resistance
23, 24
vs Output power
25, 26
vs Ambient temperature
27
vs Gain
28
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
VOLTAGE GAIN
1%
THD+N -Total Harmonic Distortion + Noise
THD+N -Total Harmonic Distortion + Noise
10%
RL = 4 Ω
1%
RL = 8 Ω
RL = 3 Ω
0.1%
AV = 20 to 0 dB
f = 1 kHz
BTL
0.01%
0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
PO = 1 W for AV ≥ 6 dB
VO = 1 VRMS for AV ≤ 4 dB
RL = 8 Ω
BTL
0.1%
0.01%
-40
-30
-20
-10
0
PO - Output Power - W
A V - Voltage Gain - dB
Figure 1.
Figure 2.
10
20
5
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10%
RL = 3 Ω
AV = 20 to 0 dB
BTL
THD+N -Total Harmonic Distortion + Noise
THD+N -Total Harmonic Distortion + Noise
10%
1%
PO = 1 W
PO = 0.5 W
0.1%
PO = 1.75 W
0.01%
20
TOTAL HARMOINIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
0.1%
f = 20 Hz
RL = 3 Ω
AV = 20 to 0 dB
BTL
0.01%
0.01
f - Frequency - Hz
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
1k
10k 20k
10
10%
RL = 4 Ω
AV = 20 to 0 dB
BTL
1%
PO = 0.25 W
0.1%
PO = 1.5 W
PO = 1 W
0.01%
20
100
1k
f - Frequency - Hz
Figure 5.
10k 20k
THD+N -Total Harmonic Distortion + Noise
THD+N -Total Harmonic Distortion + Noise
f = 1 kHz
0.1
1
PO - Output Power - W
100
10%
6
f = 20 kHz
1%
RL = 4 Ω
AV = 20 to 0 dB
BTL
1%
f = 20 kHz
f = 1 kHz
0.1%
f = 20 Hz
0.01%
0.01
0.1
1
PO - Output Power - W
Figure 6.
10
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
10%
RL = 8 Ω
AV = 20 to 0 dB
BTL
THD+N -Total Harmonic Distortion + Noise
THD+N -Total Harmonic Distortion + Noise
10%
1%
PO = 0.25 W
0.1%
PO = 0.5 W
0.01%
20
PO = 1 W
1%
f = 20 kHz
f = 1 kHz
0.1%
f = 20 Hz
0.01%
0.01
f - Frequency - Hz
0.1
1
PO - Output Power - W
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
100
1k
10k 20k
THD+N -Total Harmonic Distortion + Noise
RL = 32 Ω
AV = 14 to 0 dB
SE
1%
0.1%
PO = 25 mW
0.01%
PO = 50 mW
0.001%
20
10
10%
10%
THD+N -Total Harmonic Distortion + Noise
RL = 8 Ω
AV = 20 to 0 dB
BTL
100
PO = 75 mW
1k
f - Frequency - Hz
Figure 9.
10k 20k
1%
f = 20 kHz
0.1%
f = 1 kHz
0.01%
0.01
f = 20 Hz
RL = 32 Ω
AV = 14 to 0 dB
SE
0.1
PO - Output Power - W
1
Figure 10.
7
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT VOLTAGE
10%
10%
THD+N -Total Harmonic Distortion + Noise
THD+N -Total Harmonic Distortion + Noise
RL = 10 kΩ
AV = 14 to 0 dB
SE
1%
0.1%
VO = 1 VRMS
0.01%
0.001%
20
1k
f = 1 kHz
0.01%
RL = 10 kΩ
AV = 14 to 0 dB
SE
10k 20k
0
f = 20 Hz
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f - Frequency - Hz
VO - Output Voltage - VRMS
Figure 11.
Figure 12.
OUTPUT NOISE VOLTAGE
vs
BANDWIDTH
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
1.8
2
0
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 4 Ω
140
Supply Ripple Rejection Ratio - dB
Vn − Output Noise Voltage − µV RMS
f = 20 kHz
0.1%
0.001%
100
160
120
100
AV = 20 dB
80
60
AV = 6 dB
40
20
0
RL = 8 Ω
C(BYP) = 0.47 µF
BTL
-20
AV = 20 dB
-40
-60
-80
AV = 6 dB
-100
-120
20
100
1k
BW − Bandwidth − Hz
Figure 13.
8
1%
10k 20k
20
100
1k
f - Frequency - Hz
Figure 14.
10k 20k
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
-40
RL = 32 Ω
C(BYP) = 0.47 µF
SE
-20
-60
-40
AV = 6 dB
-60
-80
-70
Left to Right
-80
-90
Right to Left
AV = 14 dB
-100
-100
-110
-120
-120
20
100
1k
f - Frequency - Hz
20
10k 20k
−50
−60
100
1k
10k 20k
f - Frequency - Hz
Figure 15.
Figure 16.
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
−40
PO = 1 W
RL = 8 Ω
AV = 6 dB
BTL
VO = 1 VRMS
RL = 10 kΩ
AV = 6 dB
SE
-20
-40
Crosstalk - dB
Crosstalk − dB
PO = 1 W
RL = 8 Ω
AV = 20 dB
BTL
-50
Crosstalk - dB
Supply Ripple Rejection Ratio - dB
0
−70
Left to Right
−80
−90
Right to Left
-60
Left to Right
-80
−100
Right to Left
-100
−110
−120
20
-120
100
1k
10k 20k
20
100
1k
f − Frequency − Hz
f - Frequency - Hz
Figure 17.
Figure 18.
10k 20k
9
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
SHUTDOWN ATTENUATION
vs
FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
FREQUENCY
0
120
PO = 1 W
RL = 8 Ω
BTL
VI = 1 VRMS
115
SNR − Signal-To-Noise Ratio − dB
RL = 10 kΩ, SE
-40
-60
RL = 32 Ω, SE
-80
-100
110
105
AV = 20 dB
100
95
90
AV = 6 dB
85
RL = 8 Ω, BTL
-120
20
100
1k
80
20
10k 20k
100
Figure 19.
Figure 20.
CLOSED LOOP RESPONSE
CLOSED LOOP RESPONSE
180°
RL = 8 Ω
AV = 20 dB
BTL
25
90°
5
Gain - dB
Phase
0°
10
RL = 8 Ω
AV = 6 dB
BTL
90°
20
15
Phase
180°
30
Gain
20
Gain - dB
10k 20k
f − Frequency − Hz
30
25
1k
f - Frequency - Hz
15
Phase
0°
10
5
Gain
-90°
0
-5
-5
-10
-180°
10
100
1k
10k
f - Frequency - Hz
Figure 21.
10
-90°
0
100k
1M
-10
-180°
10
100
1k
10k
f - Frequency - Hz
Figure 22.
100k
1M
Phase
Shutdown Attenuation - dB
-20
TPA0132
www.ti.com
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
3.5
1500
AV = 20 to 0 dB
BTL
1250
PO - Output Power - mW
PO - Output Power - W
3
AV = 14 to 0 dB
SE
2.5
2
10% THD+N
1.5
1
1000
750
500
10% THD+N
250
0.5
1% THD+N
1% THD+N
0
0
0
8
16
24
32
40
48
RL - Load Resistance - Ω
56
64
0
Figure 24.
POWER DISSIPATION
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
56
64
0.4
3Ω
1.6
0.35
1.4
PD - Power Dissipation - W
PD - Power Dissipation - W
16
24
32
40
48
RL - Load Resistance - Ω
Figure 23.
1.8
4Ω
1.2
1
0.8
0.6
8Ω
0.4
0.5
1
1.5
PO - Output Power - W
Figure 25.
2
4Ω
0.3
0.25
0.2
8Ω
0.15
0.1
32 Ω
f = 1 kHz
BTL
Each Channel
0.2
0
0
8
f = 1 kHz
SE
Each Channel
0.05
2.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
PO - Output Power - W
0.7
0.8
Figure 26.
11
TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
POWER DISSIPATION
vs
AMBIENT TEMPERATURE
INPUT IMPEDANCE
vs
GAIN
7
90
ΘJA4
PD - Power Dissipation - W
6
5
4
ΘJA3
3
ΘJA1,2
2
1
0
-40 -20
70
60
50
40
30
20
0
20 40 60 80 100 120 140 160
TA - Ambient Temperature - °C
Figure 27.
12
80
ZI − Input Impedance − kΩ
ΘJA1 = 45.9°C/W
ΘJA2 = 45.2°C/W
ΘJA3 = 31.2°C/W
ΘJA4 = 18.6°C/W
10
−40
−30
−20
−10
0
AV − Gain − dB
Figure 28.
10
20
TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
Volume Control Characteristics
Table 1. Typical DC Volume Control (1)
VOLUME (Terminal 3)
(1)
(2)
TYPICAL
GAIN of AMPLIFIER
(dB) (2)
VOLTAGE INCREASING
OR FIXED GAIN
(V)
VOLTAGE
DECREASING
(V)
0-0.27
0.16-0
20
0.28-0.37
0.28-0.17
18
0.38-0.48
0.39-0.29
16
0.49-0.58
0.50-0.40
14
0.59-0.69
0.61-0.51
12
0.70-0.80
0.72-0.62
10
0.81-0.91
0.84-0.73
8
0.92-1.02
0.95-0.85
6
1.03-1.13
1.06-0.96
4
1.14-1.24
1.17-1.07
2
1.25-1.35
1.29-1.18
0
1.36-1.46
1.40-1.30
-2
1.47-1.58
1.51-1.41
-4
1.59-1.68
1.62-1.52
-6
1.69-1.79
1.73-1.63
-8
1.80-1.90
1.84-1.74
-10
1.91-2.01
1.96-1.85
-12
2.02-2.12
2.06-1.97
-14
2.13-2.23
2.18-2.07
-16
2.24-2.34
2.29-2.19
-18
2.35-2.45
2.41-2.30
-20
2.46-2.56
2.52-2.42
-22
2.57-2.67
2.62-2.53
-24
2.68-2.78
2.74-2.63
-26
2.79-2.90
2.86-2.75
-28
2.91-3.01
2.97-2.87
-30
3.02-3.12
3.07-2.98
-32
3.13-3.23
3.19-3.08
-34
3.24-3.33
3.29-3.20
-36
3.34-3.44
3.40-3.30
-38
3.45-3.55
3.53-3.41
-40
3.56-5.00
5.00-3.54
-85
Each step is tested at its midpoint and characterized within ±4dB of the specified gain value for VDD =
5 V. For VDD = 4.5 V to 5.5 V, multiply values by 90% and 110%, respectively.
95% of the characterized values lie within ±0.5dB of the specified gain value. Figure 29 shows the
typical behavior of most devices.
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
GAIN HISTOGRAM AT 0 dB
100
Frequency of Occurance − %
90
80
70
60
50
40
30
20
10
Gain − dB
Figure 29. Typical Gain Variance
14
4
3
2
1
0
−1
−2
−3
−4
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION
COMPONENT SELECTION
Figure 30 and Figure 31 are schematic diagrams of typical notebook computer application circuits.
Right CIRHP
Head- 0.47 µF
phone
Input
20
Signal
CIRLINE
Right 0.47 µF
Line
Input
Signal
23
RHPIN
RLINEIN
R
MUX
32-Step
Volume
Control
+
8
RIN
CRIN
0.47 µF
PC-BEEP
14
Input
Signal CPCB
0.47 µF
VDD
Left CILHP
Head- 0.47 µF
phone
Input
Signal
CILLINE
Left 0.47 µF
Line
Input
Signal
COUTR
330 µF
PC-BEEP
+
PCBeep
CLIN
0.47 µF
ROUT-
16
VDD
1 kΩ
100 kΩ
3
17
VOLUME
15
SE/BTL
CLK
Gain/
MUX
Control
Depop
Circuitry
Power
Management
6
LHPIN
5
LLINEIN
10
21
32-Step
Volume
Control
50 kΩ
CCLK
47 nF
ROUT+
LIN
PVDD
18
VDD
19
BYPASS
SHUTDOWN
11
GND
L
MUX
32-Step
Volume
Control
See Note A
VDD
CSR
0.1 µF
VDD
CSR
0.1 µF
22
CBYP
0.47 µF
To
System
Control
+
LOUT+
4
+
LOUT-
9
1 kΩ
1, 12,
13, 24
COUTL
330 µF
32-Step
Volume
Control
100 kΩ
NOTE: A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 30. Typical TPA0132 Application Circuit Using Single-Ended Inputs and Input MUX
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
CIRHP−
0.47 µF
20
CIRIN−
0.47 µF
23
Right
Negative
Differential
Input Signal
Right
Positive
Differential
Input Signal
RHPIN
RLINEIN
R
MUX
32-Step
Volume
Control
−
CIRIN+
0.47 µF
8
PC-BEEP
Input
Signal
ROUT+
21
+
14
CPCB
0.47 µF 2
RIN
32-Step
Volume
Control
COUTR
330 µF
PC-BEEP
PCB
ENABLE
−
PCBeep
ROUT−
16
VDD
+
VDD
1 kΩ
100 kΩ
50 kΩ
3
VOLUME
17
CLK
15
SE/BTL
Gain/
MUX
Control
Depop
Circuitry
CCLK
47 nF
Power
Management
CILHP
0.47 µF
6
Left
Negative
Differential
Input Signal
Left
Positive
Differential
Input Signal
5
L
MUX
CILIN−
0.47 µF
VDD
19
BYPASS
SHUT−
DOWN
11
32-Step
Volume
Control
−
LOUT+
See Note A
VDD
CSR
0.1 µF
VDD
CSR
0.1 µF
22
CBYP
0.47 µF
To
System
Control
4
1 kΩ
1, 12,
13, 24
+
10
CILIN
0.47 µF
18
GND
LHPIN
LLINEIN
PVDD
LIN
COUTL
330 µF
32-Step
Volume
Control
−
LOUT−
9
+
100 kΩ
NOTE: A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 31. Typical TPA0132 Application Circuit Using Differential Inputs
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
VOLUME CONTROL OPERATION
The VOLUME pin controls the volume of the TPA0132. It is controlled with a dc voltage, which should not exceed
VDD. The gain voltages on the VOLUME pin are given in the Typical Characteristics section.
The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME
terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that
the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation of
the volume control can be found in Figure 32. The graph focuses on three gain steps with the trip points defined
in the first and second columns of the Typical DC Volume Control table. The dotted lines represent the hysteresis
about each gain step.
DC Volume Control Operation
2
Gain - dB
Increasing Voltage on
VOLUME Terminal
0
Decreasing Voltage on
VOLUME Terminal
-2
1.17
1.36
1.25
1.29
Voltage on VOLUME Pin - V
Figure 32.
INPUT RESISTANCE
The gain is set by varying the input resistance of the amplifier, which can range from its smallest value to over
six times that value. As a result, if a single capacitor is used in the input high pass filter, the –3 dB or cut-off
frequency also changes by over six times. Connecting an additional resistor from the input pin of the amplifier to
ground, as shown in Figure 33, reduces the cutoff-frequency variation.
Rf
C
IN
Input Signal
Ri
R
Figure 33. Resistor on Input for Cut-Off Frequency
The input resistance at each gain setting is given in the graph for Input Impedance vs Gain in the Typical
Characteristics section.
The –3-dB frequency can be calculated using Equation 1.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
ƒ–3 dB
1
2 CR R
i
(1)
To increase filter accuracy, increase the value of the capacitor and decrease the value of the resistor to ground.
In addition, the order of the filter can be increased.
INPUT CAPACITOR, Ci
In a typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined by Equation 2.
−3 dB
fc(highpass)
1
2 ZIN C i
fc
(2)
The value of Ci directly affects the bass (low frequency) performance of the circuit. Consider the example where
Zi is 55 kΩ and the specification calls for a flat bass response down to 30 Hz. Equation 2 is reconfigured as
Equation 3.
Ci
1
2 Zi f c
(3)
In this example, Ci is 72 nF, so one would likely choose a value in the range of 0.1 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high-gain applications. For this reason a low-leakage tantalum or ceramic
capacitor is the best choice. When polarized capacitors are used, connect the positive lead of the capacitor to
the amplifier input in most applications, as the dc level there is held at VDD/2, typically higher than the source dc
level. Note that it is important to confirm the capacitor polarity in the application.
POWER SUPPLY DECOUPLING, C(S)
This high-performance CMOS audio amplifier requires adequate power-supply decoupling to minimize output
total harmonic distortion (THD). Power-supply decoupling also prevents oscillations with long lead lengths
between the amplifier and the speaker. Optimum decoupling is achieved by using two capacitors of different
types that target different types of noise on the power-supply leads. To filter high-frequency transients, spikes, or
digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, placed
as close as possible to the device VDD lead, works best. For filtering low-frequency noise signals, an aluminum
electrolytic capacitor of 10 µF or greater placed near the audio power amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, C(BYP)
The midrail bypass capacitor, C(BYP), is the most critical capacitor and serves several important functions. During
startup or recovery from shutdown mode, C(BYP) determines the rate at which the amplifier starts up. The second
function is to reduce power-supply noise coupling into the output drive signal. This noise is from the midrail
generation circuit internal to the amplifier, and appears as degraded PSRR and THD+N.
Bypass capacitor (C(BYP)) values of 0.47-µF to 1-µF, and ceramic or tantalum low-ESR capacitors are
recommended for best THD and noise performance.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
OUTPUT COUPLING CAPACITOR, C(C)
In a typical single-supply SE configuration, an output coupling capacitor (C(C)) is required to block the dc bias at
the output of the amplifier to prevent dc currents in the load. As with the input coupling capacitor, the output
coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4.
−3 dB
fc(high)
1
2 RL C (C)
fc
(4)
The main disadvantage, from a performance standpoint, is that load impedances are typically small, driving the
low-frequency corner higher, degrading the bass response. Large values of C(C) are required to pass low
frequencies into the load. Consider the example where a C(C) of 330 µF is chosen and loads include 3 Ω, 4 Ω, 8
Ω, 32 Ω, 10 kΩ, and 47 kΩ. Table 2 summarizes the frequency response characteristics of each configuration.
Table 2. Common Load Impedances Vs Low Frequency
Output Characteristics in SE Mode
RL
C(C)
LOWEST FREQUENCY
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
60 Hz
8Ω
330 µF
32 Ω
330 µF
15 Hz
10,000 Ω
330 µF
0.05 Hz
47,000 Ω
330 µF
0.01 Hz
As Table 2 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate,
headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
BRIDGED-TIED LOAD VS SINGLE-ENDED MODE
Figure 34 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA0132 amplifier consists
of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this differential
drive configuration, but, initially consider power to the load. The differential drive to the speaker means that as
one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing
on the load as compared to a ground referenced load. Substituting 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 5).
V(rms)
Power
V O(PP)
2 2
V(rms)
2
RL
(5)
VDD
VO(PP)
RL
2x VO(PP)
VDD
−VO(PP)
Figure 34. Bridge-Tied Load Configuration
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power, this is a 6-dB improvement —
loudness that can be heard. In addition to increased power there are frequency-response concerns. Consider the
single-supply SE configuration shown in Figure 35. A coupling capacitor is required to block the dc offset voltage
from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF), so they tend to be
expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting the low-frequency
performance of the system. This frequency-limiting effect is due to the high-pass filter network created with the
speaker impedance and the coupling capacitance, and is calculated with Equation 6.
f(c)
1
2 RL C (C)
(6)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, eliminating the need for blocking capacitors. Low-frequency performance is
then limited only by the input network and speaker response. Cost and PCB space are also minimized by
eliminating the bulky coupling capacitor.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
VDD
−3 dB
VO(PP)
C(C)
RL
VO(PP)
fc
Figure 35. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable, since the BTL configuration produces 4× the output power of the SE configuration.
Internal dissipation versus output power is discussed further in the Crest Factor and Thermal Considerations
section.
Single-Ended Operation
In SE mode (see Figure 35), the load is driven from the primary amplifier output for each channel (LOUT+ and
ROUT+).
The amplifier switches to single-ended operation when the SE/BTL terminal is held high. This puts the negative
outputs in a high-impedance state, and reduces the amplifier's gain by 6 dB.
BTL AMPLIFIER EFFICIENCY
Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The two
components of the internal voltage drop are the headroom or dc voltage drop that varies inversely to output
power, and the sine wave nature of the output. The total voltage drop can be calculated by subtracting the RMS
value of the output voltage from VDD. The internal voltage drop multiplied by the RMS value of the supply current
(IDDrms) determines the internal power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency begins as the ratio of power from the power supply to the power
delivered to the load. To accurately calculate the RMS and average values of power in the load and in the
amplifier, the current and voltage waveforms must be understood (see Figure 36).
VO
IDD
IDD(avg)
V(LRMS)
Figure 36. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE application, the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. Therefore, RMS conversion factors are different. Keep
in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
Equation 7 and Equation 8 are the basis for calculating amplifier efficiency.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
Efficiency of a BTL amplifier
PL
PSUP
Where:
2
V Lrms 2
V
V
, and VLRMS P , therefore, P L P
RL
2 RL
2
PL
and PSUP V DD IDDavg
IDDavg 1
and
2V P
VP
VP
1
[
cos(t)] 0
sin(t) dt
RL
RL
RL
0
Therefore,
PSUP
2 V DD VP
RL
substituting PL and PSUP into equation 7,
2
Efficiency of a BTL amplifier
Where:
VP
VP
2 RL
2 VDD V P
RL
VP
4 V DD
2 P L RL
(7)
Therefore,
BTL
2 P L RL
4 VDD
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
(8)
Table 3 employs Equation 8 to calculate efficiencies for four different output-power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half-power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, the maximum draw
on the power supply is almost 3.25 W.
Table 3. Efficiency vs Output Power in 5-V, 8-Ω BTL Systems
OUTPUT POWER (W)
EFFICIENCY
(%)
PEAK VOLTAGE (V)
INTERNAL DISSIPATION (W)
0.25
31.4
2.00
0.55
0.50
44.4
2.83
0.62
1.00
62.8
4.00
0.59
1.25
70.2
4.47 (1)
0.53
(1)
High peak voltages cause the THD to increase.
Table 3 employs Equation 8 to calculate efficiencies for four different output-power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half-power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, the maximum draw
on the power supply is almost 3.25 W.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
CREST FACTOR AND THERMAL CONSIDERATIONS
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom, above the average
power output, to pass the loudest portions of the signal without distortion. In other words, music typically has a
crest factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. From the data sheet, one can see that when
the device is operating from a 5-V supply into a 3-Ω speaker that 4-W peaks are available. Use Equation 9 to
convert watts to dB.
P
P dB 10Log W 10Log 4 W 6 dB
1W
P ref
(9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
6 dB - 15 dB = -9 dB (15-dB crest factor)
6 dB - 12 dB = -6 dB (12-dB crest factor)
6 dB - 9 dB = -3 dB (9-dB crest factor)
6 dB - 6 dB = 0 dB (6-dB crest factor)
6 dB - 3 dB = 3 dB (3-dB crest factor)
Converting dB back into watts:
PW = 10PdB/10× Pref
= 63 mW (18-dB crest factor)
= 125 mW (15-dB crest factor)
= 250 mW (9-dB crest factor)
= 500 mW (6-dB crest factor)
= 1000 mW (3-dB crest factor)
= 2000 mW (0-dB crest factor)
This is valuable information to consider when estimating the heat-dissipation requirements for the amplifier
system. Comparing the worst case, 2 W of continuous power output with a 3-dB crest factor, against 12-dB and
15-dB applications, drastically affects maximum ambient temperature ratings for the system. Using the power
dissipation curves for a 5-V, 3-Ω system, the internal dissipation and maximum ambient temperatures are shown
in the table below.
Table 4. TPA0132 Power Rating, 5-V, 3-Ω Stereo
PEAK OUTPUT POWER
(W)
(1)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE
4
2 W (3 dB)
1.7
-3°C
4
1000 mW (6 dB)
1.6
6°C
4
500 mW (9 dB)
1.3
24°C
4
250 mW (12 dB)
1.0
51°C
4
125 mW (15 dB)
0.9
78°C
4
63 mW (18 dB)
0.6
85°C (1)
Package limited to 85°C ambient
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
Table 5. TPA0132 Power Rating, 5-V, 8-Ω Stereo
(1)
PEAK OUTPUT POWER
(W)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE (1)
2.5
1250 mW (3-dB crest factor)
0.53
85°C (1)
2.5
1000 mW (4-dB crest factor)
0.59
85°C (1)
2.5
500 mW (7-dB crest factor)
0.62
85°C (1)
2.5
250 mW (10-dB crest factor)
0.55
85°C (1)
Package limited to 85°C ambient
The maximum dissipated power (PDmax) is reached at a much lower output power level for a 3-Ω load than for an
8-Ω load. As a result, the formula in Equation 10for calculating PDmax may be used for a 3-Ω application:
2V2
DD
P Dmax
2R L
(10)
However, in the case of an 8-Ω load, the PDmax occurs at a point well above the normal operating power level.
The amplifier may therefore be operated at a higher ambient temperature than required by the PDmax formula for
an 8-Ω load, but do not exceed the maximum ambient temperature of 85°.
The maximum ambient temperature depends on the heatsinking ability of the PCB system. The derating factor
for the PWP package is shown in the dissipation rating table. Converting this to θJA:
1
1
θ JA
45°CW
0.022
Derating Factor
(11)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are
per-channel, so the dissipated heat is doubled for two-channel operation. Given θJA, the maximum allowable
junction temperature, and the total internal dissipation, the maximum ambient temperature can be calculated
using Equation 12. The maximum recommended junction temperature for the device is 150°C. The internal
dissipation figures are taken from the Power Dissipation vs Output Power graphs.
T A Max T J Max θJA P D
150 45(0.6 2) 96°C (15-dB crest factor)
(12)
NOTE:
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per
channel.
Due to package limitiations, the actual TAMAX is 85°C.
The power rating tables show that for some applications, no airflow is required to keep junction temperatures in
the specified range. The internal thermal protection turns the device off at junction temperatures higher than
150°C to prevent damage to the IC. The power rating tables in this section were calculated for maximum
listening volume without distortion. When the output level is reduced the numbers in the table change
significantly. Also, using 8-Ω speakers dramatically increases the thermal performance by increasing amplifier
efficiency.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
SE/BTL OPERATION
The ability of the TPA0132 to easily switch between BTL and SE modes is one of its most important cost-saving
features. This feature eliminates the requirement for an additional headphone amplifier in applications where
internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated.
Two separate internal amplifiers drive OUT+ and OUT–. The SE/BTL input controls the operation of the follower
amplifier that drives LOUT– and ROUT–. When SE/BTL is held low, the amplifier is on and the device is in the
BTL mode. When SE/BTL is held high, the OUT– amplifiers are in a high output-impedance state, which
configures the device outputs as SE drivers from LOUT+ and ROUT+. IDD is reduced by approximately one-half
in SE mode. Control of the SE/BTL input can be from a logic-level CMOS source or, more typically, from a
resistor-divider network as shown in Figure 37.
20
23
RHPIN
RLINEIN
32-Step
Volume
Control
R
MUX
−
+
8
RIN
ROUT+
21
32-Step
Volume
Control
VDD
−
+
ROUT−
16
100 kΩ
SE/BTL
COUTR
330 µF
15
1 kΩ
100 kΩ
Figure 37. TPA0132 Resistor Divider Network Circuit
Using a readily-available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is
inserted. When closed, the 100-kΩ/1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ
resistor is disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT– amplifier is
shut down, muting the speaker (virtually open-circuits the speaker). The OUT+ amplifier then drives through the
output capacitor (CO) into the headphone jack.
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TPA0132
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SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
PC-BEEP OPERATION
The PC-BEEP input allows a system beep to be sent directly from a computer through the amplifier to the
speakers with few external components. The input is activated automatically. When the PC-BEEP input is active,
both LINEIN and HPIN inputs are deselected, and both the left and right channels are driven in BTL mode with
the signal from PC-BEEP. The gain from the PC-BEEP input to the speakers is fixed at 0.3 V/V and is
independent of the volume setting. When the PC-BEEP input is deselected, the amplifier returns to the previous
operating mode and volume setting. Furthermore, if the amplifier is in shutdown mode, activating PC-BEEP takes
the device out of shutdown, outputs the PC-BEEP signal, then returns the amplifier to shutdown mode.
When PCB ENABLE is held low, the amplifier automatically switches to PC-BEEP mode after detecting a valid
signal at the PC-BEEP input. The preferred input signal is a square wave or pulse train. To be accurately
detected, the signal must have a minimum of 1.5-Vpp amplitude, rise and fall times of less than 0.1 µs and a
minimum of eight rising edges. When the signal is no longer detected, the amplifier returns to its previous
operating mode and volume setting.
To ac-couple the PC-BEEP input, choose a coupling-capacitor value to satisfy Equation 13.
C
PCB
2 ƒ
1
(100 k)
PCB
(13)
The PC-BEEP input can also be dc-coupled to avoid using this coupling capacitor. The pin normally rests at
midrail when no signal is present.
INPUT MUX OPERATION
Right
Headphone
Input Signal
CIRHP
0.47 µF
20
Right Line
Input Signal
CIRLINE
0.47 µF
23
8
CRIN
0.47 µF
RHPIN
RLINEIN
RIN
32-Step
Volume
Control
R
MUX
−
+
ROUT+
21
−
+
ROUT−
16
32-Step
Volume
Control
Figure 38. TPA0132 Example Input MUX Circuit
The input MUX provides the user with a means to select from two different audio sources. In BTL mode, the
LINE inputs are selected. In SE mode, the HP inputs are selected. RIN and LIN must be grounded in SE mode.
26
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA0132PWP
ACTIVE
HTSSOP
PWP
24
60
None
CU NIPDAU
Level-1-220C-UNLIM
TPA0132PWPR
ACTIVE
HTSSOP
PWP
24
2000
None
CU NIPDAU
Level-1-220C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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