TPA3100D2-Q1
QFN
www.ti.com ......................................................................................................................................................................................... SLOS557 – SEPTEMBER 2008
20-W STEREO CLASS-D AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
20 W/Channel Into an 8-Ω Load From
an 18-V Supply
10 W/Channel Into an 8-Ω Load From
a 12-V Supply
15 W/Channel Into an 4-Ω Load From
a 12-V Supply
Operates From 10 V to 26 V
92% Efficient Class-D Operation Eliminates
Need for Heat Sinks
Four Selectable Fixed-Gain Settings
Differential Inputs
Thermal and Short-Circuit Protection With
Auto-Recovery Feature
Clock Output for Synchronization With
Multiple Class-D Devices
Surface Mount 7-mm × 7-mm 48-pin QFN
(RGZ) Package
Televisions
DESCRIPTION
The TPA3100D2 is a 20-W per channel, efficient,
class-D audio power amplifier for driving bridged-tied
stereo speakers. The TPA3100D2 can drive stereo
speakers as low as 4 Ω. The high efficiency of the
TPA3100D2, 92%, eliminates the need for an
external heat sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20 dB, 26 dB,
32 dB, or 36 dB.
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts with an
auto-recovery feature and monitor output.
Simplified Application Circuit
1 mF
RINP
1 mF
RINN
TV Audio
Processor
0.22 mF
TPA3100D2
1 mF
LINN
1 mF
BSRN
ROUTN
ROUTP
BSRP
LINP
Shutdown
Control
Mute Control
Gain Select
PGNDR
10 nF
VREG
MUTE
GAIN0
MSTR/SLV
Sync Control
SYNC
10 V to 26 V
1 mF
SHUTDOWN
FAULT
PVCCR
PVCCL
AVCC
AGND
1 mF
VBYP
ROSC
100 kW
GAIN1
Fault Flag
0.22 mF
VCLAMPR
BSLN
LOUTN
0.22 mF
LOUTP
BSLP
VCLAMPL
PGNDL
0.22 mF
1 mF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPA3100D2-Q1
SLOS557 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
QFN – RGZ
ORDERABLE PART NUMBER
Reel of 2500
TOP-SIDE MARKING
TPA3100D2IRGZRQ1
TPA3100D2I
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range
VI
Input voltage range
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
SYNC
–0.3 V to VREG + 0.5 V
Continuous total power dissipation
See Dissipation Ratings Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range (2)
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
RLoad
Human-Body Model
Electrostatic discharge
Machine Model
(4)
(3)
(2)
(3)
(4)
(5)
(all pins)
2 kV
(all pins)
Charged-Device Model
(1)
260°C
3.2 Ω Minimum
Load resistance
(5)
150 V
(all pins)
750 V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Brief SLMA002 for more information about using the thermal pad.
In accordance with AEC Q100, Test method Q100-002
In accordance with AEC Q100, Test method Q100-003
In accordance with AEC Q100, Test method Q100-011
TYPICAL DISSIPATION RATINGS
(1)
2
PACKAGE
POWER RATING
TA ≤ 25°C
DERATING FACTOR
TA > 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
48-pin RGZ (QFN)
4.63 W
37 mW/°C (1)
2.96 W
2.41 W
This data was taken using 1-oz trace and copper pad that is soldered directly to a JEDEC standard high-K PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Brief SLMA002 for more information about using the thermal
pad.
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TPA3100D2-Q1
www.ti.com ......................................................................................................................................................................................... SLOS557 – SEPTEMBER 2008
RECOMMENDED OPERATING CONDITIONS
VCC
MIN
MAX
10
26
Supply voltage
PVCC, AVCC
VIH
High-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
VIL
Low-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
0.8
SHUTDOWN, VI = VCC, VCC = 24 V
125
IIH
High-level input current
2
UNIT
V
V
MUTE, VI = VCC, VCC = 24 V
75
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG,
VCC = 24 V
2
SHUTDOWN, VI = 0, VCC = 24 V
2
IIL
Low-level input current
SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV,
VI = 0 V, VCC = 24 V
1
VOH
High-level output voltage
FAULT, IOH = 1 mA
VOL
Low-level output voltage
FAULT, IOL = –1 mA
fOSC
Oscillator frequency
Rosc resistor = 100 kΩ, MSTR/SLV = 2 V
TA
Operating free-air temperature
VREG – 0.6
V
µA
µA
V
AGND + 0.4
V
200
300
kHz
–40
85
°C
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Class-D output offset voltage
(measured differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load, VCC = 10 V to 26 V
DC power-supply rejection ratio
VCC = 12 V to 24 V, inputs ac coupled to AGND,
Gain = 36 dB
–70
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, No load, filter,
or snubber
22
26.5
ICC(SD)
Quiescent supply current in shutdown mode
SHUTDOWN = 0.8 V, No load, filter, or snubber
180
250
µA
ICC(MUTE)
Quiescent supply current in mute mode
MUTE = 2 V, No load, filter, or snubber
8
10
mA
rDS(on)
Drain-source on-state resistance
VCC = 12 V, IO = 500 mA,
TJ = 25°C
| VOS |
PSRR
ICC
5
50
1.1
1.25
1.45
V
3.75
4
4.25
V
High side
200
Low side
200
Total
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
Gain matching
Between channels
tON
Turn-on time
tOFF
Turn-off time
Copyright © 2008, Texas Instruments Incorporated
mV
dB
mA
mΩ
400
500
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
2
%
C(VBYP) = 1 µF, SHUTDOWN = 2 V
25
ms
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
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DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Class-D output offset voltage
(measured differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, No load
4-V internal supply voltage
VREG, No load
PSRR
DC power-supply rejection ratio
VCC = 12 V to 24 V, Inputs ac-coupled to AGND,
Gain = 36 dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V,
No load, filter, or snubber
18
22.5
mA
ICC(SD)
Quiescent supply current in shutdown mode
SHUTDOWN = 0.8 V, No load, filter, or snubber
80
200
µA
ICC(MUTE)
Quiescent supply current in mute mode
MUTE = 2 V, no load, filter, or snubber
7
9
mA
| VOS |
rDS(on)
Drain-source on-state resistance
VCC = 12 V, IO = 500 mA,
TJ = 25°C
5
50
1.1
1.25
1.45
V
3.75
4
4.25
V
-70
High side
200
Low side
200
Total
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
mV
dB
mΩ
400
500
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
KSVR
Supply ripple rejection
PO
Continuous output power
THD+N
Total harmonic distortion + noise
Vn
SNR
MIN
TYP
MAX
UNIT
200-mVPP ripple from 20 Hz to 1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
–70
THD+N = 7%, f = 1 kHz, VCC = 18 V
20.6
THD+N = 10%, f = 1 kHz, VCC = 18 V
21.8
VCC = 18 V, f = 1 kHz, PO = 10 W (half power)
0.11
%
100
µV
–80
dBV
dB
W
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–92
dB
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
102
dB
150
°C
30
°C
Thermal trip point
Thermal hysteresis
4
TEST CONDITIONS
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TPA3100D2-Q1
www.ti.com ......................................................................................................................................................................................... SLOS557 – SEPTEMBER 2008
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
KSVR
PO
Supply ripple rejection
Continuous output power
TEST CONDITIONS
MIN
–70
THD+N = 7%, f = 1 kHz
9.4
THD+N = 10%, f = 1 kHz
15.6
THD+N = 10%, f = 1 kHz, RL = 4 Ω
16.4
RL = 8 Ω, f = 1 kHz, PO = 5 W (half power)
0.11
RL = 4 Ω, f = 1 kHz, PO = 8 W (half power)
0.15
Total harmonic distortion + noise
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
Po = 1 W, Gain = 20 dB, f = 1 kHz
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
Thermal trip point
Thermal hysteresis
Copyright © 2008, Texas Instruments Incorporated
MAX
10
THD+N = 7%, f = 1 kHz, RL = 4 Ω
THD+N
SNR
TYP
200-mVPP ripple from 20 Hz to 1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
UNIT
dB
W
%
100
µV
–80
dBV
–94
dB
98
dB
150
°C
30
°C
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AVCC
NC
FAULT
MUTE
SHUTDOWN
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
NC
48 PIN, QFN PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
NC
RINN
RINP
AGND
LINP
LINN
NC
GAIN0
GAIN1
MSTR/SLV
SYNC
NC
1
36
2
35
3
34
4
33
5
6
7
32
Exposed
Thermal Pad
31
30
8
29
9
28
10
27
11
26
12
25
NC
PVCCR
PVCCR
PGNDR
PGNDR
VCLAMPR
VCLAMPL
PGNDL
PGNDL
PVCCL
PVCCL
NC
NC
ROSC
VREG
VBYP
AGND
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
NC
13 14 15 16 17 18 19 20 21 22 23 24
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
4, 17
AVCC
48
BSLN
23
I/O
Bootstrap I/O for left channel, negative high-side FET
BSLP
18
I/O
Bootstrap I/O for left channel, positive high-side FET
BSRN
38
I/O
Bootstrap I/O for right channel, negative high-side FET
BSRP
43
I/O
Bootstrap I/O for right channel, positive high-side FET
FAULT
46
O
TTL-compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit
faults. Thermal faults are not reported on this terminal.
GAIN0
8
I
Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1
9
I
Gain select most significant bit. TTL logic levels with compliance to VREG.
LINN
6
I
Negative audio input for left channel. Biased at VREG/2
LINP
5
I
Positive audio input for left channel. Biased at VREG/2
LOUTN
21, 22
O
Class-D 1/2-H-bridge negative output for left channel
LOUTP
19, 20
O
Class-D 1/2-H-bridge positive output for left channel
MSTR/SLV
10
I
Master/slave select for determining direction of SYNC terminal. High = master mode, SYNC
terminal is an output; low = slave mode, SYNC terminal accepts a clock input. TTL logic
levels with compliance to VREG.
MUTE
45
I
Mute signal for quick disable/enable of outputs (high = outputs high-Z, low = outputs
enabled). TTL logic levels with compliance to AVCC.
Analog ground for digital/analog cells in core.
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL.
GND
NC
Ground. Connect to the thermal pad.
1, 7, 12, 13,
24, 25, 36,
37, 47
No internal connection
PGNDL
28, 29
Power ground for left channel H-bridge
PGNDR
32, 33
Power ground for right channel H-bridge
PVCCL
26, 27
Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
PVCCR
34, 35
Power supply for right channel H-bridge, not connected to PVCCL or AVCC
RINN
6
2
I
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Negative audio input for right channel. Biased at VREG/2.
Copyright © 2008, Texas Instruments Incorporated
TPA3100D2-Q1
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
RINP
3
I
ROSC
14
I/O
I/O for current setting resistor of ramp generator
ROUTN
39, 40
O
Class-D 1/2-H-bridge negative output for right channel
ROUTP
41, 42
O
Class-D 1/2-H-bridge positive output for right channel
SHUTDOWN
44
I
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with
compliance to AVCC.
SYNC
11
I/O
Clock input/output for synchronizing multiple class-D devices. Direction determined by
MSTR/SLV terminal. Input signal not to exceed VREG.
VBYP
16
O
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external
capacitor sizing.
VCLAMPL
30
Internally generated voltage supply for left channel bootstrap capacitor
VCLAMPR
31
Internally generated voltage supply for right channel bootstrap capacitor
VREG
15
O
Thermal Pad
Copyright © 2008, Texas Instruments Incorporated
Positive audio input for right channel. Biased at VREG/2.
4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins only. Not
specified for driving other external circuitry.
Connect to AGND and PGND. Should be star point for both grounds. Internal resistive
connection to AGND and PGND. Thermal vias on the PCB should connect this pad to a
large copper area on an internal or bottom layer for the best thermal performance. The
Thermal Pad must be soldered to the PCB for mechanical reliability.
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FUNCTIONAL BLOCK DIAGRAM
PVCCR
PVCCR
VCLAMPR
PVCCR
VBYP
BSRN
VBYP
AVCC
AVCC
Gain
RINN
Gate
Drive
Gain
Control
RINP
ROUTN
VClamp
Gen
PWM
Logic
PVCCR
VBYP
GAIN0
GAIN1
BSRP
Gain
Control
8
Gate
Drive
To Gain Adj.
Blocks and
Startup Logic
ROUTP
Gain
FAULT
PGNDR
SC
Detect
VBYP AVCC
Thermal
ROSC
VREG
Ramp
Generator
SYNC
Startup
Protection
Logic
Biases
and
References
MSTR/SLV
VREGok
PVCCL
AVCC
PVCCL
VCCok
VREG
VREG
4V Reg
PVCCL
SHUTDOWN
TLL Input
Buffer
(VCC Compliant)
MUTE
TLL Input
Buffer
(VCC Compliant)
BSLN
Gate
Drive
Gain
LINP
Gain
Control
Gain
AGND
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PVCCL
BSLP
PWM
Logic
Gate
Drive
8
LOUTN
VClamp
Gen
VBYP
LINN
VCLAMPL
LOUTP
PGNDL
Copyright © 2008, Texas Instruments Incorporated
TPA3100D2-Q1
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS (1)
FIGURE
THD+N
VCC
kSVR
(1)
Total harmonic distortion + noise
vs Frequency
1, 2, 3, 4
vs Output power
5, 6, 7, 8
Closed-loop response
vs Frequency
9, 10
Output power
vs Supply voltage
11. 12
Efficiency
vs Output power
13, 14
Supply current
vs Total output power
15, 16
Crosstalk
vs Frequency
17, 18
Supply ripple rejection ratio
vs Frequency
19, 20
All graphs were measured using the TPA3100D2 EVM.
Copyright © 2008, Texas Instruments Incorporated
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 12 V,
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 8 W,
Gain = 20 dB
1
PO = 5 W
0.1
PO = 2.5 W
PO = 0.5 W
0.01
0.005
0.003
20
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
100
1k
f - Frequency - Hz
Figure 1.
10k 20k
RL = 8 W,
Gain = 20 dB
1
PO = 10 W
0.1
PO = 5 W
0.01
0.005
0.003
20
1
PO = 10 W
0.1
PO = 5 W
PO = 1 W
100
1k
f - Frequency - Hz
Figure 3.
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
RL = 8 W,
Gain = 20 dB
0.005
0.003
20
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100
1k
f - Frequency - Hz
10k 20k
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 24 V,
0.01
PO = 1 W
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 18 V,
10k 20k
VCC = 12 V,
RL = 4 W,
Gain = 20 dB
PO = 5 W
1
PO = 10 W
0.1
PO = 1 W
0.01
0.005
0.003
20
100
1k
f - Frequency - Hz
10k 20k
Figure 4.
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THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 12 V,
RL = 8 W,
Gain = 32 dB
1
10 kHz
0.1
0.05
1 kHz
0.02
20 Hz
0.01
10m
100m 200m
1
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N - Total Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10 V = 18 V,
CC
RL = 8 W,
Gain = 32 dB
1
10 kHz
0.1
0.05
1 kHz
20 Hz
0.02
0.01
10m
10 20 40
100m 200m
PO - Output Power - W
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 24 V,
RL = 8 W,
Gain = 32 dB
1
10 kHz
0.1
0.05
1 kHz
20 Hz
0.02
0.01
10m
10 20 40
Figure 5.
100m 200m
1
PO - Output Power - W
Figure 7.
Copyright © 2008, Texas Instruments Incorporated
10 20 40
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
1
PO - Output Power - W
VCC = 12 V,
RL = 4 W,
Gain = 32 dB
1
10 kHz
0.1
1 kHz
0.05
20 kHz
0.02
0.01
10m
100m 200m
1
10 20 40
PO - Output Power - W
Figure 8.
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CLOSED LOOP RESPONSE
vs
FREQUENCY
CLOSED LOOP RESPONSE
vs
FREQUENCY
30
Gain − dB
25
40
150
35
100
30
50
25
Phase
20
0
15
10
5
RL = 8 W
VI = 0.1 Vrms
−100
10
CI = 10 mF
Gain = 32 dB
RC Filter = 100 W, 10 nF
−150
5
−200
100k
0
10
100
1k
10k
100
50
0
−50
VCC = 24 V
RL = 8 W
VI = 0.1 Vrms
−100
CI = 10 mF
Gain = 32 dB
RC Filter = 100 W, 10 nF
−150
10
100
f − Frequency − Hz
1k
−200
100k
10k
f − Frequency − Hz
Figure 9.
Figure 10.
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
35
50
45
150
20
15
0
Gain
Phase
−50
VCC = 12 V
200
Phase − °
Gain
35
200
Phase − °
Gain − dB
40
RL = 8 W
Gain = 20 dB
RL = 4 W
Gain = 20 dB
30
PO − Output Power − W
PO − Output Power − W
40
35
30
25
THD+N = 10%
20
THD+N = 1%
15
25
THD+N = 10%
20
15
THD+N = 1%
10
10
Power Represented by
Dash Lines May Require
More Heatsinking.
5
0
10
12
14
16
18
20
22
VCC - Supply Voltage - V
Figure 11.
12
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24
26
Power Represented by
Dash Lines May Require
More Heatsinking.
5
28
0
10
11
12
13
14
15
16
VCC − Supply Voltage − V
Figure 12.
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TPA3100D2-Q1
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EFFICIENCY
vs
OUTPUT POWER
100
100
VCC = 12 V
90
90
80
80
VCC = 18 V
60
VCC = 24 V
50
VCC = 12 V
70
Efficiency − %
70
Efficiency − %
EFFICIENCY
vs
OUTPUT POWER
40
60
50
40
30
30
20
20
RL = 8 W
Gain = 32 dB
10
RL = 4 Ω
Gain = 32 dB
10
0
0
0
2
4
6
8
10
12
14
16
18
0
20
2
4
6
8
10
12
14 15
PO − Output Power (Per Channel) − W
Figure 14.
PO − Output Power (Per Channel) − W
Figure 13.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
2.5
3.5
RL = 8 Ω
Gain = 20 dB
VCC = 18 V
RL = 4 Ω
Gain = 20 dB
3
ICC − Supply Current − A
ICC − Supply Current − A
2
VCC = 12 V
1.5
VCC = 24 V
1
2.5
VCC = 12 V
2
1.5
1
0.5
Power Represented by
Dash Lines May Require
More Heatsinking.
0
0
10
20
30
PO − Total Output Power − W
Figure 15.
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Power Represented by
Dash Lines May Require
More Heatsinking.
0.5
40
0
0
10
20
30
40
PO − Total Output Power − W
Figure 16.
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CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
-40
-40
−60
VCC = 12 V
RL = 8 Ω
Gain = 20 dB
VO = 1 Vrms
−60
VCC = 24 V
RL = 8 Ω
Gain = 20 dB
VO = 1 Vrms
L to R
−80
R to L
−100
Crosstalk − dB
Crosstalk − dB
L to R
R to L
−100
−120
−120
−140
20
−80
100
1k
−140
20
10k 20k
100
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
VCC = 12 V
RL = 8 Ω
Gain = 20 dB
V(RIPPLE) = 200 mVPP
kSVR − Supply Ripple Rejection Ratio − dB
kSVR − Supply Ripple Rejection Ratio − dB
−20
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
f − Frequency − Hz
Figure 19.
14
10k 20k
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
−10
1k
f − Frequency − Hz
Figure 18.
f − Frequency − Hz
Figure 17.
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10k 20k
−10
−20
VCC = 18 V
RL = 8 Ω
Gain = 20 dB
V(RIPPLE) = 200 mVPP
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
10k 20k
f − Frequency − Hz
Figure 20.
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TPA3100D2-Q1
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Fault Output
Shutdown
and Mute
Control
APPLICATION INFORMATION
33 mH
1 nF
1 mF
20 W
8W
1 mF
1 nF
33 mH
20 W
10 V - 26 V
220nF
220nF
10 mF
Differential
Analog
Inputs
NC
BSRN
ROUTN
ROUTN
ROUTP
BSRP
ROUTP
MUTE
RINN
SHUTDOWN
1 mF
NC
NC
FAULT
AVCC
1 mF
NC
10 V - 26 V
1 mF
PVCCR
RINP
PVCCR
AGND
PGNDR
LINP
PGNDR
220 mF
1 mF
1 mF
1 mF
VCLAMPR
TPA3100D2
100 kW
BSLN
BSLP
NC
LOUTN
PVCCL
LOUTN
SYNC
LOUTP
PVCCL
LOUTP
MSTR/SLV
AGND
PGNDL
VBYP
GAIN1
VREG
PGNDL
NC
Synchronize Multiple
Class-D Devices
GAIN0
ROSC
4-Step
Gain Control
1 mF
VCLAMPL
NC
NC
1 mF
LINN
NC
220 mF
1 mF
10 V - 26 V
220nF
220nF
1 nF
10 nF
20 W
1 mF
1 nF
33 mH
1 mF
8W
20 W
33 mH
1 mF
Figure 21. Stereo Class-D With Differential Inputs (QFN)
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Control
Fault Output
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1 nF
33 mH
1 mF
20 W
8W
1 mF
1 nF
33 mH
20 W
10 V - 26 V
220nF
220nF
10 mF
Single-Ended
Analog
Inputs
NC
BSRN
ROUTN
ROUTN
ROUTP
BSRP
ROUTP
MUTE
RINN
SHUTDOWN
1 mF
NC
NC
FAULT
AVCC
1 mF
NC
10 V - 26 V
1 mF
PVCCR
RINP
PVCCR
AGND
PGNDR
LINP
PGNDR
220 mF
1 mF
1 mF
1 mF
LINN
VCLAMPR
TPA3100D2
BSLN
LOUTN
BSLP
100 kW
LOUTN
PVCCL
NC
LOUTP
SYNC
LOUTP
PVCCL
VBYP
PGNDL
MSTR/SLV
AGND
GAIN1
VREG
PGNDL
NC
Synchronize Multiple
Class-D Devices
GAIN0
ROSC
4-Step
Gain Control
1 mF
VCLAMPL
NC
NC
1 mF
NC
220 mF
1 mF
10 V - 26 V
220nF
220nF
1 nF
10 nF
20 W
1 mF
1 nF
33 mH
1 mF
8W
20 W
33 mH
1 mF
Figure 22. Stereo Class-D With Single-Ended Inputs (QFN)
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Class-D Operation
This section focuses on the class-D operation of the TPA3100D2.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output in
which each output is 180° out of phase and changes from ground to the supply voltage, VCC. Therefore, the
differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V
across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 23. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and, thus, causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
-12 V
Current
Figure 23. Traditional Class-D Modulation Scheme Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3100D2 Modulation Scheme
The TPA3100D2 uses a modulation scheme that still has each output switching from 0 V to the supply voltage.
However, OUTP and OUTN are in phase with each other with no input. The duty cycle of OUTP is greater than
50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load stays at 0 V throughout
most of the switching period, greatly reducing the switching current, which reduces I2R losses in the load.
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
-12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output > 0 V
+12 V
0V
-12 V
Current
Figure 24. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3100D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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When to Use an Output Filter for EMI Suppression
Design the TPA3100D2 without the filter if the traces from amplifier to speaker are short (
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