TPA6135A2
www.ti.com .................................................................................................................................................. SLOS623A – FEBRUARY 2009 – REVISED APRIL 2009
DIRECTPATH™ Stereo Headphone Amplifier
With Differential Input and HI-Z Mode
FEATURES
1
• Patented DirectPath™ Technology Eliminates
Need for DC-Blocking Capacitors
– Outputs Biased at 0 V
– Excellent Low Frequency Fidelity
• Active Click and Pop Suppression
• HI-Z Output Mode
• 2.1 mA Typical Supply Current
• Fully Differential or Single-Ended Inputs
– Built-In Resistors Reduces Component
Count
– Improves System Noise Performance
• Constant Maximum Output Power from 2.3 V
to 5.5 V Supply
– Simplifies Design to Prevent Acoustic
Shock
• Improved RF Noise Immunity
• MicrosoftTM Windows VistaTM Compliant
• High Power Supply Noise Rejection
– 100 dB PSRR at 217 Hz
– 90 dB PSRR at 10 kHz
• Wide Power Supply Range: 2.3 V to 5.5 V
• Gain Settings: 0 dB and 6 dB
• Short-Circuit and Thermal-Overload Protection
• ±8 kV HBM ESD Protected Outputs
• Small Package Available
– 16-Pin, 3 mm × 3 mm Thin QFN
23
DESCRIPTION
The TPA6135A2 (sometimes referred to as TPA6135)
is a DirectPath™ stereo headphone amplifier that
eliminates the need for external dc-blocking output
capacitors. Differential stereo inputs and built-in
resistors set the device gain, further reducing external
component count. Gain is selectable at 0 dB or 6 dB.
The amplifier drives 25 mW into 16 Ω speakers from
a single 2.3 V supply. The TPA6135A2 (TPA6135)
provides a constant maximum output power
independent of the supply voltage, thus facilitating the
design for prevention of acoustic shock.
The TPA6135A2 (TPA6135) features HI-Z mode
which can set the outputs to a high impedance
configuration. The fully differential inputs reduce
system noise pickup between the audio source and
the headphone amplifier. The high power supply
noise rejection performance and differential
architecture provide increased RF noise immunity.
For single-ended input signals, connect INL+ and
INR+ to ground.
The device has built-in pop suppression circuitry to
completely eliminate disturbing pop noise during
turn-on and turn-off. The amplifier outputs have
short-circuit and thermal-overload protection along
with ±8 kV HBM ESD protection, simplifying end
equipment compliance to the IEC 61000-4-2 ESD
standard.
The TPA6135A2 (TPA6135) operates from a single
2.3 V to 5.5 V supply with 2.1 mA of typical supply
current. Shutdown mode reduces supply current to
less than 1 µA.
APPLICATIONS
•
•
•
•
Smart Phones / Cellular Phones
Notebook Computers
CD / MP3 Players
Portable Gaming
OUTR+
INR+
OUTR-
INR-
OUTL+
INL+
OUTL-
INL-
CODEC
OUTR
TPA6135A2
OUTL
SGND
ENABLE
GAIN
HI-Z MODE
VBAT
EN
PGND
GAIN
HI-Z
VDD
HPVSS
HPVDD
CPP
CPN
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DirectPath is a trademark of Texas Instruments.
Windows Vista is a trademark of Microsoft Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPA6135A2
SLOS623A – FEBRUARY 2009 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
VDD
HPVDD
Supply
Control
2.2 mF
PGND
HPVDD
–
INL+
Resistor
Array
OUTL
+
INL-
Short-Circuit
Protection
HPVSS
Thermal
Protection
HPVDD
Resistor
Array
OUTR
+
INR+
–
INR-
HPVDD
HPVSS
CPP
HI-Z
Click-and-Pop
Suppression
Control
GAIN
Charge
Pump
1 mF
CPN
HPVSS
1 mF
SGND
EN
2
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Product Folder Link(s) :TPA6135A2
TPA6135A2
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DEVICE PINOUT
OUTL
SGND
VDD
EN
16
15
14
13
RTE (QFN) PACKAGE
(TOP VIEW)
INR+ 3
10
PGND
INR- 4
9
8
CPN
HPVSS
7
CPP
GAIN
11
6
INL+ 2
HI-Z
HPVDD
5
12
OUTR
INL- 1
PIN FUNCTIONS
PIN
NAME
QFN
I/O/P
PIN DESCRIPTION
INL-
1
I
Inverting left input for differential signals; left input for single-ended signals
INL+
2
I
Non-inverting left input for differential signals. Connect to ground for single-ended input applications
INR+
3
I
Non-inverting right input for differential signals. Connect to ground for single-ended input applications
INR-
4
I
Inverting right input for differential signals; right input for single-ended signals
OUTR
5
O
Right headphone amplifier output. Connect to right terminal of headphone jack
HI-Z
6
I
Output impedance select. Set to logic LOW for normal operation and to logic HIGH for high output
impedance
GAIN
7
I
Gain select. Set to logic LOW for a gain of 0dB and to logic HIGH for a gain of 6dB
HPVSS
8
P
Charge pump output and negative power supply for output amplifiers; connect 1µF capacitor to GND
CPN
9
P
Charge pump negative flying cap. Connect to negative side of 1µF capacitor between CPP and CPN
PGND
10
P
Ground
CPP
11
P
Charge pump positive flying cap. Connect to positive side of 1µF capacitor between CPP and CPN
HPVDD
12
P
Positive power supply for headphone amplifiers. Connect to a 2.2µF capacitor. Do not connect to VDD
EN
13
I
Amplifier enable. Connect to logic LOW to shutdown; connect to logic HIGH to activate
VDD
14
P
Positive power supply for TPA6135A2
SGND
15
I
Amplifier reference voltage. Connect to ground terminal of headphone jack
OUTL
16
O
Left headphone amplifier output. Connect to left terminal of headphone jack
Thermal
Pad
–
P
Solder the exposed metal pad on the TPA6135A2RTE QFN package to the landing pad on the PCB.
Connect the landing pad to ground or leave it electrically unconnected (floating).
3
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BOARD LAYOUT CONCEPT
Enable
Control
13
14
15
16
To Battery
1
12
Soldered /
Electrical Float
or
GND
2
Matched Board Layout for
Differential Input Signals
2.2 mF
2.2 mF
3
11
10
4
9
8
7
6
5
1 mF
Gain
Control
HI-Z
Mode
1 mF
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, TA = 25°C (unless otherwise noted)
VALUE / UNIT
VI
Supply voltage, VDD
–0.3 V to 6.0 V
Headphone amplifier supply voltage, HPVDD (do not connect to external supply)
–0.3 V to 1.9 V
Input voltage (INR+, INR-, INL+, INL-)
1.4 VRMS
Output continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range
–40°C to 150°C
Tstg Storage temperature range
ESD Protection – HBM
–65°C to 150°C
OUTL, OUTR
8 kV
All Other Pins
2 kV
ORDERING GUIDE
TA
–40°C to 85°C
(1)
(2)
PACKAGED DEVICES (1)
16-pin, 3 mm × 3 mm Thin QFN
PART NUMBER (2)
TPA6135A2RTER
TPA6135A2RTET
SYMBOL
AOTI
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RTE packages is only available taped and reeled. The suffix “R” indicates a reel of 3000, the suffix “T” indicates a reel of 250
4
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Product Folder Link(s) :TPA6135A2
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DISSIPATION RATINGS TABLE
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
RTE (QFN)
2567 mW
DERATING FACTOR
(1)
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
1643 mW
1335 mW
48.7 °C/W
See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for using package
thermal information. See JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
Supply voltage, VDD
2.3
5.5
VIH
High-level input voltage; EN, GAIN, HI-Z
1.3
VIL
Low-level input voltage; EN, GAIN, HI-Z
TA
UNIT
V
V
0.6
V
V
Voltage applied to Output; OUTR, OUTL (when EN = 0 V)
–0.3
3.6
Voltage applied to Output; OUTR, OUTL (when EN ≥ 1.3 V and HI-Z ≥ 1.3 V)
–1.8
1.8
V
Operating free-air temperature
–40
85
°C
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output offset voltage
Power supply rejection ratio
MIN
TYP
–0.5
VDD = 2.3 V to 5.5 V
MAX
0.5
100
UNIT
mV
dB
High-level intput current (EN, HI-Z, GAIN)
1
µA
Low-level intput current (EN, HI-Z, GAIN)
1
µA
Supply Current
Shutdown Supply Current
VDD = 2.3 V, No load, EN = VDD, HI-Z = 0 V
2.1
2.8
VDD = 3.6 V, No load, EN = VDD, HI-Z = 0 V
2.1
2.8
VDD = 5.5 V, No load, EN = VDD, HI-Z = 0 V
2.2
2.9
VDD = 2.3 to 5.5 V, No load, EN = HI-Z = VDD
0.7
1
EN = 0 V, VDD = 2.3 V to 5.5 V
0.7
1.2
mA
µA
5
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OPERATING CHARACTERISTICS
VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)
PARAMETER
PO
Output power (1) (Outputs in phase)
VO
Output voltage(1) (Outputs in phase)
AV
Closed-loop voltage gain (OUT / IN–)
ΔAv
Gain matching
RIN
Input impedance (per input pin)
Input impedance in shutdown
(per input pin)
VCM
TEST CONDITIONS
MIN
25
THD = 1%, f = 1 kHz, RL = 32 Ω
22
THD = 1%, f = 1 kHz, RL = 100 Ω
1.1
VRMS
–1.0
–1.05
GAIN ≥ 1.3 V, (6 dB)
–1.95
–2.0
–2.05
Between Left and Right channels
UNIT
mW
–0.95
V/V
1%
GAIN = 0 V, (0 dB)
19.8
GAIN ≥ 1.3 V, (6 dB)
13.2
EN = 0 V
kΩ
10
–0.5
EN = HI-Z ≥ 1.3 V, f = 10 kHz
kΩ
1.5
V
40
EN = HI-Z ≥ 1.3 V, f = 1 MHz
4.5
EN = HI-Z ≥ 1.3 V, f = 10 MHz
0.75
EN = 0 V (shutdown mode)
Input-to-output attenuation in shutdown
MAX
GAIN = 0 V, (0 dB)
Input common-mode voltage range
Output impedance
TYP
THD = 1%, f = 1 kHz
EN = 0 V
kΩ
25
Ω
80
dB
200 mVpp ripple, f = 217 Hz
-100
200 mVpp ripple, f = 10 kHz
-90
kSVR
AC-power supply rejection ratio
THD+N
Total harmonic distortion plus noise (2)
SNR
Signal-to-noise ratio
PO = 20 mW; GAIN = 0 V, (AV = 0 dB)
100
dB
En
Noise output voltage
A-weighted
5.5
µVRMS
fosc
Charge pump switching frequency
tON
Start-up time from shutdown
Crosstallk
Thermal shutdown
(1)
(2)
PO = 20 mW, f = 1 kHz
0.02%
PO = 25 mW into 32 Ω, VDD = 5.5 V, f = 1 kHz
0.01%
1200
1275
dB
1350
kHz
5
ms
PO = 20 mW, f = 1 kHz
–80
dB
Threshold
150
°C
Hysteresis
20
°C
Per output channel
A-weighted
6
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TYPICAL CHARACTERISTICS
TA = 25°C, VDD = 3.6 V, Gain = 0 dB, EN = 3.6 V, CHPVDD = CHPVSS = 2.2 µF, CINPUT = CFLYING = 1 µF, Outputs in
Phase
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 16 W,
f = 1kHz
VDD = 2.5 V, In Phase
VDD = 3.6 V, In Phase
1
VDD = 2.5 V, Out of Phase
VDD = 3.6 V, Out of Phase
0.1
0.01
0.1
1
10
PO - Output Power per Channel - mW
VDD = 3.6 V, In Phase
1
VDD = 2.5 V, Out of Phase
VDD = 3.6 V, Out of Phase
0.1
1
10
PO - Output Power per Channel - mW
50
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
VDD = 2.5 V, In Phase
0.01
0.1
50
1
RL = 16 W,
VDD = 2.5 V
PO = 1 mW per Channel
0.1
0.01
PO = 4 mW per Channel
PO = 10 mW per Channel
0.001
20
100
1k
f - Frequency - Hz
10k
RL = 16 W,
VDD = 3.6 V
PO = 1 mW per Channel
0.1
PO = 20 mW per Channel
0.01
PO = 10 mW per Channel
0.001
20
20k
100
1k
f - Frequency - Hz
10k
20k
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
1
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
RL = 32 W,
f = 1kHz
RL = 16 W,
VDD = 5 V
PO = 1 mW per Channel
0.1
PO = 20 mW per Channel
0.01
PO = 10 mW per Channel
0.001
20
100
1k
f - Frequency - Hz
10k
20k
RL = 32 W,
VDD = 2.5 V
PO = 1 mW per Channel
0.1
PO = 4 mW per Channel
0.01
0.001
20
Figure 5.
PO = 10 mW per Channel
100
1k
f - Frequency - Hz
10k
20k
Figure 6.
7
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
1
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
1
RL = 32 W,
VDD = 3.6 V
PO = 1 mW per Channel
0.1
PO = 10 mW per Channel
0.01
PO = 20 mW per Channel
0.001
20
100
1k
f - Frequency - Hz
10k
20k
RL = 32 W,
VDD = 5 V
PO = 1 mW per Channel
0.1
PO = 20 mW per Channel
0.01
PO = 10 mW per Channel
0.001
20
100
Figure 7.
10k
20k
Figure 8.
OUTPUT POWER vs SUPPLY VOLTAGE
OUTPUT POWER vs SUPPLY VOLTAGE
50
50
RL = 16 W
45
45
PO - Output Power per Channel - mW
PO - Output Power per Channel - mW
1k
f - Frequency - Hz
40
THD+N = 10%
35
30
THD+N = 1%
25
20
15
10
5
RL = 32 W
40
35
THD+N = 10%
30
25
THD+N = 1%
20
15
10
5
0
2.5
3
3.5
4
4.5
VDD - Supply Voltage - V
5
0
2.5
5.5
3
Figure 9.
3.5
4
4.5
VDD - Supply Voltage - V
5
5.5
Figure 10.
OUTPUT POWER vs LOAD RESISTANCE
OUTPUT POWER vs LOAD RESISTANCE
30
40
VDD = 3.6 V, 10% THD+N
10
VDD = 2.5 V, 10% THD+N
VDD = 2.5 V, 1% THD+N
VDD = 3.6 V, 1% THD+N
25
HPVSS and Flying Cap = 2.2 mF
20
15
HPVSS and Flying Cap = 0.47 mF
10
5
THD+N = 1%,
VDD = 3.6 V
f = 1 kHz
1
10
PO - Output Power per Channel - mW
PO - Output Power per Channel - mW
HPVSS and Flying Cap = 1 mF
100
RL - Load Resistance - W
1000
0
10
100
200
RL - Load Resistance - W
Figure 11.
Figure 12.
8
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TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE vs SUPPLY VOLTAGE
SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
2
VO - Output Voltage - Vrms
1.6
1.4
Load = 600 W
1.2
1
Load = 32 W
0.8
0.6
Load = 16 W
0.4
0.2
0
2.5
3
3.5
4
4.5
5
-10
Ksvr - Supply Voltage Rejection Ratio - dB
f = 1 kHz,
THD+N = 1%
1.8
5.5
RL = 16 W
-30
-50
-70
VDD = 5 V
VDD = 2.5 V
VDD = 3.6 V
-90
-110
20
100
VDD - Supply Voltage - V
1k
f - Frequency - Hz
Figure 13.
10k
20k
Figure 14.
SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
-10
9
RL = 32 W
-30
-50
-70
VDD = 3.6 V
VDD = 5 V
VDD = 2.5 V
-90
EN = 1.3 V,
No Load
8
Quiescent Supply Current - mA
Ksvr - Supply Voltage Rejection Ratio - dB
10
7
6
5
4
3
2
1
-110
20
100
1k
f - Frequency - Hz
10k
0
2.5
20k
3
3.5
4
4.5
VDD - Supply Voltage - V
Figure 15.
5.5
Figure 16.
SUPPLY CURRENT vs TOTAL OUTPUT POWER
SUPPLY CURRENT vs TOTAL OUTPUT POWER
100
100
RL = 16 W,
f = 1kHz
RL = 32 W,
f = 1kHz
IDD - Supply Current - mA
VDD = 3 V
IDD - Supply Current - mA
5
VDD = 5 V
10
VDD = 2.5 V
VDD = 5 V
10
VDD = 3.6 V
VDD = 3 V
VDD = 3.6 V
1
0.001
0.01
VDD = 2.5 V
0.1
1
PO - Total Output Power - mW
10
50
1
0.001
Figure 17.
0.01
0.1
1
PO - Total Output Power - mW
10
50
Figure 18.
9
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TYPICAL CHARACTERISTICS (continued)
CROSSTALK vs FREQUENCY
OUTPUT SPECTRUM vs FREQUENCY
0
-10
RL = 16 W,
Power = 15 mW,
VDD = 3.6 V
-40
Crosstalk - dB
Single Channel,
Load = 16 W,
VDD = 3.6 V,
VIN = –60 dBV @ 1 kHz
-30
VO - Output Amplitude - dBV
-20
-60
-80
-100
-50
-70
-90
-110
-130
-120
-140
20
100
1k
f - Frequency - Hz
10k
-150
0
20k
5000
10000
f - Frequency - Hz
Figure 19.
20000
Figure 20.
HI-Z OUTPUT IMPEDANCE vs FREQUENCY
STARTUP WAVEFORMS vs TIME
5
100k
VDD = 3.6 V,
EN = 3.6 V,
Hi-Z = 3.6 V
4
EN
3
Right Channel
10k
V - Voltage - V
ZO - Hi-Z Output Impedance - W
15000
Left Channel
2
1
VOUT
0
1k
-1
Load = 16 W,
VDD = 3.6 V,
VI = 0.5 VRMS at 1 kHz
-2
100
10
-3
100
1000
1M
10k
100k
f - Frequency - Hz
10M
100M
0
2
4
6
t - Time - ms
Figure 21.
8
10
Figure 22.
SHUTDOWN WAVEFORMS vs TIME
5
Load = 16 W,
VDD = 3.6 V,
VI = 0.5 VRMS at 20 kHz
4
EN
V - Voltage - V
3
2
1
VOUT
0
-1
-2
-3
0
50
100
t - Time - ms
150
200
Figure 23.
10
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APPLICATION INFORMATION
APPLICATION CIRCUIT
0.22 µF x 4
INR+
OUTR
INRTPA2012D2
INL+
OUTL
INL-
0.22 µF x 4
ABB
or
TLV320AIC33
TLV320AIC3104
TLV320DAC32
PCM1774
OUTR+
INR+
OUTR–
INR-
OUTR
OUTL+
INL+
OUTL
OUTL–
INL-
TPA6135A2
SGND
ENABLE
HI-Z
GAIN
VBAT
2.2 µF
EN
PGND
HI-Z
GAIN
VDD
HPVSS
HPVDD
CPP
CPN
1 µF
2.2 µF
1 µF
Figure 24. Typical Application Configuration with Differential Input Signals
1 µF
RIGHT IN
INRINR+
OUTR
LEFT IN
1 µF
INL-
TPA6135A2
OUTL
INL+
SGND
ENABLE
EN
HI-Z
HI-Z
GAIN
GAIN
VBAT
2.2 µF
PGND
VDD
HPVDD
HPVSS
CPP
CPN
1 µF
2.2 µF
1 µF
Figure 25. Typical Application Configuration with Single-Ended Input Signals
11
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GAIN CONTROL
The TPA6135A2 has two gain settings which are controlled with the GAIN pin. The following table gives an
overview of the gain function.
GAIN VOLTAGE
AMPLIFIER GAIN
≤ 0.6 V
0 dB
≥ 1.3 V
6 dB
Table 1. Windows Vista™ Premium Mobile Mode Specifications
Device Type
Requirement
Windows Premium Mobile Vista
Specifications
TPA6135A2 Typical Performance
THD+N
≤ –65 dB FS [20 Hz, 20 kHz]
–75 dB FS [20 Hz, 20 kHz]
Analog Speaker Line Jack
(RL = 10 kΩ, FS = 0.707
Vrms)
Dynamic Range with Signal
Present
≤ –80 dB FS A-Weight
–100 dB FS A-Weight
Analog Headphone Out Jack
(RL = 32Ω, FS = 0.300
Vrms)
Line Output Crosstalk
≤ –60 dB [20 Hz, 20 kHz]
–90 dB [20 Hz, 20 kHz]
THD+N
≤ –45 dB FS [20 Hz, 20 kHz]
–65 dB FS [20 Hz, 20 kHz]
Dynamic Range with Signal
Present
≤ –80 dB FS A-Weight
–94 dB FS A-Weight
Headphone Output Crosstalk
≤ –60 dB [20 Hz, 20 kHz]
–90 dB [20 Hz, 20 kHz]
High Output Impedance
The TPA6135A2 has a HI-Z control pin that increases output impedance while mutting the amplifier. Apply a
voltage greater than 1.3 V to the HI-Z and EN pin to activate the HI-Z mode. This feature allows the headphone
output jack to be shared for other functions besides audio. For example, sharing of a headphone jack between
audio and video as shwon in Figure 26. The TPA6135A2 output impedance is high enough to prevent
attenuating the video signal.
Enable Voltage
HI-Z Voltage
Output Impedance
≤ 0.6 V
≤ 0.6 V
20 Ω – 30 Ω
≤ 0.6 V
≥ 1.3 V
20 Ω –30 Ω
≥ 1.3 V
≤ 0.6 V
Maximum
External Voltage
Applied to the
Output Pins
Comments
–0.3 V to 3.3 V (1)
Shutdown Mode
–
Active Mode
–1.8 V to 1.8 V
HI-Z Mode
≤1Ω
40 kΩ @ 10 kHz
≥ 1.3 V
≥ 1.3 V
4.5 kΩ @ 1 MHz
750 Ω @ 10 MHz
(1)
If VDD is < 3.3 V, then maximum allowed external voltage applied is VDD in this mode
Video Buffer/Amp
(i.e: THS7375)
+
75 W
–
TPA6135A2
OUTR
OUTL
Figure 26. Sharing One Connector Between Audio and Video Signals Example
12
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPA6135A2
TPA6135A2
www.ti.com .................................................................................................................................................. SLOS623A – FEBRUARY 2009 – REVISED APRIL 2009
HEADPHONE AMPLIFIERS
Single-supply headphone amplifiers typically require dc-blocking capacitors to remove dc bias from their output
voltage. The top drawing in Figure 27 illustrates this connection. If dc bias is not removed, large dc current will
flow through the headphones which wastes power, clips the output signal, and potentially damages the
headphones.
These dc-blocking capacitors are often large in value and size. Headphone speakers have a typical resistance
between 16 Ω and 32 Ω. This combination creates a high-pass filter with a cutoff frequency as shown in
Equation 1, where RL is the load impedance, CO is the dc-block capacitor, and fC is the cutoff frequency.
1
fc =
2pRLCO
(1)
For a given high-pass cutoff frequency and load impedance, the required dc-blocking capacitor is found as:
CO =
1
2p ¦C RL
(2)
Reducing fC improves low frequency fidelity and requires a larger dc-blocking capacitor. To achieve a 20 Hz
cutoff with 16 Ω headphones, CO must be at least 500 µF. Large capacitor values require large packages,
consuming PCB area, increasing height, and increasing cost of assembly. During start-up or shutdown the
dc-blocking capacitor has to be charged or discharged. This causes an audible pop on start-up and power-down.
Large dc-blocking capacitors also reduce audio output signal fidelity.
Two different headphone amplifier architectures are available to eliminate the need for dc-blocking capacitors.
The Capless amplifier architecture provides a reference voltage to the headphone connector shield pin as shown
in the middle drawing of Figure 27. The audio output signals are centered around this reference voltage, which is
typically half of the supply voltage to allow symmetrical output voltage swing.
When using a Capless amplifier do not connect the headphone jack shield to any ground reference or large
currents will result. This makes Capless amplifiers ineffective for plugging non-headphone accessories into the
headphone connector. Capless amplifiers are useful only with floating GND headphones.
13
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Product Folder Link(s) :TPA6135A2
TPA6135A2
SLOS623A – FEBRUARY 2009 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com
Conventional
CO
VOUT
CO
VOUT
GND
Capless
VOUT
VOUT
GND
VBIAS
DirectPath™
VDD
VOUT
GND
VSS
Figure 27. Amplifier Applications
The DirectPath™ amplifier architecture operates from a single supply voltage and uses an internal charge pump
to generate a negative supply rail for the headphone amplifier. The output voltages are centered around 0 V and
are capable of positive and negative voltage swings as shown in the bottom drawing of Figure 27. DirectPath
amplifiers require no output dc-blocking capacitors. The headphone connector shield pin connects to ground and
will interface with headphones and non-headphone accessories. The TPA6135A2 is a DirectPath amplifier.
ELIMINATING TURN-ON POP AND POWER SUPPLY SEQUENCING
The TPA6135A2 has excellent noise and turn-on / turn-off pop performance. It uses an integrated click-and-pop
suppression circuit to allow fast start-up and shutdown without generating any voltage transients at the output
pins. Typical start-up time from shutdown is 5 ms.
DirectPath technology keeps the output dc voltage at 0 V even when the amplifier is powered up. The DirectPath
technology together with the active pop-and-click suppression circuit eliminates audible transients during start up
and shutdown.
Use input coupling capacitors to ensure inaudible turn-on pop. Activate the TPA6135A2 after all audio sources
have been activated and their output voltages have settled. On power-down, deactivate the TPA6135A2 before
deactivating the audio input source. The EN pin controls device shutdown: Set to 0.6 V or lower to deactivate the
TPA6135A2; set to 1.3 V or higher to activate.
14
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPA6135A2
TPA6135A2
www.ti.com .................................................................................................................................................. SLOS623A – FEBRUARY 2009 – REVISED APRIL 2009
RF AND POWER SUPPLY NOISE IMMUNITY
The TPA6135A2 employs a new differential amplifier architecture to achieve high power supply noise rejection
and RF noise rejection. RF and power supply noise are common in modern electronics. Although RF frequencies
are much higher than the 20 kHz audio band, signal modulation often falls in-band. This, in turn, modulates the
supply voltage, allowing a coupling path into the audio amplifier. A common example is the 217 Hz GSM
frame-rate buzz often heard from an active speaker when a cell phone is placed nearby during a phone call.
The TPA6135A2 has excellent rejection of power supply and RF noise, preventing audio signal degradation.
CONSTANT MAXIMUM OUTPUT POWER AND ACOUSTIC SHOCK PREVENTION
Typically the output power increases with increasing supply voltage on an unregulated headphone amplifier. The
TPA6135A2 maintains a constant output power independent of the supply voltage. Thus the design for
prevention of acoustic shock (hearing damage due to exposure to a loud sound) is simplified since the output
power will remain constant, independent of the supply voltage. This feature allows maximizing the audio signal at
the lowest supply voltage.
INPUT COUPLING CAPACITORS
Input coupling capacitors block any dc bias from the audio source and ensure maximum dynamic range. Input
coupling capacitors also minimize TPA6135A2 turn-on pop to an inaudible level.
The input capacitors are in series with TPA6135A2 internal input resistors, creating a high-pass filter. Equation 3
calculates the high-pass filter corner frequency. The input impedance, RIN, is dependent on device gain. Larger
input capacitors decrease the corner frequency. See the Operating Characteristics table for input impedance
values.
1
fC =
2 p RIN CIN
(3)
For a given high-pass cutoff frequency, the minimum input coupling capacitor is found as:
1
CIN =
2 p ¦ C RIN
(4)
Example: Design for a 20 Hz corner frequency with a TPA6135A2 gain of +6 dB. The Operating Characteristics
table gives RIN as 13.2 kΩ. Equation 4 shows the input coupling capacitors must be at least 0.6 µF to achieve a
20 Hz high-pass corner frequency. Choose a 0.68 µF standard value capacitor for each TPA6135A2 input (X5R
material or better is required for best performance).
Input capacitors can be removed provided the TPA6135A2 inputs are driven differentially with less than ±1 VRMS
and the common-mode voltage is within the input common-mode range of the amplifier. Without input capacitors
turn-on pop performance may be degraded and should be evaluated in the system.
CHARGE PUMP FLYING CAPACITOR AND HPVSS CAPACITOR
The TPA6135A2 uses a built-in charge pump to generate a negative voltage supply for the headphone
amplifiers. The charge pump flying capacitor connects between CPP and CPN. It transfers charge to generate
the negative supply voltage. The HPVSS capacitor must be at least equal in value to the flying capacitor to allow
maximum charge transfer. Use low equivalent-series-resistance (ESR) ceramic capacitors (X5R material or
better is required for best performance) to maximize charge pump efficiency. Typical values are 1 µF to 2.2 µF
for the HPVSS and flying capacitors. Although values down to 0.47 µF can be used, total harmonic distortion
(THD) will increase.
15
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Product Folder Link(s) :TPA6135A2
TPA6135A2
SLOS623A – FEBRUARY 2009 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com
POWER SUPPLY AND HPVDD DECOUPLING CAPACITORS AND CONNECTIONS
The TPA6135A2 DirectPath headphone amplifier requires adequate power supply decoupling to ensure that
output noise and total harmonic distortion (THD) remain low. Use good low equivalent-series-resistance (ESR)
ceramic capacitors (X5R material or better is required for best performance). Place a 2.2 µF capacitor within
5 mm of the VDD pin. Reducing the distance between the decoupling capacitor and VDD minimizes parasitic
inductance and resistance, improving TPA6135A2 supply rejection performance. Use 0402 or smaller size
capacitors if possible. Ensure that the ground connection of each of the capacitors has a minimum length return
path to the device. Failure to properly decouple the TPA6135A2 may degrade audio or EMC performance.
For additional supply rejection, connect an additional 10 µF or higher value capacitor between VDD and ground.
This will help filter lower frequency power supply noise. The high power supply rejection ratio (PSRR) of the
TPA6135A2 makes the 10 µF capacitor unnecessary in most applications.
Connect a 2.2 µF capacitor between HPVDD and ground. This ensures the amplifier internal bias supply remains
stable and maximizes headphone amplifier performance.
WARNING:
DO NOT connect HPVDD directly to VDD or an external supply voltage. The
voltage at HPVDD is generated internally. Connecting HPVDD to an external
voltage can damage the device.
LAYOUT RECOMMENDATIONS
EXPOSED PAD ON TPA6135A2RTE
Solder the exposed metal pad on the TPA6135A2RTE QFN package to the landing pad on the PCB. Connect
the landing pad to ground or leave it electrically unconnected (floating). Do not connect the landing pad to VDD
or to any other power supply voltage.
If the pad is grounded, it must be connected to the same ground as the PGND pin (10). See the layout and
mechanical drawings at the end of the data sheet for proper sizing. Soldering the thermal pad is required for
mechanical reliability and enhances thermal conductivity of the package.
WARNING:
DO NOT connect the TPA6135A2RTE exposed metal pad to VDD or any other
power supply voltage.
GND CONNECTIONS
The SGND pin is an input reference and must be connected to the headphone ground connector pin. This
ensures no turn-on pop and minimizes output offset voltage. Do not connect more than ±0.3 V to SGND.
PGND is a power ground. Connect supply decoupling capacitors for VDD, HPVDD, and HPVSS to PGND.
16
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Product Folder Link(s) :TPA6135A2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPA6135A2RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TPA6135A2RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA6135A2RTER
WQFN
RTE
16
3000
367.0
367.0
38.0
TPA6135A2RTET
WQFN
RTE
16
250
213.0
191.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3 x 3, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
OPTION 2
0.1
0.2
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
16
13
0.1
0.05
SYMM
16X
0.30
0.18
C A B
0.5
0.3
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
17
(2.8)
(0.58)
TYP
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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