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TPD1S514x
SLVSCF6F – APRIL 2014 – REVISED MAY 2019
TPD1S514x Family USB Charger Overvoltage, Surge and ESD Protection for VBUS PIN
1 Features
3 Description
•
The TPD1S514 Family consists of single-chip
protection solutions for 5-V, 9-V or 12-V USB VBUS
lines, or other power buses. The bidirectional nFET
switch ensures safe current flow in both charging and
host mode while protecting the internal system
circuits from any over voltage condition at the
VBUS_CON pin. On the VBUS_CON pin, this device can
handle over voltage protection up to 30-V DC. After
the EN pin toggles low, any device in the TPD1S514
Family waits 20 ms before turning ON the nFET
through a soft start delay.
1
•
•
•
•
•
•
Overvoltage Protection at VBUS_CON
up to 30-V DC
Precision OVP ( < ± 1% Tolerance)
Low RON nFET Switch Supports Host and
Charging Mode
Dedicated VBUS_POWER Pin Offers Flexible Power
up Options Under Dead Battery Condition
Transient Protection for VBUS Line:
– IEC 61000-4-2 Contact Discharge ±15 kV
– IEC 61000-4-2 Air Gap Discharge ±15 kV
– IEC 61000-4-5 Open Circuit Voltage 100 V
– Precision Clamp Circuit Limits the VBUS_SYS
Voltage < VOVP
USB Inrush Current Compliant
Thermal Shutdown (TSD) Feature
2 Applications
•
•
•
•
•
Typical application interfaces for the TPD1S514
Family are VBUS lines in USB connectors typically
found in cell phones, tablets, eBooks, and portable
media players. The TPD1S514 Family can also be
applied to any system using an interface for a 5-V, 9V, or 12-V power rail.
Device Information(1)
DEVICE NAME
PACKAGE
TPD1S514x
Cell Phones
Tablets
eBook
Portable Media Players
5-V, 9-V, and 12-V Power Rails
WCSP (12)
BODY SIZE (NOM)
1.29 mm × 1.99 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
White Space
White Space
White Space
White Space
White Space
TPD1S514 Family Circuit Protection Scheme
USB Port
TPD1S514x
VBUS
D–
VBUS_SYS
TPD1S514 Family Block Diagram
PMIC/System
VBUS_CON
VBUS_CON
VIN
VBUS_POWER
VOUT
LDO
VBUS_POWER
D+
GND
POR
Surge
Clamp
Oscillator
Q-Pump
Gate Drive
EN
ID
VBUS_SYS
TSD
GND
BG
Reference
Digital
Core
GND
+
VREF
OVP
EN Buffer
EN
-
TPD4E110
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD1S514x
SLVSCF6F – APRIL 2014 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Supply Current Consumption.................................... 6
Electrical Characteristics EN Pin .............................. 7
Thermal Shutdown Feature ...................................... 7
Electrical Characteristics nFET Switch ..................... 7
Electrical Characteristics OVP Circuit....................... 8
Electrical Characteristics VBUS_POWER Circuit......... 8
Timing Requirements .............................................. 9
TPD1S514-1 Typical Characteristics .................... 10
8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Applications ................................................ 15
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
13.1 Package Option Addendum .................................. 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2015) to Revision F
•
Page
Changed IPOWER from 1 mA to 10 mA in the Absolute Maximum Ratings table..................................................................... 5
Changes from Revision D (July 2015) to Revision E
Page
•
Removed Preview status of TPD1S514-3. ............................................................................................................................. 1
•
Changed Max value of IVBUS_SLEEP PARAMETER for TPD1S514-3 (Preview) from 308 µA to 335 µA. ............................... 6
•
Updated TEST CONDITIONS for TOFF_DELAY PARAMETER. ................................................................................................ 9
Changes from Revision C (July 2015) to Revision D
•
Added TPD1S514 and TPD1S514-3 (Preview) .................................................................................................................... 1
Changes from Revision B (September 2014) to Revision C
•
Page
Removed Previewed TPD1S514-3 and Programmability Features. ..................................................................................... 1
Changes from Revision A (July 2014) to Revision B
•
Page
Page
Changed Body size to fix rounding error. .............................................................................................................................. 1
Changes from Original (April 2014) to Revision A
Page
•
Removed Preview status of TPD1S514-2. ............................................................................................................................ 1
•
Updated Device Comparison table. ....................................................................................................................................... 4
•
Updated Electrical Characteristics OVP Circuit table. ............................................................................................................ 8
2
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5 Device Comparison Table
MIN
TYP
TPD1S514-1
5.9
TPD1S514-2
9.9
TPD1S514-3
TPD1S514
(1)
VOVP_HYS
(mV)
VOVP (V)
TPD1S514 Family
VBUS_POWER (V) (1)
MAX
TYP
MIN
TYP
5.95
5.99
100
4.7
4.95
9.98
10.05
100
4.7
4.95
13.5
13.75
14
100
4.7
4.95
5.9
5.95
5.99
20
6.2
6.48
T_Startup delay (ms)
options
T_Soft Start (ms)
options
TYP
TYP
20
3.5
With VBUS_CON > 6.5V. See Sections VBUS_POWER, TPD1S514-1, TPD1S514-2, TPD1S514-3 and VBUS_POWER, TPD1S514 for full
description.
6 Pin Configuration and Functions
YZ Package
12-Pin WCSP
Top Side, See Through View
1
2
3
4
A
EN
VBUS_SYS
VBUS_SYS
GND
B
VBUS_POWER
VBUS_SYS
VBUS_CON
GND
C
GND
VBUS_CON
VBUS_CON
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
EN
A1
I
Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the
switch.
VBUS_POWER
B1
O
5-V Power source controlled by VBUS_CON.
VBUS_SYS
A2, A3, B2
I/O
Connect to internal VBUS plane.
VBUS_CON
B3, C2, C3
I/O
Connect to USB connector VBUS pin; IEC 61000-4-2 ESD protection and IEC 61000-4-5
Surge protection.
A4, B4, C1, C4
G
Connect to PCB ground plane.
GND
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VBUS_CON
Supply voltage from USB connector
–0.3
30
V
VBUS_SYS
Internal Supply DC voltage Rail on the PCB
–0.3
20
V
IBUS
Continuous input current on VBUS_CON pin (3)
3.5
A
IOUT
Continuous output current on VBUS_CON pin (3)
3.5
A
IPEAK
Peak Input and Output Current on VBUS_CON, VBUS_SYS pin (10 ms)
8
A
IDIODE
Continuous forward current through the FET body diode
1
A
IPOWER
Continuous current through VBUS_POWER
10
mA
VEN
Voltage on Input pin (EN)
VBUS_POWER
Continuous Voltage at VBUS_POWER
7
V
TPD1S514-1
See (4)
V
TPD1S514-2
See (4)
TPD1S514-3
See (4)
TPD1S514
See (4)
IEC 61000-4-5 open circuit voltage (tp = 1.2/50 µs)
VBUS_CON pin
100
IEC 61000-4-5 peak pulse current (tp = 8/20μs)
VBUS_CON pin
30
A
IEC 61000-4-5 peak pulse power (tp = 8/20μs)
VBUS_CON pin
900
W
CLOAD
Output load capacitance
VBUS_SYS pin
0.1
100
µF
CCON
Input capacitance
VBUS_CON pin
0.1
50
µF
CPOW
VBUS_POWER capacitance
VBUS_POWER pin
0.1
4.7
µF
TA
Operating free air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Thermal limits and power dissipation limits must be observed.
6.9 V or VBUS_CON + 0.3 V, whichever is smaller.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
IEC 61000-4-2 Contact Discharge
VBUS_CON pin
±15000
IEC 61000-4-2 Air-gap Discharge
VBUS_CON pin
±15000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VBUS_CON
VBUS_SYS
Supply voltage from USB
connector
Internal Supply DC voltage Rail
on the PCB
MIN
NOM
MAX
TPD1S514-1
3.5
5
5.9
TPD1S514-2
3.5
9
9.9
TPD1S514-3
3.5
12
13.5
TPD1S514
3.5
5
5.9
TPD1S514-1
3.9
5
5.9
TPD1S514-2
3.9
9
9.9
TPD1S514-3
3.9
12
13.5
TPD1S514
3.9
5
5.9
UNIT
V
V
CLOAD
Output load capacitance
VBUS_SYS pin
2.2
µF
CCON
Input capacitance
VBUS_CON pin
1
µF
CPOWER
Capacitance on VBUS_POWER
VBUS_POWER pin
TA
Operating free-air temperature
1
µF
–40
85
°C
7.4 Thermal Information
TPD1S514 Family
THERMAL METRIC (1)
YZ (WCSP)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
89
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.6
°C/W
RθJB
Junction-to-board thermal resistance
16.3
°C/W
ψJT
Junction-to-top characterization parameter
2.7
°C/W
ψJB
Junction-to-board characterization parameter
16.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Supply Current Consumption
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Measured at VBUS_CON pin,
EN = 5 V
IVBUS_SLEEP
VBUS_CON Operating
Current Consumption
Measured at VBUS_CON pin,
EN = 0 V and no load
IVBUS
IVBUS_SYS
IHOST_LEAK
6
VBUS_SYS operating current
consumption
Host mode leakage current
Measured at VBUS_SYS pin,
VBUS_CON = Hi-Z, EN = 0 V
Measured at VBUS_SYS pin,
VBUS_CON = Hi-Z, EN = 5 V
TYP
MAX
VBUS_CON = 5 V
TPD1S514-1
150
245
VBUS_CON = 9 V
TPD1S514-2
176
281
VBUS_CON = 12 V
TPD1S514-3
195
335
VBUS_CON = 5 V
TPD1S514
150
245
VBUS_CON = 5 V
TPD1S514-1
228
354
VBUS_CON = 9 V
TPD1S514-2
250
413
VBUS_CON = 12 V
TPD1S514-3
270
456
VBUS_CON = 5 V
TPD1S514
228
354
VBUS_SYS = 5 V
TPD1S514-1
210
354
VBUS_SYS = 9 V
TPD1S514-2
250
424
VBUS_SYS = 12 V
TPD1S514-3
333
461
VBUS_SYS = 5 V
TPD1S514
210
354
VBUS_SYS = 5 V
TPD1S514-1
90
218
VBUS_SYS = 9 V
TPD1S514-2
290
491
VBUS_SYS = 12 V
TPD1S514-3
506
696
VBUS_SYS = 5 V
TPD1S514
90
218
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DEVICE NAME
UNIT
µA
µA
µA
µA
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7.6 Electrical Characteristics EN Pin
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
High-level input voltage
EN
VBUS_CON = 5 V
1.2
6
VIL
Low-level input voltage
EN
VBUS_CON = 5 V
0
0.8
V
V
IIL
Input leakage current
EN
VEN = 0 V, VBUS_CON = 5 V
1
µA
IIH
Input leakage current
EN
VEN = 5 V, VBUS_CON = 5 V
10
µA
MAX
UNIT
7.7 Thermal Shutdown Feature
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TSHDN
TEST CONDITIONS
Thermal shutdown
Thermal shutdown hysteresis
MIN
TYP
VBUS_CON = 5 V, EN = 0 V, Junction temperature
decreases from thermal shutdown level until the nFET
switch turns off.
145
°C
VBUS_CON = 5 V, EN = 0 V, Junction temperature
decreases from thermal shutdown level until the nFET
switch turns on.
25
°C
7.8 Electrical Characteristics nFET Switch
T = 25°C
PARAMETER
RON
Switch ON resistance
TEST CONDITIONS
MIN
TYP MAX
VBUS_CON = 5 V, IOUT = 1 A
TPD1S514-1
39
50
VBUS_CON = 9 V, IOUT = 1 A
TPD1S514-2
39
50
VBUS_CON = 12 V, IOUT = 1 A
TPD1S514-3
39
50
VBUS_CON = 5 V, IOUT = 1 A
TPD1S514
39
50
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UNIT
mΩ
7
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7.9 Electrical Characteristics OVP Circuit
T = 25°C
PARAMETER
TEST CONDITIONS
TPD1S514-1
Input voltage protection
threshold
VOVP
VBUS_CON
VBUS_CON increasing
from 0 V to 20 V
MIN
TYP
MAX
5.90
5.95
5.99
TPD1S514-2
9.9
9.98
10.05
TPD1S514-3
13.5
13.75
14
TPD1S514
5.90
5.95
5.99
TPD1S514-1
100
TPD1S514-2
100
TPD1S514-3
100
VHYS_OVP
Hysteresis on OVP
VBUS_CON
VBUS_CON decreasing
from 20 V to 0 V
VUVLO
Input under voltage lockout
VBUS_CON
VBUS_CON voltage rising from 0 V to 5 V
TPD1S514
UNIT
V
mV
20
2.7
3.1
3.5
V
VHYS_UVLO
Hysteresis on UVLO
VBUS_CON
Difference between rising and falling UVLO
thresholds
VUVLO_FALLING
Input undervoltage lockout
VBUS_CON
VBUS_CON voltage falling from 5 V to 0 V
2.6
3.0
3.4
V
VUVLO_SYS
VBUS_SYS undervoltage lockout
VBUS_SYS
VBUS_SYS voltage rising from 0 V to 5 V
2.8
3.7
4.3
V
VHYS_UVLO_SYS
VBUS_SYS UVLO Hysteresis
VBUS_SYS
Difference between rising and falling UVLO
thresholds on VBUS_SYS
VUVLO_SYS_FALLING
VBUS_SYS undervoltage lockout
VBUS_SYS
VBUS_SYS voltage falling from 5 V to 0 V
80
mV
500
2.6
3.0
MIN
mV
3.4
V
7.10 Electrical Characteristics VBUS_POWER Circuit
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCLAMP
TEST CONDITIONS
Output voltage on VBUS_POWER during OVP
VBUS_CON = 20 V
TYP
MAX
TPD1S514-1
5.0
5.5
TPD1S514-2
5.0
5.5
TPD1S514-3
5.0
5.5
6.48
6.68
TPD1S514
VBUS_POWER
Output voltage on VBUS_POWER during normal
operation
VBUS_CON = 5 V,
IBUS_POWER = 1 mA;
IBUS_POWER_MAX
Output current on VBUS_POWER
VBUS_CON = 5 V – 15 V
8
TPD1S514-1
4.7
4.95
TPD1S514-2
4.7
4.95
TPD1S514-3
4.7
4.95
TPD1S514
4.7
4.98
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UNIT
V
V
3
mA
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7.11 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPD1S514-1
USB charging turn-ON
Delay
tDELAY
Measured from EN asserted LOW to nFET
begins to Turn ON, excludes soft-start time
TPD1S514-2
TPD1S514-3
20
ms
3.5
ms
5.5
µs
TPD1S514
TPD1S514-1
USB charging rise time
(soft-start delay)
tSS
Force 5 V on VBUS_CON, measured from
VBUS_SYS rises from 10% to 90% (with 1 MΩ
load/ NO CLOAD)
TPD1S514-2
TPD1S514-3
TPD1S514
USB charging turn-OFF
time
tOFF_DELAY
TPD1S514-1
Measured from EN asserted High to VBUS_SYS
TPD1S514-2
falling to 10% with RLOAD = 10 Ω and No CLOAD
TPD1S514-3
on VBUS_SYS
TPD1S514
OVER VOLTAGE PROTECTION
tOVP_response OVP response time
(1)
Measured from OVP Condition to FET Turn OFF (1)
100
ns
Specified by design, not production tested
6
Voltage (V)
4
2
0
-2
-5E-3
/EN
VBUS_SYS
VBUS_Power
000E+0
5E-3
10E-3
15E-3
20E-3
25E-3
30E-3
Time (s)
C002
Figure 1. TPD1S514-1 Response to Set EN Low
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7.12 TPD1S514-1 Typical Characteristics
400
1.060
1.040
Normalized VOPV (V)
Current ( A)
300
200
95C
100
25C
1.020
1.000
0.980
0.960
-50C
0
VOVP
0.940
5
10
15
20
25
30
VBUS_CON (V)
-50
-25
0
25
50
75
100
Temperature (ƒC)
C006
Figure 2. In Supply Current vs Supply Voltage
C013
Figure 3. Normalized VOVP vs Temperature
2.00
1.10
1.60
Normalized RDS_ON (m )
Normalized RDS_ON (m )
1.80
1.40
1.20
1.00
0.80
0.60
0.40
3A
2A
1.5A
0.20
0.00
-50
0
50
1.05
1.00
0.95
0.90
100
Temperature (ºC)
0.0
2.0
3.0
Current (A)
Figure 4. Normalized RON vs Temperature
C005
Figure 5. Normalized RON vs Output
5.1
5.1
5.0
5.0
4.9
4.9
VBUS_Power (V)
VBUS_Power (V)
1.0
C004
4.8
4.7
4.6
4.8
4.7
4.6
0 mA Load
3 mA Load
4.5
4.5
0
3
6
9
12
VBUS_CON (V)
3
6
VBUS_CON (V)
C008
Figure 6. VBUS_POWER vs VBUS_CON With No Load
10
0
9
12
C009
Figure 7. VBUS_POWER vs VBUS_CON With 3 mA Load
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TPD1S514-1 Typical Characteristics (continued)
40
120
Open Circuit
Voltage
100
Voltage (V)
Output (V or A)
30
VBUS_CON (V)
20
VBUS_CON (I)
VBUS_SYS (V)
80
60
40
10
20
0
-40E-6
000E+0
40E-6
80E-6
0
-25E-6
120E-6
Time (s)
C011
Figure 8. 100 V Surge With Device
25E-6
75E-6
125E-6
175E-6
Time (s)
Figure 9. 100 V Surge Without Device
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8 Detailed Description
8.1 Overview
The TPD1S514 Family provides single-chip ESD, surge, and over voltage protection solutions for portable USB
Charging and Host interfaces. Each device offers over voltage protection at the VBUS_CON pin up to 30-V DC. The
TPD1S514 Family offers an ESD and Precision Clamp for the VBUS_CON pin, thus eliminating the need for
external TVS clamp circuits in the application.
Each device has an internal oscillator and charge pump which controls turning ON the internal nFET switch. The
internal oscillator controls the timers which enable the charge pump. If VBUS_CON is less than VOVP, the internal
charge pump is enabled. After a 20 ms internal delay, the charge-pump starts-up, and turns ON the internal
nFET switch through a soft start. If at any time VBUS_CON rises above VOVP, the nFET switch is turned OFF within
100 ns.
The TPD1S514 Family of devices also have a VBUS_POWER pin which follows VBUS_CON up to 4.9 V at 3 mA
(except for TPD1S514, which follows VBUS_CON up to 6.48 V, after which it is regulated to that voltage) to power
the system from VBUS_CON. In the case where the system battery state cannot power the system, voltage from an
external charger can be provided to power the system. VBUS_POWER is supplied by an always on LDO regulator
supplied by VBUS_CON. VBUS_POWER output voltage remains regulated to 4.9 V (except for TPD1S514, which
follows VBUS_CON up to 6.48 V, after which it is regulated to that voltage) at up to 30-V DC on VBUS_CON and
during IEC 61000-4-5 surge events of up to 100 V open circuit voltage on VBUS_CON.
8.2 Functional Block Diagram
VBUS_CON
VIN
VBUS_POWER
VOUT
LDO
POR
Surge
Clamp
Oscillator
Q-Pump
Gate Drive
VBUS_SYS
TSD
GND
BG
Reference
Digital
Core
+
VREF
OVP
EN Buffer
EN
-
8.3 Feature Description
8.3.1 Over Voltage Protection on VBUS_CON up to 30 V DC
When the VBUS_CON voltage rises above VOVP, the internal nFET switch is turned OFF, removing power from the
system side. VBUS_CON can tolerate up to 30-V DC. The response to over voltage is very rapid, with the nFET
switch turning off in less than 100 ns. When the VBUS_CON voltage returns back to below VOVP – VHYS_OVP, the
nFET switch is turned ON again after an internal delay of tOVP_RECOV (tDELAY). This time delay ensures that the
VBUS_CON supply has stabilized before turning the switch back on. After tOVP_RECOV, the TPD1S514 Family device
turns on the nFET through a soft start. Once the OVP condition is cleared the nFET is turned completely ON.
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Feature Description (continued)
8.3.2 Precision OVP (< ±1% Tolerance)
1% OVP trip threshold accuracy allows use of the entire input charging range while protecting sensitive systemside components from over voltage conditions.
8.3.3 Low RON nFET Switch Supports Host and Charging Mode
The nFET switch has a total on resistance (RON) of 39 mΩ. This equates to a voltage drop of less than 140 mV
when charging at the maximum 3.5 A current level. Such low RON helps provide maximum potential to the
system as provided by an external charger or by the system when in Host Mode.
8.3.4 VBUS_POWER, TPD1S514-1, TPD1S514-2, TPD1S514-3
The VBUS_POWER pin provides up to 3 mA and 5 V for powering the system using VBUS_CON. VBUS_POWER follows
VBUS_CON after 3.5 V and up to the regulated 5 V. In the case where the system battery state cannot power the
system, voltage from an external charger can power the system. VBUS_POWER is supplied by an always on LDO
regulator supplied by VBUS_CON. The VBUS_POWER output voltage remains regulated to 5 V at up to 30-V DC on
VBUS_CON and during IEC 61000-4-5 surge events of up to 100 V.
8.3.5 VBUS_POWER, TPD1S514
The VBUS_POWER pin provides up to 3 mA and 6.48 V for powering the system using VBUS_CON. VBUS_POWER follows
VBUS_CON after 3.5 V and up to the regulated 6.48 V. In the case where the system battery state cannot power
the system, voltage from an external charger can be provided to power the system. VBUS_POWER is supplied by an
always on LDO regulator supplied by VBUS_CON. The VBUS_POWER output voltage remains regulated to 6.48 V at up
to 30-V DC on VBUS_CON and during IEC 61000-4-5 surge events of up to 100 V.
8.3.6 Powering the System When Battery is Discharged
There are two methods for powering the system under a dead battery condition. Case 1: The EN pin can be tied
to ground so that the nFET is always ON (when VUVLO < VBUS_CON < VOVP) and an external charger can power
VBUS. Case 2: If EN is controlled by a Power Management Unit (PMIC) or other logic, VBUS_POWER can be used to
power the PMIC. In Case 2, once the device is enabled, tDELAY + tSS, work together to meet the USB Inrush
Current compliance.
8.3.7 ±15 kV IEC 61000-4-2 Level 4 ESD Protection
The VBUS_CON pin can withstand ESD events up to ±15 kV Contact and Air-Gap. An ESD clamp diverts the
current to ground.
8.3.8 100 V IEC 61000-4-5 µs Surge Protection
The VBUS_CON pin can withstand surge events up to 100 V open circuit voltage (VPP), or 900 W. A Precision
Clamp diverts the current to ground and active circuitry switches OFF the nFET earlier than 100 ns before an
over voltage can get through to VBYS_SYS. The ultra-fast response time of the TPD1S514 Family holds the voltage
on VBUS_SYS to less than VOVP during surge events of up to 100 VPP.
8.3.9 Startup and OVP Recovery Delay
Upon startup or recovering from an over voltage, the TPD1S514 Family of devices have a built in startup delay.
An internal oscillator controls a charge pump to control the delay. Once a manufactured pre-programmed time,
tDELAY, has elapsed, the charge pump is enabled which turns ON the nFET. A manufactured pre-programmed
soft start, tSS, is used when turning ON the nFET. Once the device is enabled, these start delays, tDELAY + tSS,
work together to meet the USB Inrush Current compliance.
8.3.10 Thermal Shutdown
The TPD1S514 Family has an over-temperature protection circuit to protect against system faults or improper
use. The basic function of the thermal shutdown (TSD) circuit is to sense when the junction temperature has
exceeded the absolute maximum rating and shuts down the device until the junction temperature has cooled to a
safe level.
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8.4 Device Functional Modes
8.4.1 Operation With VBUS_CON < 3.5 V (Minimum VBUS_CON)
The TPD1S514 Family operates normally (nFET ON) with input voltages above 3.5 V. The maximum UVLO
voltage is 3.5 V and the device will operate at input voltages above 3.5 V. The typical UVLO voltage is 3.1 V and
the device may operate at input voltages above that point. The device may also operate at input voltages as low
as 2.7 V, the minimum UVLO. At input voltages between 0.6 V and 1.2 V, the state of output pins may not be
controlled internally.
8.4.2 Operation With VBUS_CON > VOVP
The TPD1S514 Family operates normally (nFET ON) with input voltages below VOVP_min. The typical OVP
voltage is VOVP_TYP and the device may operate at input voltages below that point. The device may also operate
at input voltages as high as VOVP_MAX.
Table 1. VOVP Values
DEVICE NAME
VOVP
MIN
TYP
TPD1S514-1
5.9
5.95
MAX
5.99
TPD1S514-2
9.9
9.98
10.05
TPD1S514-3
13.5
13.75
14
TPD1S514
5.9
5.95
5.99
8.4.3 OTG Mode
The TPD1S514 Family of devices UVLO and OVP voltages are referenced to VBUS_CON voltage. In OTG mode,
VBUS_SYS is driving the VBUS_CON. Under this situation, initially VBUS_CON is powered through the body diode of the
nFET by VBUS_SYS. Once the UVLO threshold on VBUS_CON is met, the nFET turns ON. If there is a short to
ground on VBUS_CON the OTG supply is expected to limit the current.
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD1S514 Family of devices offer VBUS port protection implementing UVLO and OVP, with an LDO supplied
VBUS_POWER pin to regulate an output supply pin of 3 mA at 5 V (except for TPD1S514, which follows VBUS_CON up
to 6.48 V, after which it is regulated to that voltage). The VBUS_POWER pin can be used to power the system from
an external source on VBUS_CON in case the system’s battery state cannot power the system.
9.2 Typical Applications
9.2.1 TPD1S514-1 USB 2.0/3.0 Case 1: Always Enabled
The EN pin can be tied to ground so that the nFET is ON when VUVLO < VBUS_CON < VOVP and an external
charger can power VBUS. VBUS_POWER should be tied to ground with a 1-μF capacitor for LDO stability. USB Inrush
Current compliance tests will need to be handled by the rest of the system since the start delays tDELAY and tSS
implement only after the device changes from disabled to enabled, or after any UVLO or OVP event.
TPD1S514x
VBUS_POWER
USB
connector
VBUS
VBUS_CON
VOUT
VBUS
VBUS_SYS
System load
DD+
ID
GND
EN
2.2 μF
1 μF
BAT
1 μF
GND
+ Battery
DD+
ID
PMIC
TPD4E110
Figure 10. Always on, TPD1S514-1
9.2.1.1 Design Requirements
For this example, use the following input parameters from Table 2.
Table 2. Design Parameters
DESIGN PARAMETERS
Signal range on VBUS_CON
Signal range on VBUS_SYS
Signal on EN
EXAMPLE VALUE
3.5 V – 5.9 V
3.9 V – 5.9 V
Tie to system ground plane
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9.2.1.2 Detailed Design Procedure
To begin the design process the designer needs to know the VBUS voltage range.
9.2.1.2.1 VBUS Voltage Range
The UVLO trip-point is a maximum 3.5 V and the OVP trip-point is a minimum 5.9 V. This provides some
headroom for the USB 2.0 specified minimum 4.4 V (Low-power) or 4.75 V (Full-power) and 5.25 V maximum; or
the USB 3.0 specified minimum 4.45 V and 5.25 V maximum.
9.2.1.2.2 Discharged Battery
Connecting EN to ground sets the part active at all times. OVP and UVLO are always active, even when the
system battery is fully discharged. In the case of a discharged system battery, VBUS_SYS can be used to power
the system when a source with voltage between VUVLO and VOVP is attached to VBUS_CON.
9.2.1.3 Application Curves
8
Voltage (V)
6
4
2
0
-2
-20E-3
VBUS_CON_Voltage (V)
VBUS_SYS_Voltage (S)
/EN_Voltage (S)
-10E-3
000E+0
10E-3
20E-3
30E-3
40E-3
50E-3
Time (s)
C001
Figure 11. VBUS_SYS Recovery Time From Over Voltage on VBUS_CON
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9
Voltage (V)
6
3
0
VBUS_CON
VBUS_SYS
-3
-100E-9
000E+0
100E-9
200E-9
300E-9
400E-9
500E-9
Time (s)
C003
Figure 12. OVP Response
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9.2.2 TPD1S514-1 USB 2.0/3.0 Case 2: PMIC Controlled EN
The TPD1S514 Family offers more flexibility to system designers to power up the system during a dead battery
condition. Refer to Figure 13, the VBUS_POWER pin supplies 4.95 V and 3 mA to power the PMIC in a dead battery
condition. Regardless of EN state, VBUS_POWER is available to the PMIC. Utilizing this power, the PMIC can
enable the TPD1S514 Family of devices when a valid VBUS_CON voltage is present.
TPD1S514x
VBUS_POWER
USB
Conenctor
VBUS
VBUS_CON
EN
VBUS_SYS
EN out
Power
VBUS
VOUT
System load
DD+
ID
GND
2.2 μF
1 μF
BAT
1 μF
GND
+ Battery
DD+
ID
PMIC
TPD4E110
Figure 13. PMIC Controlled EN, TPD1S514-1
9.2.2.1 Design Requirements
For this example, use the following table as input parameters:
Table 3. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Signal range on VBUS_CON
3.5 V – 5.9 V
Signal range on VBUS_SYS
3.9 V – 5.9 V
Drive EN low (enabled)
0 V – 0.8 V
Drive EN high (disabled)
1.2 V – 6.0 V
9.2.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon. The designer needs to know the
following:
•
•
VBUS voltage range
PMIC power requirement
9.2.2.2.1 VBUS Voltage Range
The UVLO trip-point is a maximum 3.5 V and the OVP trip-point is a minimum 5.9 V. This provides some
headroom for the USB 2.0 specified minimum 4.4 V (Low-power) or 4.75 V (Full-power) and 5.25 V maximum; or
the USB 3.0 specified minimum 4.45 V and 5.25 V maximum.
9.2.2.2.2 PMIC Power Requirement
The VBUS_POWER pin can source up to 3 mA of current and maintain a minimum 4.8 V, 4.95 V typical.
TPD1S514-1 design provides an LDO regulator supplied voltage source which can be used to provide power to a
PMIC when its internal battery supplied power is unavailable. When selecting a matching PMIC, ensure its power
requirement can be met by the VBUS_POWER pin if designing for this scenario.
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9.2.2.2.3 Discharged Battery
Powering the PMIC from VBUS_POWER allows logic control of the EN pin to set TPD1S514-1 active and begin
charging the battery and powering up the rest of the system.
9.2.2.3 Application Curve
8
Voltage (V)
6
4
2
0
-2
-20E-3
VBUS_CON_Voltage (V)
VBUS_SYS_Voltage (S)
/EN_Voltage (S)
-10E-3
000E+0
10E-3
20E-3
30E-3
40E-3
50E-3
Time (s)
C001
Figure 14. VBUS_SYS Recovery Time From Over Voltage on VBUS_CON
10 Power Supply Recommendations
The TPD1S514 Family is designed to receive power from a USB 3.0 (or lower) VBUS source. It can operate
normally (nFET ON) between a minimum 3.5 V and a maximum VOVP_MIN V. Thus, the power supply (with a
ripple of VRIPPLE) requirement for the TPD1S514 Family of devices to be able to switch the nFET ON is between
3.5 V + VRIPPLE and VOVP_MIN – VRIPPLE, where VOVP_MIN is:
Table 4. VOP_MIN Values
DEVICE NAME
VOVP_MIN
TPD1S514-1
5.90 V
TPD1S514-2
9.9 V
TPD1S514-3
13.5 V
TPD1S514
5.90 V
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11 Layout
11.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
VIA to Power Ground Plane
Power Ground
GND
VBUS_Power
EN
VBUS_CON
VBUS_SYS
VBUS_SYS
VBUS_CON
VBUS_CON
VBUS_SYS
GND
GND
GND
Power Ground
When designing layout for the TPD1S514 Family, note that VBUS_CON and VBUS_SYS pins allow extra wide traces for
good power delivery. In the example shown, these pins are routed with 50 mil (1.27 mm) wide traces. Place the
VBUS_CON, VBUS_SYS, and VBUS_POWER capacitors as close to the pins as possible. Use external and internal ground
planes and stitch them together with VIAs as close to the GND pins of TPD1S514 as possible. This allows for a low
impedance path to ground so that the device can properly dissipate any surge or ESD events.
Figure 15. Layout Recommendation
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12 Device and Documentation Support
12.1 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
TPD1S514-1YZR
Active
DSBGA
YZ
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
–40 to 85
RH5141
TPD1S514-2YZR
Active
DSBGA
YZ
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
–40 to 85
RH5142
TPD1S514-3YZR
Active
DSBGA
YZ
12
3000
Green (RoHS&
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
–40 to 85
RH5143
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
22
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13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPD1S514-1YZR
DSBGA
YZ
12
3000
180.0
8.4
1.39
2.09
0.75
4.0
8.0
Q2
TPD1S514-2YZR
DSBGA
YZ
12
3000
180.0
8.4
1.39
2.09
0.75
4.0
8.0
Q2
TPD1S514-3YZR
DSBGA
YZ
12
3000
180.0
8.4
1.39
2.09
0.75
4.0
8.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
24
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD1S514-1YZR
DSBGA
YZ
12
3000
182.0
182.0
20.0
TPD1S514-2YZR
DSBGA
YZ
12
3000
182.0
182.0
20.0
TPD1S514-3YZR
DSBGA
YZ
12
3000
182.0
182.0
20.0
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TPD1S514-xYZ
PACKAGE OUTLINE
YZ0012-C01
DSBGA - 0.625 mm max height
SCALE 7.000
DIE SIZE BALL GRID ARRAY
2.02
1.96
B
A
BALL A1
CORNER
1.32
1.26
0.625 MAX
C
SEATING PLANE
BALL TYP
0.30
0.12
0.05 C
1.2 TYP
0.4 TYP
C
SYMM
B
0.8
TYP
A
1
0.3
12X
0.2
0.015
C A
3
2
4
0.4 TYP
SYMM
B
4221703/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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TPD1S514x
SLVSCF6F – APRIL 2014 – REVISED MAY 2019
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TPD1S514-xYZ
EXAMPLE BOARD LAYOUT
YZ0012-C01
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
12X (
(0.4) TYP
0.225)
1
3
2
4
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.225)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221703/A 11/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
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Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPD1S514x
TPD1S514x
www.ti.com
SLVSCF6F – APRIL 2014 – REVISED MAY 2019
TPD1S514-xYZ
EXAMPLE STENCIL DESIGN
YZ0012-C01
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
12X ( 0.25)
1
2
3
4
A
(0.4) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4221703/A 11/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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Copyright © 2014–2019, Texas Instruments Incorporated
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