TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
SLVSAC2G – AUGUST 2010 – REVISED JUNE 2021
TPDxEUSB30 2-, 4-Channel ESD Protection for Super-Speed USB 3.0 Interface
1 Features
3 Description
•
•
•
The
TPD2EUSB30,
TPD2EUSB30A,
and
TPD4EUSB30 are 2 and 4 channel Transient Voltage
Suppressor (TVS) based Electrostatic Discharge
(ESD) protection diode arrays. The TPDxEUSB30/A
devices are rated to dissipate ESD strikes at the
maximum level specified in the IEC 61000-4-2
international standard (Contact). These devices also
offer 5 A (8/20 μs) peak pulse current ratings per IEC
61000-4-5 (Surge) specification.
•
•
•
•
Supports USB 3.0 data rates (5 Gbps)
IEC 61000-4-2 ESD protection (level 4 contact)
IEC 61000-4-5 surge protection
– 5 A (8/20 µs)
Low capacitance
– DRT: 0.7 pF (typical)
– DQA: 0.8 pF (typical)
Dynamic resistance: 0.6 Ω (typical)
Space-saving DRT, DQA packages
Flow-through pin mapping
2 Applications
•
•
•
•
•
Notebooks
Set-top boxes
DVD players
Media players
Portable computers
The TPD2EUSB30A offers low 4.5-V DC breakdown voltage. The low capacitance, low break-down
voltage, and low dynamic resistance make the
TPD2EUSB30A a superior protection device for highspeed differential IOs.
The TPD2EUSB30 and TPD2EUSB30A are offered
in space saving DRT (1 mm × 1 mm) package. The
TPD4EUSB30 is offered in space saving DQA (2.5
mm × 1.0 mm) package.
Device Information(1)
PART NUMBER
TPD2EUSB30
TPD2EUSB30A
TPD4EUSB30
(1)
PACKAGE
BODY SIZE (NOM)
SOT (3)
1.00 mm × 0.80 mm
USON (10)
2.50 mm × 1.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
D1+
D2+
D1-
D–
D+
D2-
GND
TPD4EUSB30 Circuit
GND
TPD2EUSB30/A Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
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SLVSAC2G – AUGUST 2010 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagrams......................................... 8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................8
8 Application and Implementation.................................... 9
8.1 Application Information............................................... 9
8.2 Typical Application...................................................... 9
9 Power Supply Recommendations................................11
10 Layout........................................................................... 11
10.1 Layout Guidelines................................................... 11
10.2 Layout Examples.................................................... 12
11 Device and Documentation Support..........................14
11.1 Receiving Notification of Documentation Updates.. 14
11.2 Support Resources................................................. 14
11.3 Trademarks............................................................. 14
11.4 Electrostatic Discharge Caution.............................. 14
11.5 Glossary.................................................................. 14
12 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2015) to Revision G (June 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed the Pin Functions table to clarify pin order and function..................................................................... 3
Changes from Revision E (August 2014) to Revision F (October 2015)
Page
• Moved the storage temperature to the Absolute Maximum Ratings table and updated the Handling Ratings
table to an ESD Ratings table.............................................................................................................................4
• Added test condition frequency to capacitance ................................................................................................. 5
Changes from Revision D (August 2012) to Revision E (July 2014)
Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
Changes from Revision C (December 2011) to Revision D (August 2012)
Page
• Updated Dynamic Resistance value...................................................................................................................1
• Updated Dynamic Resistance value...................................................................................................................5
Changes from Revision B (July 2011) to Revision C (December 2011)
Page
• Added Insertion Loss graphic to TYPICAL OPERATING CHARACTERISTICS section.................................... 6
Changes from Revision A (December 2010) to Revision B (July 2011)
Page
• Changed TOP-SIDE MARKING column in the Ordering Information Table .......................................................3
Changes from Revision * (August 2010) to Revision A (December 2010)
Page
• Added TPS2EUSB30A part to document........................................................................................................... 1
2
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5 Pin Configuration and Functions
D+
1
3
D–
D1+
1
10
N.C.
D1–
2
9
N.C.
GND
3
8
GND
D2+
4
7
N.C.
D2–
5
6
N.C.
GND
2
Figure 5-1. DRT Package 3-Pin SOT Top View
Figure 5-2. DQA Package 10-Pin USON Top View
Table 5-1. Pin Functions
PIN
NAME
TYPE
DRT
DQA
D1+
1
1
D1–
2
2
D2+
—
4
D2–
—
5
GND
3
3, 8
GND
—
6, 7,
9, 10
—
N.C.
ESD port
DESCRIPTION
High-speed ESD clamp, provides ESD protection to the high-speed differential
data lines.
Ground
Not normally connected
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
IO voltage (D+ and D- pins)
MIN
MAX
TPD2EUSB30, TPD4EUSB30
0
6
TPD2EUSB30A
0
4
IEC 61000-4-5 surge current (tp = 8/20 μs)
D+, D– pins
IEC 61000-4-5 surge peak power (tp = 8/20 μs)
D+, D– pins
UNIT
V
5
A
45
W
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–65
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
2500
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
1500
IEC 61000-4-2 Contact Discharge
D+, D– pins
8000
IEC 61000-4-2 Air-Gap Discharge (TPD2EUSB30/A)
D+, D– pins
8000
IEC 61000-4-2 Air-Gap Discharge (TPD4EUSB30)
D+, D– pins
9000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–40
85
TPD2EUSB30, TPD4EUSB30
0
5.5
TPD2EUSB30A
0
3.6
TA operating free-air temperature
Operating Voltage
UNIT
°C
V
6.4 Thermal Information
THERMAL METRIC(1)
TPD2EUSB30A
TPD4EUSB30
DRT (SOT)
DRT (SOT)
DQA (USON)
UNIT
3 PINS
3 PINS
10 PINS
RθJA
Junction-to-ambient thermal resistance
610.2
610.2
162.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
288.0
288.0
128.3
°C/W
RθJB
Junction-to-board thermal resistance
118.4
118.4
56.7
°C/W
ψJT
Junction-to-top characterization parameter
20.2
20.2
13.8
°C/W
ψJB
Junction-to-board characterization parameter
116.4
116.4
56.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
8.1
°C/W
(1)
4
TPD2EUSB30
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
Reverse stand-off voltage (D+ and
D- pins)
TPD2EUSB30, TPD4EUSB30
5.5
V
TPD2EUSB30A
3.6
V
Vclamp
Clamp voltage
D+,D– pins to ground,
IIO = 1 A
IIO
Current from IO port to supply pins
VIO = 2.5 V,
ID = 8 mA
VD
Diode forward voltage
D+,D– pins,
lower clamp diode,
VIO = 2.5 V,
ID = 8 mA
Rdyn
Dynamic resistance
D+,D– pins
I=1A
CIO-IO
Capacitance IO to IO
D+,D– pins
VIO = 2.5 V; ƒ = 100 kHz
0.6
D+,D– pins (DRT)
CIO-GND Capacitance IO to GND
VBR
D1+, D1-,
D2+, D2- (DQA )
8
V
0.01
0.1
μA
0.8
0.95
V
0.6
Ω
0.05
pF
0.7
VIO = 2.5 V; ƒ = 100 kHz
0.8
pF
Break-down voltage,
TPD2EUSB30, TPD4EUSB30
IIO = 1 mA
7
V
Break-down voltage,
TPD2EUSB30A
IIO = 1 mA
4.5
V
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6.6 Typical Characteristics
1.20E-12
10
TA = 25°C
5
1.10E-12
0
9.00E-13
Leakage Current (pA)
Capacitnace (Farads)
1.00E-12
DQA Package
8.00E-13
DRT Package
7.00E-13
–5
–10
–15
D–
–20
D+
–25
–30
6.00E-13
VIO = 2.5 V
–35
5.00E-13
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–40
5.0
55
25
Temperature (°C)
–40
Voltage (V)
TA = 25 °C
VIO = 2.5 V
Figure 6-1. IO Capacitance vs IO Voltage
Figure 6-2. Leakage Current vs Temperature
IPP (A)
11
55
10
5.0
50
4.5
45
4.0
40
3.5
35
3.0
30
2.5
25
Current (A)
9
8
7
6
5
4
2.0
20
1.5
15
3
1.0
10
2
Power (W)
0.5
5
1
0.0
0
0
5
10
15
20
25
30
Time (ms)
35
40
45
50
0
Figure 6-3. Peak Pulse Waveforms
100
20
90
10
80
0
70
-10
60
-20
Amplitude (V)
Amplitude (V)
5
10
15
20
Voltage (V)
25
30
35
40
Figure 6-4. D+,D– Transmission Line Pulser Plot for
TPD2EUSB30 (100 ns Pulse, 10 ns Rise Time)
Measured at one IO, the other IO open
50
40
30
-30
-40
-50
20
-60
10
-70
0
-80
-10
-90
-20
-100
0
25
50
75
100
Time (ns)
125
150
175
200
Figure 6-5. IEC Clamping Waveforms (8 kV Contact)
6
Current (A)
Measured at one IO,
the other IO open
5.5
60
PPP (W)
6.0
0
85
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0
25
50
75
100
Time (ns)
125
150
175
200
Figure 6-6. IEC Clamping Waveforms (–8 kV Contact)
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6.6 Typical Characteristics (continued)
3
Insertion Loss (dB)
0
–3
-3dB = 7.4Gbps
–6
–9
–12
1.0e+05
1.0e+06
1.0e+07
1.0e+08
1.0e+09
Bit per Second (BPS)
1.0e+10
1.0e+11
–3 dB = 7.4 Gbps
Figure 6-7. Insertion Loss
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7 Detailed Description
7.1 Overview
The TPD2EUSB30, TPD2EUSB30A, and TPD4EUSB30 are 2 and 4 channel Transient Voltage Suppressor
(TVS) based Electrostatic Discharge (ESD) protection diode arrays. The TPDxEUSB30/A devices are rated
to dissipate ESD strikes at the maximum contact level specified in the IEC 61000-4-2 international standard
(Contact). These devices also offer 5 A (8/20 μs) peak pulse current ratings per IEC 61000-4-5 (surge)
specification.
7.2 Functional Block Diagrams
D1+
D2+
D1D2-
GND
Figure 7-1. TPD4EUSB30 Circuit
D–
D+
GND
Figure 7-2. TPD2EUSB30/A Circuit
7.3 Feature Description
TPDxEUSB30/A is a family of uni-directional Electrostatic Discharge (ESD) protection devices with low
capacitance. Each IO line is rated to dissipate ESD strikes at or above the maximum level specified in the
IEC 61000-4-2 (Level 4 Contact) international standard. The TPDxEUSB30/A's low loading capacitance makes it
ideal for protection super speed high-speed signals.
7.4 Device Functional Modes
The TPDxEUSB30/A family of devices are passive integrated circuits that activate whenever voltages above
VBR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events,
voltages as high as ±8 kV (contact) can be directed to ground via the internal diode network. Once the voltages
on the protected lines fall below the trigger voltage of the device (usually within 10's of nano-seconds) the device
reverts to passive.
8
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPDxEUSB30/A family is a family of diode array type transient voltage suppressors (TVS) which are
typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human
interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop
is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS
holds this voltage, VCLAMP, to a tolerable level to the protected IC.
8.2 Typical Application
This application describes a TPDxEUSB30/A eye pattern test. Figure 10-2 shows the lab board that was
designed to demonstrate the degradation of the eye pattern quality with and without the TPD2EUSB30/A in the
USB 3.0 signal path. The measurements show that there is only ~2 ps jitter penalty to the differential signal
when the TPD2EUSB30/A device is added in the signal path. A similar setup was employed to measure the eye
diagram for the TPD4EUSB30.
Eye Pattern
Measurement Point
Pattern Generator
36” Lossy Transmission Line
TPD2EUSB30
USB3.0 Receiver PHY
Figure 8-1. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30/A
Eye Pattern
Measurement Point
Pattern Generator
36” Lossy Transmission Line
USB3.0 Receiver PHY
Figure 8-2. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30/A
8.2.1 Design Requirements
For this design example, a single TPD2EUSB30/A is used to protect a differential data pair lines, similar to a
USB 3.0 application. Given the USB application, the following parameters are known.
Table 8-1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on D+, and D–
0 V to 3.3 V
Operating Frequency
2.5 GHz
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8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
•
•
Signal range on all the protected lines
Operating frequency
8.2.2.1 Signal Range on D+, D- Pins
The TPD2EUSB30 has 2 pins which support 0 to 5.5 V and the TPD2EUSB30A has 2 pins which support 0 to
3.6 V.
8.2.2.2 Operating Frequency
The 0.7 pF (TPD2EUSB30/A typ) line capacitance supports data rates in excess of 5 Gbps.
8.2.3 Application Curves
Figure 8-3. Output Eye Diagram Without
TPD2EUSB30/A (Figure 8-2 Setup, 5 Gbps Data
Rate)
Figure 8-4. Output Eye Diagram With the
TPD2EUSB30/A (Figure 8-2 Setup, 5 Gbps Data
Rate)
Figure 8-5. Output Eye Diagram Without the TPD4EUSB30 (5 Gbps Data Rate)
Figure 8-6. Output Eye Diagram with the TPD4EUSB30 (5 Gbps Data Rate)
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9 Power Supply Recommendations
This family of devices are passive ESD protection devices and there is no need to power them. Care should be
taken to not violate the maximum voltage specification to ensure that the device functions properly. The D+ and
D– lines share a TVS diode which can tolerate up to 6 V.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
Refer to Figure 10-1, the TPD2EUSB30/A are offered in space saving DRT package. The DRT is a 1-mm ×
1-mm package with flow-through pin-mapping for the high-speed differential lines. The TPD4EUSB30 is offered
in space saving DQA package. The DQA is a 1-mm × 2.5-mm package with flow-through pin-mapping for the
high-speed differential lines. It is recommended to place the package right next to the USB 3.0 connector.
The GND pin should connected to GND plane of the board through a large VIA. If a dedicated GND plane is
not present right underneath, it is recommended to route to the GND plane through a wide trace. The current
associated with IEC ESD stress can be in the range of 30Amps or higher momentarily. A good, low impedance
GND path ensures the system robustness against IEC ESD stress.
The TPDxEUSB30/A can provide system level ESD protection to the high-speed differential ports (> 5 Gbps data
rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. It allows the
differential signal pairs couple together right after they touch the ESD ports of the TPDxEUSB30/A.
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10.2 Layout Examples
TX+
VBUS
TX-
TPD2EUSB30DRTR
D-
USB 3.0
Host/ Controller
1-mm
DGND
GND
8-mm
D+
D+
RX+
1-mm
GND
RX-
Three TPD2EUSB30 to Protect USB3.0 Class A connector (One Layer Routing)
TPD4EUSB30
D1+
TX+
VBUS
N.C.
TXD1-
GND
GND
D2+
N.C.
D2-
N.C.
2.5-mm
N.C.
D-
USB 3.0
Host/ Controller
GND
8-mm
D+
RX+
GND
RX-
1-mm
One TPD4EUSB30 & One TPD2EUSB30 to Protect USB3.0 Class A connec tor (Two Layer Routing)
Figure 10-1. TPDxEUSB30/A at the USB3.0 Class A Connector
12
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Figure 10-2. TPDxEUSB30/A EVM – TPD4EUSB30
Side
Figure 10-3. TPDxEUSB30/A EVM –
TPD2EUSB30/A Side
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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1-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD2EUSB30ADRTR
ACTIVE
SOT-9X3
DRT
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
5S
TPD2EUSB30DRTR
ACTIVE
SOT-9X3
DRT
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
5P
TPD4EUSB30DQAR
ACTIVE
USON
DQA
10
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(667, 66O, 66R, 66
V, BMR)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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