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TPD5S116
SLVSBP3C – DECEMBER 2012 – REVISED MAY 2015
TPD5S116 HDMI Companion Chip with ESD Protection, Level Shifting Buffers, 5V Load
Switch with Current Limit
1 Features
3 Description
•
TPD5S116 is a single-chip HDMI interface
Electrostatic Discharge (ESD) protection device with
auto-direction sensing I2C voltage level shifting
buffers and a 5-V HDMI compliant current limited load
switch. Other key features are hot-plug-detect and
Transient Voltage Suppression (TVS) with ESD
protection diodes. Each connector-side pin has a TVS
diode for circuit protection from ESD. An internal 3.3V node powers the CEC pin, eliminating the need for
a 3.3-V supply on board.
1
•
•
•
•
•
•
•
•
IEC 61000-4-2 Level 4 ESD Protection
– ±15-kV Contact Discharge on External Lines
– ±15-kV Air-gap Discharge on External Lines
Conforms to HDMI Control and 5VOUT
Compliance Tests without External Components
Supports HDMI1.3, HDMI1.4, and HDMI2.0
Standards
Auto-direction Sensing I2C Level Shifter with OneShot Circuit to Drive Long HDMI Cable (750-pF
Load)
Back Drive Protection
55-mA Load Switch with Current Limit for Short
Circuit Protection
Hot Plug Detect Module with Pull Down Resistor
Integrated Pull-up and Pull-down Resistors per
HDMI Specification
Utility Pin ESD Protection for Ethernet and Audio
Return
2 Applications
•
•
TPD5S116 integrates all external termination
resistors needed for the HPD, CEC, SCL, and SDA
lines. There are three non-inverting bi-directional
translation circuits for the SDA, SCL, and CEC lines.
Each has a common power rail (VCCA) on system
side from 1.1 V to 3.6 V. A 55-mA current limiting
switch regulates current sent from 5V_SYS to
5V_CON. The SCL and SDA pins meet the I2C
specification and can drive capacitive loads greater
than 750 pF, which exceeds HDMI2.0 specifications.
The HPD_CON port has a glitch filter to avoid false
detection due to plug bouncing during the HDMI
connector insertion.
The TPD5S116 offers reverse current blocking at the
5V_CON pin. In fault conditions, such as when two
HDMI transmitters are connected to the same HDMI
cable, TPD5S116 ensures that the system is safe
from powering up through an external HDMI
transmitter. The SCL_CON, SDA_CON, CEC_CON,
and HPD_CON pins also feature reverse-current
blocking, which ensures that the system sees no
leakage if an HDMI receiver is connected while the
system is powered off.
End Equipment
– Cell Phones
– eBook
– Portable Media Players
– Tablet
– Set Top Box
Interfaces
– HDMI
The EN pin enables the hot-plug detect and load
switch. The level shifters are enabled after a valid
HPD signal is detected.
Device Information(1)
PART NUMBER
TPD5S116
PACKAGE
DSBGA (15)
BODY SIZE (NOM)
2.13 mm x 1.33 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
5V
CPU
EN
CEC
SCL
SDA
HPD
UTILITY
TPD5S116
5V_SYS
EN
CEC_CON
CEC_SYS
SCL_CON
SCL_SYS
SDA_CON
SDA_SYS
5V_CON
HPD_SYS
HPD_CON
UTIL_CON
HDMI Conn
CEC
SCL
SDA
5V POWER
HPD
UTILITY
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD5S116
SLVSBP3C – DECEMBER 2012 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Voltage Level Shifter, SCL, SDA Lines..................... 7
Voltage Level Shifter, CEC Line ............................... 7
Voltage Level Shifter, HPD Line ............................... 8
EN ............................................................................. 8
Utility Pin ................................................................. 8
I/O Capacitances..................................................... 8
Dynamic Load Characteristics ................................ 9
SCL, SDA Lines, VCCA = 1.2 V ............................... 9
CEC Line, VCCA = 1.2 V.......................................... 9
HPD Line, VCCA = 1.2 V........................................ 10
SCL, SDA Lines, VCCA = 1.5 V ............................. 10
CEC Line, VCCA = 1.5 V........................................ 10
HPD Line, VCCA = 1.5 V........................................ 10
SCL, SDA Lines, VCCA = 1.8 V ............................. 11
CEC Line, VCCA = 1.8 V........................................ 11
HPD Line, VCCA = 1.8 V........................................ 11
8
11
12
12
12
12
13
13
13
13
14
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
9
SCL, SDA Lines, VCCA = 2.5 V .............................
CEC Line, VCCA = 2.5 V........................................
HPD Line, VCCA = 2.5 V........................................
SCL, SDA Lines, VCCA = 3.3 V .............................
CEC Line, VCCA = 3.3 V........................................
HPD Line, VCCA = 3.3 V........................................
SCL, SDA Lines, VCCA = 5 V ................................
CEC Line, VCCA = 5 V...........................................
HPD Line, VCCA = 5 V...........................................
Typical Characteristics ..........................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
21
Applications and Implementations .................... 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Requirements ............................. 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
5 Revision History
Changes from Revision B (April 2015) to Revision C
•
Page
Updated non-technical formatting........................................................................................................................................... 1
Changes from Revision A (March 2012) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Updated datasheet to reflect HDMI2.0 compliance. .............................................................................................................. 1
Changes from Original (December 2012) to Revision A
•
2
Page
Changed the YFF package dimensions ................................................................................................................................. 1
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SLVSBP3C – DECEMBER 2012 – REVISED MAY 2015
6 Pin Configuration and Functions
YFF Package
15-Pin DSBGA
Top View
Pin Assignments
1
2
3
CEC_SYS
VCCA
CEC_CON
B
SCL_SYS
GND
SCL_CON
C
SDA_SYS
EN
SDA_CON
A
D
5V_SYS
GND
5V_CON
E
HPD_SYS
UTI_CON
HPD_CON
Pin Functions
PIN
NAME
I/O
DSBGA
DESCRIPTION
5V_CON
D3
Output Power
5V_SYS
D1
Input Power
CEC_SYS
A1
IO Port
HDMI system-side CEC signal pin referenced to VCCA. Connect to HDMI
controller.
CEC_CON
A3
IO Port
HDMI connector-side CEC signal pin referenced to internal 3.3V supply.
Connect to HDMI connector CEC pin.
EN
C2
Control Input
B2, D2
Ground
Connect to System Ground Plane
HPD_SYS
E1
Output
HDMI system-side: Hot plug detect Output referenced to VCCA. Connect to
HDMI controller Hot plug detect input pin
HPD_CON
E3
Input
SCL_CON
B3
IO Port
HDMI connector-side SCL signal pin referenced to 5V_CON supply. Connect
to HDMI connector SCL pin.
SDA_CON
C3
IO Port
HDMI connector-side SDA signal pin referenced to 5V_CON supply.
Connect to HDMI connector SDA pin.
SCL_SYS
B1
IO Port
HDMI system-side SCL signal pin referenced to VCCA. Connect to HDMI
controller.
SDA_SYS
C1
IO Port
HDMI system-side SDA signal pin referenced to VCCA. Connect to HDMI
controller.
UTI_CON
E2
IO Port
Protects the HDMI connector's utility pin
VCCA
A2
Input Supply
GND
HDMI connector-side external 5V Supply; output of load switch
System-side PCB 5V supply; input of load switch
Disables the load switch and HPD when EN =L. The EN pin is referenced to
VCCA
HDMI connector-side: Hot plug detect Input. Connect directly to HDMI
Connector Hot Plug Detect pin
Internal PCB Low Voltage Supply (Same as the HDMI Controller Chip
Supply)
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCCA
Supply voltage range
–0.3
6
V
5V_SYS
Supply voltage range
–0.3
6
V
SCL_SYS, SDA_SYS, CEC_SYS, EN
–0.3
6
SCL_CON, SDA_CON, CEC_CON,
HPD_CON
–0.3
6
SCL_SYS, SDA_SYS, CEC_SYS,
HPD_SYS
–0.3
6
SCL_CON, SDA_CON, CEC_CON,
HPD_CON
–0.3
6
SCL_SYS, SDA_SYS,
CEC_SYS,HPD_SYS
–0.3
VCCA + 0.5
SCL_CON, SDA_CON, CEC_CON
–0.3
5V_SYS + 0.5
VI
Input voltage range (2)
VO
Voltage range applied to any output in the high-impedance or
power-off state (2) (3)
VO
Voltage range applied to any output in the high or low
state (2) (3)
UNIT
V
V
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
±100
mA
150
°C
Continuous current through 5V_SYS, or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air-gap ESD
(1)
(2)
4
All pins
UNIT
±2000
V
Pins SCL_CON,
SDA_CON, CEC_CON,
HPD_CON, 5V_CON,
UTI_CON
±15000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as 2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as 2000 V may actually have higher performance.
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SLVSBP3C – DECEMBER 2012 – REVISED MAY 2015
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCCA
Supply Voltage
1.1
5.5
V
5V_SYS
Supply Voltage
4.5
5.5
V
High-level input
voltage
VIH
Low-level input
voltage
VIL
SCL_SYS,
SDA_SYS,
VCCA = 1.1 V to 5.5 V
0.7 × VCCA
VCCA
V
CEC_SYS,
VCCA = 1.1 V to 5.5 V
0.7 × VCCA
VCCA
V
EN
VCCA = 1.1 V to 5.5 V
1
VCCA
V
SCL_CON,
SDA_CON,
5V_ SYS = 5.5 V
0.7 × 5V_SYS
5V_SYS
V
CEC_CON
5V_ SYS = 5.5 V
0.7 ×V3P3
V3P3
HPD_CON
5V_ SYS = 5.5 V
2
5V_SYS
SCL_SYS,
SDA_SYS,
VCCA = 1.1 V to 5.5 V
–0.5
0.082 × VCCA
V
CEC_SYS,
VCCA = 1.1 V to 5.5 V
–0.5
0.082 × VCCA
V
EN
VCCA = 1.1 V to 5.5 V
–0.5
0.4
V
SCL_CON,
SDA_CON,
5V_ SYS = 5.5 V
–0.5
0.3 × 5V_SYS
V
CEC_CON
5V_ SYS = 5.5 V
–0.5
0.3 × V3P3
V
HPD_CON
5V_ SYS = 5.5 V
0
0.8
V
VCCA = 1.1 V to 5.5 V
–0.5
0.0524 × VCCA
V
VCCA = 1.8 V
VILC
(contention) Lowlevel input voltage
SCL_SYS,
SDA_SYS,
CEC_SYS
VOL – VILC
Delta between VOL
and VILC
SCL_SYS,
SDA_SYS,
CEC_SYS
TA
Operating free-air temperature
0.1 × VCCA
mV
–40
85
°C
7.4 Thermal Information
TPDSS116
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
79.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.6
°C/W
RθJB
Junction-to-board thermal resistance
13
°C/W
ψJT
Junction-to-top characterization parameter
2.4
°C/W
ψJB
Junction-to-board characterization parameter
13
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) and VCCA = 1.1 V to 5.5 V and 5V_SYS = 5.5 V. Typical
values measured at VCCA = 1.8 V and 5V_SYS = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current
ICC5V
Disabled
5V_SYS =5V, 5V_CON =Open EN = GND,
HPD_CON = GND
2
10
µA
Load Switch active
5V_SYS =5V, 5V_CON =Open EN = VCCA,
HPD_CON = GND
30
50
µA
Active
5V_SYS =5V, 5V_CON =Open EN = VCCA,
HPD_CON = 5V
125
200
µA
Reverse voltage comparator trip point
5V_SYS=4V, 5V_CON > 5V_SYS
100
Load Switch
VREV
IOFF
Leakage Current
mV
5V_CON = 0V, 5V_SYS = 5 V , EN = GND,
HPD_CON = GND Measured at 5V_SYS
pin.
1
5
µA
5V_CON = 0V, 5V_SYS= 5 V , EN = GND,
HPD_CON = 5 V Measured at 5V_SYS pin
1
5
µA
5V_CON = 5V, 5V_SYS = 0 V , EN = GND,
HPD_CON = GND Measured at 5V_CON
pin.
1
5
µA
5V_CON = 5V, 5V_SYS = 0 V EN = GND,
HPD_CON = 5 V Measured at 5V_CON
pin.
1
5
µA
5V_CON = 5V, 5V_SYS = 0 V, EN=VCCA,
HPD_CON = GND Measured at 5V_CON
pin.
1
5
µA
5V_CON = 5 V, 5V_SYS = 0 V, EN = VCCA,
HPD_CON = 5 V Measured at 5V_CON
pin.
1
5
µA
140
170
mA
ISC
Short circuit current at 5V_CON
5V_SYS = 5 V, 5V_CON = GND
TDEGLITCH
Deglitch time against false short
5V_SYS = 5 V , EN = VCCA, Short 5V_CON
110
UVLO
3
µs
Under voltage lockout rising
5V_SYS = 0 V to 5 V, RL = 100 Ω, CL = 1
µF
2.85
V
UVLO_HYS
Under voltage lockout falling hysteresis
5V_SYS = 5 V to 0 V, RL = 100 Ω, CL = 1
µF
200
mV
VDROP
5V_OUT output voltage drop
5V_SYS = 5 V, I5V_OUT = 55 mA
38.5
IRUSH
Inrush Current
5V_SYS = 5 V, RL = 100 Ω, Cin=10uF, C =
1 µF
140
mA
TON
Turn on Time, EN to 5V_CON
5V_SYS = 5 V, RL = 100 Ω, Cin=10uF, C =
1 µF
92.3
µs
TOFF
Turn off Time, EN to 5V_CON
5V_SYS = 5 V, RL = 100 Ω, Cin=10uF, C =
1 µF
5
µs
TSHUT
(1)
(2)
6
Thermal Shutdown
Shutdown threshold, TRIP
(1)
HYST (2)
166
23
55
mV
°C
The TPD5S116 turns off after the device temperature reaches the TRIP temperature.
Once the thermal shut-down circuit turns off the load switch, the switch turns on again after the device junction temperature cools down
to a temperature equals to or less than TRIP-HYST.
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7.6 Voltage Level Shifter, SCL, SDA Lines
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH_SYS
IOH = –10 µA
VI = VIH
VOL_SYS
IOL = 10 µA
VI = VIL
VOH_CON
IOH = –10 µA
VI = VIH
VOL_CON
IOH = 3 mA
VI = VIL
VCCA
MIN
TYP
0.8 × VCCA
0.8 x
5V_SYS
0.3
ΔVT Hysteresis at the SDx_IN
(VT+ - VT-)
ΔVT Hysteresis at the SDx_OUT
(VT+ - VT-)
V
0.17 ×
VCCA
V
5V_SYS+
0.02
V
0.4
V
400
mV
SCL_CON,
SDA_CON
Pull-up
connected to 5V
rail
1.75
IPULLUPAC Transient Boosted Pull- SCL_CON,
up Current (rise-time accelerator) SDA_CON
Pull-up
connected to 5V
rail
13
IOZ
VCCA +
0.02
mV
Pull-up
connected to
VCCA rail
Ioff
UNIT
40
SCL_SYS,
SDA_SYS
RPU (Internal pull-up)
MAX
5
kΩ
mA
SYS Port
VCCA = 0V, VI or VO = 0 to 3.6 V
0V
±5
CON Port
5V_CON=0V, VI or VO = 0 to 5.5 V
0V
±5
SYS Port
VI = VCCI or GND
µA
±5
7.7 Voltage Level Shifter, CEC Line
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH_SYS
IOH = –10 µA
VI = VIH
VOL_SYS
IOL = 10 µA
VI = VIL
VOH_CON
IOH = –10 µA
VI = VIH
VOL_CON
IOH = 3 mA
VI = VIL
VCCA
MIN
TYP
0.8 × VCCA
MAX
UNIT
VCCA +
0.02
V
0.17 ×
VCCA
V
0.8 x V3P3
V
0.3
0.4
V
ΔVT Hysteresis at the CEC_SYS
(VT+ - VT-)
30
mV
ΔVT Hysteresis at the CEC_CON
(VT+ - VT-)
283
mV
5
kΩ
CEC_SYS
Pull-up
connected to
VCCA rail
CEC_CON
Pull-up
connected to
3.3V rail
CEC_CON
Pull-down
connected
connector-side
RPU (Internal pull-up)
RPD (Internal pull-down)
Ioff
IOZ
22
26
30
10
kΩ
MΩ
SYS Port
VCCA = 0V, VI or VO = 0 to 3.6 V
0V
±5
CON Port
5V_CON=0V, VI or VO = 0 to 5.5 V
0V
±1.8
SYS Port
VI = VCCI or GND
µA
±5
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7.8 Voltage Level Shifter, HPD Line
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
MIN
TYP
MAX
UNIT
VOH_SYS
IOH = 1 mA
VI = VIH
1.2 V to 5.0 V
VCCA × 0.7
VOH_SYS_1P1
IOH = 100 µA
VI = VIH
1.1 V
VCCA × 0.7
VOL_SYS
IOL = 3 µA
VI = VIL
1.2 V to 5.0 V
0.4
V
VOL_SYS_1P1
IOL = 3 mA
VI = VIL
1.1 V
0.68
V
ΔVT Hysteresis at the CEC_CON
(VT+ - VT-)
V
V
1.2 V to 5.0 V
500
mV
RPD_IN (Input internal pull-down
resistor)
Pull-down
connected to
GND
60
100
140
kΩ
RPD_OUT (Output internal pulldown resistor)
Pull-down
connected to
GND
60
100
140
kΩ
Glitch Filter
Duration
TFILT
HPD_CON = 5 V, EN = VCCA,
Short HPD_SYS
10
µs
7.9 EN
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RPD
EN
(Internal pull-down
resistor)
TEST CONDITIONS
VCCA
Pull-down connected to GND
1.8 V
MIN
TYP
MAX
UNIT
470
kΩ
7.10 Utility Pin
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VRWM
DESCRIPTION
TEST CONDITIONS
VCLAMP
TYP
MAX
6
Clamp voltage with ESD strike
IPP = 1 A, tp = 8/20 μSec, from
I/O to GND (1)
8
IPP = 5 A, tp = 8/20 μSec, , from
I/O to GND (1)
10
RDYN
Dynamic resistance
UTI pin to GND Pin (2)
CUTI
Line capacitance
VIO=0V, f=1GHz, I/O to GND
VBR
Break-down voltage
IIO = 1mA
ILEAK
Leakage current
VIO = 3V
(1)
(2)
MIN
Reverse stand-off voltage
UNIT
V
V
0.33
Ω
5.5
pF
7
V
1
10
TYP
MAX
nA
Non-repetitive current pulse 8/20us exponentially decaying waveform according to IEC 61000-4-5
Extraction of RDYN using least squares fit of TLP characteristics between I=10A and I=20A
7.11 I/O Capacitances
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITONS
SUPPLY & EN
SIGNAL
MIN
UNIT
CI
EN
VBIAS = VCCA/2, f = 1 MHz, 30 mV p-p AC
signal
8
9
pF
CI
HPD_CON
VBIAS = 0 V – 5 V , f = 1 MHz, 30 mV p-p
AC signal
7
7.5
pF
8
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I/O Capacitances (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SUPPLY & EN
SIGNAL
TEST CONDITONS
MIN
TYP
MAX
UNIT
SYS port
VBIAS = 1.8 V, f = 1 MHz, 30 mV p-p AC
signal
6.5
9.5
pF
CON port
VBIAS = 2.5 V, f = 1 MHz, 30 mV p-p AC
signal
15
20
pF
SCL_CON, SDA_CON
VBIAS = 2.5V, f = 100 kHz, 3.5 V p-p AC
signal
VCCA= 3.6 V, 5V_SYS
= 5 V, EN =
HPD_CON = 0 V
17
pF
CEC_CON
VBIAS = 1.65 V, f = 100 kHz, 2.5 V p-p
AC signal
VCCA= 3.6 V, 5V_SYS
= 5 V,
EN=HPD_CON = 0 V
13
pF
CEC_CON
VBIAS = 1.65 V, f = 100 kHz, 2.5 V p-p
AC signal
VCCA= 0 V 5V_SYS =
0 V EN = HPD_CON
=0V
12
pF
CIO
7.12 Dynamic Load Characteristics
Propagation delays measured from 50% threshold to 50% threshold, Rise time measured from 30% to 70% threshold, Fall
time measured from 70% to 30% threshold
PARAMETER
CL
TEST CONDITION
MIN
TYP
MAX
Bus Load Capacitance (connectorside)
UNIT
750
Bus Load Capacitance (System Side)
pF
30
7.13 SCL, SDA Lines, VCCA = 1.2 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.2 V
PARAMETER
TPHL
Propagation Delay
TPLH
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
DDC Channels Enabled
316
ns
CON to SYS
DDC Channels Enabled
286
ns
SYS to CON
DDC Channels Enabled
489
ns
CON to SYS
DDC Channels Enabled
199
ns
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
110
ns
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
229
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
FMAX
Maximum Switching Frequency
DDC Channels Enabled
86
ns
400
kHz
7.14 CEC Line, VCCA = 1.2 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.2 V
PARAMETER
TPHL
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
CEC Channels Enabled
436
CON to SYS
CEC Channels Enabled
97
ns
ns
SYS to CON
CEC Channels Enabled
13.8
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
319
ns
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
37
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
114
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
234
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
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7.15 HPD Line, VCCA = 1.2 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.2 V
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
CON to SYS
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
14
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
18
ns
7.16 SCL, SDA Lines, VCCA = 1.5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.5 V
PARAMETER
TPHL
Propagation Delay
TPLH
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
DDC Channels Enabled
297
ns
CON to SYS
DDC Channels Enabled
224
ns
SYS to CON
DDC Channels Enabled
473
ns
CON to SYS
DDC Channels Enabled
193
ns
87
ns
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
226
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
86
ns
FMAX
Maximum Switching Frequency
DDC Channels Enabled
400
kHz
7.17 CEC Line, VCCA = 1.5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.5 V
PARAMETER
TPHL
TPLH
Propagation Delay
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
CEC Channels Enabled
419
CON to SYS
CEC Channels Enabled
102
ns
ns
SYS to CON
CEC Channels Enabled
13.7
µs
CON to SYS
CEC Channels Enabled
314
ns
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
39
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
115
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
230
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
7.18 HPD Line, VCCA = 1.5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.5 V
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
CON to SYS
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
8
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
9.5
ns
10
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7.19 SCL, SDA Lines, VCCA = 1.8 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.8 V
PARAMETER
TPHL
TPLH
Propagation Delay
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
DDC Channels Enabled
292
ns
CON to SYS
DDC Channels Enabled
192
ns
SYS to CON
DDC Channels Enabled
466
ns
CON to SYS
DDC Channels Enabled
190
ns
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
75
ns
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
224
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
FMAX
Maximum Switching Frequency
DDC Channels Enabled
86
ns
400
kHz
7.20 CEC Line, VCCA = 1.8 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 1.8 V
PARAMETER
TPHL
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
CEC Channels Enabled
417
CON to SYS
CEC Channels Enabled
108
ns
ns
SYS to CON
CEC Channels Enabled
13.7
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
312
ns
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
41
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
114
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
228
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
7.21 HPD Line, VCCA = 1.8 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5V; VCCA = 1.8 V
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
CON to SYS
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
5.5
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
7
ns
7.22 SCL, SDA Lines, VCCA = 2.5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 2.5 V
PARAMETER
TPHL
TPLH
Propagation Delay
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
DDC Channels Enabled
291
ns
CON to SYS
DDC Channels Enabled
154
ns
SYS to CON
DDC Channels Enabled
455
ns
CON to SYS
DDC Channels Enabled
186
ns
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
64
ns
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
221
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
FMAX
Maximum Switching Frequency
DDC Channels Enabled
86
400
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kHz
11
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7.23 CEC Line, VCCA = 2.5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 2.5 V
PARAMETER
TPHL
TPLH
Propagation Delay
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
CEC Channels Enabled
421
CON to SYS
CEC Channels Enabled
122
ns
ns
SYS to CON
CEC Channels Enabled
13.7
µs
CON to SYS
CEC Channels Enabled
311
ns
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
49
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
114
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
225
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
7.24 HPD Line, VCCA = 2.5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 2.5 V
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
CON to SYS
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
4
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
5
ns
7.25 SCL, SDA Lines, VCCA = 3.3 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 3.3 V
PARAMETER
TPHL
Propagation Delay
TPLH
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
DDC Channels Enabled
292
ns
CON to SYS
DDC Channels Enabled
133
ns
SYS to CON
DDC Channels Enabled
449
ns
CON to SYS
DDC Channels Enabled
184
ns
57
ns
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
218
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
86
ns
FMAX
Maximum Switching Frequency
DDC Channels Enabled
400
kHz
7.26 CEC Line, VCCA = 3.3 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 3.3 V
PARAMETER
TPHL
TPLH
Propagation Delay
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
CEC Channels Enabled
428
CON to SYS
CEC Channels Enabled
138
ns
ns
SYS to CON
CEC Channels Enabled
13.7
µs
CON to SYS
CEC Channels Enabled
309
ns
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
59
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
114
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
223
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
12
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7.27 HPD Line, VCCA = 3.3 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 3.3 V
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
CON to SYS
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
3
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
3.5
ns
7.28 SCL, SDA Lines, VCCA = 5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 5 V
PARAMETER
TPHL
Propagation Delay
TPLH
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
DDC Channels Enabled
298
ns
CON to SYS
DDC Channels Enabled
113
ns
SYS to CON
DDC Channels Enabled
442
ns
CON to SYS
DDC Channels Enabled
182
ns
52
ns
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
217
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
86
ns
FMAX
Maximum Switching Frequency
DDC Channels Enabled
400
kHz
7.29 CEC Line, VCCA = 5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 5 V
PARAMETER
TPHL
TPLH
Propagation Delay
Propagation Delay
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYS to CON
CEC Channels Enabled
446
CON to SYS
CEC Channels Enabled
169
ns
ns
SYS to CON
CEC Channels Enabled
13.7
µs
CON to SYS
CEC Channels Enabled
306
ns
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
82
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
114
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
221
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
7.30 HPD Line, VCCA = 5 V
over operating free-air temperature range (unless otherwise noted) and 5V_CON = 5 V; VCCA = 5 V
PARAMETER
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
CON to SYS
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
2.5
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
2.5
ns
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7.31 Typical Characteristics
7
210
180
6
180
150
5
150
4
120
3
90
2
60
1
30
0
0
±40
0
±20
20
40
60
80
100
120
140
120
3
90
0
±30
±40
0
±20
20
40
60
80
100
120
140
160
Time ( s)
C001
C002
Figure 2. Enable to Short Circuit
9
45
Rd
90
Current
8
80
Power
35
7
70
30
6
60
5
50
4
40
3
30
2
20
Current (A)
Current (A)
30
0
Figure 1. Power up to Short Circuit
40
60
±1
160
Time ( s)
EN
5V_SYS
5V_CON
Isc
2
1
±30
±1
4
25
20
Power (W)
Voltage (V)
5
210
Voltage (V)
5V_SYS
5V_CON
Isc
6
Current (mA)
7
Current (mA)
At TA = 25°C, unless otherwise noted.
15
10
5
1
10
0
0
0
0
0
3
6
9
12
15
18
21
24
Voltage (V)
27
5
10
15
20
30
25
30
35
40
45
50
Time ( s)
C004
Figure 4. Utility Pin Surge Curves
C003
Figure 3. Utility Pin TLP Curve
3
60
0
50
40
Amplitude (V)
Gain (dB)
±3
±6
±9
±12
0
±18
±10
1M
10M
100M
1G
Frequency (Hz)
10G
±25
0
25
50
75
100
125
Time (ns)
C005
Figure 5. Utility Pin Insertion Loss
14
20
10
±15
±21
100k
30
150
175
200
225
C006
Figure 6. Utility Pin, +8kv IEC Voltage Clamp Waveform
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
1.0
10
0.8
0
0.6
Input Current (mA)
Amplitude (V)
±10
±20
±30
±40
0.4
0.2
0.0
±0.2
±0.4
±0.6
±50
±0.8
±60
±1.0
±25
0
25
50
75
100
125
150
175
200
225
Time (ns)
0
±2
8
10
12
14
C008
Figure 8. Utility Pin IV Curve
TA = 25C
ISWITCH | 55 mA
900
Switch Resistance (m
V5V_CON (V)
6
1000
5V_SYS = 4.5V
5V_SYS = 5.0V
800
700
600
500
400
300
200
100
5V_SYS = 5.5V
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
±40
2.0
VEN Input Voltage (V)
5.0
4.0
0
20
40
60
80
Temperature (C)
C010
Figure 10. RDS for ISWITCH
2.0
4.5V
5.0V
5.5V
4.5
±20
C009
Figure 9. EN VTH
EN Low
EN High
1.8
VCCA = 3.3 V
V5V_SYS = 0 V
1.6
3.5
1.4
I5V_CON ( A)
I5V_SYS ( A)
4
Input Voltage (V)
Figure 7. Utility Pin, -8kv IEC Voltage Clamp Waveform
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
2
C007
3.0
2.5
2.0
1.2
1.0
0.8
1.5
0.6
1.0
0.4
0.5
0.2
0.0
0.0
±40
±20
0
20
40
60
Temperature (C)
80
0.0
C011
Figure 11. I5V_SYS vs. Temperature
1.0
2.0
3.0
4.0
V5V_CON (V)
5.0
C012
Figure 12. Reverse Switch Current
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
6
200
5
4
160
4
160
3
120
3
120
2
80
2
80
1
CIN = 10 F
CLOAD = 1 F
VCCA = 3.3 V
V5V_SYS = 0 V
0
±1
40
1
0
0
±40
±40
±20
0
20
40
60
80
100
120
140
Time ( s)
±1
±100 ±50
160
C013
Figure 13. IINRUSH Waveform
16
240
EN
5V_SYS
Iinrush
200
Current (mA)
Voltage (V)
5
Voltage (V)
240
EN
5V_SYS
Iinrush
Current (mA)
6
40
CIN = 4.7 F
CLOAD = 4.7 F
VCCA = 3.3 V
V5V_SYS = 0 V
0
±40
0
50
100
150
200
250
300
350
Time ( s)
400
C014
Figure 14. IINRUSH Waveform
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8 Detailed Description
8.1 Overview
TPD5S116 is a single-chip HDMI interface electrostatic discharge (ESD) protection product with auto-direction
sensing I2C voltage level shift buffers, a 5-V HDMI compliant current limited load switch, hot-plug-detect, and
transient voltage suppression (TVS) with ESD protection diodes. Each connector-side pin has a TVS diode for
circuit protection from ESD. The device pin mapping can be routed to either an HDMI Type D or Type C
connector. An internal 3.3-V node powers the CEC pin, eliminating the need for a 3.3-V supply on board.
TPD5S116 integrates all of the external termination resistors at the HPD, CEC, SCL, and SDA lines. There are
three non-inverting bidirectional translation circuits for the SDA, SCL, and CEC lines. Each has a common power
rail (VCCA) on system-side from 1.1 V to 3.6V. A 55-mA current limiting switch regulates current sent from
5V_SYS to 5V_CON. The SCL and SDA pins meet the I2C specification and can drive capacitive loads greater
than 750 pF, which exceeds HDMI2.0 specifications. The HPD_CON port has a glitch filter to avoid false
detection due to plug bouncing during the HDMI connector insertion.
The TPD5S116 offers reverse current blocking at the 5V_CON pin. In fault conditions, such as when two HDMI
transmitters are connected to the same HDMI cable, TPD5S116 ensures that the system is safe from powering
up through external HDMI transmitter. The SCL_CON, SDA_CON, CEC_CON, and HPD_CON pins also feature
reverse-current blocking, which ensures that the system sees no leakage if an HDMI receiver is connected while
the system is powered off.
The EN pin enables the hot-plug detect and load switch. The level shifters are enabled after a valid HPD signal is
detected.
8.2 Functional Block Diagram
470 kΩ
100 kΩ
100 kΩ
3.3 V (Internal)2
5 kΩ
1.75 kΩ
5 kΩ
5 kΩ
1.75 kΩ
26 kΩ
10 MΩ
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8.3 Feature Description
8.3.1 IEC 61000-4-2 Level 4 ESD Protection
In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level
ESD strikes. In these cases, the TPD5S116 provides the desired system-level ESD protection, such as the IEC
61000-4-2 Level 4 ESD protection of ±15-kV Contact and Air-gap ratings by absorbing the energy associated
with the ESD strike.
8.3.2 Conforms to HDMI Control and 5VOUT Compliance Tests Without External Components
The TPD5S116 is designed to be fully compliant to the HDMI 7-13 Compliance Test. See HDMI Compliance for
a detailed procedure.
8.3.3 Auto-direction Sensing I2C Level Shifter with One-Shot Circuit to Drive Long HDMI Cable (750-pF
Load)
The TPD5S116 contains three bidirectional open-drain buffers specifically designed to support up-translation/
down-translation between the low voltage, VCCA side DDC-bus and the 5-V DDC-bus or 3.3-V CEC line. The
HDMI cable side of the DDC lines incorporates rise-time accelerators to support a high capacitive load on the
HDMI cable side. The rise time accelerators boost the cable side DDC signal independent of which side of the
bus is releasing the signal.
8.3.4 Back Drive Protection
The TPD5S116 offers reverse current blocking at the 5V_CON pin. In fault conditions, such as when two HDMI
transmitters are connected to the same HDMI cable, TPD5S116 ensures that the system is safe from powering
up through an external HDMI transmitter. The SCL_CON, SDA_CON, CEC_CON, and HPD_CON pins also
feature reverse-current blocking, which ensures that the system sees no leakage if an HDMI receiver is
connected while the system is powered off.
8.3.5 55-mA Load Switch with Short Circuit Protection
A 55-mA current limiting switch regulates current sent from 5V_SYS to 5V_CON. This provides protection from a
short-circuit or excessive load when there is a fault condition, such as a defective HDMI cable.
8.3.6 Hot Plug Detect Module with Pull Down Resistor
Once TPD5S116 is enabled and the system’s 5-V source is on, TPD5S116 is ready for continual HDMI receiver
detection. When an HDMI cable connects a receiving and transmitting device together, the 5 V on the load
switch (5V_CON) flows through the receiving device’s internal resistor and into HPD’s input (HPD_CON). The
HPD buffer’s output (HPD_SYS) then goes high, indicating to the transmitter that a receiving device is
connected. To save power, periodic detection can be done by turning on and off the TPD5S116 before a
receiving device is connected. HPD_CON port has a glitch filter to avoid false detection due to plug bouncing
during the HDMI connector insertion. An integrated pull-down resistor for HPD_CON eliminates the need for an
additional external component.
8.3.7 Integrated Pull-up and Pull-down Resistors per HDMI Specification
The system is designed to work properly according to the HDMI 2.0 specification with no external pull-up
resistors on the DDC, CEC, and HPD lines.
8.3.8 Utility Pin ESD Protection for Ethernet and Audio Return
A TVS is provided for the Utility Pin in the HDMI connector. This pin should be routed to the TPD5S116 for
proper ESD protection regardless of whether Utility is used in the application.
8.3.9 DDC/CEC LEVEL SHIFT Circuit Operation
The TPD5S116 enables DDC translation from VCCA (system-side - Port A in Figure 15) voltage levels to 5-V
(HDMI connector-side - Port B in Figure 15) voltage levels without degradation of system performance. The
TPD5S116 contains two bidirectional open-drain buffers specifically designed to support up-translation/downtranslation between the low voltage, VCCA side DDC-bus and the 5-V DDC-bus. The connector port I/Os are overvoltage tolerant to 5.5 V, even when the device is un-powered. After power-up and with enable pin and
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Feature Description (continued)
HPD_CON pin HIGH, a LOW level on the system port (below approximately VILC = 0.08 × VCCA V) turns the
connector port driver (either SDA or SCL) on and drives port B down to VOL_CON V. When the system port rises
above approximately 0.10 × VCCA V, the connector port pull-down driver is turned off and the internal pull-up
resistor pulls the pin HIGH. When the connector port falls first and goes below 0.3 × 5 V_CON V, a CMOS
hysteresis input buffer detects the falling edge, turns on the system port driver, and pulls port A down to
approximately VOLA. The connector port pull-down is not enabled unless the system port voltage goes below VILC,
in which case the connector port pull-down driver is enabled until system port rises above (VILC + ΔVT-HYSTA). If
the connector port is not externally driven LOW, its voltage will continue to rise due to the internal pull-up
resistor.
5VOUT
VCCA
IACCEL
CMP1
CMP2
ACCEL
700mV
RPUB
RPUA
150mV
Port A
GLITCH
FILTER
Port B
DDC
Lines
Only
l
300mV
Figure 15. DDC/CEC Level Shifter Block Diagram
8.3.10 DDC/CEC Level Shifter Operational Notes For VCCA = 1.8V
• The threshold of CMP1 is ~150 mV +/- the 40mV of total hysteresis.
• The comparator will trip for a falling waveform at ~130mV
• The comparator will trip for a rising waveform at ~170mV
• To be recognized as a zero, the level at system port must first go below 130mV (VILC in spec) and then stay
below 170mV (VIL_SYS in spec)
• To be recognized as a one, the level at system port must first go above 170mV and then stay above 130mV
• VILC is set to 110mV in Electrical Characteristics Table to give some margin to the 130mV
• VIL_SYS is set to 140mV in the Electrical Characteristics Table to give some margin to the 170mV
• VIH_SYS is set to 70% of VCCA to be consistent with standard CMOS levels
Figure 16. DDC Level Shifter Operation (Connector To System Direction)
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Feature Description (continued)
8.3.11
Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on
the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of
the bus is releasing the signal.
8.3.12
Noise Considerations
Ground offset between the TPD5S116 ground and the ground of devices on the system port of the TPD5S116
must be avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3
mA of current at 0.4 V will have an output resistance of 133Ω or less (R = E / I). Such a driver will share enough
current with the system port output pull-down of the TPD5S116 to be seen as a LOW as long as the ground
offset is zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since VILC can be
as low as 90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset
should not exceed 50 mV. Bus repeaters that use an output offset are not interoperable with the system port of
the TPD5S116 as their output LOW levels will not be recognized by the TPD5S116 as a LOW. If the TPD5S116
is placed in an application where the VIL_SYS does not go below VILC, it will pull connector port LOW initially when
system port input transitions LOW but the connector port will return HIGH, so it will not reproduce the system port
input on connector port. Such applications should be avoided. The connector port is interoperable with all I2Cbus slaves, masters and repeaters.
8.3.13 HDMI Compliance
The TPD5S116 is designed to be fully compliant to the HDMI 7-13 capacitance specification. Both power on and
power off capacitance measurements are done on the CEC, SDA, and SCL connector-side pins using a Hioki
3522-50 meter. In the power on setup, connect TPD5S116’s EN and HPD_CON pins low and 5V_SYS and VCCA
pins high. Use the Hioki meter to measure the test fixture with and without the TPD5S116 and subtract to obtain
the capacitance. In the power off setup, connect TPD5S116’s EN, HPD_CON, 5V_SYS, and VCCA pins low and
conduct the same test with the Hioki meter. Read the Cp result from the Hioki meter.
• SCL_CON, SDA_CON Test:
– Measure the large signal capacitance at SCL_CON & SDA_CON pins at either power-up or power down
conditions:
– VBIAS = 2.5 V
– f = 100 kHz
– 3.5 V p-p ac signal
• CEC Test:
– Measure the large signal capacitance of the CEC_CON pin at both power-up and power down conditions:
– VBIAS = 1.65 V,
– f = 100 kHz
– 2.5V p-p ac signal
2.5V P-P
1.65V DC BIAS
F= 100KHz
3.5V P-P
2.5V DC BIAS
F= 100KHz
Figure 17. Hioki Meter Signal Set-Up For Scl, Sda Cap
Measurement
20
Figure 18. Hioki Meter Signal Set-Up For Cec Cap
Measurement
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8.4 Device Functional Modes
HDMI Driver Chip is controlling the TPD5S116 via only one control line (EN). The DDC and CEC level shifting
buffers become active after HPD_CON receives a valid high signal and EN is high. EN and HPD_CON control
the TPD5S116 power saving options according to the following table:
Table 1. Function Table – Power Saving Options
HPD_CO
N
EN
VCCA
5V_SYS
5V_CON
Dxx_SYS
CEC_SYS
Pull-ups
DCC_C
ON
Pull-ups
CEC_CO
N
Pull-ups
CEC
LDO
LOAD SW
& HPD
DCC/CEC
VLTs
ICCA
Typ
ICC5V
Typ
Comments
L
L
1.2V –
5.0V
5.0V
High-Z
Off
Off
Off
Off
Off
Off
1µA
2µA
Fully
Disabled
L
H
1.2V –
5.0V
5.0V
5.0V
On
On
Off
Off
On
Off
1µA
30µA
Load Switch
on
H
L
1.2V –
5.0V
5.0V
High-Z
Off
Off
Off
Off
Off
Off
1µA
2µA
Not Valid
State
H
H
1.2V –
5.0V
5.0V
5.0V
On
On
On
On
On
On
24µA
125µA
Fully On
X
X
0V
0V
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power
Down
X
X
1.2V –
5.0V
0V
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
1
0
Power
Down
X
X
0V
5.0V
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
0
1
Power
Down
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9 Applications and Implementations
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
TPD5S116 provides IEC 61000-4-2 Level 4 Contact ESD rating to the HDMI 2.0 transmitter port, with backwards
compatibility. Buffered voltage level translators (VLT) translate DDC and CEC channels bidirectionally. The
system is designed to work properly with no external pull-up resistors on the DDC, CEC, and HPD lines. The
CEC line has an integrated 3.3-V rail, eliminating the need for a 3.3-V supply on board.
9.2 Typical Application
The TPD5S116 is placed as close as possible to the HDMI connector to provide voltage level translation,
5V_OUT current limiting and overall ESD protection for the HDMI Controller.
Figure 19. Application Schematics For HDMI Controllers With One GPIO For HDMI Interface Control
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Typical Application (continued)
9.2.1 Design Requirements
For this example, use Table 2 as the input parameters:
Table 2. HDMI Controller Using One Control Line Design Parameters
DESIGN PARAMETERS
Voltage on VCCA
EXAMPLE VALUE
1.8 V
Voltage on 5V_SYS
5.0 V
Drive EN low (disabled)
-0.5 – 0.4 V
Drive EN low (enabled)
1.0 V to 1.8 V
Drive HPD_CON low (disabled)
0 V – 0.8 V
Drive HPD_CON high (enabled)
2.0 V – 5.0 V
SYS to CON
Drive a logical "1"
CON to SYS
SYS to CON
Drive a logical "0"
CON to SYS
SCL and SDA
1.26 V – 1.8 V
CEC
SCL and SDA
3.5 V – 5.0 V
CEC
2.31 V – 3.3 V
SCL and SDA
-0.5 V – 0.11 V
CEC
SCL and SDA
-0.5 V – 1.5 V
CEC
-0.5 V – 0.99 V
9.2.2 Detailed Design Procedure
To begin the design process the designer needs to know the 5V_SYS voltage range and the logic level, VCCA,
voltage range.
9.2.2.1 Resistor Pull-Up Value Selection
The system is designed to work properly with no external pull-up resistors on the DDC, CEC, and HPD lines.
9.2.2.2 Input Capacitor (Optional)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between 5V_SYS and GND. A 10-μF
ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further
reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have
an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
9.2.2.3 Output Capacitor (Optional)
Due to the integrated body diode in the NMOS switch, a CIN greater than CLOAD is highly recommended. A CLOAD
greater than CIN can cause 5V_CON to exceed 5V_SYS when the system supply is removed. A CIN to CLOAD
ratio of 10 to 1 is recommended for minimizing 5V_SYS dip caused by inrush currents during startup.
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9.2.3 Application Curve
Figure 20. DDC Level Shifter Operation (Connector To System Direction)
10 Power Supply Requirements
TPD5S116 has two power input pins: 5V_SYS and VCCA. It can operate normally with 5V_SYS between 4.5 V
and 5.5 V; and VCCA between 1.1 V and 5.5 V. Thus, the power supply (with a ripple of VRIPPLE) requirement for
TPD5S116 for 5V_SYS is between 4.5 V + ½VRIPPLE and 5.5 V – ½VRIPPLE; and for VCCA it is between 1.1 V +
½VRIPPLE and 5.5 V – ½VRIPPLE.
5.7
5.5
5.3
Voltage (V)
Power Supply Vripple
5.1
Power Supply
Nominal Range
5V_SYS
Input Range
4.9
4.7
4.5
4.3
0
0.01
0.02
0.03
0.04
0.05
Time (s)
0.06
0.07
0.08
0.09
0.1
Figure 21. Power Supply Ripple and TPD5S116 5V_SYS Voltage Requirements
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures. Therefore, the PCB designer needs to minimize the possibility of EMI
coupling by keeping any unprotected traces away from the protected traces which are between the TVS
and the connector.
Route the protected traces as straight as possible.
Avoid using VIAs between the connecter and an I/O protection pin on TPD5S116.
Avoid 90º turns in traces.
– Electric fields tend to build up on corners, increasing EMI coupling.
Minimize impedance on the path to GND for maximum ESD dissipation.
The capacitors on 5V_CON and 5V_SYS should be placed close to their respective pins on TPD5S116.
11.2 Layout Example
LEGEND
HDMI Type C
Top Layer Trace
Signal VIA
GND VIA
Bottom Layer Trace
VIA in SMD
GND Pad
EN
CEC_SYS
CEC
UTIL_SYS
Utility
SCL_SYS
SCL
SDA_SYS
SDA
5V_SYS
GND
+ 5V
0.1 µF
0.1 µF
HPD
HPD_SYS
Figure 22. TPD5S116 HDMI Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPD5S116YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
RE116
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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